Semiconductor device manufacturing method and semiconductor device

Abstract

The application discloses a semiconductor device preparation method and a semiconductor device. The method comprises the following steps: providing a substrate, the substrate comprising a first region and a second region, wherein the first region is used for forming a gate thereon, and the second region is used for forming a source-drain region; forming a sacrificial layer on the substrate; etching the sacrificial layer to form a groove, the bottom of the groove exposing the first region of the substrate; sequentially forming a gate sidewall and a gate, the gate sidewall covering the sidewall of the groove, and the gate filling the groove; removing the sacrificial layer by ashing to expose the second region of the substrate; and performing an ion implantation process to form a source-drain region in the second region. By forming a sacrificial layer on the substrate, the sacrificial layer covers the substrate region used for forming the source-drain region during the process of forming the gate sidewall and the gate, so that damage to the substrate caused by the etching process is avoided, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor device and a semiconductor device thereof. Background Technology

[0002] Since its invention, semiconductors have profoundly transformed human production and daily life. Beyond their applications in computers, semiconductors are widely used in communications, networks, consumer electronics, and automatic control. The development of semiconductor integrated circuits is closely intertwined with fields such as electronics, mathematics, physics, chemistry, and mechanical engineering. The advancement of semiconductor integrated circuit manufacturing has significantly propelled the development of these other fields.

[0003] Semiconductor manufacturing involves numerous processes, such as oxidation, diffusion, ion implantation, photolithography, etching, epitaxy, and metallization. Taking the formation of sidewalls in a semiconductor device as an example, sidewalls are located on the sidewalls of the gate and serve to electrically isolate the gate from impurity regions (such as source / drain regions or lightly doped regions) in the transistor. Forming sidewalls requires depositing sidewall material on the substrate surface, followed by an etching process. Dry etching of the substrate surface can cause substrate damage, thus affecting the performance of the semiconductor device. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device fabrication method and semiconductor device to address the problems mentioned above in the background art, so as to avoid substrate damage during the dry etching process to form sidewalls and improve the performance of semiconductor devices.

[0005] To achieve the above and other related objectives, one aspect of this application provides a method for fabricating a semiconductor device, characterized by comprising the following steps:

[0006] A substrate is provided, the substrate including a first region and a second region, wherein the first region is used to form a gate thereon and the second region is used to form source and drain regions;

[0007] A sacrificial layer is formed on the substrate;

[0008] The sacrificial layer is etched to form a groove, the bottom of which exposes a first region of the substrate;

[0009] A gate sidewall and a gate are formed sequentially, the gate sidewall covering the sidewall of the groove, and the gate filling the groove;

[0010] The sacrificial layer is removed by ashing to expose a second region of the substrate;

[0011] An ion implantation process is performed to form a source / drain region in the second region.

[0012] In some embodiments, the sacrificial layer comprises at least one of amorphous carbon, an antireflective layer, and a polymer.

[0013] In some embodiments, the gate sidewall is tilted, and the bottom area of ​​the gate sidewall is larger than the upper opening area of ​​the gate sidewall.

[0014] In some embodiments, the ions in the source and drain regions are distributed with different concentration gradients.

[0015] In some embodiments, the substrate directly below the gate sidewall includes a gradually changing junction with a gradually varying doping concentration; the source and drain regions are adjacent to the gradually changing junction; and the gradually changing junction and the gate are isolated via an air gate isolation structure.

[0016] In some embodiments, etching the sacrificial layer to form the groove includes:

[0017] Perform vertical dry etching to form a first groove in the sacrificial layer, the bottom of the first groove exposing a first region of the substrate, and the sidewalls of the first groove being vertical;

[0018] Perform lateral dry etching to tilt the sidewalls of the first groove, forming a groove with a bottom area larger than the upper opening area.

[0019] In some embodiments, performing lateral dry etching includes:

[0020] Isotropic etching is performed at the bottom of the first groove, wherein the plasma concentration for isotropic etching in the bottom region of the first groove is greater than the plasma concentration for isotropic etching in the upper region of the first groove.

[0021] In some embodiments, the bias power of plasma etching is reduced and the pressure of plasma etching is increased so that the plasma used for isotropic etching is concentrated at the bottom of the first groove.

[0022] In some embodiments, the sequential formation of the gate sidewall and the gate includes:

[0023] A gate sidewall is formed, which at least covers the sidewall of the recess; the gate sidewall includes an inner liner layer located on the inner sidewall of the recess, and a sidewall material layer located on the side surface of the inner liner layer; a power function layer is formed, which covers the bottom and sidewall of the recess;

[0024] A dielectric layer is formed, which covers the sidewalls of the groove;

[0025] A gate is formed, which fills the groove.

[0026] In some embodiments, forming the gate sidewall includes:

[0027] An inner liner is formed, which covers the bottom and sidewalls of the groove;

[0028] Form a sidewall material layer covering the inner lining layer;

[0029] Dry etching is performed to remove a portion of the sidewall material layer at the bottom of the groove;

[0030] Perform wet etching to completely remove the sidewall material layer at the bottom of the groove, exposing the inner liner layer.

[0031] In some embodiments, after forming the gate, the method further includes:

[0032] Remove the portion of the work function layer located outside the groove to expose the top surface of the work function layer covering the sidewall of the groove;

[0033] The top surface of the work function layer is etched until the surface of the substrate is exposed to form an air gate isolation region;

[0034] The top of the air-barrier isolation area is sealed to form an air-barrier isolation structure.

[0035] Another semiconductor device of this application is prepared by any of the semiconductor device preparation methods described above.

[0036] The semiconductor device fabrication method and semiconductor device provided in the embodiments of this application have the following unexpected technical effects:

[0037] By forming a sacrificial layer on the substrate, the sacrificial layer always covers the substrate area used to form the source and drain regions during the formation of the gate sidewalls and the gate. After the gate sidewalls and the gate are formed, the sacrificial layer is removed by ashing to expose the substrate to form the source and drain regions. This avoids damage to the substrate caused by the etching process and improves the performance of the semiconductor device. Attached Figure Description

[0038] To better describe and illustrate embodiments and / or examples of the applications disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, or the best mode of conduct of these applications as currently understood.

[0039] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device provided in one embodiment;

[0040] Figure 2This is a schematic cross-sectional view of the structure obtained after forming a sacrificial layer in step S102 of the semiconductor device fabrication method provided in one embodiment.

[0041] Figure 3 This is a schematic cross-sectional view of the structure obtained after forming a groove in step S103 of the semiconductor device fabrication method provided in one embodiment.

[0042] Figure 4 This is a schematic cross-sectional view of the structure obtained after forming the sidewall material layer in step S104 of the semiconductor device fabrication method provided in one embodiment.

[0043] Figure 5 This is a schematic cross-sectional view of the structure obtained after forming the gate in step S104 of the semiconductor device fabrication method provided in one embodiment.

[0044] Figure 6 This is a schematic cross-sectional view of the structure obtained after forming an air gate isolation structure in step S104 of the semiconductor device fabrication method provided in one embodiment.

[0045] Figure 7 This is a schematic cross-sectional view of the structure obtained after removing the sacrificial layer in step S105 of the semiconductor device fabrication method provided in one embodiment.

[0046] Figure 8 This is a cross-sectional view of the structure obtained after forming the source / drain region in step S106 of the semiconductor device fabrication method provided in one embodiment.

[0047] Explanation of reference numerals in the attached figures:

[0048] 200. Substrate; 201. Sacrificial layer; 202. Hard mask layer; 203. Photoresist layer; 204. Trench; 205. Inner liner layer; 206. Sidewall material layer; 207. Work function layer; 208. Dielectric layer; 209. Gate; 210. Air gate isolation structure; 211. Source / drain region; 212. Gradual junction; 20. Gate sidewall. Detailed Implementation

[0049] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures). Thus, variations from the illustrated shape can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of the application.

[0055] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation, the form, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0056] Traditional gate sidewall fabrication processes include: Step 1, using chemical vapor deposition to prepare a gate dielectric layer and a polysilicon layer on the surface of a silicon substrate, then using a gate photomask to form a photoresist pattern, followed by dry etching of the polysilicon layer and the gate dielectric layer until the surface of the source / drain regions of the silicon substrate is exposed, forming a polysilicon gate; Step 2, using chemical vapor deposition to prepare a sidewall material layer covering the surface of the silicon substrate, the surface of the polysilicon gate, and the sidewalls, then dry etching of the sidewall material layer until the surface of the source / drain regions of the silicon substrate is exposed, forming a gate sidewall; Step 3, using plasma implantation to form the source / drain regions in the silicon substrate.

[0057] In the aforementioned conventional gate sidewall fabrication process, before performing ion implantation on the source and drain regions of the silicon substrate, steps 1 and 2 have already performed two dry etching processes on the surface of the source and drain regions, causing substrate damage and thus affecting the performance of the semiconductor device.

[0058] To address the substrate damage problem, embodiments of this application provide a method for fabricating a semiconductor device, such as... Figure 1 As shown, it includes the following steps:

[0059] Step S101: Provide a substrate, the substrate including a first region and a second region, wherein the first region is used to form a gate thereon, and the second region is used to form source and drain regions;

[0060] Step S102: Form a sacrificial layer on the substrate;

[0061] Step S103: Etch the sacrificial layer to form a groove, the bottom of which exposes a first region of the substrate;

[0062] Step S104: Sequentially form a gate sidewall and a gate, wherein the gate sidewall covers the sidewall of the groove and the gate fills the groove;

[0063] Step S105: Ash the sacrificial layer to expose the second region of the substrate;

[0064] Step S106: Perform an ion implantation process to form a source / drain region in the second region.

[0065] First, refer to Figure 2 As shown, in step S101, a substrate 200 is provided, the substrate 200 including a first region and a second region, wherein the first region is used to form a gate thereon, and the second region is used to form a source / drain region.

[0066] In some embodiments, the substrate 200 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Preferably, the substrate 200 is a single-crystal silicon substrate.

[0067] In some embodiments, the substrate 200 includes a first region for forming a gate thereon and a second region for forming a source-drain region. The second region further includes a sub-region for forming a source region and a sub-region for forming a drain region. The sub-region for forming the source region and the sub-region for forming the drain region are separated by the first region, i.e., the first region is located between the sub-region for forming the source region and the sub-region for forming the drain region.

[0068] Next, refer to Figure 2 As shown, step S102 is performed to form a sacrificial layer 201 on the substrate 200.

[0069] In some embodiments, the material of the sacrificial layer 201 is selected to be a material that can be removed without damaging the substrate 200. That is, in the step of removing the sacrificial layer 201, there is no need to use a process that damages the substrate, such as dry etching. Further, the material of the sacrificial layer 201 can be a material that can be removed by ashing, such as at least one of amorphous carbon, an anti-reflective layer (ARC), and a polymer.

[0070] In some embodiments, when amorphous carbon is used as the sacrificial layer 201, one or more of C3H6, C2H4, and C2H2 can be used as the source gas, and the sacrificial layer 201 can be formed by methods such as chemical vapor deposition (CVD). For example, one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE).

[0071] Next, refer to Figure 3 As shown, in step S103, the sacrificial layer 201 is etched to form a groove 204, the bottom of which exposes a first region of the substrate 200. Further, the sidewalls of the groove 204 are inclined, and the bottom area of ​​the groove 204 is larger than the upper opening area of ​​the groove.

[0072] Exemplarily, etching the sacrificial layer to form a groove includes: performing vertical dry etching to form a first groove (not shown) in the sacrificial layer, the bottom of the first groove exposing a first region of the substrate, and the sidewalls of the first groove being vertical; performing lateral dry etching to tilt the sidewalls of the first groove, forming a groove 204 with a bottom area larger than the upper opening area. The lateral dry etching includes: performing isotropic etching at the bottom of the first groove, wherein the plasma concentration for isotropic etching in the bottom region of the first groove is greater than the plasma concentration for isotropic etching in the upper region of the first groove, resulting in a groove 204 with an opening area gradually increasing in the direction approaching the substrate 200.

[0073] In some embodiments, first refer to Figure 2As shown, a hard mask layer 202 and a patterned photoresist layer 203 are formed on top of the sacrificial layer 201. Then, a photolithography process is performed to transfer the pattern of the photoresist layer 203 to the hard mask layer 202, forming the patterned hard mask layer 202. Next, using the patterned hard mask layer 202 as a mask, anisotropic dry etching is performed on the sacrificial layer 201 using plasma etching to achieve longitudinal etching of the sacrificial layer 201 until the surface of the substrate 200 is exposed, thereby forming a first groove (not shown) in the sacrificial layer 201. The sidewalls of the first groove are vertical, that is, the sidewalls of the first groove are perpendicular or substantially perpendicular to the surface of the substrate 200. Next, the bias power of plasma etching is reduced to weaken the directionality of the etched free radicals, while the pressure of plasma etching is increased so that the plasma used for isotropic etching gathers at the bottom of the first groove. At this time, the concentration of plasma used for isotropic etching in the bottom region of the first groove is greater than the concentration of plasma used for isotropic etching in the upper region of the first groove, thereby achieving isotropic etching of the bottom of the first groove. The etching degree of the sidewall of the first groove decreases from the bottom to the top, forming a groove sidewall that is inclined as a whole or inclined at the bottom, that is, forming a groove 204 with a bottom area larger than the upper opening area.

[0074] like Figure 3 As shown. Specifically, taking SO2 and O2 plasma as an example, when performing anisotropic etching to form the first groove, the bias power is approximately 150V and the gas pressure is approximately 10mT; when performing isotropic etching to form the inclined groove sidewalls, the bias power is approximately 100V and the gas pressure is approximately 20mT. As the bias power decreases and the gas pressure increases, the plasma accumulates at the bottom of the first groove, causing the plasma concentration to gradually increase from the top to the bottom of the first groove. The plasma concentration is proportional to the degree of etching, thereby forming the inclined groove sidewalls and obtaining a groove 204 with an opening area that gradually increases along the direction close to the substrate 200.

[0075] Next, refer to Figures 4 to 6 As shown, in step S104, a gate sidewall and a gate are formed sequentially, the gate sidewall covering the sidewall of the groove and the gate filling the groove 204.

[0076] For example, refer to Figure 4 As shown, forming the gate sidewall includes: forming an inner liner layer 205 covering the bottom and sidewalls of the recess 204; forming a sidewall material layer 206 covering the inner liner layer 205; performing dry etching to remove a portion of the sidewall material layer 206 at the bottom of the recess 204; and performing wet etching to completely remove the sidewall material layer 206 at the bottom of the recess 204, exposing the inner liner layer 205.

[0077] In some embodiments, an inner liner layer 205 may be formed using processes familiar to those skilled in the art, such as atomic vapor deposition (ALD). The inner liner layer 205 covers the entire substrate 200. Specifically, the inner liner layer 205 covers the top surface of the hard mask layer 202, the sidewalls of the recess 204, and the bottom of the recess 204, wherein the bottom of the recess 204 is the top surface of a first region of the substrate 200. The material of the inner liner layer 205 may be an oxide, such as silicon oxide (SiO2). Next, a sidewall material layer 206 that completely covers the inner liner layer 205 may be formed using processes familiar to those skilled in the art, such as chemical vapor deposition (CVD). The sidewall material layer 206 covers the sidewalls of the recess 204 and the bottom of the recess 204, and further, covers the entire inner liner layer 205. The material of the sidewall material layer 206 may be a nitride, such as silicon nitride (SiN).

[0078] Furthermore, the formed sidewall material layer 206 has sufficient thickness to fill the space below the inclined sidewall of the groove 204, making the bottom area of ​​the groove 204 the same as or similar to the upper opening area. Next, dry etching is used to re-etch the sidewall material layer 206 to thin the sidewall material layer covering the bottom of the groove 204. However, to avoid damage caused by dry etching, a portion of the sidewall material layer covering the bottom of the groove 204 is retained. Then, wet etching is used to remove the remaining sidewall material layer until the inner liner layer 205 covering the bottom of the groove 204 is exposed. In addition, through the above-described dry etching, or a combination of dry and wet etching, the sidewall material layer covering the surface of the hard mask layer 202 is completely removed to form... Figure 4 The structure shown.

[0079] Furthermore, refer to Figure 5 As shown, the sequential formation of the gate sidewall and the gate includes: forming a gate sidewall that at least covers the sidewall of the groove; forming a power function layer 207 that covers the bottom and sidewall of the groove; forming a dielectric layer 208 that covers the sidewall of the groove; and forming a gate 209 that fills the groove.

[0080] In some embodiments, after forming the gate sidewall, a work function layer 207 and a dielectric layer 208 are formed sequentially. Specifically, before forming the work function layer 207, a step of forming a gate dielectric layer (not shown) is included. The gate dielectric layer is typically made of a high-k dielectric material, including but not limited to one or more of hafnium oxide, zirconium oxide, silicon oxynitride hafnium, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide. The work function layer 207 includes but is not limited to one or more of TiN, TaN, TiC, TiAl, TiAlC, or TaAlC, preferably titanium nitride (TiN). The dielectric layer 208 is made of an oxide material, such as silicon oxide (SiO2). The methods for forming the gate dielectric layer, work function layer 207, and dielectric layer 208 can employ process techniques familiar to those skilled in the art, such as chemical vapor deposition (CVD), and will not be described in detail here. The aforementioned work function layer 207 and dielectric layer 208 both cover the bottom and sidewalls of the groove 204, and also cover the hard mask layer 202. Then, dry etching is performed to remove the portions of the gate dielectric layer, work function layer 207, and dielectric layer 208 located outside the groove and covering the hard mask layer 202, as well as the portion of dielectric layer 208 covering the bottom of the groove, leaving only the portion of dielectric layer 208 covering the sidewalls of the groove.

[0081] In some embodiments, after forming the work function layer 207 and the dielectric layer 208, a gate 209 is formed in the recess 204. Specifically, the gate 209 can be made of polysilicon or a metal material. For example, the method for forming a polysilicon gate can use silane (SiH4) as the reactant gas and helium or nitrogen as the buffer gas. By controlling the flow rates of the reactant gas and the buffer gas, as well as the temperature and pressure of the reaction chamber, a gate material layer is formed using a low-pressure chemical vapor deposition (LPCVD) process or similar method. Then, chemical mechanical polishing (CMP) is performed to remove excess gate material, thereby forming the gate 209 in the recess 204. It should be noted that the gate 209 formed by the method of the present invention can be directly used as the gate of a semiconductor device without the need to pre-form a dummy gate, thus optimizing the gate formation process in semiconductor manufacturing.

[0082] For example, refer to Figure 6 As shown, after forming the gate 209, the method further includes: removing the work function layer 207 covering the hard mask layer 202 to expose the top surface of the work function layer 207 covering the sidewall of the recess; etching the top surface of the work function layer 207 until the surface of the substrate 200 is exposed to form an air gate isolation region; and sealing the top of the air gate isolation region to form an air gate isolation structure 210.

[0083] Please continue to refer to Figure 6As shown, in some embodiments, a dry etching process is used to remove the portions of the gate dielectric layer, work function layer 207, dielectric layer 208, and liner layer 205 located outside the recess, i.e., the portions covering the hard mask layer 202, until the top surface of the hard mask layer 202 is exposed. The portions of the gate dielectric layer, work function layer 207, dielectric layer 208, and liner layer 205 located within the recess are retained. Specifically, the dielectric layer 208 covers the sidewalls of the recess, the gate dielectric layer and work function layer 207 cover the bottom and sidewalls of the recess, and the liner layer 205 covers the bottom and sidewalls of the recess. Next, an etching process is performed to etch the gate dielectric layer and work function layer 207, completely removing the portions covering the sidewalls of the recess, retaining only the portions covering the bottom of the recess, until the liner layer 205 is exposed. The liner layer 205 is then etched further until the substrate 200 is exposed. This forms an air gate isolation region between the gate 209 and the sidewalls. Next, sealing material is deposited using methods such as chemical vapor deposition (CVD). Due to the high aspect ratio of the air-gate isolation region, the sealing material only fills a portion of the top of the air-gate isolation region, forming a top seal. An air gap remains between the top seal and the substrate 200. Excess sealing material is removed using a CMP process until the top surface of the hard mask layer 202 is processed. Figure 6 As shown. At this point, an air gate isolation structure 210 is formed between the gate 209 and the sidewall.

[0084] Next, refer to Figure 7 As shown, in step S105, the sacrificial layer is ashed to expose the second region of the substrate. The remaining sidewall material layer 206 and the inner liner layer 205 located on the outer sidewall of the sidewall material layer 206 are used to jointly form the gate sidewall 20.

[0085] In some embodiments, dry etching is first performed to remove the hard mask layer 202, and then the sacrificial layer 201 is removed by ashing. Taking amorphous carbon as an example, the ashing method uses a plasma gas containing oxygen or oxygen ions to remove the amorphous carbon. The ashing process is generally performed at a high temperature, which can be 300°C to 800°C, for example, 300°C, 600°C, or 800°C. Removing the sacrificial layer 201 by ashing eliminates the need for dry etching, and ashing does not damage the second region of the substrate 200 covered by the sacrificial layer 201, thus avoiding damage to the substrate caused by dry etching. After removing the sacrificial layer 201, the exposed gate structure is as follows: Figure 7 As shown, the area at the bottom of the gate sidewall is larger than the area of ​​the opening at the top, that is, the gate sidewall is tilted.

[0086] Next, refer to Figure 8 As shown, step S106 is performed to perform an ion implantation process to form source / drain regions 211 in the second region.

[0087] Please refer to Figure 8 In some embodiments, using the inclined gate sidewall as a mask, ion implantation is performed on both sides of the gate structure. The implanted ions can be N-type or P-type ions, forming ion-doped source / drain regions 211 in the second region of the substrate. Due to the inclined gate sidewall, the ions in the formed source / drain regions 211 exhibit different concentration gradients. Furthermore, a gradual junction 212 is formed at the junction of the source / drain regions 211 (i.e., the second region of the substrate 200) and the substrate below the gate structure (i.e., the first region of the substrate 200), as shown below. Figure 8 As shown, by forming source and drain regions with different concentration gradients, and forming a gradually changing junction 212 with a gradually varying doping concentration between the source / drain regions and the gate structure, the gradually changing junction 212 is located directly below the gate sidewall 20. The source / drain regions are adjacent to the gradually changing junction 212, and the gradually changing junction 212 is isolated from the dielectric layer 208 via an air gate isolation structure 210. This allows for a smoother vertical electric field distribution near the source / drain ends, avoids peak electric field problems caused by abrupt changes in doping concentration, suppresses the hot carrier injection effect, and improves the electrical performance of the semiconductor device.

[0088] This concludes the introduction of the relevant steps in the semiconductor device fabrication method according to this embodiment of the invention. It is understood that the semiconductor device fabrication method of this embodiment includes not only the steps described above, but may also include other necessary steps before, during, or after the steps described above, all of which are included within the scope of this manufacturing method.

[0089] The method for fabricating a semiconductor device according to the embodiments of this application has the following unexpected technical effects:

[0090] By forming a sacrificial layer on the substrate, the sacrificial layer always covers the substrate area used to form the source and drain regions during the formation of the gate sidewalls and the gate. After the gate sidewalls and the gate are formed, the sacrificial layer is removed by ashing to expose the substrate to form the source and drain regions. This avoids damage to the substrate caused by the etching process and improves the performance of the semiconductor device.

[0091] Reference Figure 8 The diagram shows a schematic cross-sectional view of a semiconductor device provided according to the present invention. The semiconductor device is manufactured by the method described above.

[0092] like Figure 8 As shown, the semiconductor device includes: a substrate 200, wherein spaced source and drain regions 211 are included within the substrate 200; and a gate structure located between the source and drain regions on the top surface of the substrate, wherein the gate structure includes inclined gate sidewalls.

[0093] like Figure 8As shown, in some embodiments, the substrate 200 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Preferably, the substrate 200 is a single-crystal silicon substrate.

[0094] like Figure 8 As shown, in some embodiments, the substrate 200 includes a first region for forming a gate thereon and a second region for forming a source / drain region 211, the second region further including a source region and a drain region, the source region and the drain region being spaced apart, and the first region being located between the source region and the drain region.

[0095] like Figure 8 As shown, in some embodiments, the gate structure along a first direction includes a gate 209, a dielectric layer 208, an air gate isolation structure 210, a sidewall material layer 206, and an inner liner layer 205 arranged sequentially. The gate structure along a second direction includes a gate 209, a work function layer 207, a gate dielectric layer, and an inner liner layer 205 arranged sequentially. The first direction is perpendicular to the sidewall of the gate 209, and the second direction is perpendicular to the bottom surface of the gate 209. The gate sidewall includes a sidewall material layer 206 and an inner liner layer 205.

[0096] like Figure 8As shown, in some embodiments, the gate 209 may be made of polysilicon or a metal. A dielectric layer 208 covers the sidewalls of the gate 209 but not the bottom of the gate 209; the dielectric layer 208 is made of an oxide material, such as silicon oxide (SiO2). A work function layer 207 and a gate dielectric layer cover the bottom of the gate 209 but not the sidewalls of the gate. The work function layer 207 includes, but is not limited to, one or more of TiN, TaN, TiC, TiAl, TiAlC, or TaAlC, preferably titanium nitride (TiN). The gate dielectric layer is typically made of a high-k dielectric material, including, but not limited to, one or more of hafnium oxide, zirconium oxide, silicon oxynitride hafnium, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide. The air-gate isolation structure 210 includes a gap between the dielectric layer 208 and the sidewall material layer 206. The bottom of the air-gate isolation structure 210 is in contact with the substrate 200, and the top of the air-gate isolation structure 210 includes a top seal. That is, the air-gate isolation structure 210 is formed by the dielectric layer 208, the sidewall material layer 206, the substrate 200, and the top seal surrounding the air gap on all four sides. The sidewall material layer 206 covers the sidewalls of the gate 209 but not the bottom of the gate 209. The material of the sidewall material layer 206 can be a nitride, such as silicon nitride (SiN). The liner layer covers the bottom and sidewalls of the gate, and the liner layer 205 is penetrated by the air-gate isolation structure 210. The material of the liner layer 205 can be an oxide, such as silicon oxide (SiO2).

[0097] like Figure 8 As shown, in some embodiments, the gate sidewall is inclined, specifically, the area at the bottom of the gate sidewall is larger than the area of ​​the upper opening. The ions in the source / drain regions 211 exhibit different concentration gradients. Furthermore, a gradual junction 212 is formed between the source / drain regions 211 (i.e., the second region of the substrate 200) and the substrate below the gate structure (i.e., the first region of the substrate 200). The gradual junction 212 is located directly below the gate sidewall 20, and is isolated from the dielectric layer 208 via an air gate isolation structure 210. By forming source / drain regions with different concentration gradients and a gradually changing doping concentration junction 212 between the source / drain regions and the gate structure, the longitudinal electric field distribution near the source / drain ends can be made smoother, avoiding peak electric field problems caused by abrupt changes in doping concentration, suppressing the hot carrier injection effect, and improving the electrical performance of the semiconductor device.

[0098] The specific structure of the semiconductor device can be referred to in the corresponding section above, and will not be repeated here for the sake of brevity.

[0099] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0100] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, the substrate including a first region and a second region, wherein the first region is used to form a gate thereon and the second region is used to form source and drain regions; A sacrificial layer is formed on the substrate; The sacrificial layer is etched to form a groove, the bottom of which exposes a first region of the substrate; A gate sidewall and a gate are formed sequentially, the gate sidewall covering the sidewall of the groove, and the gate filling the groove; The sacrificial layer is removed by ashing to expose a second region of the substrate; An ion implantation process is performed to form a source / drain region in the second region; The etching of the sacrificial layer to form the groove includes: Perform vertical dry etching to form a first groove in the sacrificial layer, the bottom of the first groove exposing a first region of the substrate, and the sidewalls of the first groove being vertical; Perform lateral dry etching to tilt the sidewalls of the first groove, forming a groove with a bottom area larger than the upper opening area.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The sacrificial layer includes at least one of amorphous carbon, an anti-reflective layer, and a polymer.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The gate sidewall is inclined, and the bottom area of ​​the gate sidewall is larger than the upper opening area of ​​the gate sidewall.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The ions in the source and drain regions are distributed with different concentration gradients.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The substrate directly below the gate sidewall includes a gradually varying doping concentration junction; The source / drain region is adjacent to the gradually changing junction; The gradually changing junction is isolated from the gate via an air-gate isolation structure.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The lateral dry etching process includes: Isotropic etching is performed at the bottom of the first groove, wherein the plasma concentration for isotropic etching in the bottom region of the first groove is greater than the plasma concentration for isotropic etching in the upper region of the first groove.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, Reduce the bias power of plasma etching and increase the pressure of plasma etching so that the plasma used for isotropic etching gathers at the bottom of the first groove.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The sequential formation of the gate sidewall and the gate includes: A gate sidewall is formed, the gate sidewall at least covering the sidewall of the recess; the gate sidewall includes an inner liner layer located on the inner sidewall of the recess, and a sidewall material layer located on the side surface of the inner liner layer; A work function layer is formed, which covers the bottom and sidewalls of the groove; A dielectric layer is formed, which covers the sidewalls of the groove; A gate is formed, which fills the groove.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, Forming the gate sidewall includes: An inner liner is formed, which covers the bottom and sidewalls of the groove; Form a sidewall material layer covering the inner lining layer; Dry etching is performed to remove a portion of the sidewall material layer at the bottom of the groove; Perform wet etching to completely remove the sidewall material layer at the bottom of the groove, exposing the inner liner layer.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, After forming the gate, the process further includes: Remove the portion of the work function layer located outside the groove to expose the top surface of the work function layer covering the sidewall of the groove; The top surface of the work function layer is etched until the surface of the substrate is exposed to form an air gate isolation region; The top of the air-barrier isolation area is sealed to form an air-barrier isolation structure.

11. A semiconductor device, characterized in that, It is prepared by the method of any one of claims 1 to 10.

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