An ultra-short channel MOSFET structure resistant to short channel effect and its fabrication process

Abstract

This invention discloses an ultra-short channel MOSFET structure and its manufacturing process to resist short-channel effects, belonging to the semiconductor field. It comprises several parallel MOS cells, each including a drain, a semiconductor epitaxial layer, a source, and a gate. The semiconductor epitaxial layer includes an N-substrate layer, an N-drift layer, a P+ layer, an N-well layer, and a P-well layer. A lightly doped N-layer is provided in the middle of the N-drift layer of each MOS cell. This design significantly suppresses short-channel effects and improves device stability. The core design uses a side-symmetric P⁻ layer to form a strong depletion region, directly suppressing drain-induced barrier reduction (DIBL) and threshold voltage drift. Top P- layers, combined P- layers, rectangular P- layers, and elongated P- layers further compress the electric field distortion at the channel edge by forming auxiliary depletion regions, synergistically enhancing the suppression of short-channel effects. This solves the performance degradation problem caused by the shortening of the channel length in ultra-short channel structures, enabling the device to maintain stable electrical characteristics even at small sizes.

Description

Technical Field

[0001] This invention relates to semiconductors, and more particularly to an ultra-short channel MOSFET structure and its manufacturing process that resists short channel effects. Background Technology

[0002] As semiconductor technology advances to the deep submicron and even nanoscale, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) continues to shorten to meet the demands of high integration and high computing speed in integrated circuits. However, when the channel length is reduced to the ultra-short channel range below 100nm, the short-channel effect (SCE) becomes the core bottleneck restricting device performance—the drain electric field easily penetrates the channel region, leading to problems such as drain-induced barrier reduction (DIBL), threshold voltage drift, and deterioration of subthreshold swing, which seriously affect the switching characteristics and stability of the device.

[0003] A patent (CN106298878B) discloses a dual-gate MOSFET structure and its fabrication method. This patent uses III-V group semiconductors as the channel and source / drain materials, employing first and second gate metal layers to form a dual-gate structure. Integrated on a silicon substrate, it can achieve monolithic integration with silicon-based CMOS devices.12 It enhances gate control capability and reduces short-channel effects through the dual-gate structure, and utilizes via technology to reduce parasitic capacitance and optimize RF characteristics.1 Fabrication requires multiple steps, including depositing an isolation layer, bonding metal layers to form a bonding sheet, and then bonding and etching to form the various layers, involving multiple deposition methods.34 However, the structure contains more than ten layers, involves diverse materials, and has complex processes, potentially reducing yield. Lattice mismatch between III-V group materials and the silicon substrate may affect stability, and the high cost and complex processes are not conducive to mass production.

[0004] Therefore, developing novel MOSFET structures that can synergistically suppress short-channel effects, optimize carrier transport, and balance efficiency and stability has become a key issue in the development of ultra-short-channel devices. Summary of the Invention

[0005] Purpose of the invention: The purpose of this invention is to improve the reliability of devices in high-frequency and high-voltage scenarios. Another purpose of this invention is to shorten the current path to reduce energy loss when the device is turned on, and to accelerate carrier extraction and enhance blocking capability when the device is turned off, thereby meeting the stringent requirements of high-density integrated and high-efficiency conversion electronic systems for device switching speed and long-term stability.

[0006] Technical solution: An ultra-short channel MOSFET structure resistant to short channel effect, comprising a plurality of parallel MOS cells, each MOS cell including a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer, wherein a lightly doped N layer is provided in the middle of the N drift layer of each MOS cell;

[0007] A laterally symmetrical P-layer is provided inside a single MOS cell and on the left and right sides of the N drift layer. The laterally symmetrical P-layer has a trapezoidal outline and its bottom end is in contact with the N substrate layer.

[0008] Furthermore, a laterally symmetric N+ layer is formed on both sides of the interior of the lightly doped N layer by ion implantation. The laterally symmetric N+ layer is arc-shaped, and the bottom end of the laterally symmetric N+ layer is in contact with the N substrate layer.

[0009] Furthermore, a top P-layer is formed on both sides of the interior of the lightly doped N-layer by ion implantation, and the top of the top P-layer is in contact with the gate.

[0010] Furthermore, a bottom N+ layer is formed on both sides of the middle of the lightly doped N layer by ion implantation, and the bottom N+ layer is in contact with the N substrate layer.

[0011] Furthermore, a combined N+ layer is formed in the middle region of the lightly doped N layer by ion implantation, and the top of the combined N+ layer is in contact with the gate.

[0012] Furthermore, a combined P- layer is symmetrically formed on both sides of the combined N+ layer by ion implantation, and the top of the combined P- layer is in contact with the gate.

[0013] Furthermore, a vertical N+ layer is formed in the middle region of the lightly doped N layer by ion implantation, and a spherical P- layer is formed at the top of the vertical N+ layer by ion implantation.

[0014] Furthermore, a rectangular P- layer is formed in the middle region of the lightly doped N- layer by ion implantation, and semi-circular N+ layers are formed on both sides of the rectangular P- layer by ion implantation. The top of the rectangular P- layer is in contact with the gate, and the top of the semi-circular N+ layer is in contact with the gate.

[0015] Furthermore, a strip P- layer is formed in the middle region of the lightly doped N- layer by ion implantation, and strip N+ layers are formed on both sides of the strip P- layer by ion implantation. The top of the strip P- layer is in contact with the gate, the top of the strip N+ layer is in contact with the gate, and the ends of the two strip N+ layers away from the gate are in contact with the two sides of the strip P- layer, respectively.

[0016] According to another aspect of the present invention, an ultra-short channel MOSFET structure resistant to short channel effects and its manufacturing process are provided, comprising the following steps:

[0017] S1: Prepare the N-substrate layer as the base substrate of the entire MOSFET structure. Perform surface cleaning and pretreatment to remove impurities and the natural oxide layer.

[0018] S2: An N-drift layer is prepared on an N-substrate using epitaxial growth technology. The temperature, pressure, and doping concentration of the epitaxial growth are controlled to ensure that the thickness and electrical properties of the N-drift layer meet the design requirements.

[0019] S3: The formation region of the side-symmetric P-layer is defined by photolithography. Then, P-type impurities are implanted into the left and right sides of the N drift layer using ion implantation technology to form a trapezoidal side-symmetric P-layer with its bottom end in contact with the N substrate layer. After that, annealing is performed to activate the implanted impurities and repair lattice damage.

[0020] S4: In the middle of the N drift layer, the region of the lightly doped N layer is determined by photolithography. Low concentration of N-type impurities is implanted using ion implantation technology to form a lightly doped N layer, which is then annealed.

[0021] S5: If a side-symmetric N+ layer needs to be formed, its position is defined by photolithography. High-concentration N-type impurities are implanted into both sides of the interior of the lightly doped N layer using ion implantation technology to form an arc-shaped side-symmetric N+ layer, ensuring that its bottom end is in contact with the N substrate layer, and then annealing is performed.

[0022] S6: When it is necessary to fabricate the top P-layer, the region is determined by photolithography, and P-type impurities are implanted into both sides of the interior of the lightly doped N-layer so that the top of the top P-layer contacts the gate to be formed subsequently. After completion, annealing is performed.

[0023] S7: For the bottom N+ layer, the position is defined by photolithography, and high-concentration N-type impurities are implanted into the middle two sides of the lightly doped N layer to make it contact the N substrate layer, followed by annealing.

[0024] S8: To form a combined N+ layer, the region is determined by photolithography, and a high concentration of N-type impurities is implanted into the middle region of the lightly doped N layer to ensure that its top is in contact with the gate, and then annealing is performed.

[0025] S9: On both sides of the combined N+ layer, the position of the combined P- layer is defined by photolithography. P-type impurities are implanted with ions to make the top of the combined P- layer contact the gate. After completion, annealing is performed.

[0026] S10: When it is necessary to fabricate a vertical N+ layer and a spherical P- layer, first define the region of the vertical N+ layer by photolithography, then implant high-concentration N-type impurities with ions to form the vertical N+ layer, and then form a spherical P- layer on its top by photolithography and ion implantation, and perform annealing treatment respectively.

[0027] S11: For the rectangular P- layer and the semi-circular N+ layer, first, the region of the rectangular P- layer is defined by photolithography, and P-type impurities are implanted by ions to make its top contact with the gate; then, the regions of the semi-circular N+ layer are defined by photolithography on both sides, and high-concentration N-type impurities are implanted by ions to ensure that its top contacts the gate, and then annealing is performed respectively.

[0028] S12: When fabricating the strip P- layer and the strip N+ layer, first, the region of the strip P- layer is defined by photolithography, and P-type impurities are implanted by ions to make its top end contact the gate; then, the regions of the strip N+ layer are defined by photolithography on both sides of it, and high-concentration N-type impurities are implanted by ions to make the top end of the strip N+ layer contact the gate, and the ends of the two strip N+ layers away from the gate contact the two sides of the strip P- layer respectively. After completion, annealing is performed separately.

[0029] S13: Prepare P+ layer, N-well layer and P-well layer at corresponding positions on N-drift layer, define each layer region by photolithography, and perform ion implantation and annealing treatment respectively.

[0030] S14: The gate is fabricated using photolithography and etching processes to ensure good contact between the gate and related layers (such as combined N+ layers). The material can be polysilicon or metal.

[0031] S15: Drain and source electrodes are fabricated at both ends of the structure, and regions are defined by photolithography. High-concentration impurity implantation and metallization processes are then performed to form good ohmic contacts.

[0032] S16: Perform final annealing to optimize the electrical performance of the entire structure, followed by surface passivation and post-processing to complete the fabrication of an ultra-short channel MOSFET structure resistant to short channel effects.

[0033] Beneficial effects: It can significantly suppress short-channel effects and improve device stability. The core design is a side-symmetric P-layer that forms a strong depletion region, directly suppressing drain-induced barrier reduction (DIBL) and threshold voltage drift. The top P-layer, combined P-layer, rectangular P-layer, and long strip P-layer form auxiliary depletion regions, further compressing the electric field distortion at the channel edge, and synergistically strengthening the suppression of short-channel effects. This solves the performance degradation problem caused by the shortening of the channel length in ultra-short channel structures, enabling the device to maintain stable electrical characteristics even in small sizes.

[0034] It can optimize conduction performance and reduce energy loss. The core design features a lightly doped N-layer with a smooth vertical electric field distribution, which reduces carrier scattering and improves mobility. Highly doped structures such as laterally symmetrical N+ layers (arc-shaped), bottom N+ layers, vertical N+ layers, semi-arc N+ layers, and strip N+ layers shorten the current transmission path (lateral / vertical), widen the transmission channel, and reduce the interface barrier. The effect is to significantly reduce on-resistance, improve carrier migration efficiency and current density, reduce energy loss during conduction, and improve device operating efficiency.

[0035] It can accelerate the turn-off response and shorten the turn-off time. The core design consists of a side-symmetric N+ layer, a bottom N+ layer, a semi-circular N+ layer, a strip-shaped N+ layer, etc., which are connected to the N substrate layer or the gate, and can quickly extract the remaining carriers in the channel. The top P- layer, combined P- layer, rectangular P- layer, etc., quickly deplete the surrounding lightly doped N-layer region during turn-off, accelerating the channel cutoff. The effect is to shorten the turn-off delay, improve the device switching speed, and meet the requirements of high-frequency application scenarios for fast state switching.

[0036] It can enhance reverse withstand voltage capability and ensure stability in the turn-off state. The core design is that the P⁺ layer, N-well layer, and P-well layer form a high-resistance blocking region. The side-symmetric P⁻ layer, combined P- layer, rectangular P- layer, and long strip P- layer construct a three-dimensional blocking network through depletion effect, which works together to maintain the longitudinal blocking electric field. The effect is to ensure that the device can withstand high reverse voltage when turned off, avoid the risk of breakdown, and improve the working stability under extreme conditions.

[0037] It can optimize the electric field distribution and reduce the risk of device damage. The core design features a smooth longitudinal / lateral electric field distribution with lightly doped N-layers, spherical P-layers, and other structures. Various P-layers (side-symmetric P⁻ layers, top P-layers, etc.) suppress electric field concentration, avoid channel edge field distortion, and reduce the hot electron injection effect and carrier collision damage caused by electric field concentration, thereby extending the device life and improving long-term operational reliability. Attached Figure Description

[0038] Figure 1 This is a structural schematic diagram of Embodiment 1 of the present invention;

[0039] Figure 2 This is a structural schematic diagram of Embodiment 1 of the present invention;

[0040] Figure 3 This is a schematic diagram of the structure of Embodiment 2 of the present invention;

[0041] Figure 4 This is a schematic diagram of the structure of Embodiment 2 of the present invention;

[0042] Figure 5 This is a schematic diagram of the structure of Embodiment 3 of the present invention;

[0043] Figure 6This is a schematic diagram of the structure of Embodiment 4 of the present invention;

[0044] Figure 7 This is a schematic diagram of the structure of Embodiment 4 of the present invention;

[0045] Figure 8 This is a structural schematic diagram of Embodiment 5 of the present invention;

[0046] Figure 9 This is a structural schematic diagram of Embodiment 5 of the present invention.

[0047] In the figure: 1. Drain; 2. N substrate layer; 3. N drift layer; 4. Source; 5. Gate; 6. Lightly doped N layer; 7. Laterally symmetric P- layer; 8. P+ layer; 9. N well layer; 10. P well layer; 11. Laterally symmetric N+ layer; 12. Top P- layer; 13. Bottom N+ layer; 14. Combined N+ layer; 15. Combined P- layer; 16. Vertical N+ layer; 17. Spherical P- layer; 18. Rectangular P- layer; 19. Semi-arc N+ layer; 20. Long strip P- layer; 21. Strip N+ layer. Detailed Implementation

[0048] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] Example 1

[0050] like Figure 1 As shown, an ultra-short channel MOSFET structure with resistance to short channel effect is provided, comprising a plurality of parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 4, and a gate 5. The semiconductor epitaxial layer includes an N substrate layer 2, an N drift layer 3, a P+ layer 8, an N well layer 9, and a P well layer 10. A lightly doped N layer 6 is provided in the middle of the N drift layer 3 of each MOS cell. Laterally symmetric P-layers 7 are provided inside the MOS cell and on the left and right sides of the N drift layer 3. The laterally symmetric P-layers 7 have a trapezoidal outline, and the bottom end of the laterally symmetric P-layers 7 is in contact with the N substrate layer 2.

[0051] The side-symmetric P⁻ layer 7 is trapezoidal and its bottom end contacts the N substrate layer 2, which can form a strong depletion region on both sides of the channel, effectively suppressing the drain-induced barrier, reducing DIBL and threshold voltage drift, and significantly weakening the short-channel effect. The lightly doped N layer 6 is located in the middle of the N drift layer 3, which can smooth the longitudinal electric field distribution, reduce carrier scattering, improve mobility, and at the same time reduce the hot electron injection effect, enhancing device stability. The P⁺ layer 8 works synergistically with the N well layer 9 and the P well layer 10 to enhance the gate 5's control over the channel and improve the switching speed. When turned on, a positive voltage is applied to the gate 5, forming a conductive channel under the gate, and carriers are transported from the source 4 through the channel to the drain 1. Because the side-symmetric P⁻ layer 7 is in contact with the N substrate layer 2, it quickly depletes the surrounding N drift layer 3 under the high voltage of the drain 1, suppressing the channel edge field distortion. The lightly doped N layer 6 makes the electric field of the current path more uniform and reduces energy loss. When turned off, the gate voltage is lower than the threshold, and the channel is cut off. The P⁺ layer 8, N-well layer 9, and P-well layer 10 form a high-resistance blocking region. Combined with the depletion effect of the P⁻ layer 7, it maintains high reverse withstand voltage and achieves stable turn-off.

[0052] Example 2

[0053] like Figure 2-3 As shown, an ultra-short channel MOSFET structure with resistance to short channel effect is provided. A laterally symmetrical N+ layer 11 is formed on both sides of the interior of the lightly doped N layer 6 by ion implantation. The laterally symmetrical N+ layer 11 is arc-shaped and the bottom end of the laterally symmetrical N+ layer 11 is in contact with the N substrate layer 2. A top P- layer 12 is formed on both sides of the interior of the lightly doped N layer 6 by ion implantation. The top end of the top P- layer 12 is in contact with the gate 5.

[0054] When the device is turned on, a forward voltage is applied to the gate 5 to form a conductive channel. The side-symmetric N+ layer 11, due to its arc-shaped design, contacts the N substrate layer 2, which can quickly collect carriers, shorten the lateral current transport path, and reduce the on-resistance. Its high doping characteristics enhance the contact with the lightly doped N layer 6, reduce the interface barrier, and improve the carrier migration efficiency. The top P- layer 12 contacts the gate 5 and forms an auxiliary depletion region under the gate voltage, further compressing the electric field distortion at the channel edge. Together with the side-symmetric P⁻ layer 7, it strengthens the suppression of short-channel effects. When the device is turned off, the top P- layer 12 rapidly depletes the upper region of the lightly doped N layer 6 as the gate voltage decreases, forming a vertical blocking electric field with the P⁺ layer 8. The side-symmetric N+ layer 11, because it is connected to the N substrate layer 2, accelerates the extraction of remaining carriers on the drain side 1, shortens the turn-off time, and at the same time works with the N-well layer 9 and P-well layer 10 to maintain the reverse breakdown voltage stability of the device.

[0055] Example 3

[0056] like Figure 4-5As shown, an ultra-short channel MOSFET structure with resistance to short channel effect is provided. A bottom N+ layer 13 is formed on both sides of the middle of the lightly doped N layer 6 by ion implantation. The bottom N+ layer 13 is in contact with the N substrate layer 2. A combined N+ layer 14 is formed in the middle region of the lightly doped N layer 6 by ion implantation. The top of the combined N+ layer 14 is in contact with the gate 5. A combined P- layer 15 is formed symmetrically on both sides of the combined N+ layer 14 by ion implantation. The top of the combined P- layer 15 is in contact with the gate 5.

[0057] When turned on, the combined N+ layer 14 contacts the gate 5, forming the core of the main current channel and enhancing the gate's control over the channel. The bottom N+ layer 13 contacts the N substrate layer 2, constructing a vertical carrier transport shortcut and reducing the resistance loss of the lightly doped N layer 6. The combined P- layer 15 forms an auxiliary depletion region as the gate voltage is turned on, working with the top P- layer 12 to compress the channel edge electric field and further suppress the short-channel effect. When turned off, the combined N+ layer 14 quickly extracts the remaining carriers from the channel, and the bottom N+ layer 13 accelerates the introduction of carriers into the N substrate layer 2, shortening the turn-off delay. The combined P- layer 15 and the P⁺ layer 8 form a vertical blocking enhancement region, working with the symmetrical P⁻ layer 7 to improve reverse breakdown voltage stability and ensure the insulation performance of the device in the off state.

[0058] Example 4

[0059] like Figure 6-7 As shown, an ultra-short channel MOSFET structure with resistance to short channel effect is provided. A vertical N+ layer 16 is formed in the middle region of the lightly doped N layer 6 by ion implantation. A spherical P- layer 17 is formed at the top of the vertical N+ layer 16 by ion implantation. A rectangular P- layer 18 is formed in the middle region of the lightly doped N layer 6 by ion implantation. Semi-arc N+ layers 19 are formed on both sides of the rectangular P- layer 18 by ion implantation. The top of the rectangular P- layer 18 is in contact with the gate 5, and the top of the semi-arc N+ layer 19 is in contact with the gate 5.

[0060] During conduction, the vertical N+ layer 16 provides a high-speed vertical channel for charge carriers, enhancing current transport efficiency in conjunction with the bottom N+ layer 13. The semi-circular N+ layer 19 contacts the gate 5, widening the lateral current path and reducing on-resistance. The spherical P- layer 17 forms a local depletion region under the gate voltage, working with the rectangular P- layer 18 to suppress electric field concentration in the middle of the channel and enhance the gate 5's control over the core region. During turn-off, the rectangular P- layer 18 rapidly depletes the surrounding lightly doped N-layer 6, forming a three-dimensional blocking network with the combined P-layer 15. The semi-circular N+ layer 19 accelerates the extraction of charge carriers towards the gate 5, while the vertical N+ layer 16 guides the remaining charge carriers into the N-substrate layer 2, significantly shortening the turn-off time. The spherical P- layer 17 enhances the uniformity of the vertical electric field distribution, further improving reverse breakdown voltage stability in conjunction with the laterally symmetrical P⁻ layer 7.

[0061] Example 5

[0062] like Figure 8-9 As shown, an ultra-short channel MOSFET structure with resistance to short channel effect is provided. A strip P- layer 20 is formed in the middle region of the lightly doped N- layer 6 by ion implantation. Strip N+ layers 21 are formed on both sides of the strip P- layer 20 by ion implantation. The top of the strip P- layer 20 is in contact with the gate 5. The top of the strip N+ layer 21 is in contact with the gate 5. The ends of the two strip N+ layers 21 away from the gate 5 are in contact with the two sides of the strip P- layer 20, respectively.

[0063] When turned on, the strip-shaped N+ layer 21 contacts the gate 5. Because its top end connects to the gate and its bottom end contacts the strip-shaped P- layer 20, it forms a stepped current channel. This, together with the semi-circular N+ layer 19, widens the carrier transport path and reduces the on-resistance. Its high doping characteristics accelerate carrier migration and work synergistically with the vertical N+ layer 16 to increase the current density. Under the gate voltage, the strip-shaped P- layer 20 forms a vertical depletion region, which, together with the spherical P- layer 17 and the rectangular P- layer 18, constitutes a multi-layer electric field control network to suppress field distortion in the middle of the channel. When turned off, the strip-shaped P- layer 20 rapidly depletes the surrounding lightly doped N-layer 6, forming a three-dimensional blocking structure with the combined P-layer 15. The strip-shaped N+ layer 21 acts as a carrier extraction channel, guiding the remaining charge to both sides of the gate 5 and the strip-shaped P- layer 20. This, together with the vertical N+ layer 16, shortens the turn-off time and, in conjunction with the symmetrical P⁻ layer 7, enhances the reverse breakdown voltage stability.

[0064] According to another aspect of the present invention, an ultra-short channel MOSFET structure resistant to short channel effects and its manufacturing process are provided, comprising the following steps:

[0065] S1: Preparation of N-substrate layer 2: High-purity single-crystal silicon material is selected as N-substrate layer 2, and its crystal orientation is as follows: <100> The resistivity is controlled within the range of 1-10 Ω·cm. Surface cleaning is performed as follows: First, ultrasonic cleaning with acetone solution for 10-15 minutes removes organic contaminants. Then, ultrasonic cleaning with anhydrous ethanol for 5-8 minutes removes residual acetone. Next, the RCA cleaning method is used: first, cleaning with SC1 solution (NH4OH:H2O2:H2O=1:1:5) at 75-80℃ for 10 minutes removes particulate impurities and some metal ions; then, cleaning with SC2 solution (HCl:H2O2:H2O=1:1:6) at 75-80℃ for 10 minutes further removes metal ions. Finally, rinsing with deionized water multiple times until the surface resistivity reaches above 10^16 Ω, and then drying with nitrogen gas.

[0066] S2: Preparation of N-drift layer 3

[0067] An N-drift layer 3 was grown on an N-substrate layer 2 using chemical vapor deposition (CVD). The reaction gases were silane (SiH4) and phosphine (PH3). The flow rate of SiH4 was controlled at 50-100 sccm, and the flow rate of PH3 was adjusted according to the required doping concentration, achieving a doping concentration of 10^15-10^16 cm^-3 for the N-drift layer 3. The growth temperature was set at 1050-1150℃, and the growth pressure was controlled at 100-300 mbar. The growth time was calculated based on the required thickness, typically 2-5 μm. During the growth process, the thickness and uniformity of the epitaxial layer were monitored in real time to ensure that the thickness deviation did not exceed ±5% and the surface roughness Ra ≤ 0.5 nm.

[0068] S3: Formation of laterally symmetrical P-layer 7

[0069] Photolithography: Photoresist is coated on the surface of the N-drift layer 3. Ultraviolet light is used for exposure at a wavelength of 365nm for 10-20 seconds. The formation area of ​​the side-symmetric P-layer 7 is defined by a mask. Then, the unexposed photoresist is removed by developing with a developer to obtain the desired pattern. Ion implantation: Boron ions (B+) are selected as implantation ions. The implantation energy is set to 50-100keV and the implantation dose is 10^13-10^14cm^-2 to ensure the formation of a trapezoidal side-symmetric P-layer 7 with the bottom end in contact with the N-substrate layer 2. Annealing: Rapid thermal annealing (RTA) is performed under a nitrogen protective atmosphere at a temperature of 900-950℃ for 10-20 seconds to activate the implanted boron ions, achieving an activation rate of over 90%, while repairing lattice damage.

[0070] S4: Forming a lightly doped N-layer 6

[0071] Photolithography: Photoresist is recoated onto the surface of the N drift layer 3. The region of the lightly doped N layer 6 is defined by a mask. The exposure and development parameters are the same as those of S3. Ion implantation: Phosphorus ions (P+) are selected as implantation ions. The implantation energy is 30-60 keV and the implantation dose is 10^12-10^13 cm^-2 to form the lightly doped N layer 6. Annealing: Furnace tube annealing is performed at a temperature of 800-850℃ for 30-60 minutes in a nitrogen atmosphere to allow impurities to diffuse fully and form a uniform lightly doped N layer 6.

[0072] S5: Forming a laterally symmetric N+ layer 11 if necessary

[0073] Photolithography: Photoresist is coated on the surface of the lightly doped N layer 6. The position of the side-symmetric N+ layer 11 is defined by a mask. The exposure and development parameters are the same as S3. Ion implantation: Arsenic ions As+ are selected as implantation ions. The implantation energy is 80-120keV and the implantation dose is 10^15-10^16cm^-2 to form an arc-shaped side-symmetric N+ layer 11, ensuring that its bottom end is in contact with the N substrate layer 2. Annealing: RTA treatment is performed. The temperature is set to 1000-1050℃ and held for 5-10 seconds to activate the implanted arsenic ions and increase the carrier concentration.

[0074] S6: Create the top P-layer 12 when needed.

[0075] Photolithography: Photoresist is coated on the surface of the lightly doped N-layer 6 to define the region of the top P-layer 12. The exposure and development parameters are the same as S3. Ion implantation: Boron ions B+ are implanted at an implantation energy of 20-40 keV and an implantation dose of 5×10^12-5×10^13 cm^-2 to make the top of the top P-layer 12 contact the gate 5 subsequently formed. Annealing: Furnace tube annealing is used at a temperature of 750-800℃ for 20-30 minutes in a nitrogen atmosphere to activate impurities.

[0076] S7: Form the bottom N+ layer 13. Photolithography process: Coat the surface of the lightly doped N layer 6 with photoresist to define the position of the bottom N+ layer 13. Exposure and development parameters are the same as S3. Ion implantation: Implant arsenic ions As+ at an implantation energy of 100-150keV and an implantation dose of 10^15-10^16cm^-2 to make it contact the N substrate layer 2. Annealing treatment: RTA treatment at a temperature of 1000-1050℃ for 5-10 seconds to activate impurities.

[0077] S8: Form a combination of N+ layers 14. If...

[0078] Photolithography: Photoresist is coated on the surface of the lightly doped N layer 6 to define the region of the combined N+ layer 14. The exposure and development parameters are the same as S3. Ion implantation: Phosphorus ions P+ are implanted at an implantation energy of 50-80 keV and an implantation dose of 10^15-10^16 cm^-2 to ensure that its tip contacts the gate 5. Annealing: RTA treatment is performed at a temperature of 950-1000℃ for 8-15 seconds to activate impurities.

[0079] S9: Forming the combined P-layer 15. Photolithography: Coating photoresist on both sides of the combined N+ layer 14 to define the position of the combined P-layer 15. Exposure and development parameters are the same as in S3. Ion implantation: Implanting boron ions B+ at an implantation energy of 30-50 keV and an implantation dose of 5×10^12-5×10^13 cm^-2, so that the top of the combined P-layer 15 contacts the gate 5. Annealing: Annealing in a furnace tube at a temperature of 800-850℃ for 20-30 minutes in a nitrogen atmosphere.

[0080] S10: Fabrication of vertical N+ layer 16 and spherical P- layer 17. When needed, form vertical N+ layer 16: After photolithography to define the region, implant arsenic ions As+ at an implantation energy of 120-180keV and an implantation dose of 10^15-10^16cm^-2, and RTA treatment at 1000-1050℃ for 5-10 seconds to form spherical P- layer 17: Photolithography to define the region at the top of vertical N+ layer 16, implant boron ions B+ at an implantation energy of 10-30keV and an implantation dose of 5×10^12-5×10^13cm^-2, and furnace annealing at 750-800℃ for 20-30 minutes.

[0081] S11: Fabricate a rectangular P-layer 18 and a semi-circular N+ layer 19 to form the rectangular P-layer 18: After photolithography to define the region, implant boron ions (B+) at an implantation energy of 30-50 keV and an implantation dose of 5 × 10^12-5 × 10^13 cm^-2, ensuring that its tip contacts the gate 5. Anneal in a furnace tube at 800-850℃ for 20-30 minutes to form the semi-circular N+ layer 19: Photolithography to define the region on both sides of the rectangular P-layer 18, implant arsenic ions (As+) at an implantation energy of 80-120 keV and an implantation dose of 10^15-10^16 cm^-2, ensuring that its tip contacts the gate 5. Perform RTA treatment at 1000-1050℃ for 5-10 seconds.

[0082] S12: Fabricate a strip-shaped P-layer 20 and a strip-shaped N+ layer 21. Forming the strip-shaped P-layer 20: After photolithography to define the region, implant boron ions (B+) at an implantation energy of 30-50 keV and an implantation dose of 5 × 10^12-5 × 10^13 cm^-2, so that its top end contacts the gate 5. Anneal in furnace tube at 800-850℃ for 20-30 minutes to form the strip-shaped N+ layer 21: Photolithography to define the region on both sides of the strip-shaped P-layer 20, implant phosphorus ions (P+) at an implantation energy of 50-80 keV and an implantation dose of 10^15-10^16 cm^-2, so that the top end of the strip-shaped N+ layer 21 contacts the gate 5, and the end away from the gate 5 contacts both sides of the strip-shaped P-layer 20. Perform RTA treatment at 950-1000℃ for 8-15 seconds.

[0083] S13: Fabrication of P+ layer 8, N-well layer 9, and P-well layer 10. Photolithography: Define the regions of P+ layer 8, N-well layer 9, and P-well layer 10 respectively. Exposure and development parameters are the same as in S3. Ion implantation: Boron ions (B+) are implanted into P+ layer 8 at an energy of 50-100 keV and a dose of 10^15-10^16 cm^-2; phosphorus ions (P+) are implanted into N-well layer 9 at an energy of 80-120 keV and a dose of 10^14-10^15 cm^-2; boron ions (B+) are implanted into P-well layer 10 at an energy of 50-80 keV and a dose of 10^14-10^15 cm^-2. Annealing: Perform RTA or furnace tube annealing respectively. Adjust parameters according to the requirements of each layer to ensure impurity activation and lattice repair.

[0084] S14: Fabrication of Gate 5, Photolithography and Etching: A layer of gate material, polysilicon or metal, is deposited on the substrate surface. Polysilicon is deposited using CVD technology with a thickness of 200-500 nm; aluminum or copper is selected for metal deposition using sputtering technology with a thickness of 300-600 nm. Then, photoresist is coated to define the gate pattern. After exposure and development, dry etching, such as reactive ion etching, is used to remove excess material to form gate 5. Contact treatment: Ensure good contact between gate 5 and related layers such as the top P-layer 12 and the combined N+ layer 14, with a contact resistance ≤10^-6 Ω・cm^2.

[0085] S15: Fabrication of Drain 1 and Source 4. Photolithography definition: Coat photoresist at both ends of the structure to define the regions of Drain 1 and Source 4. Exposure and development parameters are the same as in S3. High-concentration impurity implantation: Arsenic ions As+ are implanted into both Drain 1 and Source 4 at an energy of 100-150 keV and a dose of 10^15-10^16 cm^-2 to form heavily doped regions. Metallization process: Deposit aluminum or copper metal with a thickness of 500-1000 nm using sputtering or evaporation techniques, followed by photolithography and etching to form the metal electrodes of the drain and source, ensuring good ohmic contact with a contact resistance ≤10^-6 Ω・cm^2.

[0086] S16: Final processing steps, annealing: High-temperature annealing is performed in a nitrogen and hydrogen mixed atmosphere with a volume ratio of 9:1 at 400-500℃ for 30-60 minutes to optimize the electrical performance of the entire structure and reduce contact resistance and series resistance. Surface passivation: A layer of silicon dioxide (SiO2) or silicon nitride (Si3N4) with a thickness of 500-1000nm is deposited using plasma-enhanced chemical vapor deposition (PECVD) technology to protect the device surface and prevent contamination and oxidation. Post-processing: Dicing, testing, and other processes are performed to complete the fabrication of an ultra-short channel MOSFET structure resistant to short channel effects.

[0087] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. An ultra-short channel MOSFET structure resistant to short channel effect, comprising a plurality of parallel MOS cells, each MOS cell comprising a drain (1), a semiconductor epitaxial layer, a source (4), and a gate (5); the semiconductor epitaxial layer comprising an N-substrate layer (2), an N-drift layer (3), a P+ layer (8), an N-well layer (9), and a P-well layer (10), characterized in that: A lightly doped N layer (6) is provided in the middle of the N drift layer (3) of a single MOS cell; Inside a single MOS cell, on the left and right sides of the N drift layer (3), there are side-symmetric P-layers (7). The side-symmetric P-layers (7) have a trapezoidal outline. The bottom end of the side-symmetric P-layers (7) is in contact with the N substrate layer (2). Inside the lightly doped N layer (6), side-symmetric N+ layers (11) are formed on both sides by ion implantation. The side-symmetric N+ layers (11) are arc-shaped. The bottom end of the side-symmetric N+ layers (11) is in contact with the N substrate layer (2). (6) has a top P-layer (12) formed on both sides of the interior by ion implantation. The top of the top P-layer (12) is in contact with the gate (5). The bottom N+ layer (13) is formed on both sides of the lightly doped N layer (6) by ion implantation. The bottom N+ layer (13) is in contact with the N substrate layer (2). The combined N+ layer (14) is formed in the middle region of the lightly doped N layer (6) by ion implantation. The top of the combined N+ layer (14) is in contact with the gate (5).

2. The ultra-short channel MOSFET structure resisting short channel effect according to claim 1, characterized in that: The combined N+ layer (14) is symmetrically formed with a combined P- layer (15) by ion implantation on both sides, and the top of the combined P- layer (15) is in contact with the gate (5).

3. The ultra-short channel MOSFET structure resisting short channel effect according to claim 1, characterized in that: The middle region of the lightly doped N layer (6) is formed with a vertical N+ layer (16) by ion implantation, and the top of the vertical N+ layer (16) is formed with a spherical P- layer (17) by ion implantation.

4. The ultra-short channel MOSFET structure resisting short channel effect according to claim 1, characterized in that: A rectangular P-layer (18) is formed in the middle region of the lightly doped N-layer (6) by ion implantation. A semi-circular N+ layer (19) is formed on both sides of the rectangular P-layer (18) by ion implantation. The top of the rectangular P-layer (18) is in contact with the gate (5), and the top of the semi-circular N+ layer (19) is in contact with the gate (5).

5. The ultra-short channel MOSFET structure resisting short channel effect according to claim 1, characterized in that: The middle region of the lightly doped N-layer (6) is formed with a strip P-layer (20) by ion implantation. Strip N+ layers (21) are formed on both sides of the strip P-layer (20) by ion implantation. The top of the strip P-layer (20) is in contact with the gate (5). The top of the strip N+ layer (21) is in contact with the gate (5). The ends of the two strip N+ layers (21) away from the gate (5) are in contact with the two sides of the strip P-layer (20).

6. A fabrication process for an ultra-short-channel MOSFET structure resistant to short-channel effects, characterized in that: An ultra-short channel MOSFET structure resistant to short channel effects, as described in any one of claims 1-4, comprises the following steps: S1: Prepare the N substrate layer (2) as the base substrate of the entire MOSFET structure, perform surface cleaning and pretreatment to remove impurities and natural oxide layer; S2: An N drift layer (3) is prepared on the N substrate layer (2) using epitaxial growth technology. The temperature, pressure and doping concentration of the epitaxial growth are controlled to ensure that the thickness and electrical properties of the N drift layer (3) meet the design requirements. S3: Define the formation region of the side-symmetric P-layer (7) by photolithography, and then use ion implantation technology to implant P-type impurities into the left and right sides of the N drift layer (3) to form a trapezoidal side-symmetric P-layer (7) and make its bottom end contact the N substrate layer (2). Then perform annealing to activate the implanted impurities and repair lattice damage. S4: In the middle of the N drift layer (3), the region of the lightly doped N layer (6) is determined by photolithography, and a low concentration of N-type impurities is implanted by ion implantation technology to form a lightly doped N layer (6), followed by annealing. S5: If it is necessary to form a side-symmetric N+ layer (11), its position is defined by photolithography. High-concentration N-type impurities are implanted on both sides of the interior of the lightly doped N-layer (6) using ion implantation technology to form an arc-shaped side-symmetric N+ layer (11), ensuring that its bottom end is in contact with the N substrate layer (2), and then annealing is performed. S6: For the bottom N+ layer (13), the position is defined by photolithography, and high concentration of N-type impurities are implanted into the middle two sides of the lightly doped N layer (6) to make it contact the N substrate layer (2), and then annealing is performed; S7: When it is necessary to fabricate a vertical N+ layer (16) and a spherical P- layer (17), first define the region of the vertical N+ layer (16) by photolithography, then implant high-concentration N-type impurities to form the vertical N+ layer (16), and then form the spherical P- layer (17) at its top by photolithography and ion implantation, and perform annealing treatment respectively. S8: P+ layer (8), N well layer (9) and P well layer (10) are prepared at the corresponding positions on the N drift layer (3). Each layer region is defined by photolithography and ion implantation and annealing are performed respectively. S9: The gate (5) is fabricated using photolithography and etching processes to ensure good contact between the gate (5) and related layers (such as the top P-layer (12), combined N+ layer (14), etc.). The material can be polysilicon or metal, etc. S10: Drain (1) and source (4) are fabricated at both ends of the structure respectively. The region is defined by photolithography, and high-concentration impurity implantation and metallization processes are performed to form a good ohmic contact. S11: Perform final annealing to optimize the electrical performance of the entire structure, followed by surface passivation and post-processing to complete the fabrication of an ultra-short channel MOSFET structure resistant to short channel effects.

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