Semiconductor device manufacturing method and semiconductor device

Abstract

The application discloses a semiconductor device manufacturing method and a semiconductor device. The method comprises the following steps: forming a stress offset layer and a denaturation treatment barrier layer on a pseudo-gate deposition layer to obtain a first semiconductor device; performing first chemical mechanical polishing on the first semiconductor device by taking the top surface of the top pseudo-gate platform of the pseudo-gate deposition layer as a chemical mechanical polishing stop layer to obtain a second semiconductor device; performing material denaturation treatment on the top pseudo-gate platform of the second semiconductor device to obtain a third semiconductor device; and performing second chemical mechanical polishing on the third semiconductor device by taking the top of the pseudo-gate deposition layer as a chemical mechanical polishing stop layer to obtain a fourth semiconductor device, wherein the height difference of the pseudo-gate deposition layer of the fourth semiconductor device is reduced compared with the first semiconductor device. By using the scheme provided in the application, the surface flatness of the pseudo-gate can be improved, the silicon nitride residue can be improved, the gate height loss can be reduced, and the performance of the semiconductor device can be improved.

Description

TECHNICAL FIELD

[0001] The present application generally relates to the technical field of semiconductor technology. More particularly, the present application relates to a semiconductor device manufacturing method and a semiconductor device. BACKGROUND

[0002] 28nm and below process nodes widely adopt high dielectric constant gate dielectric-metal gate process (HKMG process), and integrate high voltage (HV) / medium voltage (MV) / low voltage (LV) working zones according to requirements. In integrated circuit manufacturing, due to the fact that the shallow trench isolation oxide (STI oxide) and the active area (AA) are not at the same level, and the isolation oxide thicknesses in the high voltage / low voltage different regions are different, the above-mentioned various factors will cause the poly to form a multi-level height difference, and the poly grinding process is affected by the pattern density, thereby causing the silicon nitride thickness of the upper part of the poly after poly grinding to be inconsistent, which easily leads to the situation that the silicon nitride cannot be etched clean or the gate height is insufficient after over-etching in the subsequent process (DPRM, dummy poly remove), thereby affecting the device performance.

[0003] Therefore, it is urgent to provide a semiconductor device manufacturing method to improve the flatness of the poly surface, which is beneficial to improve the silicon nitride residue and reduce the gate height loss, and improve the performance of the semiconductor device. SUMMARY

[0004] In order to at least solve one or more technical problems as mentioned above, the present application provides a semiconductor device manufacturing method and a semiconductor device in multiple aspects. The semiconductor device manufacturing method can improve the flatness of the poly surface, which is beneficial to improve the silicon nitride residue and reduce the gate height loss, and improve the performance of the semiconductor device.

[0005] In a first aspect, the present application provides a semiconductor device manufacturing method, comprising: forming a stress offset layer and a denaturation treatment barrier layer on a poly deposition layer to obtain a first semiconductor device; the poly deposition layer has steps with different heights; performing first chemical mechanical polishing on the first semiconductor device with the top surface of the top poly platform of the poly deposition layer as a chemical mechanical polishing stop layer to obtain a second semiconductor device; performing material denaturation treatment on the top poly platform of the second semiconductor device to obtain a third semiconductor device; performing second chemical mechanical polishing on the third semiconductor device with the top of the poly deposition layer as a chemical mechanical polishing stop layer to obtain a fourth semiconductor device, wherein the height difference of the poly deposition layer of the fourth semiconductor device is reduced compared with the first semiconductor device.

[0006] In some embodiments, after obtaining the fourth semiconductor device, the method further comprises: cyclically performing the material modification treatment and the second chemical mechanical polishing until the height difference of the dummy gate deposition layer is less than a predetermined value.

[0007] In some embodiments, the number of cycles is determined based on the height difference and / or the number of steps of the dummy gate deposition layer of the first semiconductor device.

[0008] In some embodiments, the stress offset layer is an oxide layer, and the modification treatment blocking layer is a silicon nitride layer; wherein forming the stress offset layer and the modification treatment blocking layer on the dummy gate deposition layer comprises: sequentially depositing the oxide layer and the silicon nitride layer on the dummy gate deposition layer.

[0009] In some embodiments, the material modification treatment on the top dummy gate platform comprises: performing a furnace tube nitriding treatment on the top dummy gate platform, so that the top dummy gate platform is converted into silicon nitride.

[0010] In some embodiments, the stress offset layer is a silicon nitride layer, and the modification treatment blocking layer is an oxide layer; wherein forming the stress offset layer and the modification treatment blocking layer on the dummy gate deposition layer comprises: sequentially depositing the silicon nitride layer and the oxide layer on the dummy gate deposition layer.

[0011] In some embodiments, the material modification treatment on the top dummy gate platform comprises: performing a furnace tube oxidation treatment on the top dummy gate platform, so that the top dummy gate platform is converted into an oxide.

[0012] In some embodiments, the method further comprises: removing the stress offset layer and the modification treatment blocking layer remaining on the fourth semiconductor device.

[0013] In some embodiments, removing the stress offset layer and the modification treatment blocking layer remaining on the fourth semiconductor device comprises: performing any one of the following treatments on the stress offset layer and the modification treatment blocking layer remaining on the fourth semiconductor device: chemical mechanical polishing, dry etching, and wet etching.

[0014] In a second aspect, the present application provides a semiconductor device, comprising: being obtained based on the semiconductor device manufacturing method according to any one of the first aspect.

[0015] The technical scheme provided by the present application can have the following unexpected beneficial effects:

[0016] The semiconductor device manufacturing method and the semiconductor device provided by the application can form a stress offset layer and a denaturation treatment blocking layer on the pseudo gate deposition layer, obtain a first semiconductor device, and then perform first chemical mechanical polishing on the first semiconductor device by taking the top pseudo gate platform of the pseudo gate deposition layer as a chemical mechanical polishing stop layer, so that the top pseudo gate platform is exposed and the preset of the stress offset layer on the sidewall of the top pseudo gate platform is completed, thereby forming a second semiconductor device.

[0017] Further, the top pseudo gate platform of the second semiconductor device can be subjected to material denaturation treatment, so as to realize material denaturation of the top pseudo gate platform, offset the stress generated when the top pseudo gate platform is subjected to material denaturation by the stress offset layer preset on the sidewall of the top pseudo gate platform, and prevent material denaturation of positions other than the top pseudo gate platform in the second semiconductor device by the denaturation treatment blocking layer, thereby obtaining a third semiconductor device. Then, second chemical mechanical polishing is performed on the third semiconductor device by taking the pseudo gate deposition layer as a chemical mechanical polishing stop layer, so that the top pseudo gate platform subjected to material denaturation treatment can be ground off, the height difference of the pseudo gate deposition layer is reduced, the planarization of the pseudo gate deposition layer is realized, and a fourth semiconductor device is obtained. Further optionally, the deposition stress offset layer and the denaturation treatment blocking layer remaining on the fourth semiconductor device are removed to avoid negative impact of the remaining stress offset layer and the denaturation treatment blocking layer on the performance of the semiconductor device.

[0018] In general, the scheme provided by the embodiments of the application can improve the flatness of the pseudo gate surface, improve the silicon nitride residue and reduce the loss of the gate height, and improve the performance of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other objects, features and advantages of the exemplary embodiments of the present application will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram showing the height difference of the pseudo gate of the polycrystalline silicon in the current process is shown;

[0021] Figure 2 A schematic diagram showing the inconsistent SiN retention thickness on the upper part of the pseudo gate after the polycrystalline silicon is ground in the current process is shown;

[0022] Figure 3 A schematic diagram showing the insufficient gate height caused by over-etching of SiN in the current process is shown;

[0023] Figure 4 A schematic diagram showing the incomplete etching of SiN in the current process is shown.

[0024] Figure 5 An exemplary flow chart of a semiconductor device fabrication method according to some embodiments of the present application is shown;

[0025] Figure 6 An exemplary flow chart of a semiconductor device fabrication method according to some embodiments of the present application is shown;

[0026] Figure 7 An exemplary structure of a semiconductor device to be processed in a semiconductor device fabrication method according to some embodiments of the present application is shown;

[0027] Figure 8 An exemplary structure of a first semiconductor device obtained in a semiconductor device fabrication method according to some embodiments of the present application is shown;

[0028] Figure 9 An exemplary structure of a second semiconductor device obtained in a semiconductor device fabrication method according to some embodiments of the present application is shown;

[0029] Figure 10 An exemplary structure of a third semiconductor device obtained in a semiconductor device fabrication method according to some embodiments of the present application is shown;

[0030] Figure 11 An exemplary structure of a fourth semiconductor device obtained in a semiconductor device fabrication method according to some embodiments of the present application is shown;

[0031] Figure 12 An exemplary structure of a semiconductor device after a second material modification process is shown;

[0032] Figure 13 An exemplary structure of a semiconductor device after a second chemical mechanical polishing process is shown;

[0033] Figure 14 An exemplary kinetic curve of furnace tube ammonia nitridation in a semiconductor device fabrication method according to some embodiments of the present application is shown;

[0034] Figure 15 An exemplary kinetic curve of furnace tube dry oxidation in a semiconductor device fabrication method according to some embodiments of the present application is shown.

[0035] Wherein, 1 represents silicon nitride, 2 represents dummy gate, 3 represents high dielectric material, 4 represents isolation oxide, 5 represents AA region, 6 represents silicon substrate, 7 represents shallow trench isolation oxide, 8 represents gate, 9 represents residual dummy gate, 10 represents dummy gate deposition layer, 11 represents modification process barrier layer, 12 represents stress compensation layer, 13 represents CMP stop layer, 14 represents top dummy gate platform. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments of the present application. For the purpose of simplicity and clarity, the reference signs can be repeated in the drawings to indicate corresponding or similar elements, if considered appropriate. In addition, many specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, one skilled in the relevant art will understand that the embodiments described herein can be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the embodiments described herein. Also, this description is not to be taken as limiting the scope of the embodiments described herein. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort, under the premise that no creative work is made, are within the scope of protection of the present application.

[0037] It should be understood that the possible terms "first" or "second" and the like in the claims, the specification and the drawings of the present application are used to distinguish different objects, rather than to describe a particular order. The terms "comprise" and "include" used in the specification and claims of the present application indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or sets thereof.

[0038] It should also be understood that the terms used in the specification of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. As used in the specification and claims of the present application, unless otherwise clear from the context, the singular forms "a", "an" and "the" are intended to include the plural forms. It should be further understood that the term "and / or" used in the specification and claims of the present application means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0039] As used in the specification and claims, the term "if" can be interpreted as "when" or "once" or "in response to a determination" or "in response to detecting" depending on the context. Similarly, the phrases "if it is determined" or "if [a described condition or event] is detected" can be interpreted to mean "once it is determined" or "in response to the determination" or "once [the described condition or event] is detected" or "in response to the detection [of the described condition or event]", depending on the context.

[0040] As mentioned in the background, in integrated circuit manufacturing, due to the fact that the shallow trench isolation oxide (STI Oxide) and the AA region are not at the same level, and the isolation oxide thicknesses in HV / LV different regions are different, the pseudo gate (Poly) forms a multi-level height difference. Moreover, the polysilicon grinding process is affected by the pattern density, and the above various factors will cause the polysilicon grinding to have inconsistent silicon nitride (SiN) remaining thickness on the upper part of the pseudo gate, which will easily lead to the problem that the silicon nitride cannot be etched cleanly or the problem of insufficient gate height after over-etching in the subsequent process, thereby affecting the device performance.

[0041] Figure 1 A schematic diagram showing the height difference of the pseudo gate of the polysilicon in the current process is shown. As shown in Figure 1 , the STI Oxide and the AA region are not at the same level, so the pseudo gate Poly and the silicon nitride SiN above it have a multi-level height difference. Figure 2 A schematic diagram showing the inconsistent SiN remaining thickness on the upper part of the pseudo gate after the pseudo gate is formed in the current process and the polysilicon is ground is shown. It can be understood that the pseudo gate with a lower height leaves thicker silicon nitride (shown by the dashed line in the figure), and the pseudo gate with a higher height leaves thinner silicon nitride. The figure shows the difference in the residual thickness of the SiN on the upper part of the different pseudo gates, which is more than 80 Å (Angstroms, 1 Angstrom is equal to 0.1 nanometer). Figure 3 A schematic diagram showing the insufficient gate height after over-etching of the SiN in the current process, for example, the gate height on the AA region has a certain loss. Figure 4 A schematic diagram showing the case that the SiN is not etched cleanly in the current process, for example, on the STI Oxide region, the pseudo gate is left due to the fact that the SiN is not etched cleanly.

[0042] Therefore, it is urgent to provide a semiconductor device manufacturing method to improve the flatness of the pseudo gate surface, which is beneficial to improve the silicon nitride remaining condition and reduce the gate height loss, and improve the performance of the semiconductor device.

[0043] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0044] Figure 5 An exemplary flowchart 100 of a semiconductor device manufacturing method according to some embodiments of the present application is shown, Figure 7 A schematic diagram showing the structure of a semiconductor device to be processed in a semiconductor device manufacturing method according to an embodiment of the present application is shown, Figure 8 A schematic diagram showing the structure of a first semiconductor device obtained in a semiconductor device manufacturing method according to an embodiment of the present application is shown, Figure 9 A schematic diagram showing the structure of a second semiconductor device obtained in a semiconductor device manufacturing method according to an embodiment of the present application is shown, Figure 10A structure diagram of a third semiconductor device obtained in the semiconductor device manufacturing method of the embodiment of the present application is shown. The semiconductor device manufacturing method of the embodiment of the present application will be described below in conjunction with Figure 5 and Figures 7 to 10 .

[0045] In the embodiment of the present application, as shown in Figure 7 , due to the fact that the STI Oxide and the AA region are not in the same horizontal plane, the isolation oxide thicknesses in the HV / LV different regions are different, and so on, a pseudo gate step with height difference appears on the pseudo gate deposition layer of the untreated semiconductor device, forming at least one pseudo gate platform / step, for example, two steps are shown in the figure.

[0046] In step S101, a stress offset layer and a denaturation treatment blocking layer are formed on the pseudo gate deposition layer, obtaining a first semiconductor device. In the embodiment of the present application, the stress offset layer mentioned above refers to a deposition layer for offsetting the stress generated in the subsequent denaturation treatment, and the denaturation treatment blocking layer refers to a deposition layer for preventing material denaturation in the subsequent denaturation treatment. As shown in Figure 8 , the stress offset layer and the denaturation treatment blocking layer can be sequentially deposited on the pseudo gate deposition layer until the surface of the pseudo gate deposition layer is completely covered, so as to obtain the first semiconductor device.

[0047] In step S102, the first semiconductor device is subjected to first chemical mechanical polishing with the top surface of the top pseudo gate platform of the pseudo gate deposition layer as the chemical mechanical polishing stop layer, obtaining a second semiconductor device. As shown in Figure 9 , the first semiconductor device is subjected to chemical mechanical polishing (CMP, Chemical-Mechanical Polishing) with the top surface of the top pseudo gate platform of the pseudo gate deposition layer as the chemical mechanical polishing stop layer (CMP Stop Layer), so as to expose the top pseudo gate platform, obtaining the second semiconductor device.

[0048] In step S103, the top pseudo gate platform of the second semiconductor device is subjected to material denaturation treatment, obtaining a third semiconductor device. In the embodiment of the present application, the aforementioned material denaturation treatment can refer to a treatment mode for changing the characteristics and chemical composition of the material, which may, for example, include but is not limited to nitridation treatment or oxidation treatment, such as furnace tube ammonia nitridation or furnace tube dry oxygen oxidation.

[0049] As shown in Figure 10As shown, after material modification, the material of the top dummy gate platform changes from polycrystalline silicon to silicon nitride or silicon oxide. The specific modified material depends on the modification process used. During the material modification process of the top dummy gate platform, a stress-reducing layer pre-installed on the sidewall of the top dummy gate platform is used to offset the stress generated during the material modification, preventing cracks in the dummy gate deposition layer caused by expansion stress. At the same time, a modification barrier layer is used to prevent material modification at locations other than the top dummy gate platform in the second semiconductor device.

[0050] In step S104, the third semiconductor device is subjected to a second chemical mechanical polishing using the pseudo-gate deposition layer as a chemical mechanical polishing stop layer to obtain the fourth semiconductor device.

[0051] like Figure 11 As shown, a second chemical mechanical polishing (CMP) is performed on the third semiconductor device using the top surface of the dummy gate deposition layer as a CMP stop layer to obtain a fourth semiconductor device. It can be seen from the figure that the height difference of the dummy gate deposition layer is reduced in the fourth semiconductor device compared to the first semiconductor device.

[0052] It is understandable that if there is only one pseudo-gate step with a height difference (this case is not shown in the figure), only one pseudo-gate platform is formed, and the height difference is small, then the pseudo-gate deposition layer can be used as a chemical mechanical polishing stop layer to perform chemical mechanical polishing on the third semiconductor device to achieve planarization of the pseudo-gate deposition layer.

[0053] The semiconductor device fabrication method and semiconductor device provided in this application obtain a first semiconductor device by forming a stress-relief layer and a modification treatment barrier layer on a dummy gate deposition layer. Then, a first chemical mechanical polishing (CMP) is performed on the first semiconductor device using the top dummy gate platform of the dummy gate deposition layer as a CMP stop layer. This allows the stress-relief layer to be pre-set on the sidewall of the top dummy gate platform while exposing it, thus forming a second semiconductor device. Further, embodiments of this application can perform a material modification treatment on the top dummy gate platform of the second semiconductor device, thereby modifying the material of the top dummy gate platform. The stress-relief layer pre-set on the sidewall of the top dummy gate platform counteracts the stress generated during the material modification, while the modification treatment barrier layer prevents material modification at locations other than the top dummy gate platform in the second semiconductor device, thus obtaining a third semiconductor device. Then, a second CMP is performed on the third semiconductor device using the dummy gate deposition layer as a CMP stop layer, thereby grinding away the top dummy gate platform that has undergone material modification, reducing the height difference of the dummy gate deposition layer, and achieving planarization of the dummy gate deposition layer, thus obtaining a fourth semiconductor device.

[0054] It is understandable that residual stress-relief layers and deformation-reducing barrier layers may remain on the fourth semiconductor device, requiring further processing to obtain a target semiconductor device with a flat and clean pseudo-gate deposition layer. Therefore, alternatively, the residual stress-relief layers and deformation-reducing barrier layers on the fourth semiconductor device can be removed to obtain the target semiconductor device, thereby avoiding any negative impact on the performance of the semiconductor device caused by the residual stress-relief layers and deformation-reducing barrier layers.

[0055] In summary, the solutions provided in this application can reduce the height difference of the dummy gate deposition layer, improve the surface smoothness of the dummy gate, improve the silicon nitride residue and reduce gate height loss, thereby improving the performance of semiconductor devices.

[0056] In some embodiments, there may be more than one pseudo-gate step with a height difference, for example... Figure 7 The semiconductor device shown has two dummy gate steps / steps on its dummy gate deposition layer, or the height difference between the dummy gate platforms is large, making it impossible to eliminate the steps in a single process due to limitations in the modification process. In this case, multiple processes can be performed to flatten the dummy gate deposition layer. The following will combine... Figure 6 To provide a detailed explanation, Figure 6 An exemplary flowchart 200 illustrating a semiconductor device fabrication method according to other embodiments of this application is shown below. Figure 6 The semiconductor device fabrication method illustrated in this application embodiment may include:

[0057] In step S201, a stress relief layer and a deformation treatment barrier layer are formed on the dummy gate deposition layer to obtain a first semiconductor device.

[0058] In step S202, the first semiconductor device is subjected to first chemical mechanical polishing using the top surface of the top pseudo-gate platform of the pseudo-gate deposition layer as a chemical mechanical polishing stop layer to obtain the second semiconductor device.

[0059] In step S203, the top pseudo-gate platform of the second semiconductor device is subjected to material modification treatment to obtain the third semiconductor device.

[0060] In step S204, the third semiconductor device is subjected to a second chemical mechanical polishing using the top pseudo-gate platform of the pseudo-gate deposition layer as a chemical mechanical polishing stop layer to obtain the fourth semiconductor device.

[0061] Steps S201~S204 are combined with the previous steps. Figure 5 and Figures 7 to 10 The steps S101 to S104 are described similarly and will not be repeated here.

[0062] It is understandable that if there are more than one pseudo-gate step with a height difference, after the material modification treatment of the current top pseudo-gate platform is completed, the next pseudo-gate platform will become the new top pseudo-gate platform. Therefore, after step S204, as... Figure 11 As shown, the top surface of the top pseudo-gate platform (shown in the dashed box, the previous second-highest pseudo-gate platform) of the pseudo-gate deposition layer is used as the chemical mechanical polishing (CMP) stop layer to perform CMP on the third semiconductor device, thereby exposing the top pseudo-gate platform to obtain the fourth semiconductor device. It can be seen from the figure that the pseudo-gate deposition layer still has a pseudo-gate step (shown in the dashed box), and there are residual stress-reducing layers and deformation-reducing barrier layers at the bottom of the step.

[0063] Alternatively, if the height difference of the pseudo-gate platform is large, but the material modification process is significantly self-limiting due to factors such as temperature, limiting the height that can be improved in each treatment (e.g., furnace tube nitriding can improve the height difference by approximately 50 Å per treatment), then after one material modification treatment of the current top pseudo-gate platform, the current top pseudo-gate platform remains the same, only with a reduced height difference. For example, if the original pseudo-gate platform's height difference is greater than 50 Å, such as 140 Å, a single material modification treatment can transform a 50 Å thick pseudo-gate deposition layer into, for example, silicon nitride. In this case, the height difference of the pseudo-gate platform is reduced to 90 Å.

[0064] In response to the two scenarios described above, step S206 can determine whether the height difference of the dummy gate deposition layer on the fourth semiconductor device is less than a predetermined value. If it exceeds the predetermined value, the process can return to the previous steps and repeat the material modification treatment (step S203) and the second chemical mechanical polishing (step S204) until the height difference of the dummy gate deposition layer is less than the predetermined value. If it is less than the predetermined value, the loop can be terminated. In this embodiment, the number of loops can be determined based on the height difference of the dummy gate deposition layer of the first semiconductor device and / or the number of steps. For example, if the height of each step does not exceed the maximum thickness of a single material modification treatment, the number of loops is equal to the number of steps. Furthermore, the predetermined value can be set between 1 Å and 5 Å, depending on the specific application.

[0065] Figure 12A schematic diagram of a semiconductor device after a second material modification process is shown. As shown, the material of the top dummy gate platform of this semiconductor device has been modified from polysilicon to silicon nitride or silicon oxide, depending on the modification process used. Similarly, during the material modification process of the top dummy gate platform, a stress-reducing layer pre-installed on the sidewall of the top dummy gate platform is used to offset the stress generated during the material modification, preventing cracks in the dummy gate deposition layer caused by expansion stress. Simultaneously, a modification barrier layer is used to prevent material modification at locations other than the top dummy gate platform in the semiconductor device.

[0066] Figure 13 The image shows a semiconductor device that has undergone a second chemical mechanical polishing (CMP) process. As shown, the top surface of the dummy gate deposition layer serves as the CMP stop layer. Figure 12 The semiconductor device shown undergoes a second chemical mechanical polishing process to remove the top dummy gate platform that has undergone material modification. In this embodiment, the height difference of the dummy gate deposition layer is essentially eliminated, achieving planarization of the dummy gate deposition layer.

[0067] Similarly, if a deposition stress relief layer and a modification barrier layer remain on the semiconductor device after the material modification-CMP treatment cycle, these layers can be removed in step S205 to obtain the target semiconductor device. In this embodiment, the residual deposition stress relief layer and modification barrier layer on the semiconductor device can be removed by chemical mechanical polishing, dry etching, or wet etching to fully remove them.

[0068] In the above embodiments, by repeatedly performing material modification and CMP treatment, various step conditions that may occur on the pseudo-gate deposition layer can be flexibly adapted, such as large height differences of pseudo-gate steps and a large number of pseudo-gate steps, thereby obtaining a flat pseudo-gate deposition layer, which facilitates subsequent further processing.

[0069] In some embodiments, the materials of the stress-relief layer and the modification process barrier layer can be further designed, and corresponding matching processes will be used to perform material modification processing on the top pseudo-gate platform. It is understood that the stress-relief layer is used to counteract the stress generated during the material modification process. Therefore, a material with a stress direction opposite to that generated during the material modification process can be used as the stress-relief layer to counteract the stress generated during the material modification process. For example, the stress range of the oxide layer can be -60 MPa to -200 MPa, while the stress range of the silicon nitride layer can be 50 MPa to 500 MPa. Therefore, the opposite stress characteristics of the two can be used to set the stress-relief layer and the corresponding material modification process. The modification process barrier layer can be selected to be consistent with the modified material, thereby preventing the material underneath from being modified, but the embodiments of this application are not limited to this.

[0070] In some embodiments, the stress-relief layer can be an oxide layer, which may be composed of silicon dioxide, and the modification treatment barrier layer can be a silicon nitride layer, thereby allowing the oxide layer and silicon nitride layer to be deposited sequentially on the dummy gate deposition layer to form a first semiconductor device. In these embodiments, the first semiconductor device can be further subjected to first chemical-mechanical polishing (CMP) using the top dummy gate platform of the dummy gate deposition layer as a CMP stop layer, thereby exposing the top dummy gate platform to obtain a second semiconductor device. Furthermore, the top dummy gate platform can be subjected to furnace tube ammonia nitriding treatment, causing the top dummy gate platform to nitride into silicon nitride, thereby obtaining a third semiconductor device.

[0071] Figure 14 The kinetic curves of ammonia nitriding in the furnace tube during the semiconductor device fabrication method of this application are shown. Figure 14 As shown, appropriate temperature and time can be selected based on the kinetic curve of ammonia nitriding in the furnace tube to obtain the corresponding modified thickness. For example, it can be seen from the figure that the modified thickness increases with increasing temperature and longer reaction time. However, at lower temperatures, the effect of increasing reaction time on thickness is relatively small, so the reaction time can be shortened by adjusting the temperature. For example, the temperature of ammonia nitriding treatment in the furnace tube can be set between 700℃ and 1200℃, and the treatment time can be between 0.5 and 1.5 hours, as shown by the dashed box in the figure. In these embodiments, the stress range that the oxide layer can offset can be between -60 MPa and -200 MPa.

[0072] In other embodiments, the stress-relief layer can be a silicon nitride layer, and the deformation-reducing barrier layer can be an oxide layer, allowing the silicon nitride layer and the oxide layer to be deposited sequentially on the dummy gate deposition layer to form a first semiconductor device. In these embodiments, the first semiconductor device can be further subjected to first chemical-mechanical polishing (CMP) using the top dummy gate platform of the dummy gate deposition layer as a CMP stop layer, thereby exposing the top dummy gate platform to obtain a second semiconductor device. Subsequently, the top dummy gate platform is subjected to furnace tube dry oxidation treatment, transforming the top dummy gate platform into an oxide layer, thereby obtaining a third semiconductor device.

[0073] Figure 15 The kinetic curve of dry oxygen oxidation in the furnace tube during the semiconductor device fabrication method of this application is shown. For example... Figure 15 As shown, appropriate temperature and time can be selected based on the kinetic curve of dry oxidation in the furnace tube to obtain the corresponding modified thickness. For example, it can be seen from the figure that the modified thickness increases with increasing temperature and reaction time. In particular, the modified thickness increases sharply with increasing temperature and reaction time. To better control the modified thickness, a range with slightly slower thickness growth can be selected. For example, the temperature of the dry oxidation treatment in the furnace tube can be set between 750°C and 900°C, and the treatment time can be between 35 min and 85 min, as shown by the dashed box in the figure. In these embodiments, the stress range that the silicon nitride layer can offset can be between 50 MPa and 500 MPa.

[0074] pass Figure 14 and Figure 15 The comparison reveals significant differences in the kinetic curves of the two processes. Specifically, the modification thickness of furnace tube ammonia nitriding is generally between 25 Å and 55 Å, with a slower modification rate; while the modification thickness of furnace tube dry oxygen oxidation is generally between 5 nm and 15 nm, with a faster modification rate. This demonstrates that furnace tube dry oxygen oxidation offers greater modification thickness and deeper oxidation depth, enabling the achievement of pseudo-gate planarization with greater height differences when combined with chemical mechanical polishing. Furnace tube ammonia nitriding, on the other hand, is suitable for situations with smaller pseudo-gate height differences and allows for more precise control of the modification thickness.

[0075] This application also provides a semiconductor device fabricated using a semiconductor device fabrication method based on an embodiment of this application. Figure 13A schematic diagram of the target semiconductor device obtained by the semiconductor device fabrication method of this application is shown. As shown in the figure, the STI oxide and AA region of this semiconductor device are not on the same horizontal plane. In addition, due to the different thicknesses of the isolation oxides in different regions of HV / LV, the lower surface of the dummy gate deposition layer of the semiconductor device presents a step with a height difference. However, after processing by the method of this application embodiment, the upper surface of the dummy gate deposition layer is flat, that is, the dummy gate deposition layer in the semiconductor device is planarized.

[0076] While numerous embodiments of this application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will arise for those skilled in the art without departing from the spirit and intent of this application. It should be understood that various alternatives to the embodiments of this application described herein may be employed in the practice of this application. The appended claims are intended to define the scope of protection of this application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A stress-relief layer and a deformation-reducing barrier layer are formed on the pseudo-gate deposition layer to obtain a first semiconductor device; The dummy gate deposition layer has different heights in different regions, forming at least one dummy gate step; the stress relief layer of the first semiconductor device completely covers the surface of the dummy gate deposition layer; The first semiconductor device is subjected to first chemical mechanical polishing with the top surface of the highest dummy gate step of the dummy gate deposition layer as a chemical mechanical polishing stop layer to obtain a second semiconductor device; the stress relief layer of the second semiconductor device covers the side surface of the highest dummy gate step; The highest pseudo-gate step of the second semiconductor device is subjected to material modification treatment to obtain the third semiconductor device; The third semiconductor device is subjected to a second chemical mechanical polishing process with the top of the dummy gate deposition layer as the chemical mechanical polishing stop layer to obtain a fourth semiconductor device. The fourth semiconductor device has a reduced height difference in the dummy gate deposition layer compared to the first semiconductor device.

2. The semiconductor device fabrication method according to claim 1, characterized in that, After obtaining the fourth semiconductor device, the method further includes: The material modification treatment and the second chemical mechanical polishing are performed cyclically until the height difference of the pseudo-gate deposition layer is less than a predetermined value.

3. The semiconductor device fabrication method according to claim 2, characterized in that, The number of cycles is determined based on the height difference and / or step number of the pseudo-gate deposition layer of the first semiconductor device.

4. The method for fabricating a semiconductor device according to any one of claims 1-3, characterized in that, The stress-reducing layer is an oxide layer, and the modification treatment barrier layer is a silicon nitride layer; wherein, forming the stress-reducing layer and the modification treatment barrier layer on the dummy gate deposition layer includes: The oxide layer and the silicon nitride layer are sequentially deposited on the pseudo-gate deposition layer.

5. The semiconductor device fabrication method according to claim 4, characterized in that, The material modification treatment of the highest dummy gate step of the second semiconductor device includes: The highest pseudo-gate step of the second semiconductor device is subjected to furnace tube nitriding treatment, so that the highest pseudo-gate step of the second semiconductor device is converted into silicon nitride.

6. The method for fabricating a semiconductor device according to any one of claims 1-3, characterized in that, The stress-reducing layer is a silicon nitride layer, and the modification treatment barrier layer is an oxide layer; wherein, forming the stress-reducing layer and the modification treatment barrier layer on the pseudo-gate deposition layer includes: The silicon nitride layer and the oxide layer are sequentially deposited on the pseudo-gate deposition layer.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The material modification treatment of the highest dummy gate step of the second semiconductor device includes: The highest dummy gate step of the second semiconductor device is subjected to furnace tube oxidation treatment, which transforms the highest dummy gate step of the second semiconductor device into oxide.

8. The method for fabricating a semiconductor device according to any one of claims 1-3, characterized in that, The method further includes: The residual stress relief layer and deformation treatment barrier layer on the fourth semiconductor device are removed.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The removal of the residual stress-relief layer and deformation-reducing barrier layer on the fourth semiconductor device includes: The residual stress-relief layer and deformation-reducing barrier layer on the fourth semiconductor device shall be subjected to any of the following treatments: Chemical mechanical polishing, dry etching, and wet etching.

10. A semiconductor device, characterized in that, The semiconductor device is fabricated according to any one of claims 1-9.

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