Display panel and manufacturing method thereof

Abstract

The invention provides a display panel and a manufacturing method thereof. The display panel comprises a substrate, a semiconductor layer, a passivation layer, an interlayer insulating layer, a gate insulating layer, a source electrode, a drain electrode, a first connecting piece and a second connecting piece. A first through hole and a second through hole are formed in the passivation layer, the interlayer insulating layer and the gate insulating layer, and the bottom surfaces of the first through hole and the second through hole are located between the upper surface and the lower surface of the semiconductor layer in the direction perpendicular to the substrate. And a third through hole and a fourth through hole are formed in the passivation layer. One part of the first connecting piece is arranged in the first through hole and the third through hole, the first connecting piece is electrically connected with the source electrode and the semiconductor layer, one part of the second connecting piece is arranged in the second through hole and the fourth through hole, and the second connecting piece is electrically connected with the drain electrode and the semiconductor layer. According to the invention, the connecting piece is in contact with the bottom surface and the side surface of the part, located in the semiconductor layer, of the first through hole and the second through hole at the same time, the contact area is increased, the contact impedance is reduced, and the reliability of electrical connection is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Art

[0002] Low-temperature polysilicon (LTPS) thin-film transistors (TFTs) are core components of display panels such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays. Their performance directly impacts the display quality and reliability of the display panel.

[0003] During the manufacturing process of low-temperature polysilicon thin-film transistors, through-holes (VHs) are formed in the passivation layer, interlayer insulating layer, and gate insulating layer to achieve electrical connections between the different film layers. These VHs include deep holes for connecting to the semiconductor layer and shallow holes for connecting to the source and drain electrodes. Connectors establish electrical connections to the corresponding film layers through these VHs, thus forming a complete circuit path.

[0004] However, existing display panels have technical defects in the process of forming through holes. When forming deep holes for connecting semiconductor layers, due to the limitations of the etching process, the deep holes often completely penetrate the semiconductor layer and even extend into the buffer layer below the semiconductor layer. Figure 1 This over-etching phenomenon reduces the contact area between the connector and the semiconductor layer, and degrades the contact quality.

[0005] Specifically, when the deep hole completely penetrates the semiconductor layer, the contact area between the connector and the semiconductor layer is small, resulting in high contact impedance and poor contact stability, which is prone to poor contact during subsequent processes or use. In addition, when etching extends to the buffer layer, additional interface impedance may be introduced, further deteriorating the reliability of the electrical connection.

[0006] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention

[0007] The purpose of the embodiments of the present application is to provide a display panel and a method for manufacturing the same, aiming to reduce the contact impedance between the connector and the semiconductor layer in the display panel and improve the reliability of the electrical connection.

[0008] An embodiment of the present application provides a display panel, which includes a substrate, a semiconductor layer, a passivation layer, an interlayer insulating layer, a gate insulating layer, a source electrode, a drain electrode, a first connector, and a second connector; wherein a first through hole and a second through hole are provided in the passivation layer, the interlayer insulating layer, and the gate insulating layer, and the first through hole and the second through hole both penetrate the passivation layer, the interlayer insulating layer, and the gate insulating layer, and in a direction perpendicular to the substrate, the bottom surfaces of the first through hole and the second through hole are both located between the upper surface and the lower surface of the semiconductor layer; a third through hole and a fourth through hole are provided in the passivation layer, and the third through hole and the fourth through hole both penetrate the passivation layer, the third through hole exposes at least a portion of the source electrode, and the fourth through hole exposes a portion of the drain electrode; a portion of the first connector is provided in the first through hole and the third through hole, and the first connector is electrically connected to the source electrode and the semiconductor layer, and a portion of the second connector is provided in the second through hole and the fourth through hole, and the second connector is electrically connected to the drain electrode and the semiconductor layer.

[0009] In the above display panel, the thickness of the portion of the semiconductor layer located below the bottom surfaces of the first through hole and the second through hole is greater than 0 and less than 0.5 times the thickness of the portion of the semiconductor layer located in the channel region.

[0010] In the above display panel, a thickness of a portion of the semiconductor layer located below the bottom surfaces of the first through hole and the second through hole is greater than 0 and less than 0.03 times the depth of the first through hole or the second through hole.

[0011] In the above display panel, a thickness of a portion of the semiconductor layer located below the bottom surfaces of the first through hole and the second through hole is 100 angstroms to 200 angstroms.

[0012] In the above display panel, the first connecting member contacts the bottom and side surfaces of the first through hole located in the semiconductor layer, and the second connecting member contacts the bottom and side surfaces of the second through hole located in the semiconductor layer.

[0013] An embodiment of the present application also provides a method for manufacturing a display panel, comprising the following steps: etching a passivation layer, an interlayer insulating layer and a gate insulating layer to form a first through hole, a second through hole, a third through hole and a fourth through hole, wherein the first through hole and the second through hole penetrate the passivation layer, the interlayer insulating layer and the gate insulating layer, and in a direction perpendicular to the substrate, the bottoms of the first through hole and the second through hole are both located between the upper surface and the lower surface of the semiconductor layer, and the third through hole and the fourth through hole penetrate the passivation layer; and arranging a first connector and a second connector in the first through hole, the second through hole, the third through hole and the fourth through hole, wherein the first connector is electrically connected to the source electrode and the semiconductor layer, and the second connector is electrically connected to the drain electrode and the semiconductor layer.

[0014] In the above manufacturing method, the step of etching the passivation layer, the interlayer insulating layer and the gate insulating layer to form the first through hole, the second through hole, the third through hole and the fourth through hole includes: etching the passivation layer, the interlayer insulating layer and the gate insulating layer using a mixed gas of pentafluoroethane, argon and hydrogen.

[0015] In the above manufacturing method, the thickness of the portion of the semiconductor layer located below the bottom surfaces of the first through hole and the second through hole is greater than 0 and less than 0.5 times the thickness of the portion of the semiconductor layer located in the channel region.

[0016] In the above manufacturing method, the thickness of the portion of the semiconductor layer located below the bottom surfaces of the first through hole and the second through hole is greater than 0 and less than 0.03 times the depth of the first through hole or the second through hole.

[0017] In the above manufacturing method, the thickness of the portion of the semiconductor layer located below the bottom surfaces of the first through hole and the second through hole is 100 angstroms to 200 angstroms.

[0018] The display panel provided in the embodiments of the present application adopts a unique through-hole formation method. By controlling the etching depth of the first through-hole and the second through-hole, the bottom surface thereof is located between the upper surface and the lower surface of the semiconductor layer, rather than completely penetrating the semiconductor layer, thereby achieving optimized contact between the connector and the semiconductor layer.

[0019] Specifically, the technical solution of the present application retains a certain thickness of semiconductor layer at the bottom of the first through hole and the second through hole, so that the first connector and the second connector can simultaneously contact the bottom and side surfaces of the first through hole and the second through hole located in the semiconductor layer. Compared with the method in the prior art where the connector only contacts the surface of the semiconductor layer, this contact method significantly increases the contact area. According to the resistance law, under the same material and contact conditions, the increase in contact area directly leads to a decrease in contact impedance, thereby reducing power loss during current transmission and improving the electrical performance and driving efficiency of the thin film transistor.

[0020] In addition, the first connector and the second connector are in contact with the bottom and side surfaces of the first through hole and the second through hole located in the semiconductor layer, which can make the electrical connection interface more stable. During the use of the display panel, temperature changes and mechanical stress are the main factors affecting the stability of the electrical connection. In the technical solution of the present application, the connector is in contact with both the upper surface and the side surface of the semiconductor layer, which is more stable than contacting only with the upper surface of the semiconductor layer, effectively improving the reliability of the electrical connection, reducing the probability of device failure due to poor contact, and thus extending the service life of the display panel.

[0021] The technical solution of the present application also simplifies the manufacturing process by forming through holes of different depths in the same etching process. The traditional process requires multiple etchings and precise alignment to form through holes of different depths, which is a complex process and has high costs. The present application adopts a specific etching gas ratio and improves the etching selectivity of the semiconductor layer by adding hydrogen, so that the silicon oxide insulating layer can be completely etched while the semiconductor layer is only partially etched, thereby realizing the formation of through holes of different depths in a single etching process. This process simplification not only reduces manufacturing costs, but also reduces the impact of process variation on product performance, thereby improving production efficiency and product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram illustrating the phenomenon of over-etching of the semiconductor layer in a conventional display panel.

[0023] Figure 2 is a schematic diagram of a display panel provided in an embodiment of the present application.

[0024] Figures 3 to 8 yes Figure 2 Schematic diagram of a method for manufacturing a display panel shown.

[0025] Figure 9 yes Figure 2 A scanning electron microscope image of a portion of the semiconductor layer of the display panel is shown. DETAILED DESCRIPTION

[0026] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0027] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0028] The embodiments of the present application may be combined with each other.

[0029] Embodiments of the present application provide a display panel and a method for manufacturing the same. The display panel and the method for manufacturing the same adopt an improved through-hole forming method, thereby effectively improving the contact performance between the connector and the semiconductor layer.

[0030] The display panel provided in the embodiments of the present application may be, for example, a liquid crystal display panel. The display panel includes a display area and a non-display area. The display area is provided with m×n pixels arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area. The display panel also includes a plurality of gate lines, a plurality of data lines and at least one gate drive circuit. The plurality of gate lines extend along a first direction and are arranged along a second direction, and the plurality of data lines extend along a second direction and are arranged along the first direction, the first direction being perpendicular to the second direction. The gate drive circuit is provided in the non-display area and is electrically connected to the plurality of gate lines.

[0031] The display panel includes a thin-film transistor array substrate, an opposing substrate, and a liquid crystal layer disposed between the two substrates. The opposing substrate includes a substrate, a black matrix disposed on the substrate, and a color filter layer disposed on the black matrix. The black matrix is ​​made of a light-shielding material and is used to prevent light leakage and improve display contrast. The color filter layer includes red, green, and blue filter units for filtering out light of corresponding colors to create a colorful display effect. The color filter layer can also be disposed on the thin-film transistor array substrate instead of the opposing substrate.

[0032] Each pixel includes a thin-film transistor and a pixel electrode. The thin-film transistor's gate is electrically connected to the gate line, its source is electrically connected to the data line, and its drain is electrically connected to the pixel electrode. When the gate line outputs a high-level scanning signal, the thin-film transistor turns on, and the data signal on the data line is transmitted to the pixel electrode through the thin-film transistor. When the gate line outputs a low-level scanning signal, the thin-film transistor turns off, and the pixel electrode maintains the voltage corresponding to the data signal.

[0033] The gate drive circuit includes n cascaded gate drive sub-circuits, each of which is electrically connected to a gate line. The gate drive sub-circuit is used to output multiple scanning signals to scan each row of pixels in the display area row by row.

[0034] like Figure 2As shown, in an embodiment of the present application, the display panel includes a substrate 201, a buffer layer 202, a semiconductor layer 203, a gate insulating layer 204, a gate 205, an interlayer insulating layer 206, a source 207, a drain 208, a pixel electrode 209, a passivation layer 210, a common electrode 213, a first connecting member 211 and a second connecting member 212.

[0035] The substrate 201 is made of glass. The buffer layer 202 is disposed on the substrate 201. The buffer layer 202 is made of silicon oxide or silicon nitride and has a thickness of 50 nanometers to 200 nanometers.

[0036] The semiconductor layer 203 is disposed on the buffer layer 202 and is made of low-temperature polycrystalline silicon. The formation process of the semiconductor layer 203 includes the deposition of amorphous silicon and subsequent laser annealing crystallization. After doping, the semiconductor layer 203 is formed into different functional regions, including a channel region, a lightly doped region, and a heavily doped region. The channel region is located in the center of the semiconductor layer 203 and forms the conductive channel of the thin-film transistor. This region remains intrinsically or lightly doped. The lightly doped regions are located on either side of the channel region and have a relatively low doping concentration of 10^17 to 10^18 atoms per cubic centimeter. The heavily doped regions are located outside the lightly doped regions and have a higher doping concentration of 10^19 to 10^21 atoms per cubic centimeter. They form good ohmic contacts with the source electrode 207 and the drain electrode 208. The total thickness of the semiconductor layer 203 is 30 to 100 nanometers.

[0037] The gate insulating layer 204 is disposed on the semiconductor layer 203 and the buffer layer 202. The gate insulating layer 204 electrically insulates the gate 205 from the semiconductor layer 203 while allowing the gate 205 to control the electric field of carriers in the semiconductor layer 203. The gate insulating layer 204 is made of silicon oxide and has a thickness of 80 to 150 nanometers.

[0038] The gate 205 is disposed on the gate insulating layer 204 and is located directly above the channel region of the semiconductor layer 203. Applying a voltage to the gate 205 controls the conductivity of the channel region in the semiconductor layer 203, thereby achieving the switching function of the thin film transistor. The gate 205 is made of a metal material such as molybdenum, aluminum, or copper. A multi-layer metal stack can also be used to reduce resistance. The thickness of the gate 205 is 200 to 500 nanometers.

[0039] An interlayer insulating layer 206 is disposed on the gate 205 and the gate insulating layer 204 to electrically insulate the gate 205 from the subsequently formed source 207 and drain 208. The interlayer insulating layer 206 is made of silicon oxide or silicon nitride and has a thickness of 200 to 600 nanometers.

[0040] The source electrode 207 and the drain electrode 208 are disposed on the interlayer insulating layer 206 and are respectively located above the heavily doped region of the semiconductor layer 203. The source electrode 207 and the drain electrode 208 are electrically connected to the heavily doped region of the semiconductor layer 203 through a through hole, forming the source and drain electrodes of the thin film transistor. The source electrode 207 and the drain electrode 208 are made of a metal material such as molybdenum, aluminum, or copper. A multi-layer metal stack can also be used to reduce resistance and improve contact performance with the semiconductor layer 203. The source electrode 207 is connected to a data line for inputting a data signal to the thin film transistor. The drain electrode 208 is connected to a pixel electrode 209 for transmitting the data signal to the pixel electrode 209. The thickness of the source electrode 207 and the drain electrode 208 is 200 nanometers to 500 nanometers.

[0041] The pixel electrode 209 is disposed on the interlayer insulating layer 206 and is electrically connected to the drain electrode 208. A portion of the pixel electrode 209 overlaps the drain electrode 208. The pixel electrode 209 is made of a transparent conductive material, such as indium tin oxide, to ensure that light can pass through the pixel electrode 209. The pixel electrode 209 has a thickness of 50 to 150 nanometers.

[0042] The passivation layer 210 is disposed on the source electrode 207 , the drain electrode 208 , the pixel electrode 209 and the interlayer insulating layer 206 . The passivation layer 210 is made of silicon nitride or silicon oxide and has a thickness of 200 nanometers to 400 nanometers.

[0043] A first through hole 214 and a second through hole 215 are provided in the passivation layer 210, the interlayer insulating layer 206, and the gate insulating layer 204. The first through hole 214 and the second through hole 215 both penetrate the passivation layer 210, the interlayer insulating layer 206, and the gate insulating layer 204. The first through hole 214 and the second through hole 215 are only etched into a portion of the semiconductor layer 203, and do not completely penetrate the semiconductor layer 203. The first through hole 214 and the second through hole 215 do not penetrate the semiconductor layer 203. The first through hole 214 exposes a portion of the semiconductor layer 203, and the second through hole 215 exposes a portion of the semiconductor layer 203.

[0044] Specifically, in a direction perpendicular to substrate 201, the bottom surfaces of first through-hole 214 and second through-hole 215 are both located between the upper and lower surfaces of semiconductor layer 203. This means that semiconductor layer 203 retains a certain thickness at the bottoms of first through-hole 214 and second through-hole 215. The thickness of the portion of semiconductor layer 203 below the bottom surfaces of first through-hole 214 and second through-hole 215 is greater than 0 and less than 0.5 times the thickness of the portion of semiconductor layer 203 located in the channel region. This ensures sufficient contact area between the connector and semiconductor layer 203 while avoiding poor contact due to over-etching.

[0045] Furthermore, the thickness of the portion of the semiconductor layer 203 below the bottom surfaces of the first through-hole 214 and the second through-hole 215 is greater than 0 and less than 0.03 times the depth of the first through-hole 214 or the second through-hole 215. This proportional relationship ensures a reasonable ratio between the depth of the through-hole and the remaining thickness of the semiconductor layer 203, thereby ensuring the effective depth of the through-hole and maintaining the integrity of the semiconductor layer 203.

[0046] In a specific embodiment, the thickness of the semiconductor layer 203 below the bottom surfaces of the first through hole 214 and the second through hole 215 is 100 angstroms to 200 angstroms. This thickness range ensures good contact between the connector and the semiconductor layer 203 while preventing excessive damage to the semiconductor layer 203.

[0047] The passivation layer 210 is further provided with a third through hole 216 and a fourth through hole 217. Both the third through hole 216 and the fourth through hole 217 penetrate only the passivation layer 210 and do not extend into the underlying insulating layer. The third through hole 216 exposes at least a portion of the source electrode 207, and the fourth through hole 217 exposes at least a portion of the drain electrode 208.

[0048] The common electrode 213 is disposed on the passivation layer 210 and is used to provide a common voltage. The common electrode 213 is made of a transparent conductive material, such as indium tin oxide. The common electrode 213 and the pixel electrode 209 together form an electric field to control the orientation of the liquid crystal molecules, thereby achieving the display function.

[0049] The first connector 211 is disposed on the passivation layer 210, with a portion of the first connector 211 disposed within the first through-hole 214 and the third through-hole 216. The first connector 211 is electrically connected to both the source electrode 207 and the semiconductor layer 203, thereby achieving electrical connection between the source electrode 207 and the semiconductor layer 203. Because the first through-hole 214 does not completely penetrate the semiconductor layer 203, the first connector 211 can contact the bottom and side surfaces of the portion of the first through-hole 214 located within the semiconductor layer 203, thereby increasing the contact area and reducing the contact resistance. The portion of the first connector 211 within the first through-hole 214 forms an ohmic contact with the heavily doped region of the semiconductor layer 203, ensuring that current can flow smoothly between the source electrode 207 and the semiconductor layer 203.

[0050] The second connector 212 is disposed on the passivation layer 210, with a portion of the second connector 212 disposed within the second through-hole 215 and the fourth through-hole 217. The second connector 212 is electrically connected to both the drain electrode 208 and the semiconductor layer 203, thereby achieving electrical connection between the drain electrode 208 and the semiconductor layer 203. Similarly, the second connector 212 can contact the bottom and side surfaces of the portion of the second through-hole 215 located within the semiconductor layer 203. The design of the second connector 212 is the same as that of the first connector 211, ensuring a good electrical connection between the drain electrode 208 and the semiconductor layer 203.

[0051] The first connector 211 and the second connector 212 each include a metal material layer and a transparent metal layer. The metal material layer is located below and directly contacts the semiconductor layer 203. The transparent metal layer is disposed on the metal material layer. This dual-layer design balances the requirements for electrical contact performance and optical transmittance. The metal material layer comprises a stack of one or more of titanium, molybdenum, and tungsten. The thickness of the metal material layer is 3 to 7 nanometers, a thickness range that ensures good electrical contact while maintaining high transmittance. The transparent metal layer is made of indium tin oxide.

[0052] Because the transparent metal layer easily reacts with the heavily doped regions of the semiconductor layer 203 when in direct contact, forming a silicon oxide insulating layer and increasing contact resistance, a metal material layer is provided beneath the transparent metal layer to effectively avoid this problem and ensure good electrical contact between the connector and the semiconductor layer 203. The metal material layer acts as a barrier layer, preventing oxygen atoms in the transparent metal layer from diffusing into the semiconductor layer 203 while providing a stable electrical contact interface.

[0053] During the manufacturing process, the metal layer undergoes annealing, reacting with the transparent metal layer to form a metal oxide, further enhancing transmittance. The annealing temperature is controlled between 300°C and 400°C. During the annealing process, the surface of the metal layer undergoes partial oxidation, resulting in a metal oxide with improved transparency while maintaining good conductivity. The annealing time ranges from 30 to 120 minutes.

[0054] like Figures 3 to 8 As shown, the present application also provides a method for manufacturing a display panel, comprising the following steps: Step 1: forming a buffer layer 202 on a substrate 201, and forming a semiconductor layer 203 on the buffer layer 202. The substrate 201 is made of glass, the buffer layer 202 is made of silicon oxide or silicon nitride, and the semiconductor layer 203 is made of low-temperature polysilicon.

[0055] Step 2: The semiconductor layer 203 is processed so that the semiconductor layer 203 includes a channel region, a lightly doped region, and a heavily doped region. A gate insulating layer 204 is formed on the semiconductor layer 203 and the buffer layer 202. A gate metal layer is formed on the gate insulating layer 204. The gate metal layer is patterned to form a gate 205. The semiconductor layer 203 is doped by an ion implantation process. The gate insulating layer 204 is made of silicon oxide, and the gate metal layer is made of a metal material such as molybdenum, aluminum, or copper.

[0056] Step 3: An interlayer insulating layer 206 is formed on the gate insulating layer 204 and the gate 205, and a source-drain metal layer is formed on the interlayer insulating layer 206. The source-drain metal layer is patterned to form a source 207 and a drain 208. The interlayer insulating layer 206 is made of silicon oxide or silicon nitride, and the source-drain metal layer is made of a metal material such as molybdenum, aluminum, or copper.

[0057] Step 4: Form a first transparent metal layer on the interlayer insulating layer 206, the source electrode 207, and the drain electrode 208, and pattern the first transparent metal layer to form the pixel electrode 209. The first transparent metal layer is made of indium tin oxide.

[0058] Step 5: A passivation layer 210 is formed on the interlayer insulating layer 206, the source electrode 207, the drain electrode 208, and the pixel electrode 209. The passivation layer 210, the interlayer insulating layer 206, and the gate insulating layer 204 are etched to form a first through hole 214, a second through hole 215, a third through hole 216, and a fourth through hole 217. The first through hole 214, the second through hole 215, the third through hole 216, and the fourth through hole 217 are formed in the same process, which can simplify the manufacturing process and reduce production costs. The first through hole 214 and the second through hole 215 penetrate the passivation layer 210, the interlayer insulating layer 206, and the gate insulating layer 204. The first through hole 214 and the second through hole 215 are only etched into a portion of the semiconductor layer 203, and do not completely penetrate the semiconductor layer 203. That is, in a direction perpendicular to the substrate 201, the bottom surfaces of the first through hole 214 and the second through hole 215 are located between the upper and lower surfaces of the semiconductor layer 203. The portions of the semiconductor layer 203 corresponding to the first through hole 214 and the second through hole 215 still have a certain thickness. The third through hole 216 and the fourth through hole 217 penetrate the passivation layer 210.

[0059] The step of etching the passivation layer 210, the interlayer insulating layer 206 and the gate insulating layer 204 to form the first through hole 214, the second through hole 215, the third through hole 216 and the fourth through hole 217 includes: etching the passivation layer 210, the interlayer insulating layer 206 and the gate insulating layer 204 using a mixed gas of pentafluoroethane, argon and hydrogen.

[0060] During the etching process, a mixture of pentafluoroethane, argon, and hydrogen is used for etching. Conventional etching processes use a mixture of carbon tetrafluoride, oxygen, pentafluoroethane, and argon. This etching recipe has a relatively low etching selectivity for the silicon oxide insulating layer and the semiconductor layer 203, which can easily lead to the semiconductor layer 203 being completely etched through. The present application uses a mixture of pentafluoroethane, argon, and hydrogen for etching. The addition of hydrogen significantly improves the etching selectivity for the semiconductor layer 203. Specifically, hydrogen reacts with silicon atoms on the surface of the semiconductor layer 203 to form volatile silicon hydride compounds, but the rate of this reaction is much lower than the etching rate of pentafluoroethane on the silicon oxide insulating layer. Therefore, when the silicon oxide insulating layer is completely etched, the semiconductor layer 203 is only partially etched, leaving a semiconductor layer 203 thickness of approximately 100 to 200 angstroms at the bottom of the first through-hole 214 and the second through-hole 215. This improvement in etching selectivity ensures that the first connector 211 and the second connector 212 can simultaneously contact the bottom and side surfaces of the first through hole 214 and the second through hole 215 located in the semiconductor layer 203 , thereby increasing the contact area.

[0061] Step 6: A stack of a metal material layer and a second transparent metal layer is disposed within the first through-hole 214, the second through-hole 215, the third through-hole 216, and the fourth through-hole 217, and on the surface of the passivation layer 210. The stack of the metal material layer and the second transparent metal layer is patterned to form the first connector 211, the second connector 212, and the common electrode 213. The metal material layer is a stack of one or more materials selected from titanium, molybdenum, and tungsten, and the second transparent metal layer is made of indium tin oxide.

[0062] like Figure 7 、 Figure 8 and Figure 9 As shown, through the above technical solution, the display panel of the present application achieves the optimization of the contact between the connector and the semiconductor layer 203. Specifically, since the first through hole 214 and the second through hole 215 do not completely penetrate the semiconductor layer 203, the first connector 211 and the second connector 212 can simultaneously contact the upper surface and side surface of the portion of the semiconductor layer 203 located in the first through hole 214 and the second through hole 215. Compared with the method in the prior art in which the connector only contacts the upper surface of the semiconductor layer 203, this contact method has better stability, improves the reliability of the thin film transistor, and extends the service life of the display panel. The increase in contact area directly leads to a decrease in contact impedance. According to Ohm's law, under the same current conditions, the reduction in contact impedance reduces power loss and improves the driving efficiency of the thin film transistor.

[0063] From a manufacturing perspective, this application avoids the complex steps of multiple etching and alignment required in traditional processes by forming through-holes of varying depths in the same etching process. This simplified process reduces manufacturing costs, improves production efficiency, and reduces the impact of process variation on product performance. By controlling the remaining thickness of the semiconductor layer 203 at the bottom of the through-hole to within a range of 100 to 200 angstroms, good electrical contact between the connector and the semiconductor layer 203 is ensured, while avoiding exposure of the buffer layer 202 and device failure caused by over-etching.

[0064] The above is a detailed introduction to the embodiments of the present application. The contents of this specification should not be understood as limiting the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a substrate, a semiconductor layer, a passivation layer, an interlayer insulating layer, a gate insulating layer, a source electrode, a drain electrode, a first connecting member and a second connecting member; The passivation layer, the interlayer insulating layer, and the gate insulating layer are provided with a first through hole and a second through hole, the first through hole and the second through hole both penetrate the passivation layer, the interlayer insulating layer, and the gate insulating layer, and in a direction perpendicular to the substrate, the bottom surfaces of the first through hole and the second through hole are both located between the upper surface and the lower surface of the semiconductor layer; A third through hole and a fourth through hole are provided in the passivation layer, both of the third through hole and the fourth through hole penetrate the passivation layer, the third through hole exposes at least a portion of the source electrode, and the fourth through hole exposes a portion of the drain electrode; A portion of the first connector is disposed in the first through hole and the third through hole, and the first connector is electrically connected to the source and the semiconductor layer. A portion of the second connector is disposed in the second through hole and the fourth through hole, and the second connector is electrically connected to the drain and the semiconductor layer.

2. The display panel according to claim 1, wherein: The thickness of a portion of the semiconductor layer located below bottom surfaces of the first through-hole and the second through-hole is greater than 0 and less than 0.5 times the thickness of a portion of the semiconductor layer located in the channel region.

3. The display panel according to claim 1, wherein: A thickness of a portion of the semiconductor layer located below bottom surfaces of the first through-hole and the second through-hole is greater than 0 and less than 0.03 times the depth of the first through-hole or the second through-hole.

4. The display panel according to claim 1, wherein: The thickness of a portion of the semiconductor layer located below the bottom surfaces of the first through hole and the second through hole is 100 angstroms to 200 angstroms.

5. The display panel according to claim 1, wherein: The first connecting member contacts the bottom surface and side surfaces of a portion of the first through hole located in the semiconductor layer, and the second connecting member contacts the bottom surface and side surfaces of a portion of the second through hole located in the semiconductor layer.

6. A method for manufacturing a display panel, characterized in that: The following steps are involved: Etching the passivation layer, the interlayer insulating layer, and the gate insulating layer to form a first through hole, a second through hole, a third through hole, and a fourth through hole, wherein the first through hole and the second through hole penetrate the passivation layer, the interlayer insulating layer, and the gate insulating layer, and in a direction perpendicular to the substrate, the bottoms of the first through hole and the second through hole are both located between the upper surface and the lower surface of the semiconductor layer, and the third through hole and the fourth through hole penetrate the passivation layer; as well as A first connector and a second connector are provided in the first through hole, the second through hole, the third through hole, and the fourth through hole. The first connector is electrically connected to the source electrode and the semiconductor layer, and the second connector is electrically connected to the drain electrode and the semiconductor layer.

7. The manufacturing method according to claim 6, characterized in that The step of etching the passivation layer, the interlayer insulating layer and the gate insulating layer to form the first through hole, the second through hole, the third through hole and the fourth through hole comprises: The passivation layer, the interlayer insulating layer and the gate insulating layer are etched using a mixed gas of pentafluoroethane, argon and hydrogen.

8. The manufacturing method according to claim 6, characterized in that The thickness of a portion of the semiconductor layer located below bottom surfaces of the first through-hole and the second through-hole is greater than 0 and less than 0.5 times the thickness of a portion of the semiconductor layer located in the channel region.

9. The manufacturing method according to claim 6, characterized in that A thickness of a portion of the semiconductor layer located below bottom surfaces of the first through-hole and the second through-hole is greater than 0 and less than 0.03 times the depth of the first through-hole or the second through-hole.

10. The manufacturing method according to claim 6, characterized in that The thickness of a portion of the semiconductor layer located below the bottom surfaces of the first through hole and the second through hole is 100 angstroms to 200 angstroms.

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