Preparation method of silicon-based heterojunction solar cell, heterojunction cell and photovoltaic module
By using the method of electroplating copper seed layer and screen printing to prepare grid line grooves in copper grid line heterojunction solar cells, combined with wet and light injection processes, the formation of copper-tin alloy and tin oxide is avoided, the problem of poor welding performance is solved, and the component power is improved.
Patent Information
- Application Number
- CN202510891203.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-30
- Publication Date
- 2025-09-30
AI Technical Summary
In the prior art, copper-grid heterojunction solar cells produce copper-tin alloy and tin oxide during the light injection process, resulting in poor surface contact, low tension and high contact resistance during cell welding, affecting component power.
The gate line grooves are prepared by electroplating a copper seed layer and screen printing combined with exposure and development. After electroplating the copper gate line, the ink layer and copper seed layer are removed in the same wet process equipment, and then transferred to the light injection equipment for light injection and wet copper deoxidation treatment. Finally, a tin layer is deposited on the surface of the copper gate line to avoid the formation of copper-tin alloy and tin oxide.
The surface welding performance during the cell welding process is improved, the module power is enhanced, and by avoiding the formation of copper-tin alloy and tin oxide during the light injection process, better welding results and higher module power are ensured.
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Figure CN120730876A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of heterojunction solar cells, and in particular to a method for preparing a silicon-based heterojunction solar cell, a heterojunction cell, and a photovoltaic module. Background Art
[0002] Among the many silicon-based solar cell technologies, silicon-based heterojunction solar cells have higher conversion efficiency due to the use of amorphous silicon thin film passivation on the front and back sides. They are currently the most likely to become the next generation of mass-produced photovoltaic technology. However, because amorphous silicon thin films cannot withstand temperatures above 300°C, most cells using this technology currently use screen-printed low-temperature silver paste to prepare metal grid lines. The organic matter in the low-temperature silver paste is then volatilized through curing to form grid lines. Finally, the performance of the amorphous silicon thin film is further enhanced through a light injection process.
[0003] However, printing silver paste will result in very high metal grid line costs, which is not conducive to its large-scale mass production. Nowadays, electroplating copper grid line technology has been used to replace screen printing low-temperature silver paste metallization. A tin layer is prepared on the surface of the electroplated copper through a chemical reaction to protect the copper grid line from subsequent oxidation, thereby achieving a low-cost and high-efficiency preparation process, which is expected to further promote the industrialization process of silicon-based heterojunction solar cells.
[0004] However, in actual applications, it was found that in the related technology, the copper grid cell with a tin layer has a copper-tin alloy phase and a tin oxide layer on the surface of the copper grid line during the preparation process. These substances affect the subsequent cell welding and component preparation process, resulting in poor surface contact, low tension and high contact resistance, and the surface welding performance deteriorates, resulting in lower final component power. Summary of the Invention
[0005] The present application aims to at least solve the problems in the prior art of copper-grid heterojunction solar cells, in which the surface copper-tin alloying reaction generates different copper-tin alloy phases after the light injection process, and the tin layer is also oxidized to form tin oxide. These substances lead to poor surface contact, low tension and high contact resistance in the subsequent cell welding process to prepare components.
[0006] To achieve the above objectives, in a first aspect, the present application provides a method for preparing a silicon-based heterojunction solar cell, comprising: The N-type silicon wafer is placed in an alkaline solution for double-sided texturing, and the N-type silicon wafer after texturing is cleaned and impurities removed; Depositing an intrinsic amorphous silicon layer on the front and back sides of the cleaned N-type silicon wafer, depositing a phosphorus-doped silicon layer on the surface of the intrinsic amorphous silicon layer on the front side, and depositing a boron-doped silicon layer on the surface of the intrinsic amorphous silicon layer on the back side; sequentially depositing a transparent conductive thin film layer and a copper seed layer on the exposed surfaces of the phosphorus-doped silicon layer and the boron-doped silicon layer; Printing an ink layer on the exposed surface of the copper seed layer, and grooving the ink layer to prepare a gate line groove, wherein the surface of the copper seed layer at the bottom of the gate line groove is exposed; Electroplating copper gate lines in the gate line grooves, and removing the ink layer and the copper seed layer in sequence after the copper gate lines are prepared to obtain a silicon wafer intermediate; The silicon wafer intermediate is subjected to light injection treatment, and the surface of the silicon wafer intermediate after light injection is subjected to wet removal of copper oxide and a tin layer is deposited on the surface of the copper grid line to obtain a copper grid line heterojunction solar cell.
[0007] In some possible implementations, placing the N-type silicon wafer in an alkaline solution for double-sided texturing includes: The N-type silicon wafer is placed in a KOH or NaOH solution with a concentration of 0.5% to 10% for reaction; the reaction environment temperature is 50°C to 90°C, and the reaction time is controlled within 1 minute to 20 minutes, so that a pyramid-structured velvet surface is formed on both surfaces of the N-type single crystal silicon wafer.
[0008] In some possible implementations, sequentially depositing a transparent conductive thin film layer and a copper seed layer on the exposed surfaces of the phosphorus-doped silicon layer and the boron-doped silicon layer includes: The transparent conductive film layer and the copper seed layer are sequentially deposited by ion sputtering, wherein the transparent conductive film layer has a thickness range of 50nm-200nm and a refractive index of 1.6-2.5, and the copper seed layer has a thickness range of 10nm-150nm.
[0009] In some possible implementations, electroplating copper gate lines in the gate line trenches, and sequentially removing the ink layer and the copper seed layer after forming the copper gate lines to obtain a silicon wafer intermediate includes: Immersing the electroplated N-type silicon wafer in an alkaline mixed solution to remove the ink layer, wherein the alkaline mixed solution comprises a combination of one or more of potassium hydroxide solution and sodium hydroxide solution; The N-type silicon wafer with the ink layer removed is immersed in an acidic mixed solution to remove the copper seed layer except the copper grid line, wherein the acidic mixed solution includes a combination of one or more of dilute sulfuric acid solution and dilute nitric acid solution.
[0010] In some possible implementations, immersing the electroplated N-type silicon wafer in an alkaline mixed solution to remove the ink layer includes: The concentration of the alkaline mixed solution ranges from 3% to 20%, the solution temperature ranges from 30° C. to 70° C., the spraying pressure ranges from 0.8 kg to 3.0 kg, and the reaction time ranges from 10 seconds to 100 seconds.
[0011] In some possible implementations, immersing the N-type silicon wafer from which the ink layer is removed in an acidic mixed solution to remove the copper seed layer other than the copper grid lines includes: An N-type silicon wafer is immersed in a dilute sulfuric acid aqueous solution containing an oxidant, wherein the oxidant includes a combination of one or more of hydrogen peroxide and potassium persulfate, and the oxidant concentration ranges from 0.5% to 5.0%. The dilute sulfuric acid concentration ranges from 0.5% to 10%, and the reaction time ranges from 5s to 100s. After removing the copper seed layer, the N-type silicon wafer is washed and dried.
[0012] In some possible embodiments, the light injection treatment is performed on the silicon wafer intermediate, and the copper oxide is removed from the surface of the silicon wafer intermediate after the light injection by wet method and a tin layer is deposited on the surface of the copper grid line to obtain a copper grid line heterojunction solar cell, including: In the light injection process, the light injection illumination power range is 50W / m 2 -100000W / m 2 , the wavelength range of the light source is 500nm-1000nm, which can be a single wavelength light source in the sub-wavelength range or a common LED light source, the light injection time is between 20s-180s, and the temperature is 100℃-300℃; In the wet copper oxide removal process, a dilute sulfuric acid solution with a concentration range of 0.5%-3% is used to remove copper oxide on the surface of the silicon wafer intermediate, wherein the solution temperature range is 20°C-40°C and the reaction time range is 5s-30s.
[0013] In some possible embodiments, the light injection treatment is performed on the silicon wafer intermediate, and the surface of the silicon wafer intermediate after light injection is subjected to wet removal of copper oxide and a tin layer is deposited on the surface of the copper grid line to obtain a copper grid line heterojunction solar cell, further comprising: In the tin layer deposition process, a mixed solution including tin methanesulfonate, stannous sulfate, thiourea, sodium hypophosphite, and sulfuric acid is used to deposit a tin layer on the silicon wafer intermediate from which copper oxide has been removed, wherein the concentration range of the tin methanesulfonate is 0.5%-30%, the concentration range of the stannous sulfate is 1%-10%, and the concentration range of the thiourea is 0.1%-5%. The reaction temperature range is 20°C-60°C, and the reaction time is 20s-300s.
[0014] Compared with the prior art, the technical solution provided in the first aspect of the present application has at least the following beneficial effects: In the preparation method of the silicon-based heterojunction solar cell of the present application, a copper seed layer is electroplated and screen printing is performed on the surface of the seed layer in combination with exposure and development to prepare a gate line groove, and then copper grid lines are generated in the gate line groove by electroplating. After the copper grid line preparation is completed, the photosensitive ink layer and the copper seed layer are removed in sequence on the surface of the silicon wafer in the same wet process equipment, and then the silicon wafer is transferred to a light injection equipment for a light injection process. After the light injection process is completed, the silicon wafer is transferred to another wet process equipment for copper deoxidation treatment and tin layer deposition treatment in sequence, thereby preparing a copper grid line silicon-based heterojunction solar cell. The process route of the method of the present application can effectively avoid the generation of copper-tin alloy and tin oxide during the light injection process, thereby achieving better surface welding performance and higher component power during the process of soldering the cell to prepare the component.
[0015] In a second aspect, the present application further provides a heterojunction solar cell, which is prepared by the preparation method of a silicon-based heterojunction solar cell provided in any embodiment of the first aspect.
[0016] In a third aspect, the present application further provides a photovoltaic assembly, characterized in that it includes: A cell string is formed by connecting a plurality of heterojunction solar cells formed by the method for preparing a silicon-based heterojunction solar cell according to the first aspect above; A packaging film, used to cover the surface of the battery string; A cover plate is used to cover the surface of the packaging film facing away from the battery string.
[0017] It can be understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.
[0018] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0020] Figure 1 is a flow chart of a method for preparing a silicon-based heterojunction solar cell according to an embodiment of the present application; Figure 2 This is a schematic diagram of the first structure of a cell in the preparation process of a copper grid heterojunction solar cell according to an embodiment of the present application; Figure 31 is a schematic diagram of a second structure of a cell in the preparation process of a copper grid heterojunction solar cell according to an embodiment of the present application; Figure 4 3 is a schematic diagram of the third structure of a cell in the preparation process of a copper grid heterojunction solar cell according to an embodiment of the present application; Figure 5 4 is a schematic diagram of the structure of a solar cell in the preparation process of a copper grid heterojunction solar cell according to an embodiment of the present application; Figure 6 1 is a fifth structural schematic diagram of a cell in the preparation process of a copper grid heterojunction solar cell according to an embodiment of the present application; Figure 7 1 is a sixth structural schematic diagram of a cell in the preparation process of a copper grid heterojunction solar cell according to an embodiment of the present application; Figure 8 This is the seventh structural schematic diagram of a cell in the preparation process of a copper grid heterojunction solar cell according to an embodiment of the present application.
[0021] Reference numerals: 100, N-type silicon wafer; 110, pyramid velvet surface; 200, intrinsic amorphous silicon layer; 310, phosphorus-doped silicon layer; 320, boron-doped silicon layer; 400, transparent conductive film layer; 500, copper seed layer; 600, ink layer; 610, gate line trench; 700, copper gate line; 800, tin layer. DETAILED DESCRIPTION
[0022] The embodiments of the present application are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0023] It should be noted that when an element is referred to as being “fixed to” another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or there may be an intermediate element.
[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0025] See also Figures 1 to 8 This embodiment provides a method for preparing a silicon-based heterojunction solar cell, the preparation method comprising: Step S100: placing an N-type silicon wafer in an alkaline solution for double-sided texturing, and then performing impurity removal and cleaning on the texturized N-type silicon wafer; In some embodiments, the N-type silicon wafer needs to be pre-cleaned first, and then the pre-cleaned N-type silicon wafer is double-sided textured using a texturing process, and the silicon wafer is placed in a predetermined texturing mixture, wherein the texturing mixture is composed of at least an alkaline solution and ultrapure water, and the alkaline solution includes a combination of one or more potassium hydroxide or sodium hydroxide solutions. For example, the N-type silicon wafer can be placed in a 0.5% to 10% concentration of KOH or NaOH solution for reaction; wherein the reaction environment temperature is 50°C to 90°C, and the reaction time is controlled at 1min to 20min, so that a pyramid-structured textured surface is formed on both surfaces of the N-type single crystal silicon wafer.
[0026] Of course, special additives for velvet can also be added. The main component of the special additive for velvet can be potassium sorbate, 1% to 5% of the solution; the role of velvet making is to form a pyramid light-trapping structure on the surface of single-crystal silicon, thereby increasing light absorption. The reaction time can be controlled at 200s-1800s, so that a pre-set pyramid structure is formed on the front and back (light-receiving and backlight) surfaces of the N-type silicon wafer. The size of the pyramid structure is controlled between 0.5um-10um.
[0027] Optional, such as Figure 2 As shown, a pyramid velvet 110 structure is formed on both sides of the N-type silicon wafer 100. By setting the pyramid velvet 110, the effective area of the battery surface can be increased, so that more light can be absorbed, thereby improving the photoelectric conversion efficiency. At the same time, by forming a micron-level texture on the battery surface, the reflection of light can be effectively reduced, and the absorption of light can be further enhanced. The velvet structure can optimize the movement path of carriers, reduce the recombination of carriers, and improve the current output of the battery.
[0028] Optionally, after the pyramid velvet surface 110 is prepared, the velvet-formed N-type silicon wafer 100 is cleaned and decontaminated, for example, the alkaline solution remaining on the surface of the N-type silicon wafer 100 is removed to facilitate subsequent processing steps of the N-type silicon wafer 100.
[0029] It is understandable that the thickness and specific material of the N-type silicon wafer 100, as well as other parameters in the texturing process and the required equipment can be selected according to actual needs and are not limited here. For example, optionally, the N-type silicon wafer 100 is an N-type doped single crystal or polycrystalline silicon wafer with a thickness of 80um-160um. The pre-cleaning of the N-type silicon wafer is a conventional process and will not be elaborated here.
[0030] Step S200: depositing an intrinsic amorphous silicon layer on the front and back surfaces of the cleaned N-type silicon wafer, depositing a phosphorus-doped silicon layer on the surface of the intrinsic amorphous silicon layer on the front surface, and depositing a boron-doped silicon layer on the surface of the intrinsic amorphous silicon layer on the back surface; In some embodiments, as Figure 3 As shown, plasma enhanced chemical vapor deposition technology PECVD can be used to deposit an intrinsic amorphous silicon layer 200 on the front and back sides of the silicon wafer respectively. The thickness of the intrinsic amorphous silicon layer 200 can range from 4 nm to 10 nm, thereby passivating the crystalline silicon interface. Optionally, the process gas of the intrinsic amorphous silicon layer is a combination of silane (SiH4), hydrogen (H2), and carbon dioxide (CO2), with a refractive index of 3.2-4.8. The intrinsic amorphous silicon layer can passivate the dangling bonds on the surface of the silicon wafer and reduce the surface defect state density.
[0031] Optionally, after completing the deposition of the intrinsic amorphous silicon layer, PECVD can be used to deposit a phosphorus-doped silicon layer 310 on the surface of the intrinsic amorphous silicon layer 200 on the front, and a boron-doped silicon layer 320 on the surface of the intrinsic amorphous silicon layer on the back. Specifically, doped amorphous silicon / nanocrystalline silicon layers are deposited on the front and back of the silicon wafer, respectively. Phosphorus-doped amorphous silicon / nanocrystalline silicon is deposited on the front with a thickness of 5nm-40nm to form a nn+ high-low heterostructure with crystalline silicon, and boron-doped amorphous silicon / nanocrystalline silicon is deposited on the back with a thickness of 5nm-60nm to form an np+ heterostructure with crystalline silicon as the back emitter of the battery.
[0032] Step S300: depositing a transparent conductive thin film layer and a copper seed layer in sequence on the exposed surfaces of the phosphorus-doped silicon layer and the boron-doped silicon layer; In some embodiments, as Figure 4 and Figure 5 As shown, a transparent conductive film layer 400 and a copper seed layer 500 are sequentially deposited by ion sputtering, wherein the transparent conductive film layer 400 is also called a TCO layer, and the thickness of the transparent conductive film layer 400 is in the range of 50nm-200nm, and the refractive index is 1.6-2.5, and the thickness of the copper seed layer 500 is in the range of 10nm-150nm.
[0033] Optionally, a highly transparent conductive film is sputtered on the front and back sides of the cell using PVD or RPD to form a TCO layer. The TCO layer is used to collect carriers. It can be understood that the TCO layer is a conventional setting for heterojunction solar cells, and its specific implementation conditions and principles can be achieved with existing technologies and will not be elaborated here.
[0034] Optionally, after preparing a transparent conductive thin film layer on both surfaces of the silicon wafer, a seed layer is further electroplated, and a 10nm-150nm copper seed layer 500 is deposited on the front and back sides of the battery using PVD. Of course, the seed layer can be roughly divided into three types: copper, nickel and copper-nickel alloy by using different target materials in the PVD sputtering process. The main function of the copper seed layer 500 is to enhance the bonding force between the copper grid line and the TCO, which helps the heterojunction battery to achieve double-sided electroplating. If the copper grid line is directly electroplated on the silicon surface, the sintering link is reduced, which is prone to cause grid delamination problems.
[0035] Step S400: printing an ink layer on the exposed surface of the copper seed layer, and grooving the ink layer to prepare a gate line trench, wherein the surface of the copper seed layer at the bottom of the gate line trench is exposed; In some embodiments, combined Figure 6 As shown, a surface-printed ink layer 600 is exposed on the copper seed layer 500. Specifically, a layer of photosensitive ink is printed on the front and back sides of the silicon wafer by screen printing, and then gate line grooves 610 of different widths are formed on the surface of the silicon wafer by exposure and development. The copper seed layer 500 is exposed at the bottom of the groove, and the copper seed layer 500 in the non-groove area is covered with ink. It should be noted that the exposure and development process is a prior art, and its principles and related parameter settings will not be elaborated here.
[0036] Step S500: electroplating copper gate lines in the gate line trenches, and removing the ink layer and the copper seed layer in sequence after the copper gate lines are formed to obtain a silicon wafer intermediate; In some embodiments, copper gate lines 700 are electroplated in the gate line grooves, and vertical continuous electroplating can be used to electroplate copper gate lines 700 in the double-sided gate line grooves of the silicon wafer, wherein the width range of the front main gate can be 50 um-80 um, the width range of the front sub-gate can be 10 um-40 um, and the height range can be 5 um-20 um; the width range of the back main gate can be 50 um-250 um, the width range of the back sub-gate can be 20 um-80 um; and the height range can be 5 um-20 um.
[0037] Optional, such as Figure 7 As shown, after the copper grid line 700 is electroplated, the plated N-type silicon wafer is immersed in an alkaline mixed solution to remove the ink layer, wherein the alkaline mixed solution includes a combination of one or more potassium hydroxide or sodium hydroxide solutions; the N-type silicon wafer with the ink layer removed is immersed in an acidic mixed solution to remove the copper seed layer other than the copper grid line, wherein the acidic mixed solution includes a combination of one or more dilute sulfuric acid or dilute nitric acid solutions.
[0038] Optionally, during the ink layer removal process, the concentration of the alkaline mixed solution ranges from 3% to 20%, the solution temperature ranges from 30° C. to 70° C., the spraying pressure of the alkaline mixed solution ranges from 0.8 kg to 3.0 kg, and the reaction time ranges from 10 s to 100 s.
[0039] In some embodiments, the masked silicon wafer is immersed in an acidic mixed solution to remove the copper seed layer other than the copper grid line. For example, the N-type silicon wafer is immersed in a dilute sulfuric acid aqueous solution containing an oxidant, wherein the oxidant includes a combination of one or more of hydrogen peroxide and potassium persulfate, and the oxidant concentration ranges from 0.5% to 5.0%; the dilute sulfuric acid concentration ranges from 0.5% to 10%, and the reaction time ranges from 5s to 100s. After removing the copper seed layer, the N-type silicon wafer is washed and dried.
[0040] Step S600: performing light injection treatment on the silicon wafer intermediate, removing copper oxide from the surface of the silicon wafer intermediate after light injection by wet method and depositing a tin layer on the surface of the copper grid line to obtain a copper grid line heterojunction solar cell.
[0041] In this step, it should be noted that, in the relevant technology, since the deposition of the tin layer, the removal of the ink layer, and the removal of the copper seed layer are all wet reaction processes, they can be carried out in the same equipment, and multiple reaction tanks are set in the same equipment. In this way, the transfer of the battery cells is reduced, the number of steps is reduced, and the production efficiency is improved. Then, light injection is performed. Through light injection, light will excite electrons and holes in the material, generating a large number of electron-hole pairs (photogenerated carriers). In solar cells, these photogenerated carriers will improve the photoelectric conversion efficiency of the battery and enhance the carrier concentration of the battery. The increase in carriers can effectively improve the conductivity of the battery, reduce carrier recombination, and thus improve the overall performance of the solar cell. Since light injection needs to be completed in a high-temperature environment, and the higher the temperature, the higher the light injection efficiency, and since tin treatment is performed before light injection, although the process of removing copper oxide can be reduced, experiments have found that under high-temperature conditions, copper-tin alloys and tin oxide products will be produced during the light injection process. These alloys and oxides have poor contact with the surface of the soldering ribbon used for subsequent component welding, low tension, and high contact resistance, resulting in a reduction in the final component power.
[0042] Therefore, in this embodiment, the light injection process is first performed, and then the wet removal of copper oxide and the deposition of a tin layer on the surface of the copper grid line are performed. It should be noted that, if Figure 7 and Figure 8 As shown, during the light injection process, since the copper grid lines in this step are completely exposed and affected by high temperature, a layer of copper oxide will be generated on their surface. Therefore, it is necessary to first perform a wet method to remove the copper oxide and then perform a tin layer deposition process on the copper grid line surface.
[0043] For example, in the light injection process, the light injection illumination power range is 50W / m 2 -100000W / m 2 The wavelength range of the light source is 500nm-1000nm, which can be a single wavelength light source in the sub-wavelength range or a common LED light source. The light injection time is between 20s-180s, and the temperature is 100℃-300℃. In the wet copper oxide removal process, a dilute sulfuric acid solution with a concentration range of 0.5%-3% is used to remove copper oxide on the surface of the silicon wafer intermediate, wherein the solution temperature range is 20℃-40℃, and the reaction time range is 5s-30s. In the tin layer deposition process, a mixed solution including tin methanesulfonate, stannous sulfate, thiourea, sodium hypophosphite, and sulfuric acid is used to deposit a tin layer on the silicon wafer intermediate from which copper oxide is removed, wherein the concentration range of the tin methanesulfonate is 0.5%-30%, the concentration range of the stannous sulfate is 1%-10%, and the concentration range of the thiourea is 0.1%-5%. The reaction temperature range is 20℃-60℃, and the reaction time is 20s-300s.
[0044] In the above process method, a copper seed layer is electroplated and screen printing is performed on the surface of the seed layer in combination with exposure and development to prepare a gate line groove, and then copper grid lines are generated in the gate line grooves by electroplating. After the copper grid line preparation is completed, the photosensitive ink layer and the copper seed layer are removed in sequence on the surface of the silicon wafer in the same wet process equipment, and then the wafer is transferred to a light injection equipment for a light injection process. After the light injection process is completed, the wafer is transferred to another wet process equipment for copper deoxidation treatment and tin layer deposition treatment in sequence, thereby preparing a copper grid line silicon-based heterojunction solar cell. The process route of the method of the present application can effectively avoid the generation of copper-tin alloy and tin oxide during the light injection process, thereby achieving better surface welding performance and higher component power during the process of soldering the cell to prepare the component.
[0045] In some embodiments, a comparison of experimental data of the copper-grid heterojunction solar cell prepared by the above method and the ordinary copper-grid heterojunction solar cell in subsequent welding into a module is provided, as shown in Table (1) below, wherein the control group is the ordinary copper-grid heterojunction solar cell, and the copper-grid experimental group is the copper-grid heterojunction solar cell prepared by the above method. Table (1) is a comparison of the experimental data of the copper grid heterojunction solar cells welded into modules prepared by the above method and the ordinary copper grid heterojunction solar cells welded into modules In some embodiments, a heterojunction solar cell is further provided. The heterojunction solar cell is prepared by the preparation method of a silicon-based heterojunction solar cell in any of the above embodiments.
[0046] It is understandable that the beneficial effects of the technical solution of this embodiment can be found in the relevant description of the beneficial effects of the above-mentioned method for preparing a silicon-based heterojunction solar cell, and will not be repeated here.
[0047] In some embodiments, a photovoltaic module is further provided, comprising: a cell string formed by connecting a plurality of heterojunction solar cells formed by the method for preparing silicon-based heterojunction solar cells as described in the above embodiments; A packaging film, used to cover the surface of the battery string; A cover plate is used to cover the surface of the packaging film facing away from the battery string.
[0048] It is understandable that the beneficial effects of the technical solution of this embodiment can be found in the relevant description of the beneficial effects of the above-mentioned method for preparing a silicon-based heterojunction solar cell, and will not be repeated here.
[0049] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the invention.
[0050] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.
[0051] Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Mentioning "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present embodiment application. The appearance of this phrase in various positions in the specification does not necessarily mean that they are all the same embodiments, nor are they independent or alternative embodiments that are mutually exclusive with other embodiments. It can be understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.
[0052] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.
Claims
1. A method for preparing a silicon-based heterojunction solar cell, characterized in that: include: The N-type silicon wafer is placed in an alkaline solution for double-sided texturing, and the N-type silicon wafer after texturing is cleaned and impurities removed; Depositing an intrinsic amorphous silicon layer on the front and back sides of the cleaned N-type silicon wafer, depositing a phosphorus-doped silicon layer on the surface of the intrinsic amorphous silicon layer on the front side, and depositing a boron-doped silicon layer on the surface of the intrinsic amorphous silicon layer on the back side; sequentially depositing a transparent conductive thin film layer and a copper seed layer on the exposed surfaces of the phosphorus-doped silicon layer and the boron-doped silicon layer; Printing an ink layer on the exposed surface of the copper seed layer, and grooving the ink layer to prepare a gate line groove, wherein the surface of the copper seed layer at the bottom of the gate line groove is exposed; Electroplating copper gate lines in the gate line grooves, and removing the ink layer and the copper seed layer in sequence after the copper gate lines are prepared to obtain a silicon wafer intermediate; The silicon wafer intermediate is subjected to light injection treatment, and the surface of the silicon wafer intermediate after light injection is subjected to wet removal of copper oxide and a tin layer is deposited on the surface of the copper grid line to obtain a copper grid line heterojunction solar cell.
2. The method for preparing a silicon-based heterojunction solar cell according to claim 1, wherein: Placing the N-type silicon wafer in an alkaline solution for double-sided texturing includes: The N-type silicon wafer is placed in a KOH or NaOH solution with a concentration of 0.5% to 10% for reaction; the reaction environment temperature is 50°C to 90°C, and the reaction time is controlled within 1 minute to 20 minutes, so that a pyramid-structured velvet surface is formed on both surfaces of the N-type single crystal silicon wafer.
3. The method for preparing a silicon-based heterojunction solar cell according to claim 1, wherein: The step of sequentially depositing a transparent conductive thin film layer and a copper seed layer on the exposed surfaces of the phosphorus-doped silicon layer and the boron-doped silicon layer comprises: The transparent conductive film layer and the copper seed layer are sequentially deposited by ion sputtering, wherein the transparent conductive film layer has a thickness range of 50nm-200nm and a refractive index of 1.6-2.5, and the copper seed layer has a thickness range of 10nm-150nm.
4. The method for preparing a silicon-based heterojunction solar cell according to claim 1, wherein: The method comprises electroplating copper gate lines in the gate line grooves, and sequentially removing the ink layer and the copper seed layer after preparing the copper gate lines to obtain a silicon wafer intermediate, comprising: Immersing the electroplated N-type silicon wafer in an alkaline mixed solution to remove the ink layer, wherein the alkaline mixed solution comprises a combination of one or more of potassium hydroxide solution and sodium hydroxide solution; The N-type silicon wafer with the ink layer removed is immersed in an acidic mixed solution to remove the copper seed layer except the copper grid line, wherein the acidic mixed solution includes a combination of one or more of dilute sulfuric acid solution and dilute nitric acid solution.
5. The method for preparing a silicon-based heterojunction solar cell according to claim 4, characterized in that: The step of immersing the electroplated N-type silicon wafer in an alkaline mixed solution to remove the ink layer comprises: The concentration of the alkaline mixed solution ranges from 3% to 20%, the solution temperature ranges from 30° C. to 70° C., the spraying pressure ranges from 0.8 kg to 3.0 kg, and the reaction time ranges from 10 seconds to 100 seconds.
6. The method for preparing a silicon-based heterojunction solar cell according to claim 4, characterized in that: The step of immersing the N-type silicon wafer from which the ink layer is removed in an acidic mixed solution to remove the copper seed layer other than the copper grid line comprises: An N-type silicon wafer is immersed in a dilute sulfuric acid aqueous solution containing an oxidant, wherein the oxidant includes a combination of one or more of hydrogen peroxide and potassium persulfate, and the oxidant concentration ranges from 0.5% to 5.0%. The dilute sulfuric acid concentration ranges from 0.5% to 10%, and the reaction time ranges from 5s to 100s. After removing the copper seed layer, the N-type silicon wafer is washed and dried.
7. The method for preparing a silicon-based heterojunction solar cell according to claim 1, wherein: The method comprises: performing light injection treatment on the silicon wafer intermediate, sequentially removing copper oxide from the surface of the silicon wafer intermediate after light injection by wet method, and depositing a tin layer on the surface of the copper grid line to obtain a copper grid line heterojunction solar cell, comprising: In the light injection process, the light injection illumination power range is 50W / m 2 -100000W / m 2 , the wavelength range of the light source is 500nm-1000nm, which can be a single wavelength light source in the sub-wavelength range or a common LED light source, the light injection time is between 20s-180s, and the temperature is 100℃-300℃; In the wet copper oxide removal process, a dilute sulfuric acid solution with a concentration range of 0.5%-3% is used to remove copper oxide on the surface of the silicon wafer intermediate, wherein the solution temperature range is 20°C-40°C and the reaction time range is 5s-30s.
8. The method for preparing a silicon-based heterojunction solar cell according to claim 7, characterized in that: The method further comprises: performing light injection treatment on the silicon wafer intermediate, sequentially removing copper oxide from the surface of the silicon wafer intermediate after light injection by wet method and depositing a tin layer on the surface of the copper grid line to obtain a copper grid line heterojunction solar cell; In the tin layer deposition process, a mixed solution including tin methanesulfonate, stannous sulfate, thiourea, sodium hypophosphite, and sulfuric acid is used to deposit a tin layer on the silicon wafer intermediate from which copper oxide has been removed, wherein the concentration range of the tin methanesulfonate is 0.5%-30%, the concentration range of the stannous sulfate is 1%-10%, and the concentration range of the thiourea is 0.1%-5%. The reaction temperature range is 20°C-60°C, and the reaction time is 20s-300s.
9. A heterojunction solar cell, characterized in that: The heterojunction solar cell is prepared by the preparation method of a silicon-based heterojunction solar cell according to any one of claims 1 to 9.
10. A photovoltaic module, characterized in that: include: A cell string formed by connecting a plurality of heterojunction solar cells formed by the method for preparing a silicon-based heterojunction solar cell according to any one of claims 1 to 8; A packaging film, used to cover the surface of the battery string; A cover plate is used to cover the surface of the packaging film facing away from the battery string.