LED chip capable of improving heat dissipation and slowly releasing stress and preparation method thereof

Abstract

The invention provides an LED chip capable of improving heat dissipation and slowly releasing stress and a preparation method thereof, a bonding layer, a heat conduction layer, a barrier layer, a protection layer, a reflection layer and an epitaxial layer are sequentially arranged on a substrate, the epitaxial layer comprises a p-type GaN layer, a multi-quantum well layer and an n-type GaN layer which are sequentially arranged in the direction away from the substrate, the barrier layer and the heat conduction layer realize electrical isolation between the protection layer and the bonding layer, the barrier layer realizes phosphoric acid corrosion resistance, the heat conduction layer realizes side wall passivation and heat conduction effects of the multi-quantum well layer, and slow release of stress is realized through the first stress release groove and the second stress release groove.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an LED chip with improved heat dissipation and stress relief, and a preparation method thereof. Background Art

[0002] Existing silicon substrate InGaN-based long-wavelength LED chips are mainly divided-line vertical structures, which have problems such as electrodes blocking light on the light-emitting surface, low chip light extraction efficiency, and poor current expansion performance under high current density. As a result, silicon substrate InGaN long-wavelength vertical structure LED chips have obvious limitations in high-power application scenarios. Long-wavelength LEDs have significant application needs in outdoor lighting, projection, display, automotive lighting and other fields, such as outdoor street lights, projectors, car headlights and other high-power lighting and display equipment. Therefore, there is an urgent need to solve the above problems.

[0003] Vertical via structures are currently widely used in high-power blue LED chips on sapphire and silicon substrates. They offer advantages such as excellent current spreading and high light extraction efficiency, making them the mainstream chip structure for high-power LED devices. However, their application to silicon-based InGaN-based long-wavelength LED chips currently faces numerous technical challenges. First, the high indium content in InGaN-based long-wavelength LEDs leads to significant internal stress in the epitaxial film. Silicon-based LED chip fabrication requires wafer bonding and debonding, while vertical via structures have a more complex p-face structure. After debonding, the epitaxial layer exhibits significant internal stress, which can lead to epitaxial layer cracking and electrical anomalies. Second, to fully isolate the n-electrode from the p-electrode and prevent chip short circuits, vertical via structures typically require a thick insulating layer to prevent chip short circuits and leakage. This insulating layer is typically made of dielectric materials, such as SiO2, which have a significant difference in thermal expansion coefficient from the InGaN epitaxial layer and metal, leading to significant internal stress in the chip after debonding.

[0004] Furthermore, unlike blue LED chips, which have high electro-optical conversion efficiency, low heat generation, and less demanding heat dissipation requirements, long-wavelength InGaN-based LED chips have lower electro-optical conversion efficiency due to the "yellow-green gap" effect. This results in higher heat generation under high current density operating conditions. Furthermore, the thicker insulating dielectric layer within the chip further worsens the heat dissipation environment of the silicon-based InGaN-based long-wavelength vertical through-hole LED chip, making the LED chip more susceptible to reliability issues. Therefore, compared to high-power blue LED chips with vertical through-hole structures, silicon-based InGaN-based long-wavelength LED chips with vertical through-hole structures have higher internal heat dissipation requirements. Furthermore, the fabrication process of silicon-based InGaN-based long-wavelength LED chips generally requires the use of hot phosphoric acid to etch the GaN epitaxial layer to isolate the epitaxial layers of adjacent chips. This requires that the material in direct contact with the GaN epitaxial layer in the grooves of adjacent chips be able to withstand hot phosphoric acid corrosion to prevent the hot phosphoric acid from penetrating into the chip interior, which in turn requires that the chip's insulating dielectric layer be resistant to hot phosphoric acid corrosion. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide an LED chip with improved heat dissipation and stress relief and a preparation method thereof, aiming to solve the problems of high internal stress and poor heat dissipation in InGaN-based long-wavelength LED chips with vertical through-hole structures on silicon substrates in the prior art.

[0006] According to an embodiment of the present invention, an LED chip with improved heat dissipation and stress relief is a silicon-based InGaN long-wavelength LED chip. The epitaxial layer growth substrate is a silicon substrate. The main emission wavelength range is 500nm-620nm. The LED chip includes a substrate and a bonding layer, a thermal conductive layer, a barrier layer, a protective layer, a reflective layer, and an epitaxial layer sequentially arranged on the substrate. The epitaxial layer includes a p-type GaN layer, a multi-quantum well layer, and an n-type GaN layer sequentially arranged in a direction away from the substrate. A passivation layer is provided on the surface of the epitaxial layer and on a portion of the barrier layer. The heat-conducting layer, the barrier layer, and the protective layer are in a step-like structure and are wrapped layer by layer, wherein the heat-conducting layer extends toward the n-type GaN layer to form an accommodation space embedded in the epitaxial layer, and an n-electrode is provided in the accommodation space, and the n-electrode is in contact with the n-type GaN layer; A groove formed by the passivation layer and the protective layer is provided on a side surface of the epitaxial layer, and a p-electrode is provided in the groove; During the preparation process, the stress is relieved by etching the epitaxial layer to obtain a first stress relief groove, and etching the thermal conductive layer to form a second stress relief groove.

[0007] Preferably, the barrier layer material is SiO2, and the barrier layer thickness is 50nm~300nm.

[0008] Preferably, the material of the thermal conductive layer is one or a combination of SiN, AlN, Al2O3, MgO, HfO2, and the thickness of the thermal conductive layer is 300nm~1500nm.

[0009] Preferably, the reflective layer material is one or a combination of Ni, Ag, Al, Au, Ti, and Pt, and the reflective layer has a thickness of 50 nm to 400 nm.

[0010] Preferably, the protective layer material is one or a combination of Cr, Pt, Au, Al, Ti, Ni, and TiW, and the thickness of the protective layer is 200 nm to 1200 nm. According to an embodiment of the present invention, a method for preparing an LED chip with improved heat dissipation and stress relief is provided, and the method comprises: Step S1, providing a silicon substrate, and sequentially growing an AlN buffer layer, a first n-type GaN layer, a first multi-quantum well layer, and a first p-type GaN layer on the surface of the silicon substrate; Step S2, preparing a reflective layer on the surface of the first p-type GaN layer, and preparing a protective layer on the surface of the reflective layer; Step S3, etching a portion of the first p-type GaN layer and the first multi-quantum well layer to expose the first n-type GaN layer, forming an n-electrode hole and a first stress relief trench; Step S4, preparing a barrier layer, etching a portion of the barrier layer, preparing a thermal conductive layer, etching a portion of the thermal conductive layer to expose the second n-type GaN layer, forming a second stress relief trench, and preparing an n-electrode; Step S5, preparing a bonding layer and bonding it to the substrate, peeling off the silicon substrate to expose the AlN buffer layer; Step S6, etching the AlN buffer layer and the second n-type GaN layer; Step S7, etching a portion of the initial hexagonal pyramidal n-GaN layer, the third n-type GaN layer, the second multi-quantum well light-emitting layer, and the second p-type GaN layer to expose the barrier layer and the protective layer, thereby preparing a passivation layer; Step S8, etching a portion of the passivation layer to expose the protective layer, preparing a p-electrode on the surface of the protective layer, and completing the preparation of the LED chip.

[0011] Preferably, after the step of providing a silicon substrate and sequentially growing an AlN buffer layer, a first n-type GaN layer, a first multi-quantum well layer, and a first p-type GaN layer on the surface of the silicon substrate, the step further includes: preparing a reflective layer on the surface of the p-type GaN layer; Etching a portion of the first p-type GaN layer and the first multi-quantum well layer to expose the first n-type GaN layer, forming an n-electrode hole and a third stress relief trench; While preparing an n-electrode on the exposed surface of the n-type GaN layer, a protective layer is prepared on the reflective layer; Prepare a barrier layer, etch a portion of the barrier layer, prepare a thermal conductive layer, etch a portion of the thermal conductive layer to expose the second n-type GaN layer, and form a second stress relief groove; Prepare a bonding layer and bond it to the substrate, peel off the silicon substrate to expose the AlN buffer layer; Etching the AlN buffer layer and the second n-type GaN layer; Etching the initial hexagonal pyramidal n-GaN layer, the third n-type GaN layer, the second multi-quantum well light-emitting layer, and the second p-type GaN layer in a portion of the area to expose the barrier layer and the protective layer, and prepare a passivation layer; The passivation layer in some areas is etched to expose the protective layer, and a p-electrode is prepared on the surface of the protective layer to complete the preparation of the LED chip.

[0012] Preferably, the etching in step S3 is dry etching, and the etching depth is 400 nm to 1500 nm.

[0013] Preferably, in step S5, the silicon substrate and the base plate are bonded by solid-liquid interdiffusion bonding.

[0014] Preferably, the etching methods in step S6 and step S7 are both wet etching.

[0015] An embodiment of the present invention provides an LED chip with improved heat dissipation and stress relief, and a preparation method thereof. The LED chip comprises a bonding layer, a thermal conductive layer, a barrier layer, a protective layer, a reflective layer, and an epitaxial layer sequentially arranged on a substrate. The epitaxial layer comprises a p-type GaN layer, a multi-quantum well layer, and an n-type GaN layer sequentially arranged in a direction away from the substrate. The barrier layer and the thermal conductive layer achieve electrical isolation between the protective layer and the bonding layer, the barrier layer achieves protection against phosphoric acid corrosion, the thermal conductive layer achieves sidewall passivation and thermal conductivity of the multi-quantum well layer, and stress relief is achieved through a first stress relief groove and a second stress relief groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the structure of LED chips to improve heat dissipation and relieve stress; Figure 2 Schematic diagram of the structure of the silicon substrate, AlN buffer layer, first n-type GaN layer, first multi-quantum well layer and first p-type GaN layer; Figure 3 This is a schematic diagram of the structure of depositing a reflective layer on the surface of the first p-type GaN layer; Figure 4 is a schematic diagram of a structure with a protective layer; Figure 5 is a schematic diagram of a structure having an n-electrode hole and a first stress relief groove; Figure 6 is a top view of the n-electrode hole and the first stress relief groove after etching; Figure 7 is a schematic diagram of a structure with a barrier layer; Figure 8 A schematic diagram of a structure having a heat-conducting layer and a second stress relief groove; Figure 9 is a schematic diagram of a structure having a bonding layer; Figure 10 Schematic diagram of the structure in which the silicon substrate is completely peeled off; Figure 11 Schematic diagram of the structure of n-GaN with initial hexagonal pyramidal shape; Figure 12 Schematic diagram of a structure with a passivation layer; Figure 13 A top view of a single chip; Figure 14 Schematic diagram of a structure having a reflective layer, an n-electrode hole and a third stress relief groove; Figure 15 A schematic diagram of the structure for preparing an n-electrode in an n-electrode hole and preparing a protective layer; Figure 16 It is a schematic diagram of a structure having a barrier layer, a heat conducting layer, an n-electrode and a second stress relief groove.

[0017] Component symbol description: Silicon substrate 1, AlN buffer layer 2, n-type GaN layer 33, multi-quantum well layer 42, p-type GaN layer 52, reflective layer 6, protective layer 7, n-electrode hole 8, first stress relief trench 9, barrier layer 10, thermal conductive layer 11, second stress relief trench 12, n-electrode 13, substrate 14, bonding layer 15, hexagonal pyramidal n-GaN 161, passivation layer 17, p-electrode 18, chip light-emitting surface 19, initial hexagonal pyramidal n-GaN 16, second n-type GaN layer 31, second p-type GaN layer 51, second multi-quantum well light-emitting layer 41, first n-type GaN layer 3, first multi-quantum well layer 4, first p-type GaN layer 5, third n-type GaN layer 32, third stress relief trench 91. DETAILED DESCRIPTION

[0018] The present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0019] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0021] Example 1 The first embodiment of the present invention provides an LED chip that improves heat dissipation and relieves stress. Figure 1 , which is a structural schematic diagram of an LED chip with improved heat dissipation and stress relief, wherein the LED chip with improved heat dissipation and stress relief includes a substrate 14 and a bonding layer 15, a thermal conductive layer 11, a barrier layer 10, a protective layer 7, a reflective layer 6 and an epitaxial layer sequentially arranged on the substrate 14, and the epitaxial layer includes a p-type GaN layer 52, a multi-quantum well layer 42 and an n-type GaN layer 33 sequentially arranged in a direction away from the substrate 14. It should be noted that the substrate is a 4-inch silicon substrate, and the substrate 14 is a metal substrate or a metal and semiconductor composite substrate. In the embodiment of the present invention, the substrate 14 is a 4-inch silicon and metal composite substrate.

[0022] Furthermore, the LED chip is a silicon-based InGaN long-wavelength LED chip with a main emission wavelength range of 500nm~620nm. In the embodiment of the present invention, the size of the prepared silicon substrate InGaN-based vertical through-hole structure LED chip is 1mm×1mm, and the main emission wavelength of the prepared silicon substrate InGaN-based vertical through-hole structure LED chip is 550nm under 350mA current injection.

[0023] Furthermore, the barrier layer 10 is made of SiO2, and the thickness of the barrier layer 10 is 50nm~300nm to prevent phosphoric acid corrosion. For example, the thickness of the barrier layer 10 is 50nm, 100nm, 150nm, 200nm, 250nm or 300nm, but is not limited thereto; the thermal conductive layer 11 is made of one or a combination of SiN, AlN, Al2O3, MgO, HfO2, and the thickness of the thermal conductive layer 11 is 300nm. m~1500nm, illustratively, the thickness of the thermal conductive layer 11 is 300nm, 400nm, 600nm, 800nm, 1000nm, 1200nm or 1500nm, etc., but not limited thereto; the material of the reflective layer 6 is one or a combination of Ni, Ag, Al, Au, Ti, Pt, and the thickness of the reflective layer 6 is 50nm~400nm, illustratively, the thickness of the reflective layer 6 is 50nm, 100nm, 150nm, 20 0nm, 250nm, 300nm or 400nm, etc., but not limited thereto. In an embodiment of the present invention, NiAgNiAg with a total thickness of 200nm is prepared on the surface of the p-type GaN layer by physical vapor deposition equipment as the reflective layer 6, and after preparation, the reflective layer 6 is annealed in N2 and O2 atmospheres to obtain better p-type ohmic contact performance; the protective layer 7 material is one or a combination of Cr, Pt, Au, Al, Ti, Ni, and TiW, and the protective layer 7 has a thickness of 200nm~1200nm. Exemplarily, the protective layer 7 has a thickness of 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, 1100nm or 1200nm, etc., but not limited thereto. In an embodiment of the present invention, CrPt with a total thickness of 400nm is prepared on the surface of the reflective layer 6 by physical vapor deposition equipment as the protective layer 7.

[0024] The side of the n-type GaN layer 33 away from the substrate is in the shape of a hexagonal pyramid, i.e., a hexagonal pyramidal n-GaN 161. The hexagonal pyramidal structure is used to improve the total reflection problem of the light-emitting surface of the LED chip, so as to improve the light extraction efficiency of the LED chip. A passivation layer 17 is provided on the surface of the epitaxial layer and part of the barrier layer 10. It can be understood that since the epitaxial layer is etched during the preparation process, the upper surface and side surface of the n-type GaN layer 33, the side surface of the multi-quantum well layer 42, and the side surface of the p-type GaN layer 52 are exposed, and the exposed parts are covered by depositing the passivation layer 17.

[0025] The thermal conductive layer 11, the barrier layer 10, and the protective layer 7 have a stepped structure and are wrapped layer by layer. It can be understood that the thermal conductive layer 11 wraps the barrier layer 10, the barrier layer 10 wraps the protective layer 7, and the protective layer 7 wraps the reflective layer 6. The thermal conductive layer 11 extends toward the n-type GaN layer 33 to form an accommodating space embedded in the epitaxial layer. One side of the accommodating space is the n-type GaN layer 33, and the other side is the bonding layer 15. An n-electrode 13 is provided in the accommodating space, and both ends of the n-electrode 13 are in contact with the n-type GaN layer 33 and the bonding layer 15, respectively. A groove formed by the passivation layer 17 and the protective layer 7 is provided on the side of the epitaxial layer, and a p-electrode 18 is provided in the groove, and the bottom of the p-electrode 18 is in contact with the protective layer 7; It should be noted that the substrate 14 is electrically connected to the bonding layer 15 , the n-electrode 13 , and the n-type GaN layer 33 ; and the p-electrode 18 is electrically connected to the protective layer 7 , the reflective layer 6 , and the p-type GaN layer 52 .

[0026] During the fabrication process, etching the epitaxial layer creates a first stress relief groove, which is used to release stress in the epitaxial layer to prevent cracking during wafer bonding and silicon substrate removal. Etching the thermally conductive layer 11 also creates a second stress relief groove, which separates the entire thermally conductive layer into independent dielectric layer blocks of chip size. This reduces stress concentration and wafer warpage caused by the mismatch in thermal expansion coefficients between the dielectric layer and the metal in the LED chip. Thermally conductive layer 11 uses an insulating material with high thermal conductivity to achieve sidewall passivation of the multi-quantum wells in the n-electrode holes and improve heat dissipation from the multi-quantum wells.

[0027] Example 2 The second embodiment of the present invention provides a method for preparing an LED chip with improved heat dissipation and stress relief, including steps S1 to S8. Specifically: In step S1 , a silicon substrate is provided, and an AlN buffer layer, a first n-type GaN layer, a first multi-quantum well layer, and a first p-type GaN layer are sequentially grown on the surface of the silicon substrate.

[0028] See also Figure 2 , which is a structural schematic diagram of a silicon substrate, an AlN buffer layer, a first n-type GaN layer, a first multi-quantum well layer, and a first p-type GaN layer. Specifically, an AlN buffer layer 2, a first n-type GaN layer 3, a first multi-quantum well layer 4, and a first p-type GaN layer 5 are sequentially grown on the surface of a silicon substrate 1 by metal organic chemical vapor deposition equipment. The well layer of the first multi-quantum well layer 4 is an InGaN layer, and the barrier layer is a GaN layer.

[0029] Step S2 , preparing a reflective layer on the surface of the first p-type GaN layer, and preparing a protective layer on the surface of the reflective layer.

[0030] See also Figure 3 , which is a schematic diagram of the structure of depositing a reflective layer on the surface of the first p-type GaN layer. Specifically, NiAgNiAg with a total thickness of 200 nm is deposited on the surface of the first p-type GaN layer 5 by physical vapor deposition equipment as a reflective layer 6. After preparation, the reflective layer is annealed in N2 and O2 atmospheres to obtain better p-type ohmic contact performance.

[0031] For further information, see Figure 4 , is a schematic diagram of a structure with a protective layer. Specifically, CrPt with a total thickness of 400 nm is prepared on the surface of the reflective layer 6 by physical vapor deposition equipment as a protective layer 7, and the protective layer 7 is in a stepped shape.

[0032] In step S3 , a portion of the first p-type GaN layer and the first multi-quantum well layer is etched to expose the first n-type GaN layer, thereby forming an n-electrode hole and a first stress relief trench.

[0033] See also Figure 5 , is a schematic diagram of a structure with an n-electrode hole and a first stress relief groove, wherein the etching in this step is dry etching, and the etching depth is 400nm~1500nm. Specifically, an inductively coupled plasma device is used to etch the first p-type GaN layer 5 and the first multi-quantum well layer 4 in a part of the area, exposing the first n-type GaN layer 3, obtaining the second p-type GaN layer 51, the second multi-quantum well light-emitting layer 41 and the second n-type GaN layer 31, and simultaneously forming the n-electrode hole 8 and the first stress relief groove 9, with an etching depth of 700nm. Please refer to Figure 6 , is a top view of the n-electrode hole and the first stress relief groove after etching.

[0034] Step S4, preparing a barrier layer, etching a portion of the barrier layer, preparing a thermal conductive layer, etching a portion of the thermal conductive layer to expose the second n-type GaN layer, forming a second stress relief groove, and preparing an n-electrode.

[0035] See also Figure 7 , is a schematic diagram of a structure with a barrier layer. Specifically, SiO2 with a thickness of 100 nm is prepared by atomic layer deposition equipment as an initial barrier layer (not shown) for blocking phosphoric acid corrosion in subsequent process steps. Then, a portion of the initial barrier layer is etched by hydrofluoric acid to obtain a barrier layer 10, exposing the n-electrode hole 8.

[0036] See also Figure 8, is a schematic diagram of a structure having a heat-conducting layer and a second stress-relieving groove. Specifically, a 500nm thick SiN is prepared as an initial heat-conducting layer (not shown) by plasma-enhanced chemical vapor deposition equipment, and the initial heat-conducting layer is partially etched using hydrofluoric acid to obtain a heat-conducting layer 11, exposing the second n-type GaN layer 31 and forming a second stress-relieving groove 12. Please refer to Figure 9 , is a schematic diagram of a structure with a bonding layer, in which a CrPtAu laminated metal with a total thickness of 1300 nm is deposited in the n-electrode hole 8 by a physical vapor deposition device as the n-electrode 13.

[0037] Step S5: prepare a bonding layer and bond it to the substrate, peel off the silicon substrate, and expose the AlN buffer layer.

[0038] like Figure 9 As shown, metal Cu with a thickness of 1000 nm is prepared on the surface by physical vapor deposition equipment, and metal In with a thickness of 700 nm is prepared on the surface of the substrate 14 by physical vapor deposition equipment. Temperature and pressure are applied by wafer bonding equipment to achieve bonding of metal Cu and metal In. During the bonding process, In melts into a liquid phase and fills the platform and groove in the chip under the action of external pressure, and reacts with Cu to form a CuIn alloy as a bonding layer 15. The bonding layer 15 fills the area formed by the thermal conductive layer 11 and the n-electrode 13.

[0039] See also Figure 10 , which is a structural diagram of complete peeling of the silicon substrate. Specifically, the silicon substrate 1 is thinned by mechanical grinding until the remaining silicon substrate 1 has a thickness of about 100 μm. Then, the remaining silicon substrate 1 is removed by a mixture of nitric acid, glacial acetic acid, and hydrofluoric acid until the AlN buffer layer 2 is exposed, thereby achieving complete peeling of the silicon substrate 1.

[0040] Step S6: etching the AlN buffer layer and the second n-type GaN layer.

[0041] See also Figure 11 , which is a schematic diagram of a structure with an initial hexagonal pyramidal n-GaN, wherein the etching in this step is a wet etching method, and a potassium hydroxide solution is used to etch the AlN buffer layer 2 and the second n-type GaN layer 31 to form a third n-type GaN layer 32 and the initial hexagonal pyramidal n-GaN 16.

[0042] Step S7 , etching a portion of the initial hexagonal pyramidal n-GaN, the third n-type GaN layer, the second multi-quantum well light-emitting layer, and the second p-type GaN layer to expose the barrier layer and the protective layer, and prepare a passivation layer.

[0043] See also Figure 12, a schematic diagram of a structure with a passivation layer. Specifically, a 140°C phosphoric acid solution is used to partially etch the initial hexagonal pyramidal n-GaN 16, the third n-type GaN layer 32, the second multi-quantum well light-emitting layer 41, and the second p-type GaN layer 51. This completely isolates adjacent chip epitaxial layers and exposes the chip's protective layer 7 and barrier layer 10. A 100nm-thick SiO2 passivation layer 17 is then grown using plasma-enhanced chemical vapor deposition. It should be noted that due to the presence of barrier layer 10 and protective layer 7, the hot phosphoric acid will not further etch other materials after etching the epitaxial layers.

[0044] Step S8, etching a portion of the passivation layer to expose the protective layer, preparing a p-electrode on the surface of the protective layer, and completing the preparation of the LED chip.

[0045] See also Figure 1 , which is a structural diagram of an LED chip for improving heat dissipation and relieving stress, wherein the etching in this step is wet etching. Specifically, hydrofluoric acid is used to etch the passivation layer 17 on the surface of the protective layer 7 to expose the protective layer 7, and then Au with a thickness of 1.2 μm is deposited on the surface of the protective layer 7 by physical vapor deposition equipment as the p-electrode 18.

[0046] It should be noted that the single chip obtained by laser scribing along the peripheral separation area of ​​the chip completes the preparation of the InGaN long wavelength LED chip. The top view of the single chip is as follows Figure 13 The p-electrode 18 is electrically connected to the protective layer 7, the reflective layer 6, and the p-type GaN layer 52, serving as the anode of the LED chip. The substrate 14 is electrically connected to the bonding layer 15, the n-electrode 13, and the n-type GaN layer 33, serving as the cathode of the LED chip.

[0047] In addition, the shape of the n-electrode hole 8 can be circular, quadrilateral, hexagonal or any combination of shapes, the arrangement of the n-electrode hole 8 can be rectangular, hexagonal or any arrangement, and the shape of the chip light-emitting surface 19 can be quadrilateral, hexagonal, circular or any shape.

[0048] Example 3 Embodiment 3 of the present invention provides a method for preparing an LED chip with improved heat dissipation and stress relief. The method differs from the method for preparing an LED chip with improved heat dissipation and stress relief provided in Embodiment 2 of the present invention in that steps S2 and S3 are swapped in sequence. After the swap, the n-electrode in step S4 is prepared simultaneously with the protective layer in step S2.

[0049] It should be noted that the method for preparing an LED chip with improved heat dissipation and stress relief provided in the third embodiment of the present invention includes the following steps: A reflective layer is prepared on the surface of the p-type GaN layer, wherein the reflective layer is NiAgNiAg; Etch part of the first p-type GaN layer and the first multi-quantum well layer to expose the first n-type GaN layer, forming an n-electrode hole and a third stress relief trench. For details, please refer to Figure 4 and Figure 14 , Figure 14 Schematic diagram of a structure having a reflective layer, an n-electrode hole, and a third stress relief groove, wherein, after forming the reflective layer 6, an inductively coupled plasma device is used to etch the first p-type GaN layer 5 and the first multi-quantum well layer 4 in a portion of the area to expose the first n-type GaN layer 3, thereby obtaining a second p-type GaN layer 51, a second multi-quantum well light-emitting layer 41, and a second n-type GaN layer 31, and simultaneously forming the n-electrode hole 8 and the third stress relief groove 91; While preparing the n-electrode on the exposed n-type GaN layer surface, a protective layer is prepared on the reflective layer. For details, please refer to Figure 15 , is a schematic diagram of the structure for preparing an n-electrode in an n-electrode hole and preparing a protective layer, wherein the n-electrode 13 does not need to be prepared separately, but is prepared simultaneously with the protective layer 7. After the n-electrode hole 8 is formed, the protective layer 7 is simultaneously prepared on the surface of the reflective layer 6 by physical vapor deposition equipment, and the n-electrode 13 is prepared in the n-electrode hole 8. The protective layer 7 and the n-electrode 13 are both CrPt with a thickness of 700nm. It can be understood that there is a certain gap between the inner wall of the n-electrode hole 8 and the n-electrode 13 for the subsequent preparation of the thermal conductive layer 11; Prepare a barrier layer, etch part of the barrier layer, prepare a thermal conductive layer, etch part of the thermal conductive layer to expose the n-electrode, and form a second stress relief groove. For details, please refer to Figure 16 , is a schematic diagram of a structure having a barrier layer, a thermal conductive layer, an n-electrode, and a second stress relief groove. Specifically, after forming the protective layer 7 and the n-electrode 13, the barrier layer 10 and the thermal conductive layer 11 are formed, and hydrofluoric acid is used to etch the barrier layer 10 and the thermal conductive layer 11 in a partial area to expose the n-electrode 13 and form the second stress relief groove 12; Prepare a bonding layer and bond it to the substrate, peel off the silicon substrate to expose the AlN buffer layer; Etching the AlN buffer layer and the second n-type GaN layer; Etching the initial hexagonal pyramidal n-GaN layer, the third n-type GaN layer, the second multi-quantum well light-emitting layer, and the second p-type GaN layer in a portion of the area to expose the barrier layer and the protective layer, and prepare a passivation layer; The passivation layer in some areas is etched to expose the protective layer, and a p-electrode is prepared on the surface of the protective layer to complete the preparation of the LED chip.

[0050] In summary, the LED chip with improved heat dissipation and stress relief and the preparation method thereof in the embodiments of the present invention are achieved by sequentially arranging a bonding layer, a thermal conductive layer, a barrier layer, a protective layer, a reflective layer and an epitaxial layer on a substrate, wherein the epitaxial layer includes a p-type GaN layer, a multi-quantum well layer and an n-type GaN layer sequentially arranged in a direction away from the substrate, wherein the barrier layer and the thermal conductive layer realize electrical isolation between the protective layer and the bonding layer, the barrier layer realizes blocking of phosphoric acid corrosion, and since the thermal conductive layer extends into the multi-quantum well layer, the sidewall passivation and thermal conductive effect of the multi-quantum well layer are realized, and stress relief is achieved through the first stress release groove and the second stress release groove.

[0051] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. An LED chip with improved heat dissipation and stress relief, characterized in that: The LED chip is a silicon-based InGaN long-wavelength LED chip. The epitaxial layer growth substrate is a silicon substrate. The main emission wavelength range is 500nm~620nm. It includes a substrate and a bonding layer, a thermal conductive layer, a barrier layer, a protective layer, a reflective layer and an epitaxial layer sequentially arranged on the substrate. The epitaxial layer includes a p-type GaN layer, a multi-quantum well layer and an n-type GaN layer sequentially arranged in a direction away from the substrate. A passivation layer is provided on the surface of the epitaxial layer and on part of the barrier layer. The heat-conducting layer, the barrier layer, and the protective layer are in a step-like structure and are wrapped layer by layer, wherein the heat-conducting layer extends toward the n-type GaN layer to form an accommodation space embedded in the epitaxial layer, and an n-electrode is provided in the accommodation space, and the n-electrode is in contact with the n-type GaN layer; A groove formed by the passivation layer and the protective layer is provided on a side surface of the epitaxial layer, and a p-electrode is provided in the groove; During the preparation process, the stress is relieved by etching the epitaxial layer to obtain a first stress relief groove, and etching the thermal conductive layer to form a second stress relief groove.

2. The LED chip with improved heat dissipation and stress relief according to claim 1, characterized in that: The barrier layer material is SiO2, and the barrier layer thickness is 50nm-300nm.

3. The LED chip with improved heat dissipation and stress relief according to claim 1, characterized in that: The thermal conductive layer material is one or a combination of SiN, AlN, Al2O3, MgO, HfO2, and the thickness of the thermal conductive layer is 300nm~1500nm.

4. The LED chip with improved heat dissipation and stress relief according to claim 1, wherein: The reflective layer material is one or a combination of Ni, Ag, Al, Au, Ti, and Pt, and the reflective layer thickness is 50 nm to 400 nm.

5. The LED chip with improved heat dissipation and stress relief according to claim 1, wherein: The protective layer material is one or a combination of Cr, Pt, Au, Al, Ti, Ni, and TiW, and the thickness of the protective layer is 200 nm to 1200 nm.

6. A method for preparing an LED chip with improved heat dissipation and stress relief, characterized in that: A method for preparing an LED chip with improved heat dissipation and stress relief according to any one of claims 1 to 5, comprising: Step S1, providing a silicon substrate, and sequentially growing an AlN buffer layer, a first n-type GaN layer, a first multi-quantum well layer, and a first p-type GaN layer on the surface of the silicon substrate; Step S2, preparing a reflective layer on the surface of the first p-type GaN layer, and preparing a protective layer on the surface of the reflective layer; Step S3, etching a portion of the first p-type GaN layer and the first multi-quantum well layer to expose the first n-type GaN layer, forming an n-electrode hole and a first stress relief trench; Step S4, preparing a barrier layer, etching a portion of the barrier layer, preparing a thermal conductive layer, etching a portion of the thermal conductive layer to expose the second n-type GaN layer, forming a second stress relief trench, and preparing an n-electrode; Step S5, preparing a bonding layer and bonding it to the substrate, peeling off the silicon substrate to expose the AlN buffer layer; Step S6, etching the AlN buffer layer and the second n-type GaN layer; Step S7, etching a portion of the initial hexagonal pyramidal n-GaN layer, the third n-type GaN layer, the second multi-quantum well light-emitting layer, and the second p-type GaN layer to expose the barrier layer and the protective layer, thereby preparing a passivation layer; Step S8, etching a portion of the passivation layer to expose the protective layer, preparing a p-electrode on the surface of the protective layer, and completing the preparation of the LED chip.

7. The method for preparing an LED chip with improved heat dissipation and stress relief according to claim 6, wherein: After the steps of providing a silicon substrate and sequentially growing an AlN buffer layer, a first n-type GaN layer, a first multi-quantum well layer, and a first p-type GaN layer on the surface of the silicon substrate, the following steps are further included: preparing a reflective layer on the surface of the p-type GaN layer; Etching a portion of the first p-type GaN layer and the first multi-quantum well layer to expose the first n-type GaN layer, forming an n-electrode hole and a third stress relief trench; While preparing an n-electrode on the exposed surface of the n-type GaN layer, a protective layer is prepared on the reflective layer; Prepare a barrier layer, etch a portion of the barrier layer, prepare a thermal conductive layer, etch a portion of the thermal conductive layer to expose the second n-type GaN layer, and form a second stress relief groove; Prepare a bonding layer and bond it to the substrate, peel off the silicon substrate to expose the AlN buffer layer; Etching the AlN buffer layer and the second n-type GaN layer; Etching the initial hexagonal pyramidal n-GaN layer, the third n-type GaN layer, the second multi-quantum well light-emitting layer, and the second p-type GaN layer in a portion of the area to expose the barrier layer and the protective layer, and prepare a passivation layer; The passivation layer in some areas is etched to expose the protective layer, and a p-electrode is prepared on the surface of the protective layer to complete the preparation of the LED chip.

8. The method for preparing an LED chip with improved heat dissipation and stress relief according to claim 6, wherein: The etching in step S3 is dry etching, and the etching depth is 400 nm to 1500 nm.

9. The method for preparing an LED chip with improved heat dissipation and stress relief according to claim 6, wherein: In step S5 , the silicon substrate and the base plate are bonded by solid-liquid interdiffusion bonding.

10. The method for preparing an LED chip with improved heat dissipation and stress relief according to claim 6, wherein: The etching methods in step S6 and step S7 are both wet etching, and the etching solution in step S7 is phosphoric acid solution.

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