Data transmission method for optical computing chip and upper computer

Abstract

The invention discloses a data transmission method for an optical computing chip and an upper computer, and the method comprises the steps: setting the frequency and initial level state of a serial clock signal by the upper computer during data transmission; the upper computer sends a serial clock signal to the optical computing chip by using a clock line; at the first jump edge of the serial clock signal, the sending end sends data in parallel through the plurality of data lines; at a second jump edge of the serial clock signal, the receiving end samples the data on the data line; the interval between the first jump edge and the second jump edge is a sampling interval, the sampling interval is N / 2 cycles, and N is a positive integer; wherein the jump edge is a position where the serial clock signal jumps from a high level to a low level or jumps from the low level to the high level. According to the invention, the transmission bandwidth of the existing serial interface protocol can be increased, and the data transmission efficiency of the optical computing chip and the upper computer is improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method for an optical computing chip to transmit data to a host computer. Background Art

[0002] Optical computing chips, a new type of computing device based on photonic technology, offer advantages such as high-speed parallel processing and low energy consumption. They hold great promise for applications in large-scale matrix operations and neural network acceleration. Debugging optical computing chips requires a host computer to read signals from the chip. Currently, communication between the host computer and the optical computing chip uses a serial peripheral interface.

[0003] As a synchronous serial communication protocol, the Serial Peripheral Interface (SPI) is widely used due to its simple structure and high transmission rate. The standard SPI uses a four-wire architecture and implements data transmission through a master-slave mode. However, it can only transmit one bit of data per clock cycle, resulting in limited bandwidth. For example, at a 100MHz clock frequency, the theoretical maximum transmission rate is only 100Mbps, which is insufficient for high-speed data acquisition.

[0004] Prior art Chinese patent application CN201910826017.5 discloses a data transmission method and system based on the SPI protocol. The data transmission method based on the SPI protocol includes the following steps: receiving SPI host computer data read by an SPI host computer via a host computer-side FPGA, wherein the SPI host computer data carries data read length information having a first predetermined number of bytes and register address information to be read; transmitting the SPI host computer data from the host computer-side FPGA to an optical computing chip-side FPGA via a communication link; caching SPI optical computing chip data read back by an SPI optical computing chip via the optical computing chip-side FPGA based on the data read length information and register address information in the SPI host computer data; and transmitting the SPI optical computing chip data from the optical computing chip-side FPGA to the host computer-side FPGA via the communication link to reply to the SPI host computer.

[0005] The above-mentioned existing technologies address latency through methods such as inserting invalid data and FPGA caching, but they do not break through the essence of SPI serial transmission and thus have limited bandwidth improvement. In large-scale communication scenarios, traditional communication methods will be unable to meet communication requirements. Summary of the Invention

[0006] The purpose of the present invention is to provide a data transmission method between an optical computing chip and a host computer, which partially solves or alleviates the above-mentioned deficiencies in the prior art, can increase the transmission bandwidth of the existing serial interface protocol, and improve the data transmission efficiency between the optical computing chip and the host computer.

[0007] In order to solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions: A first aspect of the present invention is to provide a method for data transmission between an optical computing chip and a host computer, wherein the connection between the optical computing chip and the host computer comprises: The clock line is used to send a serial clock signal from the host computer to the optical computing chip; the serial clock signal is a square wave, including alternating high and low levels; Several data lines for transmitting data in parallel; When data is transmitted, the host computer sets the frequency and initial level state of the serial clock signal; The host computer uses the clock line to send a serial clock signal to the optical computing chip; At the first transition edge of the serial clock signal, the transmitting end transmits data in parallel through the plurality of data lines; At the second transition edge of the serial clock signal, the receiving end samples the data on the data line; the interval between the first transition edge and the second transition edge is a sampling interval, and the sampling interval is N / 2 cycles, where N is a positive integer; The transition edge is the position where the serial clock signal transitions from a high level to a low level or from a low level to a high level.

[0008] Furthermore, the sampling interval is fixed to one cycle.

[0009] Furthermore, the number of the data lines is 2 n , n is a natural number.

[0010] Furthermore, the number of the data lines is 16, including D0 to D15.

[0011] Furthermore, the frequency of the serial clock signal is dynamically adjusted by the host computer according to data transmission requirements, and the adjustment range is 1 MHz-500 MHz.

[0012] Furthermore, it also includes an error detection line for transmitting error detection information during data transmission, such as parity bits or cyclic redundancy check codes; the receiving end checks the received data based on the error detection information, and if the check fails, the sending end is requested to resend the data.

[0013] Furthermore, a chip select line is included for sending a chip select signal from the host computer to the optical chip; Furthermore, the host computer can establish communication links with multiple optical computing chips at the same time, and select a certain optical computing chip through different chip select lines.

[0014] Furthermore, the data transmission between the transmitting end and the receiving end adopts a differential signal transmission mode.

[0015] Furthermore, data transmission includes full-duplex mode and half-duplex mode; In full-duplex mode transmission, at the same time, half of all data lines are sent from the host computer to the optical computing chip, and the other half are sent from the optical computing chip to the host computer; When transmitting in half-duplex mode, all data lines send data from the transmitter to the receiver at the same time.

[0016] In some embodiments, the optical computing chip has multiple computing units, and the computing units include: a modulator as a receiving end, and the host computer as a transmitting end. Correspondingly, the data transmission method further includes: S41, determining whether the proportion of the number of erroneous calculation units is less than a preset threshold proportion I; wherein, when the difference between the sampling signal received by the calculation unit and the reference signal is greater than a preset difference value, the calculation unit is identified as an erroneous calculation unit; If the answer to step S41 is yes, then execute: S42, identifying the erroneous calculation unit as an adjustment object; S43, expanding the sampling interval of the adjustment object from the current first sampling interval to the second sampling interval, that is, adjusting the sampling frequency; If the answer of step S41 is no, then execute: S44, dividing the calculation partitions according to the erroneous calculation units, and identifying the calculation partitions as adjustment objects; S45, extending the sampling interval of the adjustment object from the current first sampling interval to a third sampling interval; In some embodiments, the third sampling interval is greater than or equal to the second sampling interval.

[0017] In some embodiments, the method further comprises: The corresponding third sampling interval is selected according to the error density of the calculated partition.

[0018] In some embodiments, the method further comprises: Obtaining a signal switching frequency of the optical computing chip; When the signal switching frequency is greater than a preset first frequency threshold, increasing the current second sampling interval or third sampling interval; When the signal switching frequency is less than a preset second frequency threshold, the current second sampling interval or third sampling interval is reduced.

[0019] Beneficial technical effects: This invention, centered around a high-speed serial interface protocol between an optical computing chip and a host computer, encompasses data transmission methods and related systems, offering significant advantages in data transmission efficiency, reliability, and flexibility. Specifically, it transcends the limitations of traditional serial interface protocols, improves transmission performance, and adapts to a variety of application scenarios.

[0020] 1. Efficient data transmission efficiency.

[0021] This invention uses 2ⁿ (n is a natural number) data lines for parallel data transmission, for example, 16 data lines (D0-D15). This significantly improves data transmission bandwidth compared to the 1-4 data lines used in traditional serial interface protocols. At a 100MHz clock frequency, traditional serial interface protocols transmit one bit of data per cycle, with a theoretical rate of 100Mbps. This invention can transmit 16 bits of data in parallel, achieving a theoretical rate of 100MHz x 16 bits = 1600Mbps, 16 times the maximum rate of traditional serial interface protocols. This significantly reduces data transmission time and is suitable for high-speed data transmission scenarios.

[0022] The transmitter sends data on one serial clock signal transition edge, while the receiver samples data on the other, with a period between the two transition edges. Compared to traditional serial interface protocols that transmit and receive data on adjacent transition edges, this allows for more stable data transmission time, significantly improving timing margins and reducing data transmission errors. This allows the present invention to support higher clock frequencies, further increasing data transmission rates, even under the same hardware conditions.

[0023] The present invention also provides a method for dynamically adjusting the sampling interval. By dynamically adjusting the sampling interval according to the verification results of the receiving end, the sampling moment can be more accurately aligned with the stable range of the data, reducing data errors caused by improper sampling timing, thereby improving the accuracy and reliability of the collected data. It can adapt to different working conditions and data transmission situations. For example, when data transmission fails due to abnormalities or interference, the sampling interval can be automatically increased to leave more time for data transmission and processing, reducing the error rate; and when data transmission is stable and the number of successful verifications is high, reducing the sampling interval can collect data more intensively, fully utilizing the transmission bandwidth, improving data collection efficiency, and better adapting to the complex and changing communication environment between the optical chip and the host.

[0024] 2. Reliable data transmission guarantee.

[0025] The present invention features a dedicated error detection line for transmitting error detection information such as parity bits or cyclic redundancy check codes. The receiving end verifies the received data based on this information and requests the transmitting end to resend the data if the verification fails. This ensures accurate data transmission even in complex electromagnetic environments, effectively preventing system failures caused by data errors.

[0026] 3. Flexible working mode and adaptability.

[0027] This protocol supports both full-duplex and half-duplex modes. In full-duplex mode, half of the data lines are sent from the host computer to the optical computing chip at the same time, and the other half are sent from the optical computing chip to the host computer. This is suitable for real-time interaction scenarios, such as real-time data acquisition, where the host computer can simultaneously send sampling commands and receive data from the optical computing chip. In half-duplex mode, all data lines are sent from the transmitter to the receiver at the same time, which is suitable for batch data transmission and improves bandwidth utilization.

[0028] The host computer can establish communication links with multiple optical computing chips simultaneously and select each optical computing chip through different chip select lines. This enables efficient control of complex systems and enhances the system's scalability and applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the embodiments or the description of the prior art. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the various elements or parts are not necessarily drawn according to the actual scale. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without inventive work.

[0030] Figure 1 This is a flow chart of Example 2; Figure 2 Schematic diagram of data of a signal to be sampled in an exemplary embodiment of the present invention; Figure 3 FIG. 4 is a schematic diagram of the structure of an optical computing chip in an exemplary embodiment of the present invention.

[0031] Reference numerals: 101, transition edge; 102, high level; 103, low level; 104, input traveling waveguide; 105, output column line; 106, weight modulator; 107, calculation unit. DETAILED DESCRIPTION

[0032] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0033] Herein, suffixes such as "module," "component," or "unit" used to represent elements are only used to facilitate description of the present invention and have no specific meaning. Therefore, "module," "component," or "unit" may be used interchangeably.

[0034] As used herein, terms such as "upper," "lower," "inner," "outer," "front," "back," "one end," and "the other end" indicate positions or locations based on those shown in the accompanying drawings. These terms are intended solely to facilitate and simplify the description of the present invention and are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] As used herein, unless otherwise expressly specified or limited, the terms "installed," "provided with," and "connected" should be understood broadly. For example, "connected" may refer to a fixed connection, a detachable connection, or an integral connection; it may refer to a mechanical connection, a direct connection, an indirect connection via an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention on a case-by-case basis.

[0036] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] Herein, "plurality" means two or more than two, ie, it includes two, three, four, five, etc.

[0038] Example 1: like Figure 1 As shown, this embodiment provides a data transmission method between an optical computing chip and a host computer, wherein the connection between the optical computing chip and the host computer includes: The clock line is used to send a serial clock signal from the host computer to the optical computing chip; the serial clock signal is a square wave, including alternating high and low levels.

[0039] like Figure 2 As shown, the square wave consists of alternating high and low levels 102 and 103 of equal amplitude and width, with a typical duty cycle of 50%. Furthermore, the transition time between the high and low levels is extremely short, providing a clear timing reference point. In this embodiment, the frequency of the serial clock signal can be dynamically adjusted by the host computer based on data transmission requirements within a range of 1 MHz to 500 MHz to match the performance requirements of different peripherals.

[0040] Both the transmitter and receiver (the host computer and the optical computing chip can function as either transmitter or receiver, depending on their operating states) use the serial clock signal's transition edge 101 as their operating reference. A transition edge refers to the point where the serial clock signal transitions from a high level to a low level, or vice versa. A complete clock cycle (T) consists of one high level and one low level.

[0041] The chip select line is used to send chip select signals from the host computer to the optical computing chip.

[0042] The chip select line is controlled by the host computer, which determines the target optical computing chip to communicate with by sending a chip select signal. When the host computer wants to communicate with a specific optical computing chip, it pulls the chip select line of the corresponding optical computing chip low, indicating that the optical computing chip is selected. The chip select line of the unselected optical computing chip remains high.

[0043] In this embodiment, the host computer can simultaneously establish communication links with multiple optical computing chips, selecting each optical computing chip via different chip select lines. The presence of chip select lines enables the host computer to communicate with different optical computing chips in a time-sharing manner. For example, if the host computer is connected to three optical computing chips, corresponding to chip select lines SS1, SS2, and SS3, respectively, at a given moment, the host computer pulls SS1 low. Only the optical computing chip corresponding to SS1 is activated and can transmit data with the host computer, while the other two optical computing chips remain in a waiting state. This approach avoids conflicts caused by multiple optical computing chips simultaneously responding to host computer signals, ensuring accurate and stable communication.

[0044] Chip select signals are typically digital signals, with high or low levels representing different states. Regarding electrical characteristics, the chip select line's signal quality must be ensured to prevent signal interference and unstable levels, which could lead to misselection of the optical computing chip or communication errors. During wiring, the chip select line's routing must be carefully planned to avoid excessive interference with other signal lines.

[0045] Several data lines are used to transmit data in parallel. In this embodiment, the number of the data lines is 2 n , n is a natural number. More specifically, the number of the data lines is 16, including D0 to D15.

[0046] In terms of data transmission efficiency, compared to traditional serial interface protocols with only two data lines, 16 data lines can transmit 16 bits of data in parallel per clock cycle, significantly improving transmission bandwidth. At a clock frequency of 100MHz, traditional serial interface protocols transmit one bit of data per cycle (full-duplex mode), with a theoretical transmission rate of 100Mbps. However, with 16 bits of parallel transmission, the theoretical transmission rate can reach 100MHz × 16 bits = 1600Mbps, which is 16 times the maximum speed of traditional SPI.

[0047] In addition, this embodiment also includes an error detection line for transmitting error detection information during data transmission, such as a parity bit or a cyclic redundancy check code; the receiving end checks the received data based on the error detection information, and if the check fails, the sending end is requested to resend the data.

[0048] Unlike traditional serial interfaces that mix parity bits with data, this protocol uses an independent error detection line to transmit parity information. It supports multiple parity algorithms, such as parity and CRC.

[0049] In this embodiment, both the sending end and the receiving end are provided with a data buffer for caching data to be sent or received; when the data buffer is full, the sending end suspends sending data; when the data buffer is empty, the receiving end suspends receiving data.

[0050] Data buffers on the sending and receiving ends, respectively, are responsible for caching data to be sent and received data. The sending end's buffer temporarily stores data to be sent and sends it over the data line at the appropriate time, following a specific sequence and protocol. The receiving end's buffer temporarily stores received data pending subsequent processing.

[0051] When the data buffer is full, the sender suspends sending data; when the data buffer is empty, the receiver suspends receiving data. This constitutes a flow control mechanism. Without this mechanism, the sender could continue sending data when the receiver is slow to process data, potentially leading to data loss. When the sender's buffer is full but the receiver has not yet processed previously received data, pausing sending prevents data overflow. On the receiver side, pausing reception when the buffer is empty prevents the receiver from blindly accepting data when it lacks sufficient processing power, thus ensuring orderly data processing.

[0052] In this embodiment, data transmission between the host computer and the optical computing chip includes full-duplex mode and half-duplex mode; When full-duplex mode transmission is performed, at the same time, half of all data lines are sent from the host computer to the optical computing chip, and the other half are sent from the optical computing chip to the host computer.

[0053] Specifically, the 16 data lines D0-D15 are divided into two groups: the transmit group (D0-D7) from the host computer to the optical computing chip, and the receive group (D8-D15) from the optical computing chip to the host computer. Each data line is equipped with a bidirectional buffer to support bidirectional data flow. Each direction receives 8 data bits, allowing 16 bits of data to be transmitted in both directions in a single cycle.

[0054] When transmitting in half-duplex mode, all data lines send data from the transmitter to the receiver at the same time.

[0055] Specifically, all 16-bit data lines are obtained during unidirectional transmission, and 16-bit data can be transmitted in a single cycle. The host computer → optical computing chip sending group is 16 data lines, namely D0~D15.

[0056] Full-duplex and half-duplex modes are dynamically configured. The host computer sets the operating mode via control registers. When a mode switch is required, a command is sent to the optical computing chip. Both parties reconfigure the data line direction, synchronize the clock phase, and begin data transmission in the new mode.

[0057] When performing data transmission, the specific steps include: The S1 host computer sets the frequency and initial level state of the serial clock signal.

[0058] Frequency determines the data transmission rate. For scenarios requiring high transmission speed, the frequency can be set to a higher value within the protocol's limits, such as 500MHz, to speed up data transmission. For scenarios requiring higher stability and relatively lower speeds, a lower frequency, such as 1MHz, can be selected. The initial level state setting is also critical; it provides a starting reference for subsequent transitions, ensuring that both the transmitter and receiver are in a clear state before data transmission, thus avoiding data transmission errors caused by uncertain initial states.

[0059] The S2 host computer selects the target optical computing chip through the chip select line.

[0060] In a multi-optical computing chip system, the host computer must select a specific communication partner from among the numerous optical computing chips. Only the selected optical computing chip can exchange data with the host computer. This method avoids conflicts caused by multiple optical computing chips responding to host computer signals simultaneously, ensuring accurate and stable communication and orderly data transmission.

[0061] S3 At the first transition edge of the serial clock signal, the host computer or the optical computing chip acts as a transmitter and sends data in parallel through the plurality of data lines.

[0062] Data transmission on the first transition edge fully utilizes the parallel transmission feature of the protocol. If there are 16 data lines, the transmitter can send all 16 bits of data simultaneously at this instant, greatly improving data transmission efficiency. Compared to traditional serial bit-by-bit transmission, parallel transmission can transmit more data in the same time, meeting the requirements of high-speed data transmission.

[0063] S4 At the second transition edge of the serial clock signal, the host computer or optical computing chip acts as the receiving end to sample the data on the data line; the interval between the first transition edge and the second transition edge is the sampling interval, and the sampling interval is N / 2 cycles, where N is a positive integer.

[0064] In some embodiments, the sampling interval is fixed to one cycle.

[0065] When sending data, the sending end sends data through the data line at a serial clock signal transition edge; the receiving end samples the data on the data line at another serial clock signal transition edge; the interval between the first transition edge and the second transition edge is the sampling interval, and the sampling interval is N / 2 cycles, where N is a positive integer; in this embodiment, the sampling interval between the transition edge of the sending data and the transition edge of the receiving data is one cycle.

[0066] In traditional serial interface protocols, data transmission and sampling occur on adjacent clock edges, such as rising edge transmission and falling edge sampling. Data setup time + hold time ≈ half a clock cycle (T / 2). As clock frequencies increase, T / 2 shortens, making it susceptible to routing delays and device jitter, leading to sampling errors. At a 100MHz clock, T = 10ns, leaving only 5ns of available timing margin. This requires strict control of register rollover delays on the transmitter side, PCB routing delays, and the sampling window on the receiver side, making adjustments challenging.

[0067] In this embodiment, the protocol separates the sending and sampling operations into one cycle. The rising edge of t0 drives the signal change on the data line, and the rising edge of t1 (one full cycle apart) samples the data. This way, the data setup time + hold time ≈ the entire clock cycle (T), providing ample timing margin.

[0068] Large-size optical chips such as Figure 2 As shown, it includes several computing units (each intersection in the figure can be regarded as a computing unit). When weight switching is involved, it is necessary to adjust the weights of n*n computing units. Accurate adjustment of weights is crucial to the results of AI training or reasoning.

[0069] It is understood that the present invention can provide a hierarchical communication strategy for the weight switching scenario of large-scale optical computing chips, and this hierarchical communication strategy can be adaptively adjusted in combination with application requirements. To this end, the following will explain the exemplary process of the hierarchical communication strategy through another embodiment: It is worth noting that the present invention actually provides a dynamic adjustment mechanism that dynamically selects the sampling jump edge based on the global operating status of the optical computing chip. This dynamic adjustment of the sampling jump edge can not only improve the reliability of large-scale signal transmission under large-scale optical computing chips, but also alleviate or avoid the excessive pressure caused by large-scale signal transmission on communication.

[0070] The following describes the weight adjustment process of the present invention applied to a large-scale optical computing chip, taking the host computer as the signal transmitter and the modulator of the optical computing chip (also referred to as: optical chip, computing chip) as the receiver as an example: Large-size optical chips (or large-scale optical chips) such as Figure 3 As shown, the optical chip includes several computing units (each intersection in the figure can be considered a computing unit). Specifically, the optical chip includes: N rows of input waveguides 104, and N columns of output column lines 105 (such as waveguides or electrical buses) that intersect with the N rows of input waveguides 104. N*N computing units 107 are formed at the intersection of the N rows of input waveguides 104 and the N columns of output column lines 105. The computing unit is provided with a weight modulator. The weight modulator 106 is used to modulate the input optical signal received by the computing unit using a modulation signal (such as the optical power of the modulated optical signal) to output a modulated signal (equivalent to the calculation signal) as the calculation result. The modulation signal can be an external electrical signal.

[0071] Specifically, the host computer can send N*N serial clock signals to the N*N computing units of the optical chip, and the N*N weight modulators 106 collect the serial clock signals according to the set sampling jump edge position (such as time node) to convert / generate a modulation signal (also called a sampling signal).

[0072] Preferably, the present invention includes the step of implementing a hierarchical communication strategy according to the degree of error, which includes: S41, determining whether the proportion of the number of erroneous calculation units is less than a threshold proportion I; wherein, when the degree of difference (such as the difference ratio) between the sampled signal (particularly, the collected weight switching signal) received by the calculation unit and the reference signal is greater than a preset difference value, the calculation unit is identified as an erroneous calculation unit; If the answer to step S41 is yes, then execute: S42, identifying the erroneous calculation unit as an adjustment object; S43, expanding the sampling interval of the adjustment object from the current first sampling interval to the second sampling interval, that is, adjusting the sampling frequency; For example, the sampling interval may be expanded from 0.5 cycles (equivalent to the first sampling interval) to 1.0 cycles (equivalent to the second sampling interval).

[0073] If the answer of step S41 is no, then execute: S44, dividing the calculation partitions according to the erroneous calculation units, and identifying the calculation partitions as adjustment objects; S45: Extend the sampling interval of the adjustment object from the current first sampling interval to a third sampling interval.

[0074] For example, the sampling interval may be expanded from 0.5 cycles to 1.5 cycles.

[0075] This embodiment proposes a low-scale dynamic adjustment mechanism for sampling intervals (i.e., a low-scale adjustment mechanism) for large-scale optical computing chips. Through localized dynamic adjustments, this mechanism improves signal transmission accuracy while reducing the overall signal switching pressure on the chip (i.e., reducing the pressure to adjust the sampling period). In other words, the low-scale adjustment mechanism proposed by this invention can reduce the additional adjustment burden on large-scale optical computing chips.

[0076] Preferably, in some embodiments, the third sampling interval is greater than or equal to the second sampling interval.

[0077] Preferably, in some embodiments, the third sampling interval is greater than the second sampling interval.

[0078] For example, in some embodiments, the step of dividing the computing partitions in S44 includes: Identifying an interval between at least two of the error calculation units, and when the interval is less than a preset interval threshold, grouping the two error calculation units into an error set; traversing all the error calculation units to form at least one error set; When the number of units in the error set is greater than the first threshold, a region generation step is performed, the region generation step including: Connecting edge error calculation units in the error set to form a target line, wherein the edge error calculation unit is a calculation unit located at the outermost periphery of the plurality of error calculation units; A target area is formed according to the target line, wherein the computing units passed by the target line and the computing units covered by the target line are defined as belonging to the target area; the target area can be defined as the computing partition.

[0079] Alternatively, in another exemplary embodiment, the calculation partitions may be formed by expanding outwards by a certain length or width from the target region as a core region. For example, when the density of erroneous calculation units in the target region is high, the adjusted calculation partitions may be expanded to reduce the risk of overheating through a wider range of adjustments.

[0080] In an exemplary embodiment, the size of the computing partition can be adaptively set by the user based on actual application requirements, such as the size of the optical computing chip and the requirements for communication quality.

[0081] That is, in this embodiment, when the number of erroneous calculation units in a certain area is relatively large, the regional sampling interval adjustment is performed.

[0082] In some embodiments, the computational partition can also be directly a single optical computing chip. In this embodiment, the dynamic adjustment mechanism can monitor and adjust signal acquisition for multiple optical computing chips. For example, the sampling intervals used by different optical computing chips can be dynamically adjusted based on their signal acquisition conditions (e.g., the number / ratio of erroneous computational units).

[0083] Furthermore, in some embodiments, the method further comprises the steps of: The corresponding third sampling interval is selected according to the error density of the calculated partition.

[0084] For example, in some embodiments, the error density is the proportion of erroneous computing units in the computing partition. Correspondingly, when the error density is relatively large, the corresponding third sampling interval may also be longer.

[0085] It can be understood that this embodiment is equivalent to providing a sampling period adjustment mechanism for the differences of different error sets. This difference adjustment mechanism can alleviate the risk of over-adjustment, that is, avoid the stability or reliability of the collected signal being reduced due to the sampling interval being too large.

[0086] From another perspective, the present invention provides an evaluation mechanism for local single-point adjustment (i.e., only adjusting the erroneous computing unit) and local area adjustment (i.e., adjusting the computing partition) to improve the computing reliability of the optical computing chip without increasing the adjustment pressure of the optical computing chip.

[0087] It's worth noting that optical computing chips, especially during AI training, may face frequent weight switching among their n*n computing units, each of which performs its own computational tasks. This means that optical computing chips face significant data processing pressure and are prone to overheating over extended periods of time. The low-scale dynamic adjustment mechanism proposed in this paper can effectively mitigate the impact of chip thermal noise on signal acquisition quality.

[0088] Specifically, the low-scale dynamic adjustment mechanism proposed in this invention can implement targeted regional feedback strategies for areas at risk of error. This allows for regional pre-adjustment at the onset of potential local overheating risks (e.g., when temperatures continue to rise, potentially leading to signal sampling errors in unit devices). Furthermore, this low-scale dynamic adjustment mechanism rationally selects the adjustment scale and amplitude, reducing the pressure on large-scale optical computing chips to adjust the sampling period, thereby minimizing the impact of sampling period adjustments on the chip's overall signal acquisition quality.

[0089] In this embodiment, the method can identify an erroneous calculation unit (or referred to as a first erroneous calculation unit) in a first period, and adjust the sampling interval of the adjustment object in a second period (such as expanding it from the current first sampling interval to the second sampling interval or the third sampling interval).

[0090] Furthermore, after the sampling interval of the adjustment object is expanded to the second sampling interval or the third sampling interval, the present invention further comprises the steps of: During the second period, a second erroneous calculation unit (i.e., the current erroneous calculation unit) continues to be identified; Calculating a difference in the number of the first error calculation unit and the second error calculation unit; When the quantity difference is greater than or equal to a first preset threshold, it is recommended to maintain the current sampling interval; When the quantity difference is less than the first preset threshold, it is recommended to expand the calculation partition.

[0091] Furthermore, in some embodiments, before adjusting the sampling interval, the method further includes the following steps: Obtaining the signal switching frequency (i.e., weight switching frequency) of the optical computing chip; When the signal switching frequency is greater than a preset first frequency threshold, increasing the current second sampling interval or third sampling interval; When the signal switching frequency is less than a preset second frequency threshold, the current second sampling interval or third sampling interval is reduced.

[0092] That is to say, in this embodiment, when the weight switching of the large-scale optical computing chip is more frequent (such as in the AI ​​model training scenario), you can try to increase the amplitude of the sampling period adjustment; when the weight switching frequency of the optical computing chip is less (such as in the AI ​​reasoning scenario), you can try to reduce the amplitude of the sampling period adjustment.

[0093] The present invention is based on multi-dimensional coordinated adjustment among adjustment scale, amplitude and weight switching frequency. It can ensure data accuracy by fine-tuning the limited scale of the sampling period, while avoiding the additional computing overhead and communication delay caused by frequent adjustment of the sampling interval.

[0094] In some embodiments, a preset sampling interval period table may be set for different error types or scenarios, and the corresponding sampling interval period may be found in combination with the adjustment object type (such as computing unit or computing partition) or error trend (such as error density).

[0095] Applicants note that signal acquisition errors can often exceed normal ranges due to factors such as optical link temperature variations and clock drift. In some embodiments, when the receiving end fails verification M times in a row, it can attempt to add 0.5 cycles to the current sampling interval as the next sampling interval. When the receiving end succeeds verification K times in a row, the current sampling interval is applied to actual data sampling.

[0096] For example, in some embodiments, when the verification fails for M consecutive times, for example, 5 times, it indicates that the current sampling timing may deviate from the data stability window. By increasing the interval of 0.5T, that is, N=N+1, the sampling point is moved back, the timing margin is expanded, and the signal offset caused by delay or jitter is gradually covered.

[0097] When the receiving end succeeds in K consecutive verifications (e.g., K=10), it is determined that the data is stable under the current interval, and the verified interval parameters are extended to the real data sampling, ending the test mode.

[0098] In summary, the current chip industry's pursuit of miniaturization in optical chips has resulted in extremely high device density, making them susceptible to overheating and potentially leading to inaccurate calculations. Furthermore, chip performance can degrade over time, potentially causing weight switching failures. To address this, the proposed method of implementing different communication strategies based on the severity of errors helps ensure stable data transmission.

[0099] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0100] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a computer terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0101] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A data transmission method between an optical computing chip and a host computer, characterized in that: The connection between the optical computing chip and the host computer includes: The clock line is used to send a serial clock signal from the host computer to the optical computing chip; the serial clock signal is a square wave, including alternating high and low levels; Chip select line, used for sending chip select signal from host computer to optical chip; Several data lines for transmitting data in parallel; Correspondingly, the method includes: When transmitting data, the host computer sets the frequency and initial level state of the serial clock signal; The host computer uses the clock line to send a serial clock signal to the optical computing chip; At the first transition edge of the serial clock signal, the transmitting end transmits data in parallel through the plurality of data lines; At the second transition edge of the serial clock signal, the receiving end samples the data on the data line; the interval between the first transition edge and the second transition edge is a sampling interval, and the sampling interval is N / 2 cycles, where N is a positive integer; The transition edge is the position where the serial clock signal transitions from a high level to a low level or from a low level to a high level.

2. The data transmission method between an optical computing chip and a host computer according to claim 1, characterized in that: The sampling interval is fixed at 0.5 cycles, or the sampling interval is fixed at 1 cycle.

3. The data transmission method between an optical computing chip and a host computer according to claim 1, characterized in that: The number of the data lines is 2n, where n is a natural number; And / or, the number of the data lines is 16, including D0-D15.

4. The data transmission method between an optical computing chip and a host computer according to claim 1, characterized in that: The frequency of the serial clock signal is dynamically adjusted by the host computer according to data transmission requirements, and the adjustment range is 1MHz-500MHz.

5. The data transmission method between an optical computing chip and a host computer according to claim 1, characterized in that: It also includes an error detection line for transmitting error detection information during data transmission; the receiving end verifies the received data based on the error detection information, and requests the sending end to resend the data if the verification fails; And / or, it also includes a chip select line, which is used for the host computer to send a chip select signal to the optical chip.

6. The data transmission method between an optical computing chip and a host computer according to claim 5, characterized in that: The host computer can establish communication links with multiple optical computing chips at the same time, and select a certain optical computing chip through different chip select lines; and / or, data transmission includes a full-duplex mode and a half-duplex mode; In full-duplex mode transmission, at the same time, half of all data lines are sent from the host computer to the optical computing chip, and the other half are sent from the optical computing chip to the host computer; When transmitting in half-duplex mode, all data lines send data from the transmitter to the receiver at the same time.

7. The data transmission method between an optical computing chip and a host computer according to claim 1, characterized in that: The optical computing chip has multiple computing units, and the computing units include: a modulator as a receiving end, and the host computer as a transmitting end. Correspondingly, the data transmission method also includes: S41, determining whether the proportion of the number of erroneous calculation units is less than a preset threshold proportion I; wherein, when the difference between the sampling signal received by the calculation unit and the reference signal is greater than a preset difference value, the calculation unit is identified as an erroneous calculation unit; If the answer to step S41 is yes, then execute: S42, identifying the erroneous calculation unit as an adjustment object; S43, extending the sampling interval of the adjustment object from the current first sampling interval to a second sampling interval; If the answer of step S41 is no, then execute: S44, dividing the calculation partitions according to the erroneous calculation units, and identifying the calculation partitions as adjustment objects; S45: Extend the sampling interval of the adjustment object from the current first sampling interval to a third sampling interval.

8. The data transmission method between an optical computing chip and a host computer according to claim 7, characterized in that: The third sampling interval is greater than or equal to the second sampling interval.

9. The data transmission method between an optical computing chip and a host computer according to claim 7 or 8, characterized in that: The method further comprises: The corresponding third sampling interval is selected according to the error density of the calculated partition.

10. The data transmission method between an optical computing chip and a host computer according to claim 7 or 8, characterized in that: The method further comprises: Obtaining a signal switching frequency of the optical computing chip; When the signal switching frequency is greater than a preset first frequency threshold, increasing the current second sampling interval or third sampling interval; When the signal switching frequency is less than a preset second frequency threshold, the current second sampling interval or third sampling interval is reduced.

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