Double-track power supply control method and power management chip

Abstract

The embodiment of the invention provides a double-track power supply control method and a power management chip. The method comprises the following steps: receiving a first signal sent by a system on chip (SOC); determining a receiving sequence corresponding to the first signal according to the first signal and the historical receiving information; judging whether the receiving sequence corresponding to the first signal meets a preset priority sequence or not; under the condition that the receiving sequence corresponding to the first signal meets a preset priority sequence, controlling a processor CPU or a static random access memory SRAM to sleep or wake up according to the first signal and a preset corresponding relation; under the condition that the receiving sequence corresponding to the first signal does not meet the preset priority sequence, continuously monitoring for a first preset duration to obtain a second signal; according to the method, the CPU or the control SRAM is controlled to be dormant or awakened according to the second signal, and then the CPU or the control SRAM is controlled to be dormant or awakened according to the first signal, so that the endurance of the electronic equipment can be improved.

Description

Technical Field

[0001] The present application relates to the field of power gating technology, and in particular to a dual-rail power supply control method and a power management chip. Background Art

[0002] With the advancement of technology, electronic devices are becoming increasingly ubiquitous. Mobile phones, laptops, and other electronic devices, in particular, have become essential for people's work and daily lives. Simultaneously, as the performance of electronic devices improves, the power consumption of functional modules such as processors is also increasing, placing greater pressure on the battery life of these devices. Furthermore, a system-on-chip (SoC), a purpose-built integrated circuit (IC), encompasses a complete system and all embedded software. Signal recognition and processing by the SoC can identify the operating status of the system and its functional modules, thereby facilitating further energy conservation. Therefore, how to reduce the power consumption of functional modules such as processors and improve the battery life of electronic devices through the SoC has become an urgent issue. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to provide a dual-rail power supply control method and a power management chip to solve the problem of how to reduce the power consumption of functional modules such as processors. The specific technical solution is as follows: In a first aspect of an embodiment of the present application, a dual-rail power supply control method is provided, which is applied to a power management chip PMIC. The method includes: Receive a first signal sent by a system chip (SOC), wherein the first signal includes one of a system sleep SYS_SLP power-on signal, a SYS_SLP power-off signal, a core power domain control CORE_PD power-off signal, and a CORE_PD power-on signal; Determine, according to the first signal and historical reception information, a reception order corresponding to the first signal, wherein the historical reception information includes: historical reception information of each of the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on information; Determine whether a reception order corresponding to the first signal satisfies a preset priority order, wherein the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-up signal takes precedence over the CORE_PD power-up signal; When the reception order corresponding to the first signal satisfies the preset priority order, controlling the processor CPU or the static random access memory SRAM to sleep or wake up according to the first signal and the preset correspondence, wherein the preset correspondence includes: controlling the SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling the SRAM to sleep in response to the SYS_SLP power-down signal, and controlling the CPU to sleep in response to the CORE_PD power-down signal; When the receiving order corresponding to the first signal does not meet the preset priority order, continue to monitor the first preset time length to obtain the second signal; first control the CPU or SRAM according to the second signal to sleep or wake up, and then control the CPU or SRAM according to the first signal to sleep or wake up.

[0004] In a possible implementation, determining the reception order corresponding to the first signals according to the first signals and historical reception information includes: In a case where the first signal is a SYS_SLP power-off signal, determining, based on the historical reception information, whether a CORE_PD power-off signal is received within a previous second preset time period; if so, the reception order corresponding to the first signal is that the CORE_PD power-off signal is prioritized; if not, the reception order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized; In a case where the first signal is a CORE_PD power-on signal, determining, based on the historical reception information, whether a SYS_SLP power-on signal is received within a previous second preset time period; if so, the receiving order corresponding to the first signal is that the SYS_SLP power-on signal is prioritized; if not, the receiving order corresponding to the first signal is that the CORE_PD power-on signal is prioritized; In a case where the first signal is a CORE_PD power-off signal, determining, based on the historical reception information, whether a SYS_SLP power-off signal is received within a previous second preset time period; if so, the receiving order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized; if not, the receiving order corresponding to the first signal is that the CORE_PD power-off signal is prioritized; In the case that the first signal is a SYS_SLP power-on signal, determine whether a CORE_PD power-on signal is received within the previous second preset time period based on the historical reception information; if so, the receiving order corresponding to the first signal is that the CORE_PD power-on signal is prioritized; if not, the receiving order corresponding to the first signal is that the SYS_SLP power-on signal is prioritized.

[0005] In a possible implementation, determining whether the reception order of the first signals satisfies a preset priority order includes: If the first signal is a CORE_PD power-down signal, if the reception order corresponding to the first signal is CORE_PD power-down signal priority, it is determined that the condition is satisfied; if the first signal is a CORE_PD power-on signal, if the reception order corresponding to the first signal is SYS_SLP power-on signal priority, it is determined that the condition is satisfied; if the first signal is a SYS_SLP power-on signal, if the reception order corresponding to the first signal is SYS_SLP power-on signal priority, it is determined that the condition is satisfied; if the first signal is a SYS_SLP power-down signal, if the reception order corresponding to the first signal is CORE_PD power-down signal priority, it is determined that the condition is satisfied; In the case where the first signal is a CORE_PD power-on signal, if the receiving order corresponding to the first signal is that the CORE_PD power-on signal is prioritized, it is determined that it is not satisfied; in the case where the first signal is a SYS_SLP power-off signal, if the receiving order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized, it is determined that it is not satisfied.

[0006] In one possible implementation, the second signal is a SYS_SLP power-on signal or a CORE_PD power-off signal, and the first signal is a SYS_SLP power-off signal or a CORE_PD power-on signal; and the first step of controlling the CPU or SRAM to enter sleep or wake-up according to the second signal and then controlling the CPU or SRAM to enter sleep or wake-up according to the first signal includes: When the first signal is a CORE_PD power-on signal, the receiving order of the first signal is that the CORE_PD power-on signal is prioritized, and when the second signal is a SYS_SLP power-on signal, the SRAM is first controlled to wake up according to the SYS_SLP power-on signal, and then the CPU is controlled to wake up according to the CORE_PD power-on signal; When the first signal is a SYS_SLP power-off signal, the receiving order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized, and the second signal is a CORE_PD power-off signal, the CPU is first controlled to sleep according to the CORE_PD power-off signal, and then the SRAM is controlled to sleep according to the SYS_SLP power-off signal.

[0007] In a possible implementation, when the reception order corresponding to the first signal satisfies the preset priority order, controlling the processor CPU or controlling the static random access memory SRAM to sleep or wake up according to the first signal and the preset correspondence includes: In the case where the first signal is a CORE_PD power-off signal, if the reception order corresponding to the first signal is that the CORE_PD power-off signal is prioritized, controlling the CPU to sleep according to the CORE_PD power-off signal; In the case where the first signal is a CORE_PD power-on signal, if the receiving order corresponding to the first signal is that the SYS_SLP power-on signal is prioritized, controlling the CPU to wake up according to the CORE_PD power-off signal; In a case where the first signal is a SYS_SLP power-on signal, if the receiving order corresponding to the first signal is that the SYS_SLP power-on signal is prioritized, controlling the SRAM to wake up according to the SYS_SLP power-on signal; In the case where the first signal is a SYS_SLP power-down signal, if the receiving order corresponding to the first signal is that the CORE_PD power-down signal is prioritized, the SRAM is controlled to wake up according to the SYS_SLP power-up signal.

[0008] According to a second aspect of an embodiment of the present application, a power management chip is provided, the chip comprising: A first signal receiving module is configured to receive a first signal sent by a system chip (SOC), wherein the first signal comprises one of a system sleep SYS_SLP power-on signal, a SYS_SLP power-off signal, a core power domain control CORE_PD power-off signal, and a CORE_PD power-on signal; a sequence determination module, configured to determine a reception sequence corresponding to the first signal based on the first signal and historical reception information, wherein the historical reception information includes historical reception information of each of the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on information; a priority determination module, configured to determine whether a reception order corresponding to the first signal satisfies a preset priority order, wherein the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-up signal takes precedence over the CORE_PD power-up signal; A response control module is used to control the processor CPU or the static random access memory SRAM to sleep or wake up according to the first signal and the preset correspondence when the reception order corresponding to the first signal meets the preset priority order, wherein the preset correspondence includes: controlling the SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling the SRAM to sleep in response to the SYS_SLP power-down signal, and controlling the CPU to sleep in response to the CORE_PD power-down signal; when the reception order corresponding to the first signal does not meet the preset priority order, continue to monitor the first preset time length to obtain a second signal; first control the CPU or control the SRAM to sleep or wake up according to the second signal, and then control the CPU or control the SRAM to sleep or wake up according to the first signal.

[0009] In a possible implementation manner, the sequence determination module is specifically configured to, when the first signal is a SYS_SLP power-off signal, determine, based on the historical reception information, whether a CORE_PD power-off signal is received within the previous second preset time period; if so, the reception sequence corresponding to the first signal is that the CORE_PD power-off signal is prioritized; if not, the reception sequence corresponding to the first signal is that the SYS_SLP power-off signal is prioritized; when the first signal is a CORE_PD power-on signal, determine, based on the historical reception information, whether a SYS_SLP power-on signal is received within the previous second preset time period; if so, the reception sequence corresponding to the first signal is that the SYS_SLP power-on signal is prioritized; if not, the reception sequence corresponding to the first signal is that the CORE_PD power-on signal is prioritized. The ORE_PD power-on signal takes priority; in the case where the first signal is a CORE_PD power-off signal, determine whether a SYS_SLP power-off signal is received within the previous second preset time period based on the historical reception information; if so, the receiving order corresponding to the first signal is the SYS_SLP power-off signal priority, if not, the receiving order corresponding to the first signal is the CORE_PD power-off signal priority; in the case where the first signal is a SYS_SLP power-on signal, determine whether a CORE_PD power-on signal is received within the previous second preset time period based on the historical reception information; if so, the receiving order corresponding to the first signal is the CORE_PD power-on signal priority, if not, the receiving order corresponding to the first signal is the SYS_SLP power-on signal priority.

[0010] In a possible implementation, the priority judgment module is specifically configured to, when the first signal is a CORE_PD power-down signal, determine that the condition is satisfied if the receiving order corresponding to the first signal is CORE_PD power-down signal priority; when the first signal is a CORE_PD power-on signal, determine that the condition is satisfied if the receiving order corresponding to the first signal is SYS_SLP power-on signal priority; when the first signal is a SYS_SLP power-on signal, determine that the condition is satisfied if the receiving order corresponding to the first signal is SYS_SLP power-on signal priority; when the first signal is a SYS_SLP power-down signal, determine that the condition is satisfied if the receiving order corresponding to the first signal is CORE_PD power-down signal priority; when the first signal is a CORE_PD power-up signal, determine that the condition is not satisfied if the receiving order corresponding to the first signal is CORE_PD power-on signal priority; when the first signal is a SYS_SLP power-down signal, determine that the condition is not satisfied if the receiving order corresponding to the first signal is SYS_SLP power-down signal priority.

[0011] In a possible implementation, the response control module is specifically configured to, when the first signal is a CORE_PD power-on signal and the corresponding reception order of the first signal is that the CORE_PD power-on signal takes priority, and the second signal is a SYS_SLP power-on signal, first control the SRAM to wake up according to the SYS_SLP power-on signal, and then control the CPU to wake up according to the CORE_PD power-on signal; when the first signal is a SYS_SLP power-off signal and the corresponding reception order of the first signal is that the SYS_SLP power-off signal takes priority, and the second signal is a CORE_PD power-off signal, first control the CPU to sleep according to the CORE_PD power-off signal, and then control the SRAM to sleep according to the SYS_SLP power-off signal.

[0012] In a possible implementation, the response control module is specifically configured to, when the first signal is a CORE_PD power-down signal, control the CPU to hibernate according to the CORE_PD power-down signal if the reception order corresponding to the first signal is that the CORE_PD power-down signal takes priority; when the first signal is a CORE_PD power-on signal, control the CPU to wake up according to the CORE_PD power-down signal if the reception order corresponding to the first signal is that the SYS_SLP power-on signal takes priority; when the first signal is a SYS_SLP power-on signal, control the SRAM to wake up according to the SYS_SLP power-on signal if the reception order corresponding to the first signal is that the SYS_SLP power-on signal takes priority; and when the first signal is a SYS_SLP power-down signal, control the SRAM to wake up according to the SYS_SLP power-on signal if the reception order corresponding to the first signal is that the CORE_PD power-down signal takes priority.

[0013] Another aspect of the embodiments of the present application further provides an electronic device, comprising: a PMIC, a SOC, a CPU, and an SRAM, wherein the PMIC is electrically connected to the SOC, the CPU, and the SRAM, respectively; The PMIC is used to execute any of the above-mentioned dual-rail power supply control methods.

[0014] In another aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, any of the above-mentioned dual-rail power supply control methods is implemented.

[0015] In another aspect of the embodiments of the present application, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute any of the above-described dual-rail power supply control methods.

[0016] Beneficial effects of the embodiments of the present application: An embodiment of the present application provides a dual-rail power supply control method and a power management chip, the method comprising: receiving a first signal sent by a system chip (SOC), wherein the first signal comprises: a system sleep SYS_SLP power-on signal, a SYS_SLP power-off signal, a core power domain control CORE_PD power-off signal, and one of the CORE_PD power-on signals; determining a receiving order corresponding to the first signal according to the first signal and historical reception information, wherein the historical reception information comprises: historical reception information of each signal in the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on information; judging whether the receiving order corresponding to the first signal satisfies a preset priority order, wherein the preset priority order comprises: the CORE_PD power-off signal takes precedence over the SYS_SLP power-off signal, and the S The YS_SLP power-on signal takes precedence over the CORE_PD power-on signal; when the receiving order corresponding to the first signal meets the preset priority order, the processor CPU is controlled or the static random access memory SRAM is controlled to sleep or wake up according to the first signal and the preset correspondence, wherein the preset correspondence includes: controlling SRAM wake-up in response to the SYS_SLP power-on signal, controlling CPU wake-up in response to the CORE_PD power-on signal, controlling SRAM sleep in response to the SYS_SLP power-off signal, and controlling CPU sleep in response to the CORE_PD power-off signal; when the receiving order corresponding to the first signal does not meet the preset priority order, continue to monitor the first preset time length to obtain the second signal; first control the CPU or control the SRAM to sleep or wake up according to the second signal, and then control the CPU or control the SRAM to sleep or wake up according to the first signal. Through the method of the embodiment of the present application, after receiving the first signal, the reception order corresponding to the first signal can be determined according to the first signal and historical reception information, and it can be judged whether the reception order corresponding to the first signal meets the preset priority order. When the reception order corresponding to the first signal meets the preset priority order, the processor CPU or static random access memory SRAM is controlled to wake up or sleep according to the first signal and the preset correspondence, thereby reducing the power consumption of the CPU or SRAM and improving the battery life of the electronic device by controlling the wake-up and sleep of the CPU or SRAM.

[0017] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0019] Figure 1 A schematic flow chart of a dual-rail power supply control method according to an embodiment of the present application; Figure 2 Another flowchart of the dual-rail power supply control method according to an embodiment of the present application; Figure 3 A schematic diagram of the structure of a power management chip provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0021] In the first aspect of the embodiment of the present application, a dual-rail power supply control method is first provided, which is applied to a PMIC (power management chip). Figure 1 , Figure 1 This is a flow chart of a dual-rail power supply control method according to an embodiment of the present application, the method comprising: Step S11, receiving a first signal sent by the system chip SOC, wherein the first signal includes: a system sleep SYS_SLP power-on signal, a SYS_SLP power-off signal, a core power domain control CORE_PD power-off signal, and a CORE_PD power-on signal; Step S12: determining a reception order corresponding to the first signal based on the first signal and historical reception information, wherein the historical reception information includes historical reception information of each of the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on information; Step S13: determining whether the receiving order corresponding to the first signal satisfies a preset priority order, wherein the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-up signal takes precedence over the CORE_PD power-up signal; Step S14, when the receiving order corresponding to the first signal meets the preset priority order, according to the first signal and the preset correspondence, the processor CPU is controlled or the static random access memory SRAM is controlled to sleep or wake up, wherein the preset correspondence includes: controlling the SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling the SRAM to sleep in response to the SYS_SLP power-down signal, and controlling the CPU to sleep in response to the CORE_PD power-down signal; when the receiving order corresponding to the first signal does not meet the preset priority order, continue to monitor the first preset time length to obtain the second signal; first control the CPU or control the SRAM to sleep or wake up according to the second signal, and then control the CPU or control the SRAM to sleep or wake up according to the first signal.

[0022] Corresponding to the above-mentioned step S11, the method of the embodiment of the present application is applied to a PMIC and can be executed by the PMIC. The PMIC can be electrically connected to the SOC, CPU, and SRAM. Specifically, the PMIC can obtain the SYS_SLP power-down signal or the CORE_PD power-up signal sent by the SOC through the electrical connection with the SOC. Among them, SYS_SLP is a sleep state control signal in power management and is sent by the SOC; CORE_PD inputs the CPU core voltage enable signal and is also sent by the SOC. SYS_SLP and CORE_PD can be used to represent the working or stopping signals of the CPU or SRAM, so that the CPU and SRAM can be operated or woken up according to the signals, which can not only ensure the normal operation of the device, but also reduce power consumption, thereby achieving the purpose of energy saving and increasing battery life. Among them, the SYS_SLP power-up signal can be determined by detecting the falling edge of the SYS_SLP signal, the CORE_PD power-up signal can be determined by detecting the falling edge of the CORE_PD signal, the SYS_SLP power-down signal can be determined by detecting the rising edge of the SYS_SLP signal, and the CORE_PD power-down signal can be determined by detecting the rising edge of the CORE_PD signal. Receiving the first signal sent by the system chip SOC indicates that when one of the YS_SLP power-up signal, the SYS_SLP power-down signal, the CORE_PD power-down signal, and the CORE_PD power-up signal is received, the received signal is identified as the first signal.

[0023] Corresponding to step S12 above, the historical reception information includes historical reception information of each of the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on information. Specifically, the historical reception information may include whether one or more of the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on information has been previously received, and may include information such as the specific time of receipt. Based on the first signal and the historical reception information, the order in which the first signal is received is determined, and it can be determined whether the received first signal was received first or later. For example, when the first information is a CORE_PD power-on signal, if the historical reception information indicates that a SYS_SLP power-on signal is received, the CORE_PD power-on signal is a signal received later, and the determined reception order corresponding to the first signal is that the SYS_SLP power-on signal has priority; when the first information is a CORE_PD power-on signal, if the historical reception information indicates that the SYS_SLP power-on signal has not been received, the CORE_PD power-on signal is a signal received earlier, and the reception order corresponding to the first signal is that the CORE_PD power-on signal has priority; similarly, when the first information is a SYS_SLP power-off signal, if the historical reception information indicates that a CORE_PD power-off signal is received, the SYS_SLP power-off signal is a signal received later, and the reception order corresponding to the first signal is that the CORE_PD power-off signal has priority; when the first information is a SYS_SLP power-off signal, if the historical reception information indicates that the CORE_PD power-off signal has not been received, the SYS_SLP power-off signal is a signal received earlier, and the reception order corresponding to the first signal is that the SYS_SLP power-off signal has priority. In actual use, the historical reception information can record reception information within a time period only, or can record reception information for a longer time period and then select reception information within a time period for identification. Specifically, the time period can be 1 second or other preset time lengths.

[0024] Corresponding to the above-mentioned step S13, the preset priority order includes: the CORE_PD power-off signal takes precedence over the SYS_SLP power-off signal, and the SYS_SLP power-on signal takes precedence over the CORE_PD power-on signal. Specifically, as described in the previous paragraph, according to the first signal and the historical reception information, determining the reception order corresponding to the first signal may include: SYS_SLP power-on signal priority, CORE_PD power-on signal priority, CORE_PD power-off signal priority, and SYS_SLP power-off signal priority. Then, to determine whether the reception order corresponding to the first signal meets the preset priority order, the obtained reception order corresponding to the first signal can be compared with the preset priority order. If they are the same, it is determined that they meet the requirements, otherwise it is determined that they do not meet the requirements. That is, if the reception order corresponding to the first signal is SYS_SLP power-on signal priority or CORE_PD power-off signal priority, it is determined that it meets the requirements.

[0025] Corresponding to step S14 above, the preset correspondence includes: controlling SRAM wake-up in response to a SYS_SLP power-up signal, controlling CPU wake-up in response to a CORE_PD power-up signal, controlling SRAM hibernation in response to a SYS_SLP power-down signal, and controlling CPU hibernation in response to a CORE_PD power-down signal. If the reception order of the first signal does not meet the preset priority order, continuing to monitor for the first preset duration to obtain a second signal; first controlling the CPU or SRAM to hibernate or wake up based on the second signal, and then controlling the CPU or SRAM to hibernate or wake up based on the first signal. If the reception order of the first signal meets the preset priority order, the CPU (processor) can be controlled to wake up or the SRAM (static random access memory) to hibernate based on the first signal and the preset correspondence. For example, when the first signal is a SYS_SLP power-up signal and the reception order of the first signal is that the SYS_SLP power-up signal takes priority, the SRAM is controlled to wake up. When the first signal is a CORE_PD power-down signal and the reception order of the first signal is that the CORE_PD power-down signal takes priority, the CPU is controlled to hibernate. If the reception order corresponding to the first signal does not meet the preset priority order, continue to monitor the first preset time length to obtain a second signal; first control the CPU or SRAM to sleep or wake up according to the second signal, and then control the CPU or SRAM to sleep or wake up according to the first signal. For example, when the first signal is a CORE_PD power-on signal, and the reception order corresponding to the first signal is that the CORE_PD power-on signal is prioritized, continue to monitor the first preset time length, receive the second signal, the SYS_SLP power-on signal, first control the SRAM to wake up according to the SYS_SLP power-on signal, and then control the CPU to wake up according to the CORE_PD power-on signal. For example, when the first signal is a SYS_SLP power-off signal, and the reception order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized, continue to monitor the first preset time length, receive the second signal, the CORE_PD power-off signal, first control the CPU to sleep according to the CORE_PD power-off signal, and then control the SYS_SLP to sleep according to the CORE_PD power-on signal. In actual use, by controlling the CPU to sleep before SYS_SLP sleep and the CPU to wake up later than SYS_SLP wake up, normal data storage can be ensured and data errors can be prevented. Specifically, the second preset time length can be a pre-set time length, for example, 50ms, 60ms, 80ms, etc.

[0026] It can be seen that through the method of the embodiment of the present application, after receiving the first signal, the reception order corresponding to the first signal can be determined according to the first signal and historical reception information, and it can be judged whether the reception order corresponding to the first signal meets the preset priority order. When the reception order corresponding to the first signal meets the preset priority order, the processor CPU or static random access memory SRAM is controlled to wake up or sleep according to the first signal and the preset correspondence, thereby reducing the power consumption of the CPU or SRAM and improving the battery life of the electronic device by controlling the wake-up and sleep of the CPU or SRAM.

[0027] In a possible implementation, determining the reception order corresponding to the first signals according to the first signals and historical reception information includes: In a case where the first signal is a SYS_SLP power-off signal, determining, based on the historical reception information, whether a CORE_PD power-off signal is received within a previous second preset time period; if so, the reception order corresponding to the first signal is that the CORE_PD power-off signal is prioritized; if not, the reception order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized; In a case where the first signal is a CORE_PD power-on signal, determining, based on the historical reception information, whether a SYS_SLP power-on signal is received within a previous second preset time period; if so, the receiving order corresponding to the first signal is that the SYS_SLP power-on signal is prioritized; if not, the receiving order corresponding to the first signal is that the CORE_PD power-on signal is prioritized; In a case where the first signal is a CORE_PD power-off signal, determining, based on the historical reception information, whether a SYS_SLP power-off signal is received within a previous second preset time period; if so, the receiving order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized; if not, the receiving order corresponding to the first signal is that the CORE_PD power-off signal is prioritized; In the case that the first signal is a SYS_SLP power-on signal, determine whether a CORE_PD power-on signal is received within the previous second preset time period based on the historical reception information; if so, the receiving order corresponding to the first signal is that the CORE_PD power-on signal is prioritized; if not, the receiving order corresponding to the first signal is that the SYS_SLP power-on signal is prioritized.

[0028] Among them, the reception order corresponding to the first signal is determined based on the first signal and the historical reception information, and whether the first information is the priority received information can be determined based on the historical reception information. In actual use, if the system is dormant, the CORE_PD power-off signal and the SYS_SLP power-off signal will be received. If the system is awake, the CORE_PD power-on signal and the SYS_SLP power-on signal will be received. Therefore, in the embodiment of the present application, when determining the reception order of the first signal, only the CORE_PD power-off signal and the SYS_SLP power-off signal can be compared, and only the CORE_PD power-on signal and the SYS_SLP power-on signal can be compared. Specifically, when the first signal is a SYS_SLP power-off signal, determine whether there is a CORE_PD power-off signal in the historical received information. If so, the CORE_PD power-off signal takes precedence, otherwise the SYS_SLP power-off signal takes precedence; when the first signal is a SYS_SLP power-on signal, determine whether there is a CORE_PD power-on signal in the historical received information. If so, the CORE_PD power-on signal takes precedence, otherwise the SYS_SLP power-on signal takes precedence; when the first signal is a CORE_PD power-off signal, determine whether there is a SYS_SLP power-off signal in the historical received information. If so, the SYS_SLP power-off signal takes precedence, otherwise the CORE_PD power-off signal takes precedence; when the first signal is a CORE_PD power-on signal, determine whether there is a SYS_SLP power-on signal in the historical received information. If so, the SYS_SLP power-on signal takes precedence, otherwise the CORE_PD power-on signal takes precedence.

[0029] In a possible implementation, determining whether the reception order of the first signals satisfies a preset priority order includes: If the first signal is a CORE_PD power-down signal, if the reception order corresponding to the first signal is CORE_PD power-down signal priority, it is determined that the condition is satisfied; if the first signal is a CORE_PD power-on signal, if the reception order corresponding to the first signal is SYS_SLP power-on signal priority, it is determined that the condition is satisfied; if the first signal is a SYS_SLP power-on signal, if the reception order corresponding to the first signal is SYS_SLP power-on signal priority, it is determined that the condition is satisfied; if the first signal is a SYS_SLP power-down signal, if the reception order corresponding to the first signal is CORE_PD power-down signal priority, it is determined that the condition is satisfied; In the case where the first signal is a CORE_PD power-on signal, if the receiving order corresponding to the first signal is that the CORE_PD power-on signal is prioritized, it is determined that it is not satisfied; in the case where the first signal is a SYS_SLP power-off signal, if the receiving order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized, it is determined that it is not satisfied.

[0030] Specifically, in the previous step, the determined reception order corresponding to the first signal may include: when the first signal is a SYS_SLP power-down signal, the CORE_PD power-down signal takes precedence or the SYS_SLP power-down signal takes precedence; when the first signal is a SYS_SLP power-up signal, the CORE_PD power-up signal takes precedence or the SYS_SLP power-up signal takes precedence; when the first signal is a CORE_PD power-down signal, the SYS_SLP power-down signal takes precedence or the CORE_PD power-down signal takes precedence; when the first signal is a CORE_PD power-up signal, the SYS_SLP power-up signal takes precedence or the CORE_PD power-up signal takes precedence. The preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-up signal takes precedence over the CORE_PD power-up signal. If the receiving order corresponding to the first signal is CORE_PD power-down signal priority, it is determined to be satisfied; if the receiving order corresponding to the first signal is SYS_SLP power-up signal priority, it is determined to be satisfied; if the receiving order corresponding to the first signal is SYS_SLP power-up signal priority, it is determined to be satisfied; if the receiving order corresponding to the first signal is CORE_PD power-down signal priority, it is determined to be satisfied. If the receiving order corresponding to the first signal is CORE_PD power-up signal priority, it is determined to be not satisfied; if the receiving order corresponding to the first signal is SYS_SLP power-down signal priority, it is determined to be not satisfied.

[0031] In a possible implementation, when the reception order corresponding to the first signal satisfies the preset priority order, controlling the processor CPU or controlling the static random access memory SRAM to sleep or wake up according to the first signal and the preset correspondence includes: In the case where the first signal is a CORE_PD power-off signal, if the reception order corresponding to the first signal is that the CORE_PD power-off signal is prioritized, controlling the CPU to sleep according to the CORE_PD power-off signal; In the case where the first signal is a CORE_PD power-on signal, if the receiving order corresponding to the first signal is that the SYS_SLP power-on signal is prioritized, controlling the CPU to wake up according to the CORE_PD power-off signal; In a case where the first signal is a SYS_SLP power-on signal, if the receiving order corresponding to the first signal is that the SYS_SLP power-on signal is prioritized, controlling the SRAM to wake up according to the SYS_SLP power-on signal; In the case where the first signal is a SYS_SLP power-down signal, if the receiving order corresponding to the first signal is that the CORE_PD power-down signal is prioritized, the SRAM is controlled to wake up according to the SYS_SLP power-up signal.

[0032] In the embodiment of the present application, in response to the CORE_PD power-down signal and the CORE_PD power-up signal, the CPU can be controlled to sleep or wake up. The PMIC can raise VDDCPU (CPU core voltage) to power down the CPU and control it to sleep, or lower VDDCPU to power up the CPU and control it to wake up. In response to the SYS_SLP power-up signal and the SYS_SLP power-down signal, the SRAM can be controlled to sleep or wake up. The PMIC can raise VDDSRAM (SRAM core voltage) to power down the SRAM and control it to sleep, or lower VDDSRAM to power up the SRAM and control it to wake up. As described above, in the following four cases: when the first signal is a CORE_PD power-down signal, if the receiving order corresponding to the first signal is the CORE_PD power-down signal priority; when the first signal is a SYS_SLP power-on signal, if the receiving order corresponding to the first signal is the SYS_SLP power-on signal priority; when the first signal is a SYS_SLP power-down signal, if the receiving order corresponding to the first signal is the CORE_PD power-down signal priority; when the first signal is a CORE_PD power-down signal, if the receiving order corresponding to the first signal is the CORE_PD power-down signal priority; when the first signal is a CORE_PD power-on signal, if the receiving order corresponding to the first signal is the SYS_SLP power-on signal priority; if the corresponding order meets the preset priority order, the processor CPU can be directly controlled or the static random access memory SRAM can be controlled to perform sleep or wake-up.

[0033] In one possible implementation, the second signal is a SYS_SLP power-on signal or a CORE_PD power-off signal, and the first signal is a SYS_SLP power-off signal or a CORE_PD power-on signal; and the first step of controlling the CPU or SRAM to enter sleep or wake-up according to the second signal and then controlling the CPU or SRAM to enter sleep or wake-up according to the first signal includes: When the first signal is a CORE_PD power-on signal, the receiving order of the first signal is that the CORE_PD power-on signal is prioritized, and when the second signal is a SYS_SLP power-on signal, the SRAM is first controlled to wake up according to the SYS_SLP power-on signal, and then the CPU is controlled to wake up according to the CORE_PD power-on signal; When the first signal is a SYS_SLP power-off signal, the receiving order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized, and the second signal is a CORE_PD power-off signal, the CPU is first controlled to sleep according to the CORE_PD power-off signal, and then the SRAM is controlled to sleep according to the SYS_SLP power-off signal.

[0034] In an embodiment of the present application, in the following two cases: when the first signal is a CORE_PD power-on signal, the corresponding receiving order of the first signal is CORE_PD power-on signal priority; when the first signal is a SYS_SLP power-off signal, the corresponding receiving order of the first signal is SYS_SLP power-off signal priority, which does not meet the preset priority order. In the case where the preset priority order is not met, the second signal can continue to be acquired. Since the CORE_PD power-on signal, the SYS_SLP power-on signal, or the CORE_PD power-off signal and SYS_SLP power-off signal are received when the system wakes up or sleeps, it will receive the CORE_PD power-on signal, the corresponding receiving order of the first signal is CORE_PD power-on signal priority, and the second signal is generally the SYS_SLP power-on signal; when the first signal is a SYS_SLP power-off signal, the corresponding receiving order of the first signal is SYS_SLP power-off signal priority, and the second signal is generally the CORE_PD power-off signal. Therefore, when the second signal is the SYS_SLP power-on signal, the SRAM is first controlled to wake up according to the SYS_SLP power-on signal, and then the CPU is controlled to wake up according to the CORE_PD power-on signal; when the second signal is the CORE_PD power-down signal, the CPU is first controlled to sleep according to the CORE_PD power-down signal, and then the SRAM is controlled to sleep according to the SYS_SLP power-down signal, thereby achieving normal startup or sleep of the system when the startup sequence is met.

[0035] In order to illustrate the method of the embodiment of the present application, a specific embodiment is described below. Figure 2 ,include: 1. Asynchronous control mode selection: In actual use, users can select asynchronous mode, which allows the CPU and SRAM to be powered down and awakened separately. Specifically, the PMIC supports separate control of VDDSRAM and VDDCPU by SYS_SLP and CORE_PD. SYS_SLP can be set to power on and off VDDSRAM, while CORE_PD can be set to power on and off VDDCPU.

[0036] 2. Set detection priority. For the sleep state, set the power-off signal monitoring priority for SYS_SLP and CORE_PD. Then, monitor the real-time status of the power-off signals of SYS_SLP and CORE_PD, and then make a sequential judgment. The solution of this application supports setting the monitoring priority of the PMIC's response to the power-off signals of SYS_SLP and CORE_PD. Set the CORE_PD signal response priority to be higher than SYS_SLP. That is, when the system CORE_PD is pulled high, VDDCPU powers off first, and then SYS_SLP pulls up VDDSRAM and then powers off, meeting the timing requirement that VDDCPU powers off before VDDSRAM. The response interval between CORE_PD and SYS_SLP can also be recorded. For exiting the sleep state, set the power-on signal monitoring priority for SYS_SLP and CORE_PD. Then, monitor the real-time status of the power-on signals of SYS_SLP and CORE_PD, and then make a sequential judgment. The solution of this application supports setting the monitoring priority of the PMIC's response to the power-on signals of SYS_SLP and CORE_PD. Set the SYS_SLP signal response priority to be higher than CORE_PD. That is, when the system SYS_SLP is pulled low, VDDSRAM is powered on first, and then CORE_PD pulls down VDDCPU before powering it on, which meets the timing requirement that VDDSRAM is powered on before VDDCPU. The response interval between SYS_SLP and CORE_PD can also be recorded.

[0037] 3. For the sleep state, after the power-off detection is performed, determine whether the sequence is normal. If normal, follow the VDDSRAM / VDDCPU power-off sequence normally, and then enter the sleep state. If abnormal, follow the VDDSRAM / VDDCPU power-off sequence normally after the normal timing is restored. Specifically, the solution of the present application can support making an abnormal record and recording the response interval between SYS_SLP and CORE_PD when the system SYS_SLP is pulled high before CORE_PD is pulled high. At the same time, the abnormal timing recovery mechanism is started, that is, when the SYS_SLP signal response is earlier than CORE_PD, a delayed wait (the wait time is configurable by the software) can be performed, and then VDDSRAM is powered off after CORE_PD pulls up VDDCPU to power off, thereby ensuring the timing requirement that VDDCPU is powered off before VDDSRAM. The same applies to the case where the SYS_SLP signal response priority is set higher than CORE_PD. For exiting the sleep state, after the power-on test, determine whether the sequence is normal. If normal, the VDDSRAM / VDDCPU power-on sequence will be carried out normally, and then the system exits the sleep state. If abnormal, the VDDSRAM / VDDCPU power-on sequence will be carried out normally after the timing is restored. Specifically, the solution of the present application can support making an abnormal record and recording the response interval between CORE_PD and SYS_SLP when the system CORE_PD is pulled low before SYS_SLP is pulled low. At the same time, the abnormal timing recovery mechanism is started, that is, when the CORE_PD signal responds before SYS_SLP, a delay wait (the wait time can be configured by the software) can be performed, and then VDDCPU is powered on after SYS_SLP pulls down VDDSRAM to power on, thereby ensuring the timing requirement that VDDSRAM is powered on before VDDCPU. The same applies to the case where the CORE_PD signal response priority is set higher than SYS_SLP.

[0038] In a second aspect of the embodiment of the present application, a power management chip is provided. Figure 3 , Figure 3 A schematic diagram of the structure of a power management chip provided in an embodiment of the present application, wherein the chip includes: The first signal receiving module 301 is configured to receive a first signal sent by the system chip SOC, wherein the first signal includes one of a system sleep SYS_SLP power-on signal, a SYS_SLP power-off signal, a core power domain control CORE_PD power-off signal, and a CORE_PD power-on signal; An order determination module 302 is configured to determine a reception order corresponding to the first signal based on the first signal and historical reception information, wherein the historical reception information includes historical reception information of each of the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on information; a priority determination module 303, configured to determine whether a reception order corresponding to the first signal satisfies a preset priority order, wherein the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-up signal takes precedence over the CORE_PD power-up signal; The response control module 304 is used to control the processor CPU or the static random access memory SRAM to sleep or wake up according to the first signal and the preset correspondence relationship when the reception order corresponding to the first signal meets the preset priority order, wherein the preset correspondence includes: controlling the SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling the SRAM to sleep in response to the SYS_SLP power-down signal, and controlling the CPU to sleep in response to the CORE_PD power-down signal; when the reception order corresponding to the first signal does not meet the preset priority order, continue to monitor the first preset time length to obtain a second signal; first control the CPU or control the SRAM to sleep or wake up according to the second signal, and then control the CPU or control the SRAM to sleep or wake up according to the first signal.

[0039] In a possible implementation manner, the sequence determination module is specifically configured to, when the first signal is a SYS_SLP power-off signal, determine, based on the historical reception information, whether a CORE_PD power-off signal is received within the previous second preset time period; if so, the reception sequence corresponding to the first signal is that the CORE_PD power-off signal is prioritized; if not, the reception sequence corresponding to the first signal is that the SYS_SLP power-off signal is prioritized; when the first signal is a CORE_PD power-on signal, determine, based on the historical reception information, whether a SYS_SLP power-on signal is received within the previous second preset time period; if so, the reception sequence corresponding to the first signal is that the SYS_SLP power-on signal is prioritized; if not, the reception sequence corresponding to the first signal is that the CORE_PD power-on signal is prioritized. The ORE_PD power-on signal takes priority; in the case where the first signal is a CORE_PD power-off signal, determine whether a SYS_SLP power-off signal is received within the previous second preset time period based on the historical reception information; if so, the receiving order corresponding to the first signal is the SYS_SLP power-off signal priority, if not, the receiving order corresponding to the first signal is the CORE_PD power-off signal priority; in the case where the first signal is a SYS_SLP power-on signal, determine whether a CORE_PD power-on signal is received within the previous second preset time period based on the historical reception information; if so, the receiving order corresponding to the first signal is the CORE_PD power-on signal priority, if not, the receiving order corresponding to the first signal is the SYS_SLP power-on signal priority.

[0040] In a possible implementation, the priority judgment module is specifically configured to, when the first signal is a CORE_PD power-down signal, determine that the condition is satisfied if the receiving order corresponding to the first signal is CORE_PD power-down signal priority; when the first signal is a CORE_PD power-on signal, determine that the condition is satisfied if the receiving order corresponding to the first signal is SYS_SLP power-on signal priority; when the first signal is a SYS_SLP power-on signal, determine that the condition is satisfied if the receiving order corresponding to the first signal is SYS_SLP power-on signal priority; when the first signal is a SYS_SLP power-down signal, determine that the condition is satisfied if the receiving order corresponding to the first signal is CORE_PD power-down signal priority; when the first signal is a CORE_PD power-up signal, determine that the condition is not satisfied if the receiving order corresponding to the first signal is CORE_PD power-on signal priority; when the first signal is a SYS_SLP power-down signal, determine that the condition is not satisfied if the receiving order corresponding to the first signal is SYS_SLP power-down signal priority.

[0041] In a possible implementation, the response control module is specifically configured to, when the first signal is a CORE_PD power-on signal and the corresponding reception order of the first signal is that the CORE_PD power-on signal takes priority, and the second signal is a SYS_SLP power-on signal, first control the SRAM to wake up according to the SYS_SLP power-on signal, and then control the CPU to wake up according to the CORE_PD power-on signal; when the first signal is a SYS_SLP power-off signal and the corresponding reception order of the first signal is that the SYS_SLP power-off signal takes priority, and the second signal is a CORE_PD power-off signal, first control the CPU to sleep according to the CORE_PD power-off signal, and then control the SRAM to sleep according to the SYS_SLP power-off signal.

[0042] In a possible implementation, the response control module is specifically configured to, when the first signal is a CORE_PD power-down signal, control the CPU to hibernate according to the CORE_PD power-down signal if the reception order corresponding to the first signal is that the CORE_PD power-down signal takes priority; when the first signal is a CORE_PD power-on signal, control the CPU to wake up according to the CORE_PD power-down signal if the reception order corresponding to the first signal is that the SYS_SLP power-on signal takes priority; when the first signal is a SYS_SLP power-on signal, control the SRAM to wake up according to the SYS_SLP power-on signal if the reception order corresponding to the first signal is that the SYS_SLP power-on signal takes priority; and when the first signal is a SYS_SLP power-down signal, control the SRAM to wake up according to the SYS_SLP power-on signal if the reception order corresponding to the first signal is that the CORE_PD power-down signal takes priority.

[0043] It can be seen that through the chip of the embodiment of the present application, after receiving the first signal, the receiving order corresponding to the first signal can be determined according to the first signal and historical receiving information, and whether the receiving order corresponding to the first signal meets the preset priority order. When the receiving order corresponding to the first signal meets the preset priority order, the processor CPU or static random access memory SRAM is controlled to wake up or sleep according to the first signal and the preset correspondence, thereby reducing the power consumption of the CPU or SRAM and improving the battery life of the electronic device by controlling the wake-up and sleep of the CPU or SRAM.

[0044] Another aspect of the present application embodiment further provides an electronic device, see Figure 4 , Figure 4A schematic diagram of the structure of an electronic device provided in an embodiment of the present application includes: a PMIC, a SOC, a CPU, and an SRAM: the PMIC is electrically connected to the SOC, the CPU, and the SRAM respectively; The PMIC is used to execute any of the above-mentioned dual-rail power supply control methods.

[0045] In another embodiment provided in the present application, a computer-readable storage medium is further provided, which stores a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned dual-rail power supply control methods are implemented.

[0046] In another embodiment provided by the present application, a computer program product including instructions is further provided, which, when executed on a computer, enables the computer to execute the dual-rail power supply control method described in any one of the above embodiments.

[0047] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or solid-state drive (SSD).

[0048] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0049] Each embodiment in this specification is described in a related manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments. In particular, the chip, electronic device, and storage medium embodiments are generally similar to the method embodiments, so their descriptions are relatively simple. For related portions, refer to the descriptions of the method embodiments.

[0050] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. A dual-rail power supply control method, characterized in that: Applied to a power management chip PMIC, the method includes: Receive a first signal sent by a system chip (SOC), wherein the first signal includes one of a system sleep SYS_SLP power-on signal, a SYS_SLP power-off signal, a core power domain control CORE_PD power-off signal, and a CORE_PD power-on signal; Determine, according to the first signal and historical reception information, a reception order corresponding to the first signal, wherein the historical reception information includes: historical reception information of each of the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on information; Determine whether a reception order corresponding to the first signal satisfies a preset priority order, wherein the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-up signal takes precedence over the CORE_PD power-up signal; When the reception order corresponding to the first signal satisfies the preset priority order, controlling the processor CPU or the static random access memory SRAM to sleep or wake up according to the first signal and the preset correspondence, wherein the preset correspondence includes: controlling the SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling the SRAM to sleep in response to the SYS_SLP power-down signal, and controlling the CPU to sleep in response to the CORE_PD power-down signal; When the receiving order corresponding to the first signal does not meet the preset priority order, continue to monitor the first preset time length to obtain the second signal; first control the CPU or SRAM according to the second signal to sleep or wake up, and then control the CPU or SRAM according to the first signal to sleep or wake up.

2. The method according to claim 1, characterized in that The determining, according to the first signal and historical reception information, a reception order corresponding to the first signal includes: In a case where the first signal is a SYS_SLP power-off signal, determining, based on the historical reception information, whether a CORE_PD power-off signal is received within a previous second preset time period; if so, the reception order corresponding to the first signal is that the CORE_PD power-off signal is prioritized; if not, the reception order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized; In a case where the first signal is a CORE_PD power-on signal, determining, based on the historical reception information, whether a SYS_SLP power-on signal is received within a previous second preset time period; if so, the receiving order corresponding to the first signal is that the SYS_SLP power-on signal is prioritized; if not, the receiving order corresponding to the first signal is that the CORE_PD power-on signal is prioritized; In a case where the first signal is a CORE_PD power-off signal, determining, based on the historical reception information, whether a SYS_SLP power-off signal is received within a previous second preset time period; if so, the receiving order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized; if not, the receiving order corresponding to the first signal is that the CORE_PD power-off signal is prioritized; In the case that the first signal is a SYS_SLP power-on signal, determine whether a CORE_PD power-on signal is received within the previous second preset time period based on the historical reception information; if so, the receiving order corresponding to the first signal is that the CORE_PD power-on signal is prioritized; if not, the receiving order corresponding to the first signal is that the SYS_SLP power-on signal is prioritized.

3. The method according to claim 2, characterized in that The determining whether the receiving order of the first signal satisfies a preset priority order includes: If the first signal is a CORE_PD power-down signal, if the reception order corresponding to the first signal is CORE_PD power-down signal priority, it is determined that the condition is satisfied; if the first signal is a CORE_PD power-on signal, if the reception order corresponding to the first signal is SYS_SLP power-on signal priority, it is determined that the condition is satisfied; if the first signal is a SYS_SLP power-on signal, if the reception order corresponding to the first signal is SYS_SLP power-on signal priority, it is determined that the condition is satisfied; if the first signal is a SYS_SLP power-down signal, if the reception order corresponding to the first signal is CORE_PD power-down signal priority, it is determined that the condition is satisfied; In the case where the first signal is a CORE_PD power-on signal, if the receiving order corresponding to the first signal is that the CORE_PD power-on signal is prioritized, it is determined that it is not satisfied; in the case where the first signal is a SYS_SLP power-off signal, if the receiving order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized, it is determined that it is not satisfied.

4. The method according to claim 3, characterized in that The second signal is a SYS_SLP power-on signal or a CORE_PD power-off signal, and the first signal is a SYS_SLP power-off signal or a CORE_PD power-on signal; and the method of first controlling the CPU or the SRAM to enter sleep or wake-up according to the second signal, and then controlling the CPU or the SRAM to enter sleep or wake-up according to the first signal, includes: When the first signal is a CORE_PD power-on signal, the receiving order of the first signal is that the CORE_PD power-on signal is prioritized, and when the second signal is a SYS_SLP power-on signal, the SRAM is first controlled to wake up according to the SYS_SLP power-on signal, and then the CPU is controlled to wake up according to the CORE_PD power-on signal; When the first signal is a SYS_SLP power-off signal, the receiving order corresponding to the first signal is that the SYS_SLP power-off signal is prioritized, and the second signal is a CORE_PD power-off signal, the CPU is first controlled to sleep according to the CORE_PD power-off signal, and then the SRAM is controlled to sleep according to the SYS_SLP power-off signal.

5. The method according to claim 3, characterized in that When the reception order corresponding to the first signal satisfies the preset priority order, controlling the processor CPU or the static random access memory SRAM to sleep or wake up according to the first signal and the preset correspondence, including: In the case where the first signal is a CORE_PD power-off signal, if the reception order corresponding to the first signal is that the CORE_PD power-off signal is prioritized, controlling the CPU to sleep according to the CORE_PD power-off signal; In the case where the first signal is a CORE_PD power-on signal, if the receiving order corresponding to the first signal is that the SYS_SLP power-on signal is prioritized, controlling the CPU to wake up according to the CORE_PD power-off signal; In a case where the first signal is a SYS_SLP power-on signal, if the receiving order corresponding to the first signal is that the SYS_SLP power-on signal is prioritized, controlling the SRAM to wake up according to the SYS_SLP power-on signal; In the case where the first signal is a SYS_SLP power-down signal, if the receiving order corresponding to the first signal is that the CORE_PD power-down signal is prioritized, the SRAM is controlled to wake up according to the SYS_SLP power-up signal.

6. A power management chip, characterized in that: The chip includes: A first signal receiving module is configured to receive a first signal sent by a system chip (SOC), wherein the first signal comprises one of a system sleep SYS_SLP power-on signal, a SYS_SLP power-off signal, a core power domain control CORE_PD power-off signal, and a CORE_PD power-on signal; a sequence determination module, configured to determine a reception sequence corresponding to the first signal based on the first signal and historical reception information, wherein the historical reception information includes historical reception information of each of the SYS_SLP power-on signal, the SYS_SLP power-off signal, the CORE_PD power-off signal, and the CORE_PD power-on information; a priority determination module, configured to determine whether a reception order corresponding to the first signal satisfies a preset priority order, wherein the preset priority order includes: the CORE_PD power-down signal takes precedence over the SYS_SLP power-down signal, and the SYS_SLP power-up signal takes precedence over the CORE_PD power-up signal; A response control module is used to control the processor CPU or the static random access memory SRAM to sleep or wake up according to the first signal and the preset correspondence when the reception order corresponding to the first signal meets the preset priority order, wherein the preset correspondence includes: controlling the SRAM to wake up in response to the SYS_SLP power-on signal, controlling the CPU to wake up in response to the CORE_PD power-on signal, controlling the SRAM to sleep in response to the SYS_SLP power-down signal, and controlling the CPU to sleep in response to the CORE_PD power-down signal; when the reception order corresponding to the first signal does not meet the preset priority order, continue to monitor the first preset time length to obtain a second signal; first control the CPU or control the SRAM to sleep or wake up according to the second signal, and then control the CPU or control the SRAM to sleep or wake up according to the first signal.

7. The chip according to claim 6, characterized in that The sequence determination module is specifically used to determine, when the first signal is a SYS_SLP power-off signal, whether a CORE_PD power-off signal is received within the previous second preset time period based on the historical reception information; if so, the reception sequence corresponding to the first signal is CORE_PD power-off signal priority, and if not, the reception sequence corresponding to the first signal is SYS_SLP power-off signal priority; when the first signal is a CORE_PD power-on signal, determine, when the first signal is a CORE_PD power-on signal, whether a SYS_SLP power-on signal is received within the previous second preset time period based on the historical reception information; if so, the reception sequence corresponding to the first signal is SYS_SLP power-on signal priority, and if not, the reception sequence corresponding to the first signal is CORE_PD The power-on signal takes priority; in the case where the first signal is a CORE_PD power-off signal, determine whether a SYS_SLP power-off signal is received within the previous second preset time period based on the historical reception information; if so, the receiving order corresponding to the first signal is SYS_SLP power-off signal priority, if not, the receiving order corresponding to the first signal is CORE_PD power-off signal priority; in the case where the first signal is a SYS_SLP power-on signal, determine whether a CORE_PD power-on signal is received within the previous second preset time period based on the historical reception information; if so, the receiving order corresponding to the first signal is CORE_PD power-on signal priority, if not, the receiving order corresponding to the first signal is SYS_SLP power-on signal priority.

8. The chip according to claim 6, characterized in that The priority judgment module is specifically configured to, when the first signal is a CORE_PD power-down signal, determine that the condition is satisfied if the receiving order corresponding to the first signal is CORE_PD power-down signal priority; when the first signal is a CORE_PD power-on signal, determine that the condition is satisfied if the receiving order corresponding to the first signal is SYS_SLP power-on signal priority; when the first signal is a SYS_SLP power-on signal, determine that the condition is satisfied if the receiving order corresponding to the first signal is SYS_SLP power-on signal priority; when the first signal is a SYS_SLP power-down signal, determine that the condition is satisfied if the receiving order corresponding to the first signal is CORE_PD power-down signal priority; when the first signal is a CORE_PD power-up signal, determine that the condition is not satisfied if the receiving order corresponding to the first signal is CORE_PD power-on signal priority; when the first signal is a SYS_SLP power-down signal, determine that the condition is not satisfied if the receiving order corresponding to the first signal is SYS_SLP power-down signal priority.

9. The chip according to claim 8, characterized in that The response control module is specifically configured to, when the first signal is a CORE_PD power-on signal and the corresponding receiving order of the first signal is that the CORE_PD power-on signal takes precedence, and the second signal is a SYS_SLP power-on signal, first control the SRAM to wake up according to the SYS_SLP power-on signal, and then control the CPU to wake up according to the CORE_PD power-on signal; and when the first signal is a SYS_SLP power-off signal and the corresponding receiving order of the first signal is that the SYS_SLP power-off signal takes precedence, and the second signal is a CORE_PD power-off signal, first control the CPU to sleep according to the CORE_PD power-off signal, and then control the SRAM to sleep according to the SYS_SLP power-off signal.

10. An electronic device, characterized in that: include: PMIC, SOC, CPU and SRAM: the PMIC is electrically connected to the SOC, CPU and SRAM respectively; The PMIC is used to execute the method according to any one of claims 1 to 5.

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