Performance accelerated analysis method and system of test case and storage medium

Abstract

The invention is suitable for the technical field of test case analysis, and particularly relates to a test case performance accelerated analysis method and system and a storage medium. The method comprises the following steps: running a test case comprising a plurality of instructions through a simulator, and when the test case is executed to a preset interval, obtaining instruction information corresponding to each instruction in the preset interval; the instruction information comprises an instruction type, an operand and a calculation result; based on a first preset rule, according to the instruction information, judging whether each instruction in a preset interval has dependency or not, and obtaining an instruction dependency statistical result; segmenting the test case into a plurality of read-only memory files and a plurality of random access memory files based on a second preset rule; running the plurality of read-only memory files and the plurality of random access memory files in parallel; and analyzing the test case according to the instruction dependency statistical result and the operation result to obtain an analysis result. Compared with the prior art, the test case analysis efficiency is higher, and the analysis effect is better.

Description

Technical Field

[0001] The present invention is applicable to the technical field of test case analysis, and in particular relates to a performance acceleration analysis method, system and storage medium for a test case. Background Art

[0002] As a key tool for software and hardware development, the CPU simulator's main function is to simulate the target CPU's core behaviors, such as instruction execution, register interaction, and memory access, through software without the need for real hardware. This supports cross-architecture program running and debugging, reduces hardware dependency costs, and accelerates the verification process for new architectures or new functions.

[0003] QEMU, an open-source CPU emulator, is capable of simulating CPUs of various architectures. By accurately modeling key components of the target CPU, such as the instruction set, registers, and memory management, it can effectively reproduce the operating characteristics of CPUs of different architectures in a simulated environment, providing strong support for cross-platform software development and system debugging. The QEMU emulator provides a plug-in interface that allows users to extend functionality. This interface allows users to develop plug-ins that analyze running use cases under different architectures, such as counting instructions and printing instruction execution paths. These functions are very helpful for software performance optimization and program error troubleshooting. However, the built-in plug-ins in the QEMU simulator often have relatively simple functionality, making them inadequate for RISC-V architecture use case analysis. RISC-V architecture is modular and extensible, and its use case analysis often requires more complex functionality, such as counting the execution cycles of specific instructions and monitoring privilege level switches. Existing simulator plug-ins lack effective support for these aspects, making them inadequate for RISC-V architecture testing.

[0004] Therefore, there is an urgent need for a new performance acceleration analysis method, system and storage medium for test cases to solve the above technical problems. Summary of the Invention

[0005] The present invention provides a performance acceleration analysis method, system and storage medium for a test case, aiming to improve the analysis efficiency and analysis effect of the test case.

[0006] In a first aspect, the present invention provides a performance acceleration analysis method for a test case, the performance acceleration analysis method comprising the following steps: S1. Running a test case including multiple instructions through a simulator, and when the test case reaches a preset interval, obtaining instruction information corresponding to each instruction in the preset interval; the instruction information includes an instruction type, an operand, and a calculation result; S2. Determine whether each instruction in the preset interval has a dependency based on the instruction information based on a first preset rule, and obtain instruction dependency statistics; S3. Divide the test case into a plurality of read-only memory files and a plurality of random access memory files based on a second preset rule; run the plurality of read-only memory files and the plurality of random access memory files in parallel to obtain a running result; S4. Analyze the test case according to the instruction dependency statistical result and the running result to obtain an analysis result.

[0007] Preferably, the first preset rule is: determining whether the operand of each instruction within the preset interval is the same as the calculation result corresponding to at least one executed instruction within the preset range: If so, the dependency relationship between the instruction and the executed instruction is recorded.

[0008] Preferably, in step S3, the second preset rule is: S31, running the test case completely once based on a basic block vector generation tool and collecting feature points of the test case to obtain a test case feature file; S32. Analyze and sample the use case feature file based on a simulation point tool to obtain a cutting point file; wherein the cutting point file includes a plurality of designated cutting positions; S33. The simulator runs the test case again and cuts the test case according to the cutting point file to obtain a plurality of read-only memory files and a plurality of random access memory files.

[0009] Preferably, step S33 includes the following sub-steps: S331, determining whether the current simulator's instruction for running the test case reaches the specified cutting position of the cutting point file: if so, proceeding to step S332; if not, the simulator continues to run the next instruction of the test case; S332, querying all current register information from the simulator, and storing all current register information in a new read-only memory file in sequence; querying current memory information from the simulator, and storing the current memory information in a new random access memory file; S333. Determine whether the simulator has run all the specified cutting positions in the cutting point file: if so, output the multiple read-only memory files and the multiple random access memory files; if not, the simulator runs the next instruction of the test case and returns to step S331.

[0010] In a second aspect, the present invention further provides a performance acceleration analysis system for a test case, the performance acceleration analysis system for a test case comprising: An execution module, configured to run a test case including a plurality of instructions through a simulator, and when the test case is executed to a preset interval, obtain an instruction type, an operand, and a calculation result corresponding to each instruction in the preset interval; A statistics module, configured to determine whether each of the instructions within the preset interval has a dependency based on a first preset rule, and obtain instruction dependency statistics; a splitting module, configured to split the test case into a plurality of read-only memory files and a plurality of random access memory files based on a second preset rule; and run the plurality of read-only memory files and the plurality of random access memory files in parallel to obtain a running result; The analysis module is used to analyze the test case according to the instruction dependency statistical result and the running result to obtain an analysis result.

[0011] Preferably, the first preset rule is: determining whether the operand of each instruction within the preset interval is the same as the calculation result corresponding to at least one executed instruction within the preset range: If so, the dependency relationship between the instruction and the executed instruction is recorded.

[0012] Preferably, in the segmentation module, the second preset rule is: Based on the basic block vector generation tool, the test case is completely run once and the feature points of the test case are collected to obtain a test case feature file; Analyzing and sampling the use case feature file based on a simulation point tool to obtain a cutting point file; wherein the cutting point file includes a plurality of specified cutting positions; The simulator runs the test case again and cuts the test case according to the cutting point file to obtain a plurality of read-only memory files and a plurality of random access memory files.

[0013] Preferably, the segmentation module further includes the following subunits: A judging unit, configured to judge whether the current instruction of the simulator running the test case reaches the specified cutting position of the cutting point file: if so, jump to the query unit; if not, the simulator continues to run the next instruction of the test case; a query unit, configured to query all current register information from the simulator and store all current register information in a new read-only memory file in sequence; query current memory information from the simulator and store the current memory information in a new random access memory file; The output unit is used to determine whether the simulator has run all the specified cutting positions in the cutting point file: if so, multiple read-only memory files and multiple random access memory files are output; if not, the simulator runs the next instruction of the test case and returns to the judgment unit.

[0014] In a third aspect, the present invention also provides a computer device comprising: a memory, a processor, and a performance acceleration analysis program for a test case stored in the memory and runnable on the processor, wherein when the processor executes the performance acceleration analysis program for the test case, the processor implements the steps in the performance acceleration analysis method for the test case as described in any one of the above embodiments.

[0015] In a fourth aspect, the present invention also provides a computer-readable storage medium, on which a performance acceleration analysis program for a test case is stored. When the performance acceleration analysis program for a test case is executed by a processor, the steps in the performance acceleration analysis method for a test case as described in any one of the above embodiments are implemented.

[0016] Compared to the prior art, the present invention uses a simulator to run a test case including multiple instructions. When the test case executes to a preset interval, instruction information corresponding to each instruction within the preset interval is obtained; the instruction information includes the instruction type, operand, and calculation result; based on a first preset rule, the instruction information determines whether each instruction within the preset interval has a dependency, thereby obtaining instruction dependency statistics; based on a second preset rule, the test case is divided into multiple read-only memory files and multiple random access memory files; the multiple read-only memory files and multiple random access memory files are run in parallel to obtain an execution result; and the test case is analyzed based on the instruction dependency statistics and the execution results to obtain an analysis result. The present invention can count the number of different types of instructions and the dependencies between instructions to obtain instruction dependency statistics, thereby facilitating chip optimization through analysis based on the instruction dependency statistics. Furthermore, when analyzing large test cases, the execution time is long due to the limited speed of the simulator. The second preset rule allows the large test case to be divided into multiple representative read-only memory files and random access memory files. When analyzing the test case, the performance of the read-only memory files and random access memory files is first analyzed to equivalently replace the performance of the large test case. Moreover, multiple read-only memory files and random access memory files can run in parallel, which greatly reduces the running time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings. In the accompanying drawings: Figure 1This is a flowchart of a performance acceleration analysis method for a test case provided by an embodiment of the present invention; Figure 2 Schematic diagram of the performance acceleration analysis system for test cases provided by an embodiment of the present invention; Figure 3 It is a structural diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0019] Example 1 Please refer to Figure 1 The present invention provides a performance acceleration analysis method for a test case, the performance acceleration analysis method comprising the following steps: S1. Run a test case including multiple instructions through a simulator. When the test case is executed to a preset interval, obtain instruction information corresponding to each instruction in the preset interval; the instruction information includes instruction type, operand and calculation result.

[0020] In an embodiment of the present invention, the simulator is a QEMU (Quick Emulator) simulator, and the preset interval can be the range from any starting instruction to the ending instruction set in the test case. For example, when the simulator runs the test case and reaches the starting instruction, it starts to record the instruction information corresponding to the instruction (including the starting instruction) until it runs to the ending instruction. The range size of the preset interval can be set according to actual conditions.

[0021] S2. Based on the first preset rule and the instruction information, determine whether each of the instructions in the preset interval has a dependency, and obtain instruction dependency statistics.

[0022] In an embodiment of the present invention, the first preset rule is to determine whether the operands of each instruction within the preset interval are identical to the computation results of at least one previously executed instruction within the preset range. If so, the dependency relationship between the instruction and the previously executed instruction is recorded. The preset range refers to the n instructions that have been executed before the current instruction, with a maximum of 64 instructions. For example, the determination is made as to whether the operands of the current instruction are identical to the computation results of the 64 previously executed instructions.

[0023] Specifically, when optimizing for the characteristics of a test case, it's crucial to understand the number of instructions, instruction types, and dependencies between instructions within that test case. By counting the number of different types of instructions and the dependencies between them, we can obtain instruction dependency statistics. By calculating the dependencies between instructions, we can determine which instruction pairs appear most frequently in the test case. For example, addition instructions appear the most frequently, so subsequent chip design can prioritize optimizing the addition module to improve test case performance.

[0024] S3. Divide the test case into multiple read-only memory files and multiple random access memory files based on a second preset rule; run the multiple read-only memory files and the multiple random access memory files in parallel to obtain an operation result.

[0025] In this embodiment of the present invention, in step S3, the second preset rule is: S31. Based on the Basic Block Vector Generation Tool, the test case is completely run and the characteristic points of the test case are collected to obtain a test case characteristic file. The Basic Block Vector Generation Tool is a tool for statistically analyzing and quantifying the execution behavior of the Basic Block during program execution to generate "Basic Block Vectors" (i.e., characteristic points). The Basic Block Vector Generation Tool monitors the program execution process through instrumentation technology, records the number of executions of each Basic Block, and ultimately forms characteristic points reflecting the program behavior, thereby obtaining a test case characteristic file with multiple characteristic points.

[0026] S32. Analyze and sample the use case signature file using a simulation point tool (Simpoint tool) to obtain a cutpoint file. The cutpoint file includes multiple specified cutpoint locations. The Simpoint tool analyzes the basic block vectors generated by the use case signature file during runtime, divides the entire execution process into several "stages" with similar behaviors, and selects the most representative stages (called "Simpoints") from these stages. The cutpoint locations between each stage are determined. These stages accurately reflect the overall execution characteristics of the program, avoiding ineffective simulation of redundant or repetitive execution portions.

[0027] S33. The simulator runs the test case again and segments it according to the segmentation point file, generating multiple read-only memory (ROM) files (BootROM files) and multiple random access memory (RAM) files (MainRAM files). The ROM files store all register information at the time the slices were generated. The random access memory (RAM) files store all memory information at the time the slices were generated and are used for restoring the test case during runtime.

[0028] For example, a large test case (one with a particularly large number of instructions), such as 3 billion instructions, takes a while to run. The basic block vector generation tool identifies its characteristic points, and the simulation point tool slices it into six sections (the number of sections and the specific cut locations are customizable). The first section starts at instruction 0, the second at instruction 500 million, and so on. The result is six sets of slice files, each containing one ROM file and one RAM file, for a total of twelve files.

[0029] Step S33 includes the following sub-steps: S331, determining whether the current simulator's instruction for running the test case reaches the specified cutting position of the cutting point file: if so, proceeding to step S332; if not, the simulator continues to run the next instruction of the test case; S332, querying all current register information from the simulator, and storing all current register information in a new read-only memory file in sequence; querying current memory information from the simulator, and storing the current memory information in a new random access memory file; S333. Determine whether the simulator has run all the specified cutting positions in the cutting point file: if so, output the multiple read-only memory files and the multiple random access memory files; if not, the simulator runs the next instruction of the test case and returns to step S331.

[0030] S4. Analyze the test case according to the instruction dependency statistical result and the running result to obtain an analysis result.

[0031] Compared to the prior art, the present invention uses a simulator to run a test case including multiple instructions. When the test case executes to a preset interval, instruction information corresponding to each instruction within the preset interval is obtained; the instruction information includes the instruction type, operand, and calculation result; based on a first preset rule, the instruction information determines whether each instruction within the preset interval has a dependency, thereby obtaining instruction dependency statistics; based on a second preset rule, the test case is divided into multiple read-only memory files and multiple random access memory files; the multiple read-only memory files and multiple random access memory files are run in parallel to obtain an execution result; and the test case is analyzed based on the instruction dependency statistics and the execution results to obtain an analysis result. The present invention can count the number of different types of instructions and the dependencies between instructions to obtain instruction dependency statistics, thereby facilitating chip optimization through analysis based on the instruction dependency statistics. Furthermore, when analyzing large test cases, the execution time is long due to the limited speed of the simulator. The second preset rule allows the large test case to be divided into multiple representative read-only memory files and random access memory files. When analyzing the test case, the performance of the read-only memory files and random access memory files is first analyzed to equivalently replace the performance of the large test case. Moreover, multiple read-only memory files and random access memory files can run in parallel, which greatly reduces the running time. Example 2 The embodiment of the present invention also provides a performance acceleration analysis system for test cases, please refer to Figure 2 , Figure 2 FIG. 2 is a schematic diagram of a performance acceleration analysis system 200 for a test case according to an embodiment of the present invention, which includes: 201. An execution module, configured to run a test case including multiple instructions through a simulator, and when the test case is executed to a preset interval, obtain an instruction type, an operand, and a calculation result corresponding to each instruction in the preset interval.

[0032] In an embodiment of the present invention, the simulator is a QEMU (Quick Emulator) simulator, and the preset interval can be the range from any starting instruction to the ending instruction set in the test case. For example, when the simulator runs the test case and reaches the starting instruction, it starts to record the instruction information corresponding to the instruction (including the starting instruction) until it runs to the ending instruction. The range size of the preset interval can be set according to actual conditions.

[0033] 202. A statistical module, configured to determine whether each of the instructions within the preset interval has a dependency based on a first preset rule, and obtain instruction dependency statistics.

[0034] In an embodiment of the present invention, the first preset rule is: determine whether the operand of each instruction within the preset interval is the same as the calculation result corresponding to at least one executed instruction within the preset range: if so, record the dependency relationship between the instruction and the executed instruction.

[0035] 203. A splitting module, configured to split the test case into a plurality of read-only memory files and a plurality of random access memory files based on a second preset rule; and run the plurality of read-only memory files and the plurality of random access memory files in parallel to obtain a running result.

[0036] In the embodiment of the present invention, in the segmentation module 203, the second preset rule is: Based on the basic block vector generation tool, the test case is completely run once and the feature points of the test case are collected to obtain a test case feature file; Analyzing and sampling the use case feature file based on a simulation point tool to obtain a cutting point file; wherein the cutting point file includes a plurality of specified cutting positions; The simulator runs the test case again and cuts the test case according to the cutting point file to obtain a plurality of read-only memory files and a plurality of random access memory files.

[0037] In this embodiment of the present invention, the segmentation module 203 further includes the following subunits: 2031, a judgment unit, configured to judge whether the current instruction of the simulator running the test case reaches the specified cutting position of the cutting point file; if so, jump to the query unit 2032; if not, the simulator continues to run the next instruction of the test case; 2032. A query unit, configured to query all current register information from the simulator and store all current register information in a new read-only memory file in sequence; query current memory information from the simulator and store the current memory information in a new random access memory file; 2033. An output unit, used to determine whether the simulator has run all the specified cutting positions in the cutting point file: if so, multiple read-only memory files and multiple random access memory files are output; if not, the simulator runs the next instruction of the test case and returns to the judgment unit 2031.

[0038] 204. An analysis module is configured to analyze the test case according to the instruction dependency statistical result and the running result to obtain an analysis result.

[0039] The performance acceleration analysis system 200 for the test case can implement the steps in the performance acceleration analysis method for the test case in the above embodiment, and can achieve the same technical effects. Please refer to the description in the above embodiment and will not be repeated here.

[0040] Example 3 The embodiment of the present invention also provides a computer device, please refer to Figure 3 , Figure 3 300 is a structural diagram of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a performance acceleration analysis program for test cases stored in the memory 302 and executable on the processor 301.

[0041] The processor 301 calls the performance acceleration analysis program of the test case stored in the memory 302 and executes the steps of the performance acceleration analysis method of the test case provided by the embodiment of the present invention. Figure 1 , specifically including the following steps: S1. Run a test case including multiple instructions through a simulator. When the test case is executed to a preset interval, obtain instruction information corresponding to each instruction in the preset interval; the instruction information includes instruction type, operand and calculation result.

[0042] In an embodiment of the present invention, the simulator is a QEMU (Quick Emulator) simulator, and the preset interval can be the range from any starting instruction to the ending instruction set in the test case. For example, when the simulator runs the test case and reaches the starting instruction, it starts to record the instruction information corresponding to the instruction (including the starting instruction) until it runs to the ending instruction. The range size of the preset interval can be set according to actual conditions.

[0043] S2. Based on the first preset rule and the instruction information, determine whether each of the instructions in the preset interval has a dependency, and obtain instruction dependency statistics.

[0044] In an embodiment of the present invention, the first preset rule is to determine whether the operands of each instruction within the preset interval are identical to the computation results of at least one previously executed instruction within the preset range. If so, the dependency relationship between the instruction and the previously executed instruction is recorded. The preset range refers to the n instructions that have been executed before the current instruction, with a maximum of 64 instructions. For example, the determination is made as to whether the operands of the current instruction are identical to the computation results of the 64 previously executed instructions.

[0045] Specifically, when optimizing for the characteristics of a test case, it's crucial to understand the number of instructions, instruction types, and dependencies between instructions within that test case. By counting the number of different types of instructions and the dependencies between them, we can obtain instruction dependency statistics. By calculating the dependencies between instructions, we can determine which instruction pairs appear most frequently in the test case. For example, addition instructions appear the most frequently, so subsequent chip design can prioritize optimizing the addition module to improve test case performance.

[0046] S3. Divide the test case into multiple read-only memory files and multiple random access memory files based on a second preset rule; run the multiple read-only memory files and the multiple random access memory files in parallel to obtain an operation result.

[0047] In this embodiment of the present invention, in step S3, the second preset rule is: S31. Based on the Basic Block Vector Generation Tool, the test case is completely run and the characteristic points of the test case are collected to obtain a test case characteristic file. The Basic Block Vector Generation Tool is a tool for statistically analyzing and quantifying the execution behavior of the Basic Block during program execution to generate "Basic Block Vectors" (i.e., characteristic points). The Basic Block Vector Generation Tool monitors the program execution process through instrumentation technology, records the number of executions of each Basic Block, and ultimately forms characteristic points reflecting the program behavior, thereby obtaining a test case characteristic file with multiple characteristic points.

[0048] S32. Analyze and sample the use case signature file using a simulation point tool (Simpoint tool) to obtain a cutpoint file. The cutpoint file includes multiple specified cutpoint locations. The Simpoint tool analyzes the basic block vectors generated by the use case signature file during runtime, divides the entire execution process into several "stages" with similar behaviors, and selects the most representative stages (called "Simpoints") from these stages. The cutpoint locations between each stage are determined. These stages accurately reflect the overall execution characteristics of the program, avoiding ineffective simulation of redundant or repetitive execution portions.

[0049] S33. The simulator runs the test case again and segments it according to the segmentation point file, generating multiple read-only memory (ROM) files (BootROM files) and multiple random access memory (RAM) files (MainRAM files). The ROM files store all register information at the time the slices were generated. The random access memory (RAM) files store all memory information at the time the slices were generated and are used for restoring the test case during runtime.

[0050] For example, a large test case (one with a particularly large number of instructions), such as 3 billion instructions, takes a while to run. The basic block vector generation tool identifies its characteristic points, and the simulation point tool slices it into six sections (the number of sections and the specific cut locations are customizable). The first section starts at instruction 0, the second at instruction 500 million, and so on. The result is six sets of slice files, each containing one ROM file and one RAM file, for a total of twelve files.

[0051] Step S33 includes the following sub-steps: S331, determining whether the current simulator's instruction for running the test case reaches the specified cutting position of the cutting point file: if so, proceeding to step S332; if not, the simulator continues to run the next instruction of the test case; S332, querying all current register information from the simulator, and storing all current register information in a new read-only memory file in sequence; querying current memory information from the simulator, and storing the current memory information in a new random access memory file; S333. Determine whether the simulator has run all the specified cutting positions in the cutting point file: if so, output the multiple read-only memory files and the multiple random access memory files; if not, the simulator runs the next instruction of the test case and returns to step S331.

[0052] S4. Analyze the test case according to the instruction dependency statistical result and the running result to obtain an analysis result.

[0053] The computer device 300 provided in the embodiment of the present invention can implement the steps in the performance acceleration analysis method of the test case in the above embodiment and can achieve the same technical effects. Please refer to the description in the above embodiment and will not be repeated here.

[0054] Example 4 An embodiment of the present invention also provides a computer-readable storage medium, which stores a performance acceleration analysis program for a test case. When the performance acceleration analysis program for the test case is executed by a processor, the various processes and steps in the performance acceleration analysis method for the test case provided by the embodiment of the present invention are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0055] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented using a computer program or hardware associated with instructions. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0056] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0057] Through the above description of the embodiments, those skilled in the art will clearly understand that the methods of the above embodiments can be implemented using software plus the necessary general-purpose hardware platform. Of course, hardware can also be used, but in many cases the former is the more preferred implementation method. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, or optical disk) and includes a number of instructions for enabling a terminal (such as a mobile phone, computer, server, air conditioner, or network device) to execute the methods described in the various embodiments of the present invention.

[0058] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A performance acceleration analysis method for a test case, characterized in that: The performance acceleration analysis method comprises the following steps: S1. Running a test case including multiple instructions through a simulator, and when the test case reaches a preset interval, obtaining instruction information corresponding to each instruction in the preset interval; the instruction information includes an instruction type, an operand, and a calculation result; S2. Determine whether each instruction in the preset interval has a dependency based on the instruction information based on a first preset rule, and obtain instruction dependency statistics; S3. Divide the test case into a plurality of read-only memory files and a plurality of random access memory files based on a second preset rule; run the plurality of read-only memory files and the plurality of random access memory files in parallel to obtain a running result; S4. Analyze the test case according to the instruction dependency statistical result and the running result to obtain an analysis result.

2. The performance acceleration analysis method for a test case according to claim 1, wherein: The first preset rule is: determining whether the operand of each instruction within the preset interval is the same as the calculation result corresponding to at least one executed instruction within the preset range: If so, the dependency relationship between the instruction and the executed instruction is recorded.

3. The performance acceleration analysis method for a test case according to claim 1, wherein: In step S3, the second preset rule is: S31, running the test case completely once based on a basic block vector generation tool and collecting feature points of the test case to obtain a test case feature file; S32. Analyze and sample the use case feature file based on a simulation point tool to obtain a cutting point file; wherein the cutting point file includes a plurality of designated cutting positions; S33. The simulator runs the test case again and cuts the test case according to the cutting point file to obtain a plurality of read-only memory files and a plurality of random access memory files.

4. The performance acceleration analysis method for a test case according to claim 3, wherein: Step S33 includes the following sub-steps: S331, determining whether the current simulator's instruction for running the test case reaches the specified cutting position of the cutting point file: if so, proceeding to step S332; if not, the simulator continues to run the next instruction of the test case; S332, querying all current register information from the simulator, and storing all current register information in a new read-only memory file in sequence; querying current memory information from the simulator, and storing the current memory information in a new random access memory file; S333. Determine whether the simulator has run all the specified cutting positions in the cutting point file: if so, output the multiple read-only memory files and the multiple random access memory files; if not, the simulator runs the next instruction of the test case and returns to step S331.

5. A performance acceleration analysis system for test cases, characterized in that: The performance acceleration analysis system for the test case includes: An execution module, configured to run a test case including a plurality of instructions through a simulator, and when the test case is executed to a preset interval, obtain an instruction type, an operand, and a calculation result corresponding to each instruction in the preset interval; A statistics module, configured to determine whether each of the instructions within the preset interval has a dependency based on a first preset rule, and obtain instruction dependency statistics; a splitting module, configured to split the test case into a plurality of read-only memory files and a plurality of random access memory files based on a second preset rule; and run the plurality of read-only memory files and the plurality of random access memory files in parallel to obtain a running result; The analysis module is used to analyze the test case according to the instruction dependency statistical result and the running result to obtain an analysis result.

6. The performance acceleration analysis system for test cases according to claim 5, characterized in that: The first preset rule is: determining whether the operand of each instruction within the preset interval is the same as the calculation result corresponding to at least one executed instruction within the preset range: If so, the dependency relationship between the instruction and the executed instruction is recorded.

7. The performance acceleration analysis system for test cases according to claim 5, characterized in that: In the segmentation module, the second preset rule is: Based on the basic block vector generation tool, the test case is completely run once and the feature points of the test case are collected to obtain a test case feature file; Analyzing and sampling the use case feature file based on a simulation point tool to obtain a cutting point file; wherein the cutting point file includes a plurality of specified cutting positions; The simulator runs the test case again and cuts the test case according to the cutting point file to obtain a plurality of read-only memory files and a plurality of random access memory files.

8. The performance acceleration analysis system for test cases according to claim 7, wherein: The segmentation module also includes the following subunits: A judging unit, configured to judge whether the current instruction of the simulator running the test case reaches the specified cutting position of the cutting point file: if so, jump to the query unit; if not, the simulator continues to run the next instruction of the test case; A query unit, configured to query all current register information from the simulator and store all current register information in a new read-only memory file in sequence; Querying current memory information from the simulator and storing the current memory information in a new random access memory file; The output unit is used to determine whether the simulator has run all the specified cutting positions in the cutting point file: if so, multiple read-only memory files and multiple random access memory files are output; if not, the simulator runs the next instruction of the test case and returns to the judgment unit.

9. A computer device, characterized in that: include: A memory, a processor, and a performance acceleration analysis program for a test case stored in the memory and executable on the processor, wherein the processor implements the steps of the performance acceleration analysis method for a test case as described in any one of claims 1 to 4 when executing the performance acceleration analysis program for the test case.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a performance acceleration analysis program for a test case, and when the performance acceleration analysis program for a test case is executed by a processor, the steps in the performance acceleration analysis method for a test case according to any one of claims 1 to 4 are implemented.

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