Adapter plate

Abstract

The invention discloses an adapter plate, and relates to the technical field of computers. The adapter plate comprises a first connector which is connected with two device end connectors of the storage device, and the device end connectors are used for transmitting dual-channel communication signals; the second connector is connected with a hard disk end connector of the solid state disk, and the hard disk end connector is used for transmitting four-channel communication signals; the conversion module comprises a circuit system, an end point subsystem and a root complex subsystem, the end point subsystem is connected with the first connector, and the root complex subsystem is connected with the second connector; wherein the conversion module is used for converting two paths of dual-channel communication signals, which are input to the first connector by the two equipment end connectors, into one path of four-channel communication signals, and transmitting the one path of four-channel communication signals to the hard disk end connector through the second connector. The solid state disk in a single-port mode can be adaptively used in the storage device through the adapter plate.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an adapter board. Background Art

[0002] Compared to mechanical hard disk drives (HDDs), solid-state drives (SSDs) offer significant advantages in read / write speed, power consumption, capacity, noise, and reliability. With the continuous advancements in storage media manufacturing processes and layering, capacity density continues to increase, and the capacity of single SSDs is increasing, while prices are becoming increasingly affordable. This has led to the widespread use of SSDs in servers and storage devices. Among these, solid-state drives based on the high-speed Peripheral Component Interconnect Express (PCIe) standard, or PCIe SSDs, offer significant advantages in bandwidth, latency, and other performance, and are gaining increasing market share.

[0003] Typically, PCIe SSDs operate in single-port mode, with four lanes in the SSD PCIe link connected to a central processing unit (CPU). However, single-port SSDs cannot function properly as storage devices.

[0004] How to properly use a single-port SSD on a storage device is one of the technical issues that urgently need to be solved in this field. Summary of the Invention

[0005] The present application provides an adapter board to at least solve the problem in the related art that a solid-state hard disk in a single-port mode cannot be normally used on a storage device.

[0006] The present application provides a transfer board, comprising: A first connector connected to two device-side connectors of a storage device, wherein the device-side connectors are used to transmit dual-channel communication signals; A second connector is connected to a hard disk end connector of the solid state drive, wherein the hard disk end connector is used to transmit four-channel communication signals; a conversion module, comprising a circuit system, an endpoint subsystem, and a root complex subsystem, wherein the endpoint subsystem is connected to the first connector, and the root complex subsystem is connected to the second connector; Among them, the conversion module is used to convert the two dual-channel communication signals input from the two device-end connectors to the first connector into one four-channel communication signal, and transmit the one four-channel communication signal to the hard disk-end connector through the second connector.

[0007] Through this application, including a first connector, a second connector and a conversion module, the circuit system, endpoint subsystem and root complex subsystem of the conversion module are used to convert two dual-channel communication signals from the storage device into one four-channel communication signal and transmit it to the solid-state drive. The single-port mode solid-state drive can be adaptively used in the storage device through the adapter board. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0009] Figure 1 A schematic diagram of the structure of the connection between the adapter board provided in an embodiment of the present application and the solid-state hard disk and storage device; Figure 2 One of the structural diagrams of the adapter board provided in the embodiment of the present application; Figure 3 The second structural diagram of the adapter board provided in the embodiment of the present application; Figure 4 This is the third structural diagram of the adapter board provided in the embodiment of the present application.

[0010] Reference numerals: First connector 100, first main power pin 110, first auxiliary power pin 120, first communication pin 130, first clock pin 140, first reset pin 150, first serial communication interface 160, first general input and output interface 170, first interface detection pin 180, first presence detection pin 190, second connector 200, second main power pin 210, second auxiliary power pin 220, fourth communication pin 230, fourth clock pin 240, fourth reset pin 250, second serial communication interface 260, second general input and output interface 270, second interface detection pin 280, second presence detection pin 290, Conversion module 300, power supply module 310, first step-down circuit 311, second step-down circuit 312, third step-down circuit 313, power supply redundancy switch 320, external storage device 330, firmware storage unit 340, debugging device 350, Power supply interface 301, external reset pin 302, third serial communication interface 303, third general input and output interface 304, debug interface 305, firmware interface 306, clock bus interface 307, external clock input pin 308, Endpoint subsystem 360, second communication pin 361, second clock pin 362, second reset pin 363, Root complex subsystem 370, third communication pin 371, third clock pin 372, third reset pin 373, fourth general input and output interface 374, Clock generator 380, first status indication interface 391, first status indicator light 392, second status indication interface 393, second status indicator light 394, Storage device 400, device-side connector 410, device-side central processing unit 420, Solid state drive 500 and hard drive connector 510 . DETAILED DESCRIPTION

[0011] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0012] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0013] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0014] Solid-state drives (SSDs) based on the high-speed Peripheral Component Interconnect Express (PCIe) standard, also known as PCIe SSDs, typically operate in single-port mode. Four lanes in the SSD's PCIe link connect to a central processing unit (CPU), making it suitable for server products.

[0015] The storage device has two device-side CPUs. The four lanes in the PCIe link are divided into two paths: two lanes connected to one device-side CPU and the other two lanes connected to the other device-side CPU. Therefore, a single-port SSD cannot be used properly in the storage device.

[0016] How to properly use a single-port SSD on a storage device is one of the technical issues that urgently need to be solved in this field.

[0017] An embodiment of the present application provides an adapter board that is connected between a storage device 400 and a solid-state drive 500, and can enable the storage device 400 to normally use the solid-state drive 500 in single-port mode.

[0018] like Figure 1 As shown, the adapter board includes: a first connector 100 , a second connector 200 and a conversion module 300 .

[0019] The first connector 100 is connected to two device-side connectors 410 of the storage device 400 , and the device-side connectors 410 are used to transmit dual-channel communication signals.

[0020] The communication signal transmitted by the storage device 400 is divided into two paths. One device-side connector 410 transmits one dual-channel communication signal, and the other device-side connector 410 transmits the other dual-channel communication signal.

[0021] For example, the storage device 400 has two device-side central processors 420, and the four lanes in the PCIe link are divided into two paths. The communication signals of two lanes are transmitted through one device-side connector 410, and the communication signals of the other two lanes are transmitted through another device-side connector 410. That is, the storage device 400 transmits two PCIe×2 signals through two device-side connectors 410 respectively, and one device-side connector 410 transmits one PCIe×2 signal.

[0022] The first connector 100 is connected to the two device-end connectors 410 of the storage device 400. The device-end connector 410 can be a female connector of the U.2 interface standard, and the first connector 100 can be a male connector of the U.2 interface standard. Two PCIe×2 signals are transmitted between the first connector 100 and the two device-end connectors 410.

[0023] The second connector 200 is connected to the hard disk end connector 510 of the solid state disk 500 , and the hard disk end connector 510 is used to transmit four-channel communication signals.

[0024] For example, the solid-state drive 500 supports a single-port mode, and the hard disk connector 510 transmits four channels of communication signals, that is, the hard disk connector 510 transmits one PCIe×4 signal.

[0025] The second connector 200 is connected to the hard disk end connector 510 of the solid-state hard disk 500. The second connector 200 can be a female connector of the U.2 interface standard, and the hard disk end connector 510 can be a male connector of the U.2 interface standard. One PCIe×4 signal is transmitted between the second connector 200 and the hard disk end connector 510.

[0026] The conversion module 300 includes a circuit system, an endpoint subsystem 360 and a root complex subsystem 370 . The endpoint subsystem 360 is connected to the first connector 100 , and the root complex subsystem 370 is connected to the second connector 200 .

[0027] It is understandable that the circuit system refers to the most basic hardware and software configuration that enables the conversion module 300 to start and operate normally, that is, the minimum system that constitutes the conversion module 300.

[0028] In this embodiment, the conversion module 300 is used to convert the two dual-channel communication signals input from the two device-end connectors 410 to the first connector 100 into one four-channel communication signal, and transmit the one four-channel communication signal to the hard disk-end connector 510 through the second connector 200.

[0029] For example, the conversion module 300 is used to convert two PCIe×2 signals from the storage device 400 into one PCIe×4 signal, and transmit the PCIe×4 signal to the solid-state drive 500, so that the storage device 400 can normally use the solid-state drive 500 in single-port mode.

[0030] It should be noted that the endpoint subsystem 360 is connected to the first connector 100, and the endpoint subsystem 360 is used to receive and process the two-way dual-channel communication signals transmitted by the first connector 100. The root complex subsystem 370 is connected to the second connector 200, and the root complex subsystem 370 is used to generate a four-channel communication signal based on the two-way dual-channel communication signals, and transmit the four-channel communication signal to the second connector 200.

[0031] A specific embodiment is described below.

[0032] The solid-state drive 500 has an external PCIe interface that supports single-port mode. The external PCIe interface supports 4 lanes, corresponding to 4 groups of PCIe transmit signals (TX) and receive signals (RX), 1 group of reset signals (RSTn) and 1 group of reference clock signals (REFCLK). The solid-state drive 500 adopts the PCIe3.0 interface standard. The solid-state drive 500 is hereinafter referred to as PCIe3.0×4 single-port SSD.

[0033] It should be noted that the PCIe3.0 interface standard is only an example. The adapter board in the embodiment of the present application is also applicable to the PCIe4.0 interface standard, PCIe5.0 interface standard, PCIe6.0 interface standard, etc.

[0034] In a server product system, the solid-state drive 500 can be used directly. In a storage product system, the solid-state drive 500 and the storage device 400 are connected via an adapter board.

[0035] The adapter board includes a first connector 100, a second connector 200 and a conversion module 300. The circuit system, endpoint subsystem 360 and root complex subsystem 370 of the conversion module 300 are used to convert two PCIe×2 signals from the storage device 400 into one PCIe×4 signal, thereby realizing the application of PCIe3.0×4 single-port SSD on the storage device 400. The device-side central processor 420 of the storage device 400 can realize read and write business operations on the solid-state drive 500 that supports a single port through the adapter board, which makes up for the functional defects of the single-port SSD and helps to improve the comprehensive competitiveness of the single-port SSD.

[0036] According to the adapter board provided in the embodiment of the present application, including a first connector 100, a second connector 200 and a conversion module 300, the circuit system, endpoint subsystem 360 and root complex subsystem 370 of the conversion module 300 are used to convert the two-way dual-channel communication signals from the storage device 400 into one-way four-channel communication signals and transmit them to the solid-state drive 500. The solid-state drive 500 in single-port mode can be adaptively used in the storage device 400 through the adapter board.

[0037] In some embodiments, the circuit system includes a power module 310 , a clock input circuit, a reset circuit, a debug interface 305 , and a firmware storage unit 340 .

[0038] The debugging interface 305 is an interface for developing and testing the adapter board. The debugging interface 305 can be connected to the debugging device 350 to provide a debugging function for the adapter board.

[0039] In actual implementation, the debugging interface 305 can be a hardware interface such as an international standard test protocol Joint Test Action Group (JTAG) interface, an asynchronous receiver-transmitter (UART) interface, etc., which is connected to the external debugging device 350 to provide online debugging and serial port debugging functions of the adapter board.

[0040] Among them, the clock input circuit is a circuit used to receive and process clock signals.

[0041] In actual implementation, an external 25 MHz crystal or crystal oscillator can be connected to the clock input circuit, that is, connected to the crystal oscillator input or external clock input pin 308 of the conversion module 300 to provide the working system clock of the adapter board and the external hardware unit clock.

[0042] In this embodiment, if Figure 2 As shown, the conversion module 300 is provided with a firmware interface 306 , and the firmware interface 306 is connected to an external firmware storage unit 340 .

[0043] In actual implementation, the firmware interface 306 may be a synchronous serial communication interface (Serial Peripheral Interface, SPI) and the firmware storage unit 340 may be a NOR Flash memory. The capacity of the firmware storage unit 340 is determined according to requirements, such as 32 megabits (Mb), 64Mb, 128Mb, etc.

[0044] In this embodiment, the firmware storage unit 340 is used to store system firmware, and the system firmware is used to configure port operating modes of the endpoint subsystem 360 and the root complex subsystem 370 .

[0045] For example, the endpoint subsystem 360 supports a port working mode of one PCIe3.0×8 and a port working mode of two PCIe3.0×4. The endpoint subsystem 360 needs to convert the two PCIe3.0×2 signals from the storage device 400 into a PCIe3.0×4 signal. The endpoint subsystem 360 is configured to a port working mode of two PCIe3.0×4. The port working mode run by the endpoint subsystem 360 is implemented by the firmware of the firmware storage unit 340.

[0046] For another example, the root complex subsystem 370 supports a port working mode of two PCIe 3.0×4 lanes, a port working mode of one PCIe 3.0×4 lane plus two PCIe 3.0×2 lanes, a port working mode of two PCIe 3.0×2 lanes plus one PCIe 3.0×4 lanes, and a port working mode of four PCIe 3.0×2 lanes.

[0047] In this embodiment, the root complex subsystem 370 is connected to the hard disk end connector 510 through the second connector 200, and requires the transmission of one PCIe3.0×4 signal. The root complex subsystem 370 can be configured as a port working mode of two PCIe3.0×4 or a port working mode of one PCIe3.0×4 plus two PCIe3.0×2. The root complex subsystem 370 can also be configured as a port working mode of two PCIe3.0×2 plus one PCIe3.0×4. The port working mode run by the root complex subsystem 370 is implemented by the firmware of the firmware storage unit 340.

[0048] It can be understood that in the circuit system of the conversion module 300, the power module 310 is a module in the adapter board that implements the power supply function, and the reset circuit is a circuit that generates and manages the reset signal, which is used to initialize the adapter board.

[0049] In some embodiments, the power module 310 includes a first buck circuit 311 , a second buck circuit 312 , and a third buck circuit 313 .

[0050] like Figure 3 As shown, the input end of the first buck circuit 311 is connected to the first main power pin 110 of the first connector 100, the output end of the first buck circuit 311 is connected to the input end of the second buck circuit 312, and the input end of the third buck circuit 313 is connected to the first main power pin 110.

[0051] In this embodiment, the first step-down circuit 311 is used to convert the first power supply voltage provided by the first main power supply pin 110 into a second power supply voltage, and output the second power supply voltage to the second step-down circuit 312. The second step-down circuit 312 is used to convert the second power supply voltage into a third power supply voltage to power the conversion module 300; the third step-down circuit 313 is used to convert the first power supply voltage into a fourth power supply voltage to power the conversion module 300; wherein the fourth power supply voltage is less than the third power supply voltage.

[0052] It is understandable that the first buck circuit 311 , the second buck circuit 312 and the third buck circuit 313 may be DC / DC buck circuits.

[0053] For example, the first main power pin 110 provides a power voltage of 12 volts (V).

[0054] The first main power pin 110 provides a first power voltage of 12V, and the first step-down circuit 311 converts the first power voltage of 12V provided by the first main power pin 110 into a second power voltage of 3.3V.

[0055] The second power supply voltage 3.3V serves as the input of the second step-down circuit 312 , and the output end of the second step-down circuit 312 is connected to the power interface 301 of the conversion module 300 . The second step-down circuit 312 converts the second power supply voltage 3.3V into a third power supply voltage 1.8V to power the conversion module 300 .

[0056] The first main power pin 110 provides a first power supply voltage of 12V and also serves as an input of the third step-down circuit 313. The output end of the third step-down circuit 313 is connected to the power interface 301 of the conversion module 300. The third step-down circuit 313 converts the first power supply voltage of 12V into a fourth power supply voltage of 0.9V to power the conversion module 300.

[0057] In some embodiments, the first buck circuit 311 is also used to output a power status signal to the second buck circuit 312 to generate an enable signal for the second buck circuit 312; the second buck circuit 312 is also used to output a power status signal to the third buck circuit 313 to generate an enable signal for the third buck circuit 313.

[0058] The power status signal (Power Good, PG) is a signal used to indicate whether the power supply is stable, and the enable signal is used to start and stop the buck circuit.

[0059] In this embodiment, the first buck circuit 311 outputs the second power supply voltage to the second buck circuit 312 while outputting a power status signal corresponding to the first buck circuit 311 to generate an enable signal for the second buck circuit 312 to control the second buck circuit 312 to start voltage conversion.

[0060] While performing voltage conversion, the second step-down circuit 312 outputs a power state signal corresponding to the second step-down circuit 312 , generates an enable signal for the third step-down circuit 313 , and controls the third step-down circuit 313 to start voltage conversion.

[0061] In some embodiments, the third step-down circuit 313 is further configured to output a power status signal to generate an external reset signal for the conversion module 300 .

[0062] In this embodiment, the third step-down circuit 313 serves as part of the reset circuit. The third step-down circuit 313 is connected to the external reset pin 302 . The third step-down circuit 313 outputs its corresponding power state signal as the external reset signal of the conversion module 300 .

[0063] It should be noted that, by outputting a power status signal through the first step-down circuit 311, the second step-down circuit 312 is enabled, the second step-down circuit 312 outputs a power status signal, the third step-down circuit 313 is enabled, the third step-down circuit 313 outputs a power status signal, and an external reset signal is provided, so that the third power supply voltage can be powered on first and the fourth power supply voltage can be powered on later. After the power supply is stable, the timing circuit control of the external reset signal is pulled high.

[0064] It can be understood that the first connector 100 includes a first main power pin 110 and a first auxiliary power pin 120, and the second connector 200 includes a second main power pin 210 and a second auxiliary power pin 220. The main power pin provides the main operating voltage, and the auxiliary power pin can power non-core functions or low-power modules.

[0065] In some embodiments, the first auxiliary power pin 120 of the first connector 100 and the output end of the first step-down circuit 311 are connected to the external storage device 330 through a power redundancy switch 320. The power redundancy switch 320 is used to convert the auxiliary power voltage and the second power voltage provided by the first auxiliary power pin 120 into an external power voltage to power the external storage device 330. The external storage device 330 is used to store product data.

[0066] In this embodiment, the power redundancy switch 320 may be a power switching circuit including a metal-oxide-semiconductor field-effect transistor (MOSFET) or a diode, the external storage device 330 may be an electrically erasable programmable read-only memory (EEPROM), and the product data is vital product data (VPD).

[0067] For example, the first main power pin 110 provides a power voltage of 12 volts (V).

[0068] The first main power pin 110 provides a first power voltage of 12V, and the first step-down circuit 311 converts the first power voltage of 12V provided by the first main power pin 110 into a second power voltage of 3.3V.

[0069] The power redundancy switch 320 converts the auxiliary power voltage and the second power voltage 3.3 V provided by the first auxiliary power pin 120 into an external power voltage 3.3 V to power the external storage device 330. When the first main power pin 110 cannot supply power normally, the baseboard management controller (BMC) of the storage device 400 can obtain the VPD information of the adapter board through the external storage device 330.

[0070] In some embodiments, the first main power pin 110 of the first connector 100 is connected to the second main power pin 210 of the second connector 200 ; the first auxiliary power pin 120 of the first connector 100 is connected to the second auxiliary power pin 220 of the second connector 200 .

[0071] In this embodiment, the first main power pin 110 of the first connector 100 is connected to the second main power pin 210 of the second connector 200, and the first auxiliary power pin 120 of the first connector 100 is connected to the second auxiliary power pin 220 of the second connector 200, so that the storage device 400 supplies power to the solid state drive 500.

[0072] The endpoint subsystem 360 and the root complex subsystem 370 are respectively introduced in detail below.

[0073] In some embodiments, the endpoint subsystem 360 is provided with at least four second communication pins 361 .

[0074] When the endpoint subsystem 360 operates in a four-channel working mode, the four first communication pins 130 of the first connector 100 are connected to the four second communication pins 361 of the endpoint subsystem 360 in a one-to-one correspondence to transmit two dual-channel communication signals.

[0075] For example, Figure 4 As shown, the endpoint subsystem 360 has eight second communication pins 361, and one second communication pin 361 can transmit a communication signal of one channel. The endpoint subsystem 360 supports one PCIe3.0×8 port working mode and two PCIe3.0×4 port working modes.

[0076] When the endpoint subsystem 360 operates in a four-channel working mode, that is, the endpoint subsystem 360 operates in a two-channel PCIe3.0×4 port working mode, the four first communication pins 130 of the first connector 100 are connected one-to-one with the four second communication pins 361 of the endpoint subsystem 360, thereby building a communication link between the endpoint subsystem 360 and the storage device 400 and completing the transmission of two-channel PCIe×2 signals.

[0077] In some embodiments, the two first clock pins 140 of the first connector 100 are connected to the two second clock pins 362 of the endpoint subsystem 360 in a one-to-one correspondence to transmit two clock signals.

[0078] In this embodiment, the first clock pin 140 of the first connector 100 is connected to the second clock pin 362 of the endpoint subsystem 360 , so that the storage device 400 provides two clock signals (eg, a 100 MHz clock signal) to the endpoint subsystem 360 .

[0079] In some embodiments, the two first reset pins 150 of the first connector 100 are connected to the two second reset pins 363 of the endpoint subsystem 360 in a one-to-one correspondence to transmit two reset signals.

[0080] In this embodiment, the first reset pin 150 of the first connector 100 is connected to the second reset pin 363 of the endpoint subsystem 360 , so that the storage device 400 provides two reset signals to the endpoint subsystem 360 .

[0081] It is understandable that, with the coordinated action of two clock signals, two reset signals, and two dual-channel communication signals, stable link communication can be achieved between the storage device 400 and the endpoint subsystem 360 .

[0082] It should be noted that the endpoint subsystem 360 has eight second communication pins 361 , and the four-channel working mode only uses four second communication pins 361 , and the read and write signals of the remaining four second communication pins 361 not connected to the first connector 100 are left floating.

[0083] In some embodiments, the conversion module 300 is further provided with two first status indication interfaces 391 , which are used to connect to first status indicator lights 392 , and the two first status indicator lights 392 are used to respectively indicate the transmission status of the two dual-channel communication signals.

[0084] like Figure 4 As shown, the first status indication interface 391 is connected to the first status indicator light 392. The first status indicator light 392 lights up in different colors to indicate different signal transmission states. Green indicates that the signal transmission is valid, and amber indicates a signal transmission failure. The storage device 400 and the endpoint subsystem 360 transmit two PCIe×2 signals. One first status indicator light 392 indicates the transmission status of one PCIe×2 signal, and the other first status indicator light 392 indicates the transmission status of the other PCIe×2 signal.

[0085] In actual implementation, the driving logic of the first status indicator light 392 may be stored in the firmware storage unit 340 .

[0086] In some embodiments, the root complex subsystem 370 is provided with at least four third communication pins 371 .

[0087] When the root complex subsystem 370 operates in a four-channel working mode, the four third communication pins 371 of the root complex subsystem 370 are connected to the four fourth communication pins 230 of the second connector 200 in a one-to-one correspondence to transmit one four-channel communication signal.

[0088] For example, Figure 4 As shown, the root complex subsystem 370 has eight third communication pins 371, and one third communication pin 371 can transmit the communication signal of one channel. The root complex subsystem 370 supports the port working mode of two PCIe3.0×4, the port working mode of one PCIe3.0×4 plus two PCIe3.0×2, the port working mode of two PCIe3.0×2 plus one PCIe3.0×4, and the port working mode of four PCIe3.0×2.

[0089] When the root complex subsystem 370 operates in a four-channel working mode, that is, the endpoint subsystem 360 operates in a two-lane PCIe3.0×4 port working mode, a one-lane PCIe3.0×4 plus two-lane PCIe3.0×2 port working mode, or a two-lane PCIe3.0×2 plus one-lane PCIe3.0×4 port working mode, the four third communication pins 371 of the root complex subsystem 370 are connected one-to-one with the four fourth communication pins 230 of the second connector 200, thereby building a communication link between the root complex subsystem 370 and the solid-state drive 500 and completing the transmission of one PCIe×4 signal.

[0090] In some embodiments, the adapter board also includes a clock generator 380, which is connected to the third clock pin 372 of the root complex subsystem 370 and the fourth clock pin 240 of the second connector 200. The clock generator 380 is used to generate two clock signals and transmit the two clock signals to the root complex subsystem 370 and the second connector 200 respectively.

[0091] In this embodiment, the clock generator 380 provides a homologous clock signal to the solid-state drive 500 connected to the second connector 200 and the root complex subsystem 370 .

[0092] In actual implementation, the clock generator 380 can be a 100MHz dual-channel clock output generator. The 25MHz crystal outputs a 25MHz reference clock to the clock generator 380 . The first clock output of the clock generator 380 is given to the root complex subsystem 370 , and the second clock output is given to the second connector 200 .

[0093] In some embodiments, the third reset pin 373 of the root complex subsystem 370 is connected to the fourth reset pin 250 of the second connector 200 to transmit a reset signal.

[0094] It should be noted that the root complex subsystem 370 has eight third communication pins 371, and the four-channel working mode only uses four third communication pins 371. The read and write signals of the remaining four third communication pins 371 that are not connected to the second connector 200 are left floating, and the remaining three third reset pins 373 that are not connected to the second connector 200 are also left floating.

[0095] It is understandable that, with the coordinated effects of two clock signals, one reset signal, and one four-channel communication signal, a stable link communication between the solid-state drive 500 and the root complex subsystem 370 can be achieved.

[0096] In some embodiments, the conversion module 300 is further provided with a second status indication interface 393, which is used to connect to a second status indicator light 394, and the second status indicator light 394 is used to indicate the transmission status of the communication signal of one channel and four channels.

[0097] like Figure 4 As shown, the second status indication interface 393 is connected to the second status indicator light 394. The second status indicator light 394 lights up in different colors to indicate different signal transmission states. A PCIe×4 signal is transmitted between the solid-state drive 500 and the root complex subsystem 370. The second status indicator light 394 indicates the transmission state of the PCIe×4 signal. The driving logic of the second status indicator light 394 can also be stored in the firmware storage unit 340.

[0098] In some embodiments, the first connector 100 is provided with a first serial communication interface 160 , the second connector 200 is provided with a second serial communication interface 260 , and the conversion module 300 is provided with a third serial communication interface 303 .

[0099] The first serial communication interface 160 , the second serial communication interface 260 and the third serial communication interface 303 are connected to a system management bus, which is also connected to an external storage device 330 .

[0100] The System Management Bus (SMBus) is a serial bus protocol used for communication between computer hardware components.

[0101] In this embodiment, the third serial communication interface 303 provided in the conversion module 300 may be an Inter-Integrated Circuit (I2C) serial communication protocol interface, which is connected to the external storage device 330 via a system management bus.

[0102] like Figure 2 As shown, the first serial communication interface 160, the second serial communication interface 260 and the third serial communication interface 303 are connected to the system management bus, and the external storage device 330 is also connected to the system management bus, so that the BMC of the storage device 400 can obtain the VPD information of the adapter board, the VPD information of the solid-state drive 500, and out-of-band management information, etc.

[0103] It is understandable that the adapter board can also be configured with a general purpose input and output interface (GPIO).

[0104] In some embodiments, the first connector 100 is provided with a first universal input / output interface 170 , and the second connector 200 is provided with a second universal input / output interface 270 . The first universal input / output interface 170 is connected to the second universal input / output interface 270 .

[0105] The first GPIO interface 170 outputs a level signal to the second GPIO interface 270 , so that the SSD 500 determines the type of device connected to the SSD 500 based on the received level signal.

[0106] In this embodiment, the first universal input / output interface 170 of the first connector 100 is connected to the second universal input / output interface 270 of the second connector 200. When the storage device 400 is inserted into the solid-state hard disk 500 connected to the adapter board, the first universal input / output interface 170 can output a low level, and the second universal input / output interface 270 receives a low level, indicating that the host into which the solid-state hard disk 500 is inserted is the storage device 400, not a server product.

[0107] In some embodiments, the first connector 100 is provided with a first universal input / output interface 170 , the conversion module 300 is provided with a third universal input / output interface 304 , and the first universal input / output interface 170 is connected to the third universal input / output interface 304 .

[0108] The first GPIO interface 170 outputs a level signal to the third GPIO interface 304 , so that the conversion module 300 runs the system firmware stored in the firmware storage unit 340 of the circuit system based on the received level signal.

[0109] In this embodiment, the first universal input / output interface 170 of the first connector 100 is connected to the third universal input / output interface 304 of the conversion module 300. When the storage device 400 is inserted into the solid-state hard disk 500 connected to the adapter board, the first universal input / output interface 170 can output a low level, and the third universal input / output interface 304 receives the low level and runs the system firmware stored in the firmware storage unit 340, so that the endpoint subsystem 360 and the root complex subsystem 370 can operate according to the set port working mode.

[0110] In some embodiments, the first connector 100 is further provided with a first interface detection pin 180 and a first presence detection pin 190 .

[0111] The signal of the first interface detection pin 180 may be an interface detection signal (IFDET), and the signal of the first presence detection pin 190 may be a present signal (PRSNT).

[0112] In this embodiment, the first interface detection pin 180 is grounded, and the first presence detection pin 190 is left floating, indicating that the first connector 100 is connected to the storage device 400 .

[0113] In some embodiments, the second connector 200 is further provided with a second interface detection pin 280 and a second presence detection pin 290 .

[0114] The signal of the second interface detection pin 280 may be an IFDET signal, and the signal of the second presence detection pin 290 may be a PRSNT signal.

[0115] like Figure 2 As shown, the conversion module 300 is provided with a clock bus interface 307 , the clock generator 380 is connected to the clock bus interface 307 , and the clock bus interface 307 may be an I2C interface.

[0116] The clock generator 380 has dual clock outputs, and the first clock output enable signal is grounded, indicating that the first clock output of the clock generator 380 is given to the root complex subsystem 370, and the second clock output enable signal is connected to the second interface detection pin 280, and the second interface detection pin 280 is grounded. When the adapter card is inserted into the solid-state drive 500, the second clock output enable signal is grounded, and the second clock of the clock generator 380 is given to the solid-state drive 500 through the second connector 200.

[0117] In actual implementation, the second interface detection pin 280 is also connected to the fourth general input and output interface 374 of the conversion module 300 to provide the IFDET signal of the solid state drive 500 to the conversion module 300 .

[0118] In this embodiment, the second presence detection pin 290 is left floating, indicating that the solid state drive 500 is connected.

[0119] The adapter board of the embodiment of the present application includes a first connector 100, a second connector 200 and a conversion module 300. By utilizing the reasonable configuration of the hardware circuits and firmware such as the circuit system, endpoint subsystem 360 and root complex subsystem 370 of the conversion module 300, two PCIe×2 signals from the storage device 400 are converted into one PCIe×4 signal, thereby realizing communication between the storage device 400 and the solid-state drive 500 in single-port mode, making up for the functional defects of the solid-state drive 500 in single-port mode, and helping to improve the overall competitiveness of the solid-state drive 500 in single-port mode.

[0120] The above is a detailed introduction to the adapter board provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A transfer plate, characterized in that: include: A first connector connected to two device-side connectors of a storage device, wherein the device-side connectors are used to transmit dual-channel communication signals; A second connector is connected to a hard disk end connector of the solid state drive, wherein the hard disk end connector is used to transmit four-channel communication signals; a conversion module, comprising a circuit system, an endpoint subsystem, and a root complex subsystem, wherein the endpoint subsystem is connected to the first connector, and the root complex subsystem is connected to the second connector; Among them, the conversion module is used to convert the two dual-channel communication signals input from the two device-end connectors to the first connector into one four-channel communication signal, and transmit the one four-channel communication signal to the hard disk-end connector through the second connector.

2. The adapter plate according to claim 1, wherein: The circuit system includes a power supply module, a clock input circuit, a reset circuit, a debugging interface and a firmware storage unit. The firmware storage unit is used to store system firmware, and the system firmware is used to configure the port working mode of the endpoint subsystem and the root complex subsystem.

3. The adapter plate according to claim 2, characterized in that: The power supply module includes a first step-down circuit, a second step-down circuit and a third step-down circuit; The input end of the first step-down circuit is connected to the first main power pin of the first connector, the output end of the first step-down circuit is connected to the input end of the second step-down circuit, and the input end of the third step-down circuit is connected to the first main power pin; The first step-down circuit is used to convert the first power supply voltage provided by the first main power supply pin into a second power supply voltage, and output the second power supply voltage to the second step-down circuit, and the second step-down circuit is used to convert the second power supply voltage into a third power supply voltage to power the conversion module; The third step-down circuit is used to convert the first power supply voltage into a fourth power supply voltage to power the conversion module; The fourth power supply voltage is lower than the third power supply voltage.

4. The adapter plate according to claim 3, characterized in that: The first step-down circuit is further configured to output a power state signal to the second step-down circuit to generate an enable signal for the second step-down circuit; The second buck circuit is further configured to output a power state signal to the third buck circuit to generate an enable signal for the third buck circuit.

5. The adapter plate according to claim 3, characterized in that: The third step-down circuit is further configured to output a power state signal to generate an external reset signal for the conversion module.

6. The adapter plate according to claim 3, characterized in that: The first auxiliary power pin of the first connector and the output end of the first step-down circuit are connected to an external storage device through a power redundancy switch. The power redundancy switch is used to convert the auxiliary power voltage provided by the first auxiliary power pin and the second power voltage into an external power voltage to power the external storage device, which is used to store product data.

7. The adapter plate according to any one of claims 1 to 6, characterized in that: The first main power pin of the first connector is connected to the second main power pin of the second connector; the first auxiliary power pin of the first connector is connected to the second auxiliary power pin of the second connector.

8. The adapter plate according to any one of claims 1 to 6, characterized in that: The endpoint subsystem is provided with at least four second communication pins; When the endpoint subsystem operates in a four-channel working mode, the four first communication pins of the first connector are connected to the four second communication pins of the endpoint subsystem in a one-to-one correspondence to transmit two dual-channel communication signals.

9. The adapter plate according to claim 8, characterized in that: The two first clock pins of the first connector are connected to the two second clock pins of the endpoint subsystem in a one-to-one correspondence to transmit two clock signals; The two first reset pins of the first connector are connected to the two second reset pins of the endpoint subsystem in a one-to-one correspondence to transmit two reset signals.

10. The adapter plate according to claim 8, characterized in that: The conversion module is further provided with two first status indication interfaces, which are used to connect to first status indicator lights, and the two first status indicator lights are used to respectively indicate the transmission status of the two dual-channel communication signals.

11. The adapter plate according to any one of claims 1 to 6, characterized in that: The root complex subsystem is provided with at least four third communication pins; When the root complex subsystem operates in a four-channel working mode, the four third communication pins of the root complex subsystem are connected to the four fourth communication pins of the second connector in a one-to-one correspondence to transmit one four-channel communication signal.

12. The adapter plate according to claim 11, characterized in that: Also includes: a clock generator connected to the third clock pin of the root complex subsystem and the fourth clock pin of the second connector, the clock generator being configured to generate two clock signals and transmit the two clock signals to the root complex subsystem and the second connector respectively; The third reset pin of the root complex subsystem is connected to the fourth reset pin of the second connector to transmit a reset signal.

13. The adapter plate according to claim 11, characterized in that: The conversion module is further provided with a second status indication interface, which is used to connect to a second status indicator light, and the second status indicator light is used to indicate the transmission status of the communication signal of one channel and four channels.

14. The adapter plate according to any one of claims 1 to 6, characterized in that: The first connector is provided with a first universal input / output interface, the second connector is provided with a second universal input / output interface, and the first universal input / output interface is connected to the second universal input / output interface; The first universal input / output interface outputs a level signal to the second universal input / output interface, so that the solid state drive determines the type of device connected to the solid state drive based on the received level signal.

15. The adapter plate according to any one of claims 1 to 6, characterized in that: The first connector is provided with a first universal input / output interface, the conversion module is provided with a third universal input / output interface, and the first universal input / output interface is connected to the third universal input / output interface; The first universal input / output interface outputs a level signal to the third universal input / output interface, so that the conversion module runs the system firmware stored in the firmware storage unit of the circuit system based on the received level signal.

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