Mixed directory setting method, storage medium and electronic equipment

Abstract

The invention discloses a mixed directory setting method, a storage medium and electronic equipment, and relates to the technical field of data processing, and the method comprises the following steps: determining the number of processor cores of data copies with shared resources; if the number of the processor cores does not exceed a preset number threshold value, a limited pointer directory is used as a target directory, and pointers of the limited pointer directory are associated with the processor cores storing data copies of the shared resources; otherwise, using the two-stage sparse catalog as the target catalog, dividing the processor core into a plurality of subsets, and using the first-stage table item and the second-stage table item in the two-stage sparse catalog to associate the processor core stored with the data copy in the target subset; and if the processor cores for carrying out consistency change operation on the shared resources exist, the data copies of the processor cores storing the data copies are adjusted through the target directory, so that the processor cores synchronize the consistency change operation, and the availability of the directory is improved.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a hybrid directory setting method, storage medium and electronic equipment. Background Art

[0002] In computer architecture, cache coherence refers to ensuring that data on shared resources remains consistent across multiple local caches. This is particularly important in multi-core processor environments, where multiple clients (e.g., processor cores) in the system may cache shared memory resources, leading to data inconsistencies. With the prevalence of multi-core processors, the primary challenge facing cache coherence is maintaining the consistency of the same data across multiple caches and memories.

[0003] In single-core processor systems, since there is only one CPU core and its cache, cache coherence across multiple cores is not an issue. However, in multi-processor or multi-core systems, each processor or core is typically equipped with its own private cache to improve system performance. These caches play a key role in computer architecture by providing fast and convenient access to frequently accessed data. However, maintaining the consistency of data in these private caches is a challenging task, often leading to cache coherence issues.

[0004] The primary function of a cache coherence directory system is to address data consistency. This system relies on a centralized directory to maintain cache coherence. In this system, coherence states typically include Modified (M), Exclusive (E), Shared (S), and Invalid (I). When a processor initiates a memory access request, the directory is queried to verify the current state of the data block, which determines subsequent memory operations. Furthermore, when the state of a data block in a processor's cache changes, the latest state must be promptly updated in the directory to maintain cache coherence in multiprocessor systems.

[0005] In related technologies, the status and location of cache blocks are directly reflected by replicating the tag and status information in all private caches. This method is easy to manage and can find the corresponding location of each processor's data block in the replicated directory, thereby providing optimal performance. However, this solution has low space utilization and poor scalability. In particular, when the number of processor cores increases, the required storage space increases significantly, making it difficult to support system expansion. Therefore, although the replicated directory has advantages in some aspects, its limitations in handling scale issues affect its general usability. Summary of the Invention

[0006] The present invention aims to solve one of the technical problems in the related art to at least a certain extent. To this end, one object of the present invention is to provide a hybrid directory setting method, storage medium and electronic device to improve the usability of the directory.

[0007] According to a first aspect of an embodiment of the present invention, a method for setting a hybrid directory is provided, the method comprising: Determine the number of processor cores that have data replicas of shared resources; If the number of processor cores does not exceed a preset number threshold, a limited pointer directory is used as the target directory, wherein the pointers of the limited pointer directory are associated with the processor cores storing the data copies of the shared resource; Otherwise, using a two-level sparse directory as a target directory, dividing the processor cores into multiple subsets, using the first-level table entries in the two-level sparse directory to identify the target subset where the processor cores storing the data copies are located, recording the consistency status of the data copies in the first-level table entries, and using the second-level table entries in the sparse directory to associate the processor cores storing the data copies in the target subset; If there is a processor core that performs a consistency change operation on the shared resource, the data copy of the processor core storing the data copy is adjusted through the target directory, so that each processor core synchronizes the consistency change operation.

[0008] Optionally, when the pointers of the limited pointer directory are associated with C processor cores, each pointer has bit field.

[0009] Optionally, the first-level table entry includes a tag field, a status bit and a first bit vector, wherein the tag field identifies the address of the shared resource, the status bit records the consistency status, and the first bit vector identifies a subset of data copies having the shared resource.

[0010] Optionally, the secondary table entry includes a subset number and a second bit vector, where the second bit vector identifies the processor core having the data copy in the subset identified by the subset number.

[0011] Optionally, the first index of the first-level table entry is obtained based on the address information of the data block where the data copy is located; the second bit vector contains the second index of the second-level table entry, and the second index is obtained based on the hash operation of the first index and the subset number.

[0012] Optionally, the limited pointer directory and the two-level sparse directory share directory storage space; If there is a target entry to be allocated and there is an empty entry in the directory storage space, the empty entry is allocated to the target entry.

[0013] Optionally, if there is no empty entry in the directory storage space, the target entry is used to replace a non-empty entry in the directory storage space, and the data copy corresponding to the replaced non-empty entry is invalidated.

[0014] Optionally, the first-level table entry and the second-level table entry are stored in the same data block and are distinguished by the highest bit of the table entry.

[0015] According to a second aspect of an embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned hybrid directory setting method is implemented.

[0016] According to a third aspect of an embodiment of the present invention, an electronic device is provided, comprising: a memory and a processor; a computer program is stored in the memory, and when the computer program is executed by the processor, the above-mentioned hybrid directory setting method is implemented.

[0017] In the solution provided by the embodiment of the present invention, according to the solution provided by the embodiment of the present invention, when the number of processor cores with data copies is small, a limited pointer directory is used to record the processor cores, and the pointers in the limited pointer directory can directly retrieve the cores that specifically contain the data copies. The directory search process is simple, which can significantly improve the overall processing efficiency of the system and the management efficiency of data sharing information; after exceeding a preset number threshold, when the number of processor cores sharing resources is large, it automatically switches to a two-level sparse directory to maintain the efficiency and continuity of data access, and manages the shared information of all processor cores by subset. When performing a directory query, it is no longer necessary to traverse all processor cores in the system, but only to focus on those subsets related to data copies, which can accommodate more processor cores, reduce storage overhead, and enable the system to maintain high efficiency while expanding scale. This directory switching mechanism ensures that the management strategy is dynamically adjusted according to different usage scenarios, avoids the shortcomings of a single directory structure, and brings significant performance improvement and stronger adaptability to large-scale multi-processor systems. Therefore, the present invention increases the scalability, efficiency and flexibility of data sharing management, effectively reduces network traffic and performance bottlenecks while improving system processing capabilities, and improves the availability of the directory.

[0018] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a flow chart of a hybrid directory setting method provided by an embodiment of the present invention; Figure 2This is a schematic diagram of the structure of a hybrid directory provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a sparse directory provided by an embodiment of the present invention; Figure 4 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0021] The hybrid directory setting method, storage medium, and electronic device according to embodiments of the present invention will be described below with reference to the accompanying drawings.

[0022] In one embodiment of the present invention, see Figure 1 , provides a hybrid directory setting method, which includes the following steps S101-S104.

[0023] S101: Determine the number of processor cores storing data copies of shared resources; S102: If the number of processor cores does not exceed a preset number threshold, a limited pointer directory is used as a target directory, where pointers in the limited pointer directory are associated with processor cores storing data copies of shared resources; S103: Otherwise, use the two-level sparse directory as the target directory, divide the processor cores into multiple subsets, use the first-level table entries in the two-level sparse directory to identify the subset where the processor cores with data copies are located, record the consistency status of the data copies in the first-level table entries, and use the second-level table entries in the sparse directory to associate the processor cores with data copies in the target subset; S104: If there is a processor core that performs a consistency change operation on the shared resource, adjust the data copy of the processor core that stores the data copy through the target directory, so that each processor core synchronizes the consistency change operation.

[0024] In step S101 , each processor core may set up a cache to store data copies of shared resources.

[0025] When the number is less than a preset threshold, it can be considered that the number of processor cores is small. In this way, the pointers in the limited pointer directory can directly point to the processor cores, which is convenient for searching and management.

[0026] like Figure 2As shown, the limited pointer directory includes table entries of SetM~SetN, where each table entry contains pointer 1, pointer 2,..., pointer i is the pointer of the limited pointer directory, and different pointers can point to different data block addresses of processor cores where data copies are stored, thereby achieving association.

[0027] Figure 2 It is stated that when the number of sharers is less than or equal to n, a limited pointer directory is used, where n is the preset number threshold.

[0028] Other association methods include recording a unique serial number of each processor core, etc., which is not limited in the embodiment of the present invention.

[0029] In one embodiment of the present invention, a first-level table entry includes a tag field, a status bit, and a first bit vector, wherein the tag field identifies the address of the shared resource, the status bit records the consistency status, and the first bit vector identifies the subset of data copies having the shared resource.

[0030] The tag field is the tag in the first-level table entry. Different shared resources have different addresses in memory, so they can be distinguished by address.

[0031] Similar, such as Figure 2 As shown, the secondary table entry may also contain a Tag field. Figure 2 and Figure 3 In the embodiment, the consistency status of the primary table entry and the limited pointer directory is the status bit.

[0032] Figure 2 In the example, if the number of sharers is greater than n, that is, the number of processor cores exceeds the preset threshold, a two-level coefficient directory is used as the target directory. Assume that the C processor cores of a multi-core system are coded from 1 to C, and every N cores form a subset, with a total of C / N subsets. The bit vector of the first-level table entry is C / N bits. Assuming that the i-th bit is 1, it means that there is a processor core with a copy of the data in the i-th subset. For example, if the bit vector is 01001, it means that there are processor cores with a copy of the data in the second and fifth subsets, which are the target subsets. The consistency states recorded in the first-level table entry include modification, exclusive, sharing, invalidation, etc. Different states can be represented by different bit sequences to distinguish them.

[0033] If the number of processor cores storing data copies is increased, the length of the bit vector can be increased accordingly for recording.

[0034] Figure 2In the second-level table entry, the subset number is used to select the subset. Continuing with the above embodiment, if there are processor cores with data copies in the second and fifth subsets, then the subset number is 2, and the current second-level table entry selects the second subset.

[0035] The secondary table entry includes a subset number and a second bit vector, where the second bit vector identifies the processor cores having a copy of the data within the subset identified by the subset number.

[0036] The second vector is Figure 2 The bit vector within the secondary table entry.

[0037] The C cores of the multi-core system are coded from 1 to C. Every N cores form a subset, and there are C / N subsets in total. The bit vector of the first-level table entry in the directory is C / N bits. Assuming that the i-th bit is 1, it means that there is a processor core with a data copy in the i-th subset. Assuming that the j-th bit of the fine-grained bit vector is 1, it means that the number of the processor core holding the data copy is .

[0038] In this way, when a consistency change operation occurs, the data copy status of all processor cores holding data copies can be searched and updated through the two-level sparse directory.

[0039] The first-level table entries and the second-level table entries are stored in the same data block and are distinguished by the highest bit of the table entry. Figure 2 The most significant bit is 0 or 1 in the table. In the figure, the most significant bit is displayed on the left side of each entry. 0 indicates a first-level entry, and 1 indicates a second-level entry.

[0040] By dividing processor cores into subsets and employing a two-level sparse directory, the present invention accurately records information about data sharers, improving data management efficiency. The first level uses bit vectors to identify the subset containing data copies, while the second level further locates specific processor cores within the subset, optimizing the system's overall processing performance.

[0041] Consistency change operations can include modifying the contents of a shared resource or deleting a shared resource on one processor core, causing the consistency state of the data replica to change. For example, if other processor cores holding copies of the data for the unified shared resource need to synchronize the modified contents, they will use the target directory to locate the processor core holding these copies and synchronize the data of the processor core to achieve the adjustment.

[0042] According to the solution provided by an embodiment of the present invention, when the number of processor cores with data copies is small, a limited pointer directory is used to record the processor cores. The pointers in the limited pointer directory can directly retrieve the cores that specifically contain data copies. The directory search process is simple, which can significantly improve the overall processing efficiency of the system and the management efficiency of data sharing information. After exceeding a preset number threshold, when the number of processor cores sharing resources is large, it automatically switches to a two-level sparse directory to maintain the efficiency and continuity of data access, and manages the shared information of all processor cores by subset. When performing a directory query, it is no longer necessary to traverse all processor cores in the system, but only to focus on those subsets related to data copies. This can accommodate more processor cores, reduce storage overhead, and enable the system to maintain high efficiency while expanding its scale. This directory switching mechanism ensures that the management strategy is dynamically adjusted according to different usage scenarios, avoids the shortcomings of a single directory structure, and brings significant performance improvement and stronger adaptability to large-scale multi-processor systems. Therefore, the present invention increases the scalability, efficiency and flexibility of data sharing management, effectively reduces network traffic and performance bottlenecks while improving system processing capabilities, and improves the availability of the directory.

[0043] In one embodiment of the present invention, when the pointers of the limited pointer directory are associated with C processor cores, each pointer has bit field.

[0044] Each pointer has A 1-bit field that identifies a specific processor core number.

[0045] In related technologies, a bit vector requires a bit for each potential sharer, which results in a significant storage overhead when there are many processor cores. To improve efficiency, a pointer approach is used to record shared resources. Specifically, in a chip with C processor cores, each core occupies one bit in the bit vector. If the i-th bit in the bit vector corresponding to the i-th processor core is set to 1 and all other bits are set to 0, a C-bit bit vector is required to share all C processor cores.

[0046] As an improvement, each processor core uses Bit pointer representation, after improvement, record the total number of processor cores i Research has shown that many cache blocks actually have no sharers, where a sharer refers to a processor core that holds a copy of the data, or there is only one sharer, so in most cases , limited pointer directories offer higher storage efficiency. This efficiency difference becomes more pronounced in large-scale systems involving more cores. In a hybrid directory architecture, whenever a new data block is accessed, the system prioritizes allocating an entry in the limited pointer directory. This entry links to the data replica via a pointer, enabling rapid location and access, thus significantly improving operational efficiency in scenarios with a small number of sharers.

[0047] When using a directory to synchronize data copies, in addition to sequentially searching the directory to find all processor cores holding the same data copy and then adjusting the data copies according to consistency change operations, you can also use an index. The first index of the first-level table entry is obtained based on the address information of the data block where the data copy is located; the second bit vector contains the second index of the second-level table entry, and the second index is obtained based on the hash operation of the first index and the subset number.

[0048] This allows the two levels of indexes to be associated, and after the first index is found, the second index can be quickly obtained based on the hash operation of the first index.

[0049] The specific first index uses the low-order address excluding the offset within the data block. M bits are used as set index. Figure 3 As shown in Figure 2, the first-level and second-level entries of a two-level sparse directory are stored in the same data block. Each row in the block stores an entry, and M is the total number of rows in the block.

[0050] Figure 3 and Figure 2 middle, , ,……, , which are n processor cores that share resources. Figure 3 The structure of the two-level sparse directory and Figure 2 The structures of the two-level sparse directories are the same and will not be described in detail here.

[0051] In another embodiment, the limited pointer directory and the two-level sparse directory share directory storage space.

[0052] If there is a target entry to be allocated and there is an empty entry in the directory storage space, the empty entry is allocated to the target entry.

[0053] like Figure 2 As shown, the hybrid directory includes a limited pointer directory and a two-level sparse directory, which are stored together in Set0-SetN In the MySQL database, since each piece of data may correspond to multiple entries, to improve directory query speed, each way is implemented using a static random-access memory (SRAM) to support parallel access. SetM-SetN is a path, and Set0-SetM-1 is a path, forming a two-way set associative structure.

[0054] The target entry is any entry to be added in the limited pointer directory. In a two-level sparse directory, it can be a first-level or second-level entry. If there is an empty entry, the shared information in each field of the target entry is directly filled in.

[0055] The Set index of the two-level sparse directory, that is, the first index and the second index mentioned above are set to log2M bits, and the Set index of the limited pointer directory is set to log2(NM) bits; for the limited pointer directory, the value of the log2(NM) bits of the address excluding the offset within the block plus the number of Sets M in the sparse directory is used as the Set index.

[0056] Depending on the degree of data sharing in the system, M and N can be implemented as configurable parameters, and the most suitable M and N for the system can be determined through experiments. By adjusting the ratio of bit vectors to pointer records, the architecture can strike a balance between sparse directories and limited pointer directories while reducing additional hardware investment.

[0057] In one embodiment of the present invention, if there is no empty entry in the directory storage space, the target entry is used to replace a non-empty entry in the directory storage space, and the data copy corresponding to the replaced non-empty entry is invalidated.

[0058] When a block conflict occurs due to insufficient directory capacity, a pseudo LRU (Least Recently Used) replacement strategy can be used. In other embodiments, other directory replacement strategies, such as a first-in-first-out algorithm or a best replacement algorithm, can also be used, and the present invention is not limited to this.

[0059] If the item being replaced is a secondary table item, the Valid value of the item needs to be set to 0, all processor cores in the subset that have copies of the data need to be disabled, and the bit corresponding to the subset number in the bit vector of the primary table item is reset. According to the above embodiment, the 1 representing the subset position is reset to 0. If the item being replaced is a primary table item, all processor cores that have copies of the data need to be disabled, that is, the data copies in these processor cores are deleted, and the Valid position of all secondary table items corresponding to the primary table item is set to an invalid position, and the Valid position is Figure 2The V field in the first and second level entries of the finite pointer directory and the two-level sparse directory indicates whether the entry is valid. Specifically, the Valid field can be set to 0 to indicate invalidity and 1 to indicate validity. After allocation is complete, the Valid field of the valid pointer entry is set to 0. Compared to the traditional sparse directory replacement, which requires invalidating all sharers, this solution only invalidates all processor cores with data copies when the first level directory is replaced. The second level directory only invalidates a subset of processor cores with data copies, reducing the data processing required during the invalidation process.

[0060] In one embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the hybrid directory setting method described in any of the above embodiments is implemented.

[0061] In one embodiment of the present invention, an electronic device is provided, comprising: a memory and a processor; a computer program is stored in the memory, and when the computer program is executed by the processor, the hybrid directory setting method described in any of the above embodiments is implemented.

[0062] Figure 4 It is a structural block diagram of an electronic device according to an embodiment of the present invention.

[0063] like Figure 4 As shown, electronic device 400 includes: a processor 401 and a memory 403. Processor 401 and memory 403 are connected, for example, via a bus 402. Optionally, electronic device 400 may further include a transceiver 404. It should be noted that in actual applications, the number of transceivers 404 is not limited to one, and the structure of electronic device 400 does not constitute a limitation on the embodiments of the present invention.

[0064] Processor 401 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the present disclosure. Processor 401 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0065] Bus 402 may include a path for transmitting information between the above components. Bus 402 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. Bus 402 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0066] The memory 403 is used to store a computer program corresponding to the hybrid directory setting method of the above embodiment of the present invention, and the computer program is controlled and executed by the processor 401. The processor 401 is used to execute the computer program stored in the memory 403 to implement the content shown in the above method embodiment.

[0067] Among them, the electronic device 400 includes but is not limited to: mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 4 The electronic device 400 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present invention.

[0068] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0069] It should be understood that various components of the present invention may be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods may be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof may be used: a discrete logic circuit having logic gate circuits for implementing logic functions on data signals, an application-specific integrated circuit having suitable combinational logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0070] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0071] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0072] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0073] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0074] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0075] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A method for setting a hybrid directory, characterized in that: The method comprises: Determine the number of processor cores that have data replicas of shared resources; If the number of processor cores does not exceed a preset number threshold, a limited pointer directory is used as the target directory, wherein the pointers of the limited pointer directory are associated with the processor cores storing the data copies of the shared resource; Otherwise, using a two-level sparse directory as a target directory, dividing the processor cores into multiple subsets, using the first-level table entries in the two-level sparse directory to identify the target subset where the processor cores storing the data copies are located, recording the consistency status of the data copies in the first-level table entries, and using the second-level table entries in the sparse directory to associate the processor cores storing the data copies in the target subset; If there is a processor core that performs a consistency change operation on the shared resource, the data copy of the processor core storing the data copy is adjusted through the target directory, so that each processor core synchronizes the consistency change operation.

2. The method according to claim 1, characterized in that In the case where the pointers in the finite pointer directory are associated with C processor cores, each pointer has bit field.

3. The method according to claim 1, characterized in that The first-level table entry includes a tag field, a status bit, and a first bit vector, wherein the tag field identifies the address of the shared resource, the status bit records the consistency state, and the first bit vector identifies a subset of data copies of the shared resource.

4. The method according to claim 3, characterized in that The secondary table entry includes a subset number and a second bit vector, where the second bit vector identifies a processor core having a copy of the data within the subset identified by the subset number.

5. The method according to claim 4, characterized in that The first index of the first-level table entry is obtained according to the address information of the data block where the data copy is located; the second bit vector contains the second index of the second-level table entry, and the second index is obtained based on the hash operation of the first index and the subset number.

6. The method according to claim 1, characterized in that The limited pointer directory and the two-level sparse directory share directory storage space; If there is a target entry to be allocated and there is an empty entry in the directory storage space, the empty entry is allocated to the target entry.

7. The method according to claim 6, characterized in that If there is no empty entry in the directory storage space, the target entry is used to replace a non-empty entry in the directory storage space, and the data copy corresponding to the replaced non-empty entry is invalidated.

8. The method according to claim 1, characterized in that The first-level table entry and the second-level table entry are stored in the same data block and are distinguished by the highest bit of the table entry.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the hybrid directory setting method according to any one of claims 1 to 8 is implemented.

10. An electronic device, characterized in that: include: Memory, processor; The memory stores a computer program, and when the processor executes the computer program, the hybrid directory setting method according to any one of claims 1 to 8 is implemented.

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