Wafer pre-scan method with multi-camera coordinated scanning

Abstract

The application discloses a wafer pre-scanning method based on multi-camera cooperative scanning, and relates to the chip technical field.The method uses a camera array formed by multiple cameras to acquire multiple target surface images at each scanning position, the acquisition frame rate of each pre-scanning camera reaches a frame rate threshold, thereby ensuring the requirement of fast moving scanning, and combining with an image splicing technology, a larger frame global scanning image at the scanning position is obtained, so that each global scanning image has the acquisition speed, the image quality and the frame size, the relative positions of the target surface images are fixed, so that the image splicing technology can be directly used to perform pixel-level image fusion on the overlapping parts of the target surface images of different pre-scanning cameras, and the additional de-duplication operation on the chips in the overlapping area is avoided, and the larger single global scanning range is beneficial to reducing the number of moving scanning required for completing the global pre-scanning of the wafer, so that the wafer pre-scanning speed is improved as a whole.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly to a wafer pre-scanning method based on multi-camera cooperative scanning. BACKGROUND

[0002] A large number of chips are arranged in an array structure on a wafer, and each chip has its own chip level (Bin value). In order to sort chips of different chip levels, a wafer needs to be pre-scanned to obtain a pre-scanning map, which includes the global row and column coordinates and the mechanical coordinates of each chip in the wafer. Then, the same chip in the pre-scanning map and the wafer Map is manually matched, and the wafer Map records the global row and column coordinates and the corresponding chip level of each chip in the wafer. In this way, the pre-scanning map and the wafer Map can be matched and sorted to obtain a sorting map, which includes the global row and column coordinates, the mechanical coordinates, and the chip level of each chip. In the subsequent sorting stage, the sorting map is combined with the mechanical coordinates of each chip to realize sorting, which can effectively improve the accuracy.

[0003] At present, when a wafer is pre-scanned, a camera motor is controlled to drive a pre-scanning camera to move to each scanning position in turn to obtain a target surface image. The mechanical coordinates of each chip in the target surface image can be located by the mechanical coordinates of the camera motor combined with image recognition technology, and then the global row and column coordinates of each chip in the target surface image can be given according to the pre-defined theoretical chip spacing. Since the pre-scanning camera needs to move quickly to realize high-speed shooting during wafer pre-scanning, in order to avoid image blurring caused by motion, the frame rate of the pre-scanning camera needs to be high to ensure better target surface image clarity. However, the target surface of the camera hardware with a high frame rate is usually small, which leads to the need for more shooting times to complete wafer pre-scanning, resulting in a time-consuming wafer pre-scanning process. SUMMARY

[0004] In view of the above problems and technical needs, the present application proposes a wafer pre-scanning method based on multi-camera cooperative scanning. The technical solution of the present application is as follows:

[0005] A wafer pre-scanning method based on multi-camera cooperative scanning, the wafer pre-scanning method comprising:

[0006] The control motor drives the wafer to move horizontally, causing the camera array to move sequentially to various scanning positions on the wafer. When the camera array is at each scanning position, each pre-scan camera in the camera array is synchronously triggered to acquire the target surface image within its respective target surface range. The camera array includes multiple pre-scan cameras arranged together according to a predetermined structure. The acquisition frame rate of each pre-scan camera reaches the frame rate threshold. The continuous area covered by the target surface range of all pre-scan cameras constitutes the global scanning range of the camera array. The movement step of the motor between each scanning position is determined according to the global scanning range of the camera array, and the global scanning range of the camera array overlaps at adjacent scanning positions.

[0007] The target surface images acquired by each pre-scanning camera in the camera array at each scanning position are stitched together to obtain the global scanning image at the current scanning position;

[0008] The wafer pre-scan result is obtained by determining the chip information of each chip on the wafer based on the global scan image at each scan position. The chip information of each chip includes mechanical coordinates and global row and column coordinates.

[0009] The beneficial technical effects of this application are:

[0010] This application discloses a wafer pre-scanning method using multi-camera collaborative scanning. This method utilizes a camera array constructed from multiple high-frame-rate cameras to acquire multiple target surface images at each scanning position. These images are then combined with image stitching technology to form a larger global scan image. This allows for the acquisition of a global scan image at each scanning position that combines acquisition speed, image quality, and image size. The fixed relative positions of the target surface images acquired by different pre-scanning cameras enable pixel-level image fusion of the overlapping areas of the target surface images from different pre-scanning cameras using image stitching technology. This avoids the need for additional deduplication operations on the chips in these overlapping areas. Furthermore, the larger single global scan range helps reduce the number of moving scans required to complete the full-area pre-scanning of the wafer, thus improving the overall wafer pre-scanning speed.

[0011] This method uses global row and column coordinates to identify duplicate chips when performing deduplication operations between different global scan images. Furthermore, by using the type flag bit added to the chip information, peripheral chips in the global scan image can be filtered out. Only peripheral chips that may appear to be duplicated in the global scan image are traversed and compared to identify duplicate chips, which greatly reduces the number of traversals and comparisons when identifying duplicate chips, thereby reducing the time spent on deduplication operations and improving the wafer pre-scanning speed.

[0012] Furthermore, by utilizing the image identifiers of the global scan images added to the chip information, peripheral chips in the global scan images at adjacent locations of each global scan image can be further filtered out, further reducing the number of comparisons required when identifying duplicate chips, further reducing the time spent performing deduplication operations, and thus improving the wafer pre-scan speed.

[0013] By using global row and column coordinates to calculate a unique coordinate transformation value, and by comparing whether the coordinate transformation values ​​are consistent, the consistency of the global row and column coordinates can be indirectly compared, which can further improve the comparison speed, thereby further reducing the time spent on deduplication operations and thus improving the wafer pre-scan speed.

[0014] This method achieves asynchronous processing of three parts: moving scan, image stitching, and data processing through the collaborative processing of the acquisition thread, stitching thread, and processing thread. Further introducing multi-threaded parallelism can further improve the pre-scanning speed. Attached Figure Description

[0015] Figure 1 This is a flowchart of a wafer pre-scanning method according to an embodiment of this application.

[0016] Figure 2 This is a schematic diagram of the camera array layout and the global scanning range in one embodiment of this application.

[0017] Figure 3 This is a flowchart illustrating how, in one embodiment of this application, chip information of each chip on a wafer is determined based on global scan images at various scan locations to obtain wafer pre-scan results.

[0018] Figure 4 This is a schematic diagram of the chip array of peripheral and internal chips in the i-th global scan image obtained in an instance.

[0019] Figure 5 This is a flowchart illustrating the pre-scanning results of a wafer obtained by determining the chip information of each chip on the wafer based on the global scan image at each scan position, as described in another embodiment of this application. Detailed Implementation

[0020] The specific embodiments of this application will be further described below with reference to the accompanying drawings.

[0021] This application discloses a wafer pre-scanning method using multi-camera collaborative scanning. The wafer pre-scanning method includes the following steps, please refer to... Figure 1 :

[0022] Step 110: Control the motor to drive the wafer to move horizontally so that the camera array moves sequentially to each scanning position on the wafer. When the camera array is at each scanning position, the pre-scanning cameras in the camera array are synchronously triggered to acquire the target surface image within their respective target surface range.

[0023] The wafer pre-scanning method of this application adopts the same scanning process framework as the existing single-camera wafer pre-scanning method. It controls a motor to move the wafer and camera relative to each other, allowing the camera to scan different areas of the wafer and process the data. However, the difference lies in the hardware structure. This application uses a camera array, which comprises multiple pre-scanning cameras arranged in a predetermined structure. Each pre-scanning camera has its own target area, and the continuous area covered by the target areas of all pre-scanning cameras constitutes the global scanning range of the camera array. Therefore, the global scanning range of the camera array is larger than the target area of ​​a single pre-scanning camera. The acquisition frame rate of each pre-scanning camera reaches a frame rate threshold. All pre-scanning cameras are triggered synchronously. In actual implementation, multiple pre-scanning cameras can be triggered by external I / O through the same I / O information. This ensures a high acquisition speed for each individual pre-scanning camera while expanding the scanning range at a single scanning position through the camera array, thus achieving good results in both acquisition speed and scanning range.

[0024] In one embodiment, to avoid missed scans, the target surface ranges of two pre-scan cameras with adjacent positions overlap within a predetermined range, ensuring that the camera array can perform a complete scan within its global scanning range.

[0025] The number and arrangement of pre-scan cameras in the camera array can be customized. Considering that too few pre-scan cameras in the camera array will still limit the global scanning range, while too many pre-scan cameras will impose a large computational burden on subsequent image stitching, in one embodiment, taking into account the actual scanning characteristics, the camera array includes four pre-scan cameras of the same specifications, arranged in a 2*2 array. Figure 2 As shown, the target area of ​​a single pre-scan camera is generally rectangular. Figure 2 The target area corresponding to each pre-scan camera is shown using different shading patterns. The distribution of the target area corresponds to the arrangement of the pre-scan cameras. Figure 2As can be seen, the target surface areas of adjacent pre-scan cameras 21 and 22 have multiple overlapping columns of pixels; the target surface areas of adjacent pre-scan cameras 23 and 24 have multiple overlapping columns of pixels; the target surface areas of adjacent pre-scan cameras 21 and 23 have multiple overlapping rows of pixels; and the target surface areas of adjacent pre-scan cameras 22 and 24 have multiple overlapping rows of pixels. The global scanning range of this camera array is rectangular. Furthermore, in actual implementation, the specifications of each pre-scan camera are consistent to ensure uniformity of control. For example, in one instance, the target surface area of ​​a single pre-scan camera includes 1280 pixel columns and 1024 pixel rows, containing 121 chips in 11 rows and 11 columns. If two adjacent target surfaces overlap by 10%, the resulting global scan range includes 2432 pixel columns and 1954 pixel rows. The global scan range contains 21 rows and 21 columns, totaling 441 chips, which greatly expands the range of a single scan. As a result, the entire wafer can be scanned at fewer locations.

[0026] In addition, the camera array also includes an illumination source that covers the entire scanning range of the camera array to prevent uniform lighting across all pre-scan cameras. In one embodiment, the illumination source is a ring-shaped shadowless light source or a coaxial light source.

[0027] The movement step of the motor between each scanning position is determined based on the global scanning range of the camera array, and the global scanning range of the camera array overlaps at adjacent scanning positions to avoid missed scans. The scanning logic can follow the existing wafer pre-scanning scanning logic, such as the common zigzag scanning method. However, in the current wafer pre-scanning process, the movement step of the motor is determined based on the target area of ​​a single pre-scanning camera. In this application, after using a camera array, the movement step of the motor is determined based on the global scanning range of the entire camera array. The specific determination method is consistent with the existing practice and will not be elaborated here.

[0028] Step 120 involves stitching together the target surface images acquired by each pre-scan camera in the camera array at each scanning position to obtain a global scan image for the current scanning position. The stitched global scan image includes all chips within the global scanning range. This step uses existing image stitching techniques to perform pixel-level image stitching. In another embodiment, since the target surface ranges of two adjacent pre-scan cameras overlap, there is an overlapping area in the target surface images acquired by the two adjacent pre-scan cameras. Therefore, when stitching the target surface images acquired by each pre-scan camera, the overlapping area in the target surface images acquired by the two adjacent pre-scan cameras is smoothed. The overall image stitching operation includes feature extraction, feature matching, transform estimation, image deformation, and image fusion, which can be referred to in existing image stitching techniques and will not be elaborated further.

[0029] Step 130: Based on the global scan images at each scan position, determine the chip information of each chip on the wafer to obtain the wafer pre-scan result. The chip information for each chip includes mechanical coordinates and global row and column coordinates.

[0030] The wafer pre-scanning method provided in this embodiment utilizes a camera array constructed from multiple high-frame-rate pre-scanning cameras. This camera array acts as a whole to scan the wafer, resulting in a larger global scan range covered in a single scan operation compared to a single pre-scanning camera. By leveraging the high-frame-rate pre-scanning cameras within the array, high-quality target surface images can be rapidly acquired. Combined with image processing techniques, a larger global scan image can be obtained from the target surface images of multiple pre-scanning cameras. This results in superior performance in terms of acquisition speed, image quality, and image size for a single global scan. Because the global scan range covered in a single scan is larger, fewer scanning operations are required to complete the full-area pre-scanning of the wafer. Furthermore, since the arrangement of the pre-scanning cameras is fixed and known in advance, image stitching technology can be directly used to perform pixel-level image fusion on the overlapping areas of the target surface images from different pre-scanning cameras. During image processing, deduplication of chips within the overlapping areas of the target surface images is performed, eliminating the need for subsequent deduplication operations on these chips. Therefore, the overall wafer pre-scanning speed is improved.

[0031] In another embodiment, three types of threads are introduced into the software architecture to implement asynchronous processing and jointly implement the wafer pre-scanning method in the above embodiment. The three types of threads include an acquisition thread, a stitching thread, and a processing thread, and their collaborative execution process is as follows:

[0032] The acquisition thread executes step 110 above to control the motor to drive the wafer to move horizontally, so that the camera array moves sequentially to each scanning position on the wafer. When the camera array is at each scanning position, each pre-scan camera in the camera array is synchronously triggered to acquire the target surface image within its respective target surface range as the raw data at the current scanning position, and the raw data at each scanning position is stored in the acquisition list. The raw data at each scanning position includes each target surface image acquired at the scanning position.

[0033] The stitching thread executes step 120 above to sequentially read the raw data at each scanning position from the acquisition list, and stitches the target surface images included in the read raw data to obtain the global scan image at the corresponding scanning position, which is then stored in the image list.

[0034] The processing thread executes step 130 above to sequentially read global scan images at each scan position from the image list and performs data processing on the read global scan images.

[0035] The stitching thread begins execution after the acquisition thread writes the raw data from the first scan position into the acquisition list, and the processing thread begins execution after the stitching thread stores the global scan image from the first scan position into the image list. In actual operation, the acquisition thread's execution speed of acquiring raw data and writing it into the acquisition list is relatively fast, as the high frame rate of the camera array can meet the requirements for high-quality raw data acquisition during rapid movement. However, the data processing involved in the stitching and processing threads is relatively time-consuming; therefore, the execution speed of the stitching and processing threads directly affects the overall time consumption of the wafer pre-scanning method. To further improve scanning efficiency, multiple stitching threads are used in parallel to execute the step of sequentially reading raw data from each scan position from the acquisition list, and multiple processing threads are used in parallel to execute the step of sequentially reading the global scan image from each scan position from the image list and processing the read global scan image. Introducing multi-threaded parallelism further improves data processing speed, thereby increasing the wafer pre-scanning speed.

[0036] In step 130 above, image processing technology can be used to determine the mechanical coordinates of each chip in the global scan image at each scanning position. A chip on the wafer is pre-defined as a reference chip and its global row and column coordinates are calibrated. Then, the difference between the mechanical coordinates of each chip in the global scan image and the mechanical coordinates of the reference chip is divided by a pre-set chip interval and rounded to determine the difference between the global row and column coordinates of the chip and the global row and column coordinates of the reference chip. Thus, the global row and column coordinates of the chip can be determined. The specific implementation of this part can refer to the existing methods for identifying the mechanical coordinates and row and column coordinates of chips in the target image of a single pre-scan camera, which will not be elaborated here.

[0037] Because the global scanning range of the camera array needs to overlap at adjacent scanning positions to avoid missed scans, there are also overlapping regions in the global scan images of two adjacent scanning positions. Since the scanning positions of the two global scan images are different, it is difficult to directly use image stitching to fuse the overlapping regions, as the stitching quality will be inconsistent. Therefore, it is necessary to perform data processing on the global scan image at each scanning position to determine the chip information of all chips in the global scan image, and then perform a deduplication operation on the duplicate chips between the global scan images to ensure that the chip information of each chip in the final wafer pre-scan result is unique. This is also the general framework of the existing single-camera wafer pre-scanning process.

[0038] The time consumed by deduplication is also a significant factor affecting the wafer pre-scanning process. If the existing deduplication method is used in step 130 above, the process is as follows: First, initialize the wafer pre-scanning result to empty. Then, sequentially traverse the global scan image at each scan position for data processing. Using image processing techniques, determine the mechanical coordinates and global row and column coordinates of each chip in the global scan image at the first scan position and add them to the wafer pre-scanning result. Starting from the global scan image at the second scan position, after determining the mechanical coordinates and global row and column coordinates of each chip in the global scan image, for each chip in the current global scan image, calculate the Euclidean distance between the chip and the mechanical coordinates of each chip already stored in the wafer pre-scanning result. When the Euclidean distance between the mechanical coordinates of two chips is less than the chip's half-width and half-height, it is determined that these two chips actually belong to the same chip, and deduplication is performed. If no duplicate chips are found in the wafer pre-scanning result, it is determined that the chip is newly scanned, and its chip information is added to the wafer pre-scanning result.

[0039] The above process uses the Euclidean distance between the mechanical coordinates of the chips to identify duplicate chips and achieve deduplication. The calculation of the Euclidean distance is time-consuming, and each chip in the global scan image needs to be traversed and compared with the wafer pre-scan results. The number of chips on the wafer is huge, for example, there are typically 280,000 chips, which results in a huge amount of computation consumed by the deduplication operation. The deduplication process is very time-consuming and directly affects the pre-scan speed.

[0040] Therefore, to improve the pre-scanning speed, this embodiment optimizes the deduplication process. The process of determining the chip information of each chip on the wafer based on the global scan image at each scan position to obtain the wafer pre-scanning result includes the following steps, please refer to... Figure 3 Flowchart:

[0041] Step 310: Initialize the wafer pre-scan result to be empty.

[0042] Step 320: Process the global scan images at each scan position sequentially. For the currently processed i-th global scan image, use image processing techniques to determine the mechanical coordinates and global row and column coordinates of each chip in the i-th global scan image. The i-th global scan image is the global scan image at the i-th scan position.

[0043] Step 330: When i = 1, add the chip information of each chip in the i-th global scan image to the wafer pre-scan result and process the next global scan image in sequence.

[0044] Step 340: When i≥2, based on the global row and column coordinates of each chip in the i-th global scan image, select multiple chips located in the image boundary region of the i-th global scan image as peripheral chips, and select other chips located in the middle region of the image as internal chips.

[0045] Based on the common rectangular structure of global scan images, multiple columns of chips located at each boundary of the wafer's horizontal direction and multiple rows of chips located at each boundary of the wafer's vertical direction in the i-th global scan image can be taken as peripheral chips, and the other chips as internal chips. The overlap range of the global scan range at adjacent scan positions can generally be predetermined when designing the motor movement logic, and this overlap range is generally not too large. Currently, in row and column specifications, the global scan images of two adjacent scan positions in the wafer's horizontal direction generally overlap 2-3 columns of chips, and the global scan images of two adjacent scan positions in the wafer's vertical direction generally overlap 2-3 rows of chips. Based on this, the number of rows and columns covered by the peripheral chips can be predetermined. For example, in an example, the chip array in a single global scan image is as follows: Figure 4 As shown, a global scan image contains 21 rows and 21 columns of chips. Taking 2 columns at the left and right boundaries and 2 rows at the top and bottom boundaries, totaling 152 chips, as peripheral chips, as shown... Figure 4 As shown in the shaded rectangle. The 289 chips (17 rows and 17 columns) in the middle region of the global scan image are used as internal chips, as shown below. Figure 4 As shown in the white rectangle in the middle.

[0046] Step 350: After performing a deduplication operation on the chip information of the peripheral chips in the i-th global scan image and the existing chip information in the wafer pre-scan result, update the wafer pre-scan result. Add the chip information of the internal chips in the i-th global scan image directly to the wafer pre-scan result, and process the next global scan image in sequence.

[0047] Since global scan images at adjacent scan positions overlap at image boundaries, but not in the middle region, chips that overlap in a global scan image with those at other scan positions are always located in the boundary region of the global scan image. This means only peripheral chips in the global scan image are likely to have been scanned and included in the wafer pre-scan result; internal chips in the global scan image are definitely not scanned and are not included in the wafer pre-scan result. Therefore, it is unnecessary to perform deduplication on all chips in the global scan image; only the chip information of peripheral chips needs to be deduplicated. The chip information of internal chips can be directly added to the wafer pre-scan result. By filtering out potentially duplicate peripheral chips before performing deduplication, the number of chips requiring deduplication in the i-th global scan image is greatly reduced, thus reducing the time spent on deduplication. For example, in... Figure 4 In the example, it was originally necessary to compare all 441 chips with the chip information in the wafer pre-scan results and perform deduplication. After filtering, only 152 chips need to be compared with the chip information in the wafer pre-scan results and perform deduplication. This greatly reduces the number of deduplication comparisons, reduces the time spent on deduplication, and helps to improve the pre-scan speed.

[0048] As the pre-scanning process progresses, the number of chips included in the wafer pre-scanning results increases. Even if only the chip information of peripheral chips in the i-th global scan image needs to be deduplicated with the existing chip information in the wafer pre-scanning results, this process is still time-consuming when the number of chip information in the wafer pre-scanning results is very large. Therefore, further, the chip information in the wafer pre-scanning results that is compared with the chip information of peripheral chips in the i-th global scan image is also filtered.

[0049] As mentioned above, the overlap between global scan images at adjacent scan positions occurs at image boundaries. Therefore, the repetition of chips in the global scan image is a repetition between peripheral chips. Thus, when performing deduplication on the chip information of peripheral chips in the i-th global scan image and the chip information already present in the wafer pre-scan result, it is only necessary to perform deduplication on the chip information of peripheral chips in the i-th global scan image and the peripheral chips in other previously scanned global scan images. It is not necessary to perform deduplication on the chip information of peripheral chips in the i-th global scan image and the internal chips in other previously scanned global scan images. In order to filter out peripheral chips from other previously scanned global scan images from the wafer pre-scan result, this embodiment adds a chip type flag bit to the chip information of each chip when writing the chip information of each chip into the wafer pre-scan result. The chip type flag bit is either a first flag bit or a second flag bit. The first flag bit indicates that the chip is a peripheral chip in the global scan image to which it belongs, and the second flag bit indicates that the chip is an internal chip in the global scan image to which it belongs. For example, 1 and 0 can be commonly used to distinguish between the first flag bit and the second flag bit. In order to add a chip type flag bit to each chip, when processing the first global scan image, step 330 will actually select multiple chips located in the image boundary area as peripheral chips based on the global row and column coordinates of each chip in the first global scan image, and other chips located in the middle area of ​​the image as internal chips. After adding a type flag bit to each chip, the chip information of each chip will be added to the wafer pre-scan result.

[0050] Based on this, please refer to Figure 5 The flowchart shown above includes the following steps in step 350:

[0051] Step 351: Select a comparison list from the wafer pre-scan results. The comparison list includes chip information of multiple chips with the first flag bit in the wafer pre-scan results.

[0052] In one embodiment, chip information of all chips with a first flag bit is selected from the wafer pre-scan results to form a comparison list. The number of chip information contained in the comparison list is greatly reduced compared to the number of chip information contained in the wafer pre-scan results, which helps to reduce the number of comparisons with peripheral chips in the i-th global scan image, thereby helping to reduce the time consumed by deduplication operations.

[0053] Considering that the i-th global scan image will only have duplicate chips with global scan images at its neighboring scan positions, and cannot have duplicate chips with global scan images at scan positions that are far apart, we can further filter out the peripheral chips in the global scan images at the neighboring scan positions of the i-th global scan image to form a comparison list. In this way, the number of chip information contained in the selected comparison list can be further reduced, thereby further reducing the number of duplicate comparisons.

[0054] To achieve the above filtering, when adding the chip information of each chip to the wafer pre-scan results, an image identifier of the global scan image to which the chip belongs is also added to the chip information. A correspondence exists between the image identifier of each global scan image and the scan position where that global scan image was obtained; each global scan image's image identifier is unique. Alternatively, the scan position corresponding to the global scan image to which the chip belongs can be directly added to the chip information, but storing the image identifier requires relatively less memory.

[0055] When selecting the comparison list from the wafer pre-scan results, the Euclidean distance between the i-th scan position and the previous i-1 scan positions corresponding to the i-th global scan image is calculated. Global scan images at multiple scan positions whose Euclidean distance to the i-th scan position is within a distance threshold are selected as the neighborhood images of the i-th global scan image. This distance threshold is a custom value, set according to the image size of the global scan image, generally slightly larger than the image size of the global scan image, ensuring that the selected neighborhood images are global scan images of adjacent scan positions of the i-th scan position in the horizontal and vertical directions of the wafer. Then, the chip information of each chip corresponding to the image identifier of the neighborhood image of the i-th global scan image and possessing a first flag bit is selected from the wafer pre-scan results to obtain the comparison list. Thus, the comparison list includes the chip information of some chips with the first flag bit from the wafer pre-scan results.

[0056] Because this application covers a large global scan range at a single scan position, the number of scan positions across the entire wafer is significantly reduced. As a result, the number of global scan images is relatively limited. Therefore, the computational load for calculating the Euclidean distance between the i-th scan position and the previous i-1 scan positions in the i-th global scan image is also relatively limited. Thus, although Euclidean distance calculation is involved, the time consumption is within an acceptable range. Furthermore, this filtering method can further reduce the number of chips in the comparison list that need to be compared with peripheral chips in the i-th global scan image, resulting in a considerable overall speed improvement.

[0057] Step 352: Iterate through the chip information of each chip in the comparison list in turn, and detect whether the peripheral chip j and chip k belong to the same chip based on the global row and column coordinates of the currently traversed chip k and the global row and column coordinates of the peripheral chip j.

[0058] The number of chip information contained in the comparison list selected through the above steps is greatly reduced compared to the number of chip information contained in the wafer pre-scan results. Therefore, the number of duplicate comparisons of any peripheral chip j in the i-th global scan image is reduced, which helps to improve the processing speed.

[0059] In addition, unlike traditional methods that use mechanical coordinates to identify duplicate chips, this embodiment uses the global row and column coordinates of the chip to identify duplicate chips. Compared to the approach of using mechanical coordinates to calculate Euclidean distance, this method only needs to compare whether the global row and column coordinates are consistent, which requires less computation, lower computing power, and is faster.

[0060] Considering that comparing the global row and column coordinates of chip k and peripheral chip j requires comparing both row and column coordinates, there are actually two comparison processes. Therefore, to further improve speed, in another embodiment, after determining the global row and column coordinates of each chip, the corresponding coordinate transformation value is calculated based on the global row and column coordinates of each chip, and the chip's coordinate transformation value is added to the chip information. The chip's coordinate transformation value corresponds one-to-one with the global row and column coordinates. The specific calculation method can be pre-defined, for example, the chip's coordinate transformation value can be calculated as k*row+col, where row is the row coordinate in the chip's global row and column coordinates, and col is the column coordinate in the chip's global row and column coordinates. Here, k is pre-set to ensure a unique correspondence between the coordinate transformation value and the global row and column coordinates. For example, considering that the number of rows and columns of chips on a typical wafer generally does not exceed 1000, k can be taken as a large value, such as 10000, so that the chip's global row and column coordinates can be converted into a unique coordinate transformation value. When comparing the global row and column coordinates of chip k with the global row and column coordinates of peripheral chip j, the global row and column coordinates are not compared directly. Instead, the coordinate transformation values ​​of the two chips are compared. When the coordinate transformation value of the currently traversed chip k is found to be consistent with the coordinate transformation value of peripheral chip j, it is determined that peripheral chip j and chip k belong to the same chip. Otherwise, it is determined that peripheral chip j and chip k do not belong to the same chip. This can further improve the comparison speed.

[0061] Step 353: When it is determined that peripheral chip j and chip k belong to the same chip, update the chip information of chip k using the chip information of peripheral chip j and complete the traversal of the comparison list, then continue to compare the next peripheral chip j in the i-th global scan image. Otherwise, continue to traverse the next chip in the comparison list.

[0062] In one embodiment, the chip information for each chip includes mechanical coordinates, global row and column coordinates, coordinate transformation values, the image identifier of the global scan image to which the chip belongs, and a type flag. The global row and column coordinates of the same chip identified in two global scan images are identical, but the mechanical coordinates may have some deviations; therefore, the coordinate transformation values ​​calculated from the global row and column coordinates are also identical. A chip included in multiple global scan images is considered a peripheral chip in each global scan image.

[0063] Therefore, the global row and column coordinates, coordinate transformation values, and type flag bits contained in the chip information of peripheral chip j and chip k are the same, but the mechanical coordinates and the image identifier of the global scan image to which the chip belongs are different. Updating the chip information of chip k using the chip information of peripheral chip j includes: keeping the global row and column coordinates, coordinate transformation values, and the first flag bit of chip k unchanged; using the weighted result of the mechanical coordinates of peripheral chip j and chip k as the updated mechanical coordinates of chip k; and adding the image identifier of the i-th global scan image to which peripheral chip j belongs as the image identifier of the global scan image to which chip k belongs to chip k into the chip information. Thus, when a chip belongs to multiple global scan images simultaneously, the chip information of that chip contains the image identifiers of multiple global scan images.

[0064] Step 354: After traversing the comparison list and determining that no chip in the comparison list belongs to the same chip as peripheral chip j, add the chip information of peripheral chip j to the wafer pre-scan result. In one test instance, pre-scanning a wafer containing 280,000 chips took more than an hour using traditional pre-scanning methods, while the pre-scanning using the method provided in this embodiment took less than 10 minutes, greatly improving the wafer pre-scanning speed.

[0065] The above descriptions are merely preferred embodiments of this application, and this application is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of this application should be considered to be included within the protection scope of this application.

Claims

1. A wafer pre-scanning method using multi-camera collaborative scanning, characterized in that, The wafer pre-scanning method includes: The control motor drives the wafer to move horizontally, causing the camera array to move sequentially to various scanning positions on the wafer. When the camera array is at each scanning position, each pre-scan camera in the camera array is synchronously triggered to acquire the target surface image within its respective target surface range. The camera array includes multiple pre-scan cameras arranged together according to a predetermined structure. The acquisition frame rate of each pre-scan camera reaches a frame rate threshold. The continuous area covered by the target surface range of all pre-scan cameras constitutes the global scanning range of the camera array. The movement step of the motor between each scanning position is determined according to the global scanning range of the camera array, and the global scanning range of the camera array overlaps at adjacent scanning positions. The target surface images acquired by each pre-scanning camera in the camera array at each scanning position are stitched together to obtain the global scanning image at the current scanning position; The initial wafer pre-scan result is empty. The global scan image at each scan position is sequentially traversed for data processing. For the currently processed... i The first global scan image was used to determine the first image using image processing techniques. i The mechanical coordinates and global row and column coordinates of each chip in the global scan image; where, the first... i The global scan image is the first i Global scan image at each scan location; when i=1 At that time, the first i The chip information of each chip in the global scan image is added to the wafer pre-scan result and the next global scan image is processed in sequence; the chip information of each chip includes mechanical coordinates and global row and column coordinates, and the chip information of each chip also includes a type flag bit. The type flag bit of each chip is either a first flag bit or a second flag bit. The first flag bit indicates that the chip is a peripheral chip in the global scan image, and the second flag bit indicates that the chip is an internal chip in the global scan image. when i≥2 At that time, according to the first i The global row and column coordinates of each chip in the global scan image are used to filter out the first chip. i In a global scan image, multiple chips located within the image boundary region are designated as peripheral chips, while other chips located in the middle region of the image are designated as internal chips. A comparison list is generated from the wafer pre-scan results, comprising chip information for multiple chips with a first flag bit from the wafer pre-scan results. For the first... i Peripheral chips in a global scan image j The chip information of each chip in the comparison list is traversed sequentially, and the chip information is determined according to the chip currently being compared. k Global row and column coordinates and peripheral chips j Global row and column coordinate detection peripheral chip j With chips k Whether they belong to the same chip, once the peripheral chip is determined. j With chips k When they belong to the same chip, use peripheral chips. j Chip information update chip k If the chip information is not found, continue iterating through the next chip. This continues until the comparison list has been exhausted and it is determined that no chip or peripheral chip exists in the comparison list. j When they belong to the same chip, the peripheral chips j Add the chip information to the wafer pre-scan results; i The chip information of the internal chip in the global scan image is directly added to the wafer pre-scan result, and the next global scan image is processed in sequence.

2. The wafer pre-scanning method according to claim 1, characterized in that, The chip information for each chip also includes the image identifier of the global scan image to which the chip belongs; the comparison list selected from the wafer pre-scan results includes: Calculate the first one respectively i The first global scan image corresponding to the i Each scan position and the previous i-1 The Euclidean distance between the scan positions is used to filter out those with the same Euclidean distance as the first scan position. i The Euclidean distance of the nth scan position to the global scan image at multiple scan positions within the distance threshold is used as the nth scan position. i The neighborhood image of the global scan image; Select from the wafer pre-scan results that match the first... i The chip information of each chip, which corresponds to the image identifier of the neighboring images of the global scan image and has the first flag bit, is used to obtain the comparison list.

3. The wafer pre-scanning method according to claim 1, characterized in that, The wafer pre-scanning method further includes: calculating the corresponding coordinate transformation value based on the global row and column coordinates of each chip, and including the chip's coordinate transformation value in the chip information and adding it to the wafer pre-scanning result, wherein the chip's coordinate transformation value corresponds one-to-one with the global row and column coordinates; The chip based on the currently traversed chip k Global row and column coordinates and peripheral chips j Global row and column coordinate detection peripheral chip j With chips k Whether they belong to the same chip includes: When the currently traversed chip is detected k coordinate transformation values ​​and peripheral chips j When the coordinate transformation values ​​are consistent, the peripheral chip is determined. j With chips k If they belong to the same chip, otherwise identify them as peripheral chips. j With chips k They do not belong to the same chip.

4. The wafer pre-scanning method according to claim 2, characterized in that, Using peripheral chips j Chip information update chip k The chip information includes: Keep the chip k The global row and column coordinates and the first flag remain unchanged, and the peripheral chip is... j Mechanical coordinates and chips k The weighted result of the mechanical coordinates is used as the chip k The updated mechanical coordinates; the peripheral chip j Belonging to the i Image identifiers for the entire global scan image are also used as chips. k The image identifier of the global scan image is added to the chip. k The chip information.

5. The wafer pre-scanning method according to claim 1, characterized in that, The wafer pre-scanning method: The acquisition thread controls the motor to drive the wafer to move horizontally, so that the camera array moves to each scanning position on the wafer in sequence. When the camera array is at each scanning position, each pre-scan camera in the camera array is synchronously triggered to acquire the target surface image within its respective target surface range as the raw data of the current scanning position. The raw data of each scanning position is stored in the acquisition list. The stitching thread sequentially reads the raw data from each scanning position from the acquisition list, and stitches the target images included in the read raw data to obtain the global scan image at the corresponding scanning position, which is then stored in the image list. The processing thread sequentially reads global scan images from the image list at each scan position and performs data processing on the read global scan images.

6. The wafer pre-scanning method according to claim 1, characterized in that, The target surface areas of two pre-scan cameras with adjacent positions overlap. When stitching the target surface images acquired by each pre-scan camera, the overlapping areas in the target surface images acquired by the two pre-scan cameras with adjacent positions are smoothed.

7. The wafer pre-scanning method according to claim 5, characterized in that, The wafer pre-scanning method further includes: The process involves using multiple stitching threads to execute in parallel the steps of sequentially reading raw data from each scan position in the acquisition list, and using multiple processing threads to execute in parallel the steps of sequentially reading global scan images from each scan position in the image list and processing the read global scan images.

8. The wafer pre-scanning method according to claim 1, characterized in that, The camera array also includes an illumination source that covers the entire scanning range of the camera array. The illumination source is either a ring-shaped shadowless light source or a coaxial light source.

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