LPDDR5 Read Training method and system for eliminating fine delay and coarse delay errors

Abstract

The invention aims to provide an LPDDR5 Read Training method and an LPDDR5 Read Training system for eliminating fine delay and coarse delay errors. The method comprises the following steps: scanning and reading a trained unit interval; acquiring the position of the scanned eye pattern boundary; and adjusting the calibration delay line according to the position of the eye pattern boundary. According to the method and the device, the influence caused by an error that the 1UI of the Fine Delay is not equal to the 1UI of the Coarse Delay can be avoided as much as possible on the premise of not influencing the correctness of Read Training.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and more particularly to an LPDDR5 Read Training method and system for eliminating fine delay and coarse delay errors. Background Art

[0002] In LPDDR5, the DQ[15:0] signals returned by the chip must be sampled by the returning RDQS clock. However, due to the high frequency and short period, the RDQS delay must be trained for each DQ to ensure that RDQS can correctly sample all DQs. Coarse delay and fine delay are typically designed to adjust the RDQS delay (the clock after the delay is called RxClk). Coarse delay is implemented using digital logic, so one unit is 1 UI (one UI represents half an RDQS cycle). Fine delay, on the other hand, is implemented using analog LCD logic, with one unit being 1 / 64 UI. Furthermore, as a dual-edge sampling serial port, LPDDR5 requires consistent coarse delays for both the rising-edge clock (RDQS_C) and the falling-edge clock (RDQS_T) during sampling, thus sharing the coarse delay configuration. Taking the IO of a certain DQ as the description object, the training process generally starts with Delay Training of RDQS_C. At the same time, the common Coarse Delay of RDQS_C and RDQS_T must also be trained. Then, the Fine Delay of RDQS_T is trained.

[0003] Figure 2 The dotted line on the right is the middle point in the eye diagram of RxClk_c obtained after training. The delay corresponding to this point can allow RDQS_C to correctly sample the corresponding DQ. However, since the Fine Delay is too close to the 2UI position of LCDL, it is easy to cause the RDQS_T to be backfilled to a position beyond 2UI during training, resulting in training failure and possible retrain failure. Therefore, the Fine Delay should generally be backfilled to a position close to 1UI. Figure 2In the current state, 1UI of Fine Delay needs to be carried forward to Coarse Delay, adjusting the Fine Delay from 1.9UI to 0.9UI. In the Read Training, Coarse Delay is implemented using digital logic, with one unit being 1UI. The accuracy of Coarse Delay is based on the PHYPLL clock output, which has minimal jitter and is considered essentially error-free. Fine Delay, on the other hand, is implemented using analog LCDL, with one unit being 1 / 64UI. Its accuracy is affected by PVT, the LCDL calibration algorithm, LCDL linearity, and the LCDL's structural design. For these reasons, 1UI of LCDL is not equivalent to 1UI of Coarse Delay. Summary of the Invention

[0004] The purpose of the present invention is to provide an LPDDR5 Read Training method and system for eliminating fine delay and coarse delay errors. This method can minimize the impact of the error caused by the inequality between 1UI of fine delay and 1UI of coarse delay without affecting the correctness of Read Training.

[0005] An LPDDR5 Read Training method for eliminating fine delay and coarse delay errors includes: Scan and read the unit interval of training; Get the position of the scanned eye diagram boundary; Adjust the calibrated delay line based on the location of the eye diagram boundaries.

[0006] Preferably, the unit interval of the scanning and reading training includes: One scan reads one unit interval in training.

[0007] Preferably, obtaining the position of the scanned eye diagram boundary includes: Scan the left boundary of the eye diagram in the 0-1 unit interval; If the left boundary of the eye diagram is not scanned in the 0-1 unit interval, adjust the delay line parameters to continue scanning; If the left edge of the eye diagram is found in the 0-1 unit interval, the scan continues to search for the right edge.

[0008] Preferably, the calibration delay line comprises a coarse delay line and a fine delay line.

[0009] Preferably, adjusting and calibrating the delay line according to the position of the eye diagram boundary comprises: Determine the midpoint of the eye diagram according to the position of the eye diagram boundary; Determine whether to adjust the fine delay line or the coarse delay line based on the position of the middle point in the eye diagram.

[0010] Preferably, determining whether to adjust the fine delay line or the coarse delay line according to the position of the point in the eye diagram comprises: If the left edge of the eye diagram is not scanned in the 0-1 unit interval, the coarse delay line is incremented by 1 and the fine delay line is accumulated again from 0; If the left boundary of the eye diagram is scanned in the 0-1 unit interval, the coarse delay line remains unchanged and the fine delay line continues to accumulate to the 1-2 unit interval until the right boundary of the eye diagram is found.

[0011] Preferably, the adjusting and calibrating the delay line according to the position of the eye diagram boundary further comprises: According to the standard range of the eye diagram, the LCDL Delay set range of the left edge of the eye diagram is controlled to be (0UI, 1UI); According to the standard range of the eye diagram, the LCDL Delay set range of the right edge of the eye diagram is controlled to be (1UI, 2UI); According to the standard range of the eye diagram, the set range of the middle points of the left and right boundaries of the eye diagram is controlled to belong to (0.5UI, 1.5UI).

[0012] An LPDDR5 Read Training system for eliminating fine delay and coarse delay errors includes: Scanning module, used to scan and read the training unit interval; A judgment module is used to obtain the position of the scanned eye diagram boundary; The calibration module is used to adjust and calibrate the delay line according to the position of the eye diagram boundary.

[0013] An electronic device includes: a chip, a processor, and a memory, wherein the memory is used to store computer program code, the computer program code including computer instructions, and when the chip executes the computer instructions, the electronic device performs an LPDDR5 read training method that eliminates fine delay and coarse delay errors.

[0014] A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When executed by a processor of an electronic device, the program instructions cause the processor to perform an LPDDR5 read training method that eliminates fine delay and coarse delay errors.

[0015] The present invention has the following advantages: 1. The present invention ensures that the Read Training eye diagram appears within a 2UI range of an LCDL, thereby avoiding the need for the Fine Delay to perform a borrow or carry operation on the Coarse Delay during the final delay configuration backfill; 2. The present invention determines whether to carry the Fine Delay to the Coarse Delay Read Training algorithm based on whether the left boundary is found. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 Schematic diagram of an algorithm for an LPDDR5 Read Training method for eliminating fine delay and coarse delay errors according to the present invention; Figure 2 FIG1 is a diagram showing a solution of performing Delay Scan on RDQS_C in the prior art of the present invention; Figure 3 FIG2 is a second diagram of a solution for performing Delay Scan on RDQS_C in the prior art of the present invention; Figure 4 FIG1 is an eye diagram error diagram that may be caused by Training RDQS_C in the prior art of the present invention; Figure 5 This figure shows a delay backfill skew situation that may be caused when training RDQS_C in the prior art of the present invention; Figure 6 Figure 2 shows the delay backfill skew situation that may be caused when training RDQS_C in the prior art of the present invention; Figure 7 This is a diagram showing the effect of delay backfill skew situation 1 that may be caused when the algorithm used in the present invention addresses Training RDQS_C; Figure 8 This is a diagram showing the effect of the second delay backfill skew situation that may be caused when the algorithm used in the present invention copes with Training RDQS_C; Figure 9The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0021] In addition, the descriptions of "first", "second", etc. in the present invention are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0022] Figure 2 The dotted line on the right is the middle point in the eye diagram of RxClk_c obtained after training. The delay corresponding to this point can allow RDQS_C to correctly sample the corresponding DQ. However, since the Fine Delay is too close to the 2UI position of LCDL, it is easy to cause the RDQS_T to be backfilled to a position beyond 2UI during training, resulting in training failure and possible retrain failure. Therefore, the Fine Delay should generally be backfilled to a position close to 1UI. Figure 2In the current state, 1UI of Fine Delay needs to be carried forward to Coarse Delay, adjusting the Fine Delay from 1.9UI to 0.9UI. In the Read Training, Coarse Delay is implemented using digital logic, with one unit being 1UI. The accuracy of Coarse Delay is based on the PHYPLL clock output, which has minimal jitter and is considered essentially error-free. Fine Delay, on the other hand, is implemented using analog LCDL, with one unit being 1 / 64UI. Its accuracy is affected by PVT, the LCDL calibration algorithm, LCDL linearity, and the LCDL's structural design. For these reasons, 1UI of LCDL is not equivalent to 1UI of Coarse Delay.

[0023] The present invention ensures that the Read Training eye diagram must appear within a 2UI range of an LCDL, thereby avoiding the need for the Fine Delay to perform a borrow or carry operation on the Coarse Delay during the final delay configuration backfill. The present invention determines whether to carry the Fine Delay to the Coarse Delay Read Training algorithm based on whether the left boundary is found.

[0024] Example 1 A LPDDR5 Read Training method to eliminate fine delay and coarse delay errors, reference Figure 1 ,include: S100, scanning and reading the training unit interval; In this embodiment of the present invention, a unit interval is 1UI, which represents the duration of a bit period in timing. Specifically, 1UI refers to the duration of one bit of information and is equal to the inverse of the data transmission period, that is, 1 / data rate. For example, if the data rate is 1 Gbps, then 1UI is approximately 1 nanosecond. In digital communications and signal integrity analysis, 1UI is used to measure parameters such as jitter and eye width. As the transmission rate increases, the length of 1UI decreases. For example, if the code rate doubles, the time of 1UI will be halved.

[0025] S200, obtaining the position of the scanned eye diagram boundary; By superimposing signal waveforms from multiple symbol periods, an eye diagram visually reflects signal distortion, inter-symbol interference, and noise interference. A wider eye diagram opening indicates a stronger system's noise immunity, lower inter-symbol interference, and thus better system performance.

[0026] S300, adjusting and calibrating the delay line according to the position of the eye diagram boundary.

[0027] LCDL delay refers to the delay time of the local calibration delay line. In DDR memory, the delay line is a hardware module used to delay and adjust signals to meet timing requirements. LCDL delay specifically refers to the delay time of the local calibration delay line. It is calibrated once during initialization and is mainly used to adjust the phase of the data signal (DQ) and data strobe signal (DQS) to ensure that they are sampled or written to the memory on the correct clock edge. The delay line is used to adjust the phase of the data signal (DQ) and data strobe signal (DQS) to ensure that they are sampled or written to the memory on the correct clock edge. Due to changes in voltage and temperature, the delay effect of the delay line may change. This phenomenon is called drift. LCDL uses a PVT compensation mechanism to detect and compensate for drift, ensuring that the delay value remains consistent under different conditions.

[0028] Preferably, in S100, the unit interval of the scanning and reading training includes: One scan reads one unit interval in training.

[0029] If the actual delay of LCDL is greater than the calculated delay due to PVT, the right edge of the Rxclk eye diagram will appear earlier. In high-speed communication interfaces, the eye diagram width is inherently small. Narrowing the eye diagram range may make training more difficult to succeed and also lead to inaccurate backfill delays. Figure 4 As shown. Figure 2 In the algorithm shown, the final backfilling process carries 1UI of the Fine Delay (i.e., LCDL Delay) over to the Coarse Delay as the final delay configuration backfill. This may result in the backfilled delay configuration not necessarily being in the center of the actual eye diagram, but rather deviating from it. If the eye diagram is too small, this carry adjustment may reveal that the backfilled delay configuration is incorrect. Figure 2 and Figure 3 The above problems may lead to the following results: Figure 5 and Figure 6 shown.

[0030] Preferably, S200, obtaining the position of the scanned eye diagram boundary includes: Scan the left boundary of the eye diagram in the 0-1 unit interval; If the left boundary of the eye diagram is not scanned in the 0-1 unit interval, adjust the delay line parameters to continue scanning; If the left edge of the eye diagram is found in the 0-1 unit interval, the scan continues to search for the right edge.

[0031] Preferably, the calibration delay line comprises a coarse delay line and a fine delay line.

[0032] In an embodiment of the present invention, Fine Delay and Coarse Delay are respectively a fine delay line and a coarse delay line. Fine Delay can fine-tune the delay and is mainly used for fine adjustment of the delay. Its adjustment range is smaller and is suitable for scenarios that require precise control of the delay time. Coarse Delay performs coarse delay adjustment and is mainly used for rough adjustment of the delay. Its adjustment range is larger and is suitable for scenarios that require quick setting of the delay time. Fine Delay has a smaller adjustment range and is suitable for precise adjustment; while Coarse Delay has a larger adjustment range and is suitable for quick adjustment. When precise control of the delay time is required, use Fine Delay; when quick setting of the delay time is required, use Coarse Delay.

[0033] Preferably, S300, adjusting and calibrating the delay line according to the position of the eye diagram boundary includes: S310, determining the midpoint of the eye diagram according to the position of the eye diagram boundary; S320 , determining whether to adjust the fine delay line or the coarse delay line according to the position of the middle point in the eye diagram.

[0034] If the left edge of the eye diagram is not found during the LCDL scan from 0 to 1UI, the Coarse Delay is incremented by 1 and the Fine Delay (LCDL Delay) is reset from 0. If the left edge of the eye diagram is found during the LCDL scan from 0 to 1UI, the Coarse Delay remains unchanged and the Fine Delay is incremented from 1UI to 2UI until the right edge is found.

[0035] Preferably, reference Figure 1 , according to the position of the point in the eye diagram, it is determined whether to adjust the fine delay line or the coarse delay line. If the left edge of the eye diagram is not scanned in the 0-1 unit interval, the coarse delay line is incremented by 1 and the fine delay line is accumulated again from 0; If the left boundary of the eye diagram is scanned in the 0-1 unit interval, the coarse delay line remains unchanged and the fine delay line continues to accumulate to the 1-2 unit interval until the right boundary of the eye diagram is found.

[0036] During the Read Training scan of six UIs, the LCDL's 2UI fine delay does not need to be fully scanned each time. Instead, if the left edge of the eye diagram is not reached during the 0-1UI scan of the LCDL, the CoarseDelay is incremented by 1, and the Fine Delay (LCDL Delay) is reset from 0. If the left edge of the eye diagram is reached during the 0-1UI scan, the Coarse Delay remains unchanged, and the Fine Delay continues to be incremented by the next 1UI-2UI position until the right edge is found.

[0037] Preferably, adjusting and calibrating the delay line according to the position of the eye diagram boundary further comprises: According to the standard range of the eye diagram, the LCDL Delay set range of the left edge of the eye diagram is controlled to be (0UI, 1UI); According to the standard range of the eye diagram, the LCDL Delay set range of the right edge of the eye diagram is controlled to be (1UI, 2UI); According to the standard range of the eye diagram, the set range of the middle points of the left and right boundaries of the eye diagram is controlled to belong to (0.5UI, 1.5UI).

[0038] Since the range of the standard eye diagram is 1UI, according to the algorithm described in the patent, the LCDL Delay set range corresponding to the left boundary is (0UI, 1UI), and the LCDL Delay set range corresponding to the right boundary is (1UI, 2UI); therefore, the set range of the midpoint between the left and right boundaries is (0.5UI, 1.5UI).

[0039] In this embodiment of the present invention, the midpoint of the trained eye diagram is guaranteed to be between (0.5UI, 1.5UI). There is no need to perform carry or borrow processing between the Fine Delay and the Coarse Delay during the final backfill, thus avoiding the impact of the error caused by the inequality between 1UI of the Fine Delay and 1UI of the Coarse Delay.

[0040] As a preferred embodiment, if LCDL is x UIs greater than 2UI, the judgment in the algorithm remains the same, that is, if the left boundary of the eye diagram is not scanned during the 0-1UI scanning of LCDL, then Fine Delay is added to Coarse Delay by 1; if the left boundary is scanned, no carry is performed.

[0041] Example 2 An LPDDR5 Read Training system for eliminating fine delay and coarse delay errors includes: Scanning module, used to scan and read the training unit interval; A judgment module is used to obtain the position of the scanned eye diagram boundary; The calibration module is used to adjust and calibrate the delay line according to the position of the eye diagram boundary.

[0042] Figure 7 and Figure 8 Describes the algorithm used in the solution of the present invention in the face of Figure 4 、 Figure 5 and Figure 6 The effect of the algorithm scenario on the problem shown.

[0043] If you are still Figure 4 and Figure 5 In the middle eye diagram state scenario, the LCDL delay will be directly backfilled to 0.9UI, that is, Coarse=3UI, Fine=0.9UI. The eye diagram range of this method does not include the span from LCDL from 2UI to 0UI, so there is no hole in the middle part of the RxClk Eye, avoiding Figure 3 In addition, this method also avoids the Fine Delay's carry processing of the Coarse Delay during backfilling, thus avoiding Figure 5 For details on the problem shown, see Figure 7 .

[0044] If you are still Figure 5 In the middle eye diagram state scenario, the LCDL delay will be directly backfilled to 1.1UI, that is, Coarse = 1UI, Fine = 1.1UI. This method avoids the borrowing of Coarse Delay by Fine Delay when backfilling the eye diagram range, thus avoiding Figure 5 For details on the problem shown, see Figure 8 .

[0045] Example 3 An electronic device includes: a chip, a processor, and a memory, wherein the memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device performs an LPDDR5 read training method to eliminate fine delay and coarse delay errors.

[0046] refer to Figure 9The electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, which may include various interfaces, transmission lines, or buses, etc., but this is not limited in the present embodiment. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, such as connection via various interfaces, transmission lines, buses, etc.

[0047] The processor 21 may be one or more graphics processing units (GPUs). If the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Alternatively, the processor 21 may be a processor group consisting of multiple GPUs, with the multiple processors coupled to each other via one or more buses. Alternatively, the processor may be another type of processor, and this is not limited in this embodiment of the present invention.

[0048] The memory 22 can be used to store computer program instructions and various computer program codes, including program codes for executing the embodiments of the present invention. Optionally, the memory includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM), and is used for related instructions and data.

[0049] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 can be independent devices or an integrated device.

[0050] Example 4 A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When executed by a processor of an electronic device, the program instructions cause the processor to perform an LPDDR5 read training method that eliminates fine delay and coarse delay errors.

[0051] The present invention ensures that the Read Training eye diagram must appear within a 2UI range of an LCDL, thereby avoiding the need for the Fine Delay to perform a borrow or carry operation on the Coarse Delay during the final delay configuration backfill. The present invention determines whether to carry the Fine Delay to the Coarse Delay Read Training algorithm based on whether the left boundary is found.

[0052] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is intended to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A LPDDR5 Read Training method for eliminating fine delay and coarse delay errors, characterized in that: include: Scan and read the unit interval of training; Get the position of the scanned eye diagram boundary; Adjust the calibrated delay line based on the location of the eye diagram boundaries.

2. The LPDDR5 Read Training method for eliminating fine delay and coarse delay errors according to claim 1, wherein: The unit interval of the scanning and reading training includes: One scan reads one unit interval in training.

3. The LPDDR5 Read Training method for eliminating fine delay and coarse delay errors according to claim 1, wherein: The position of the scanned eye diagram boundary is obtained by: Scan the left boundary of the eye diagram in the 0-1 unit interval; If the left boundary of the eye diagram is not scanned in the 0-1 unit interval, adjust the delay line parameters to continue scanning; If the left edge of the eye diagram is found in the 0-1 unit interval, the scan continues to search for the right edge.

4. The LPDDR5 Read Training method for eliminating fine delay and coarse delay errors according to claim 1, wherein: The calibration delay line includes a coarse delay line and a fine delay line.

5. The LPDDR5 Read Training method for eliminating fine delay and coarse delay errors according to claim 4, wherein: The adjusting and calibrating the delay line according to the position of the eye diagram boundary comprises: Determine the midpoint of the eye diagram according to the position of the eye diagram boundary; Determine whether to adjust the fine delay line or the coarse delay line based on the position of the middle point in the eye diagram.

6. The LPDDR5 Read Training method for eliminating fine delay and coarse delay errors according to claim 5, wherein: The step of determining whether to adjust the fine delay line or the coarse delay line according to the position of the midpoint in the eye diagram comprises: If the left edge of the eye diagram is not scanned in the 0-1 unit interval, the coarse delay line is incremented by 1 and the fine delay line is accumulated again from 0; If the left boundary of the eye diagram is scanned in the 0-1 unit interval, the coarse delay line remains unchanged and the fine delay line continues to accumulate to the 1-2 unit interval until the right boundary of the eye diagram is found.

7. The LPDDR5 Read Training method for eliminating fine delay and coarse delay errors according to claim 5, wherein: The adjusting and calibrating the delay line according to the position of the eye diagram boundary also includes: According to the standard range of the eye diagram, the LCDL Delay set range of the left edge of the eye diagram is controlled to be (0UI, 1UI); According to the standard range of the eye diagram, the LCDL Delay set range of the right edge of the eye diagram is controlled to be (1UI, 2UI); According to the standard range of the eye diagram, the set range of the middle points of the left and right boundaries of the eye diagram is controlled to belong to (0.5UI, 1.5UI).

8. An LPDDR5 Read Training system for eliminating fine delay and coarse delay errors, characterized in that: include: Scanning module, used to scan and read the training unit interval; A judgment module is used to obtain the position of the scanned eye diagram boundary; The calibration module is used to adjust and calibrate the delay line according to the position of the eye diagram boundary.

9. An electronic device, characterized in that: include: A chip, a processor, and a memory, the memory being used to store computer program code, the computer program code including computer instructions. When the chip executes the computer instructions, the electronic device performs an LPDDR5 Read Training method for eliminating fine delay and coarse delay errors as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor performs an LPDDR5 Read Training method for eliminating fine delay and coarse delay errors according to any one of claims 1 to 7.

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