A method for manufacturing a semiconductor structure

Abstract

This invention provides a method for fabricating a semiconductor structure. The method includes the following steps: providing a substrate, the substrate including a base, a pad oxide layer, and at least one trench group, the trench group including a first trench and a second trench, the pad oxide layer being formed on the surface of the substrate, the first trench and the second trench being disposed within the substrate and penetrating the pad oxide layer at their upper portions; forming a first barrier layer on the sidewalls of the first trench and the sidewalls of the second trench; forming a second barrier layer on the sidewalls of the first barrier layer; forming an isolation layer between the second barrier layers on both sides of the second trench; replacing the second barrier layer with a first epitaxial layer and a heavily doped region arranged sequentially from bottom to top, and replacing the first barrier layer with a second epitaxial layer and a lightly doped region arranged sequentially from bottom to top; forming a gate structure in the channel between the first trench and the second trench, and forming sidewall structures on both sides of the gate structure. The fabrication method of this invention simplifies the manufacturing process, improves production efficiency, and reduces manufacturing costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing, with the development of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the shrinking feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortening, and the distance between the source and drain of the device is also shortening. This increases the electric field strength, accelerating electrons or holes in the channel and giving them high energy. These electrons or holes may be injected into the gate oxide layer, leading to device reliability issues, such as a decrease in threshold voltage, a worsening of the subthreshold slope, and drain-induced barrier lowering (DIBL). By introducing a lightly doped drain (LDD) between the drain and source, the electric field strength near the drain can be reduced, thereby reducing the impact of hot carrier effects. Traditional fabrication methods require a separate mask when forming trench isolation structures, and additional masking and implantation steps are needed when ion implanting the lightly doped region, source, and drain, increasing the process cycle and manufacturing cost. Summary of the Invention

[0003] This invention provides a method for preparing a semiconductor structure, which simplifies the manufacturing process, improves production efficiency, and reduces manufacturing costs.

[0004] The present invention provides a method for fabricating a semiconductor structure, comprising the following steps:

[0005] A substrate is provided, the substrate including a substrate, a pad oxide layer and at least one trench group, the trench group including a first trench and a second trench, the pad oxide layer being formed on the surface of the substrate, the first trench and the second trench being disposed within the substrate and having an opening formed through the pad oxide layer at the top, the width of the first trench being smaller than the width of the second trench.

[0006] A first barrier layer is formed on both sides of the first trench and on both sides of the second trench.

[0007] A second barrier layer is formed on the sidewall of the first barrier layer in the first trench and the second trench respectively, and the second barrier layer fills the first trench.

[0008] An isolation layer is formed between the second barrier layers on both sides of the second trench;

[0009] The second barrier layer is replaced with a first epitaxial layer and a heavily doped region arranged sequentially from bottom to top, and the first barrier layer is replaced with a second epitaxial layer and a lightly doped region arranged sequentially from bottom to top.

[0010] A gate structure is formed in the channel between the first trench and the second trench, and sidewall structures are formed on both sides of the gate structure.

[0011] In one embodiment of the present invention, the substrate includes a plurality of trench groups, the heavily doped regions of the plurality of trench groups include P-type heavily doped regions and N-type heavily doped regions, and the lightly doped regions of the plurality of trench groups include P-type lightly doped regions and N-type lightly doped regions. Replacing the second barrier layer with a first epitaxial layer and a heavily doped region arranged sequentially from bottom to top, and replacing the first barrier layer with a second epitaxial layer and a lightly doped region arranged sequentially from bottom to top, includes the following steps:

[0012] A first mask layer is disposed on the substrate, exposing the trench group corresponding to the heavily doped P-type region and the lightly doped P-type region. A second barrier layer is removed from the trench group corresponding to the heavily doped P-type region and the lightly doped P-type region. A first N-type epitaxial layer and a heavily doped P-type region are sequentially generated at the corresponding positions of the second barrier layer. The first barrier layer is then removed from the trench group corresponding to the heavily doped P-type region and the lightly doped P-type region. A second N-type epitaxial layer and a lightly doped P-type region are sequentially generated at the corresponding positions of the first barrier layer.

[0013] A second mask layer is disposed on the substrate, the second mask layer exposing the trench group corresponding to the N-type heavily doped region and the N-type lightly doped region. A second barrier layer in the trench group corresponding to the N-type heavily doped region and the N-type lightly doped region is removed, and a first P-type epitaxial layer and an N-type heavily doped region are sequentially generated at the corresponding positions of the second barrier layer. A first barrier layer in the trench group corresponding to the N-type heavily doped region and the N-type lightly doped region is removed, and a second P-type epitaxial layer and an N-type lightly doped region are sequentially generated at the corresponding positions of the first barrier layer.

[0014] In one embodiment of the present invention, a first barrier layer is formed on both sidewalls of the first trench and on both sidewalls of the second trench, comprising the following steps:

[0015] A first barrier is deposited in the first trench and the second trench, the first barrier covering the substrate;

[0016] Remove the first obstruction in the horizontal direction, and form the first obstruction layer on both side walls of the first trench and on both side walls of the second trench, respectively.

[0017] In one embodiment of the present invention, a second barrier layer is formed on the sidewall of the first barrier layer in the first trench and the second trench, respectively, and the second barrier layer fills the first trench, comprising the following steps:

[0018] A second barrier is deposited in the first trench and the second trench, the second barrier covering the pad oxide layer, the first trench, the second trench and the first barrier layer;

[0019] Remove the second obstruction in the horizontal direction, and form a second obstruction layer on the sidewall of the first obstruction layer in the first trench and the second trench, respectively.

[0020] In one embodiment of the present invention, the depths of the first trench and the second trench are 150~330nm.

[0021] In one embodiment of the present invention, the thickness of the lightly doped region is 20~100nm, and the thickness of the heavily doped region is 50~220nm.

[0022] In one embodiment of the present invention, the ion concentration of the heavily doped region is 1 × 10⁻⁶. 20 ~5×10 20 cm -3 The ion concentration of the lightly doped region is 1×10⁻⁶. 17 ~5×10 17 cm -3 .

[0023] In one embodiment of the present invention, after removing the first barrier layer and sequentially forming a second epitaxial layer and a lightly doped region at the corresponding position of the first barrier layer, the preparation method further includes removing the pad oxide layer and performing a thermal oxidation treatment on the surface of the substrate to form an oxide layer on the surface of the substrate.

[0024] In one embodiment of the present invention, the temperature of the thermal oxidation treatment is 1000~1200℃, the time of the thermal oxidation treatment is 40~80s, and the thickness of the oxide layer is 20~30Å.

[0025] In one embodiment of the present invention, the second barrier layer is replaced by a first epitaxial layer and a heavily doped region arranged sequentially from bottom to top, and the first barrier layer is replaced by a second epitaxial layer and a lightly doped region arranged sequentially from bottom to top, comprising the following steps:

[0026] Remove the second barrier layer, and sequentially form the first epitaxial layer and the heavily doped region at the corresponding positions of the second barrier layer;

[0027] Remove the first barrier layer, and sequentially form the second epitaxial layer and the lightly doped region at the corresponding positions of the first barrier layer;

[0028] The removal of the first barrier layer and the removal of the second barrier layer are carried out by wet etching, and the wet etching has different selectivity ratios for the first barrier layer, the second barrier layer and the isolation layer.

[0029] In summary, this invention provides a method for fabricating a semiconductor structure. A first barrier layer and a second barrier layer are formed in a first trench, and a first barrier layer, a second barrier layer, and an isolation layer are formed in a second trench. The second barrier layer is replaced by a first epitaxial layer and a heavily doped region arranged sequentially from bottom to top, and the first barrier layer is replaced by a second epitaxial layer and a lightly doped region arranged sequentially from bottom to top. A gate structure is formed on the channel between the first and second trenches, and sidewalls are formed on both sides of the gate structure. An unexpected advantage of this application is that the isolation layer is formed in the second trench, eliminating the need for a separate mask fabrication. Furthermore, no additional masking or implantation processes are required when forming the source, drain, and lightly doped regions, simplifying the fabrication process, improving production efficiency, and reducing manufacturing costs. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0031] In the attached diagram:

[0032] Figure 1 This is a flowchart illustrating the fabrication process of a semiconductor structure according to an embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram of forming a pad oxide layer and a pad nitride layer on a substrate according to an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the formation of a photoresist layer provided in one embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram illustrating the formation of a first trench and a second trench according to one embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the removal of the photoresist layer and the pad nitride layer provided in one embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of the deposition of a first barrier provided in one embodiment of the present invention;

[0038] Figure 7This is a schematic diagram of the formation of a first barrier layer provided in one embodiment of the present invention;

[0039] Figure 8 This is a schematic diagram of the deposition of a second barrier provided in one embodiment of the present invention;

[0040] Figure 9 This is a schematic diagram of the formation of a second barrier layer provided in one embodiment of the present invention;

[0041] Figure 10 This is a schematic diagram of a deposited insulating medium provided in one embodiment of the present invention;

[0042] Figure 11 This is a schematic diagram of the formation of an isolation layer provided in one embodiment of the present invention;

[0043] Figure 12 This is a schematic diagram of removing the second blocking layer according to an embodiment of the present invention;

[0044] Figure 13 This is a schematic diagram of the formation of a first epitaxial layer and a heavily doped region provided in one embodiment of the present invention;

[0045] Figure 14 This is a schematic diagram of removing the first blocking layer according to an embodiment of the present invention;

[0046] Figure 15 This is a schematic diagram of the formation of a second epitaxial layer and a lightly doped region provided in one embodiment of the present invention;

[0047] Figure 16 This is a schematic diagram of removing the oxide layer from the pad according to one embodiment of the present invention;

[0048] Figure 17 This is a schematic diagram of the formation of an oxide layer provided in one embodiment of the present invention;

[0049] Figure 18 This is a schematic diagram of the formation of the gate and sidewall structure provided in one embodiment of the present invention;

[0050] Figure 19 This is a schematic diagram of forming a first barrier layer, a second barrier layer, and an isolation layer on a substrate according to another embodiment of the present invention;

[0051] Figure 20 This is a schematic diagram of setting a first mask layer according to another embodiment of the present invention;

[0052] Figure 21 This is a schematic diagram of the formation of a first N-type epitaxial layer, a heavily doped P-type region, a second N-type epitaxial layer, and a lightly doped P-type region provided in another embodiment of the present invention;

[0053] Figure 22This is a schematic diagram of setting a second mask layer according to another embodiment of the present invention;

[0054] Figure 23 This is a schematic diagram of the formation of a first P-type epitaxial layer and an N-type heavily doped region, and a second P-type epitaxial layer and an N-type lightly doped region, provided in another embodiment of the present invention.

[0055] The attached figures are labeled as follows:

[0056] 100, Substrate; 110, Substrate; 111, Well Region; 1111, P-type Well Region; 1112, N-type Well Region; 120, Pad Oxide Layer; 130, First Trench; 140, Second Trench; 141, Groove; 150, Pad Nitride Layer; 160, Photoresist Layer; 161, First Trench Region; 162, Second Trench Region; 170, Oxide Layer; 180, Isolation Structure; 200, First Barrier Layer; 300, Second Barrier Layer; 400, Isolation Layer; 500, First Epitaxial Layer; 501. First P-type epitaxial layer; 502, First N-type epitaxial layer; 510, Heavily doped region; 511, Heavily doped P-type region; 512, Heavily doped N-type region; 600, Second epitaxial layer; 601, Second P-type epitaxial layer; 602, Second N-type epitaxial layer; 610, Lightly doped region; 611, Lightly doped P-type region; 612, Lightly doped N-type region; 700, Gate structure; 710, Gate oxide layer; 720, Gate material layer; 800, Sidewall structure; 900, First mask layer; 910, Second mask layer. Detailed Implementation

[0057] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0058] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0059] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0060] Please see Figures 1 to 18 As shown, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0061] S1, providing such Figure 5 The substrate 100 shown includes a substrate 110, a pad oxide layer 120, and at least one trench group. The trench group includes a first trench 130 and a second trench 140. The substrate 110 includes a well region 111 formed by doping with impurities. The pad oxide layer 120 is formed on the surface of the substrate 110. The first trench 130 and the second trench 140 are disposed in the well region 111 of the substrate 110 and have an opening formed through the pad oxide layer 120 at the top. The width W1 of the first trench 130 is smaller than the width W2 of the second trench 140.

[0062] S2, such as Figure 7 As shown, a first barrier layer 200 is formed on both sides of the first trench 130 and the two sides of the second trench 140, respectively.

[0063] S3, such as Figure 9 As shown, a second barrier layer 300 is formed on the sidewall of the first barrier layer 200 in the first trench 130 and the second trench 140 respectively, and the second barrier layer 300 fills the first trench 130. A groove 141 is formed between the second barrier layers 300 on both sides of the second trench 140.

[0064] S4, such as Figure 11 As shown, an isolation layer 400 is formed within the groove 141;

[0065] S5, such as Figures 12 to 15 As shown, the second barrier layer 300 is replaced with the first epitaxial layer 500 and the heavily doped region 510 arranged sequentially from bottom to top, and the first barrier layer 200 is replaced with the second epitaxial layer 600 and the lightly doped region 610 arranged sequentially from bottom to top.

[0066] S6, such as Figure 18 As shown, a gate structure 700 is formed in the channel between the first trench 130 and the second trench 140, and a sidewall structure 800 is formed on both sides of the gate structure 700.

[0067] Please see Figure 5As shown, in step S1 of this invention, the substrate 110 can be any material suitable for forming a semiconductor structure, such as undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). This invention does not limit the specific material and thickness of the substrate 110, and the substrate 110 can be a silicon substrate doped with impurities. The substrate 110 includes a well region 111 formed by doping with impurities. The well region 111 can be P-type doped or N-type doped, and the doping type of the impurities can be flexibly set according to the desired semiconductor structure.

[0068] It should be noted that the substrate 100 can be a purchased semi-finished product or it can be prepared by itself. In one embodiment, the substrate 100 is prepared by itself based on the substrate 110.

[0069] Please see Figures 2 to 5 As shown, the preparation method of substrate 100 is as follows:

[0070] Please see Figure 2 As shown, in one embodiment of the present invention, a pad oxide layer 120 is formed on the surface of the well region 111 of the substrate 110. The pad oxide layer 120 can serve as a protective layer for the substrate 110, protecting the substrate 110 it covers in subsequent processes and preventing unnecessary damage to the substrate 110. Furthermore, since the subsequently formed pad nitride layer 150 has high stress, dislocations are easily generated on the surface of the substrate 110 during its formation. The pad oxide layer 120 can provide a buffer during the formation of the pad nitride layer 150, preventing dislocations from being generated on the substrate 110. Additionally, the pad oxide layer 120 can also prevent the subsequent formation of an epitaxial layer on the surface of the substrate 110. The material of the pad oxide layer 120 can be silicon dioxide or similar materials, and the pad oxide layer 120 can be formed using deposition processes, such as at least one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition. The fabrication process of substrate 100 may also include cleaning substrate 110 before forming pad oxide layer 120 on substrate 110. By cleaning substrate 110, impurities present on the surface of substrate 110 can be removed, avoiding the impact of impurities on subsequent processes, thereby ensuring device performance. For example, substrate 110 can be cleaned using a cleaning solution, or substrate 110 can be cleaned by purging with a gas such as nitrogen.

[0071] Please see Figure 2As shown, in one embodiment of the present invention, after forming the pad oxide layer 120, a pad nitride layer 150 is formed on the pad oxide layer 120. The material of the pad nitride layer 150 can be silicon nitride or silicon oxynitride; in this embodiment, the pad nitride layer 150 is, for example, silicon nitride. The pad nitride layer 150 can be prepared by any one of the following processes: low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition. For example, when preparing the pad nitride layer 150 using a low-pressure chemical vapor deposition process, silicon nitride can be generated by reacting ammonia with dichlorosilane. By providing the pad nitride layer 150, it can serve as a mask during the subsequent formation of the substrate 100, protecting the substrate 110 from damage during etching.

[0072] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, after forming the pad nitride layer 150, photoresist is coated on the pad nitride layer 150 to form a photoresist layer 160. The type of photoresist material is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, photolithography processes such as mask exposure and development are used to pattern the coated photoresist, exposing the first trench region 161 and the second trench region 162. Using the patterned photoresist layer 160 as a mask layer, the pad nitride layer 150, the pad oxide layer 120, and the well region 111 are etched sequentially to form the first trench 130 and the second trench 140. In this embodiment, the first trench 130 and the second trench 140 extend from the pad nitride layer 150 into the well region 111. Etching gases include one or a mixture of several of the following: chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or hydrogen bromide (HBr), or a combination thereof with oxygen (O2).

[0073] The first trench 130 and the second trench 140 have the same depth. For example, the depth of the first trench 130 and the second trench 140 is 150~300nm, such as any value among 150nm, 200nm, 250nm, or 300nm. The width W1 of the first trench 130 is less than the width W2 of the second trench 140. For example, the width of the first trench 130 is greater than or equal to 160nm, and the width of the second trench 140 is greater than or equal to 210nm. In some embodiments of this application, the aspect ratio of the first trench 130 is 1:1 to 2:1, such as any value among 1:1 to 2:1, such as 1:1, 1.5:1, or 2:1. The aspect ratio of the second trench 140 is 3:4 to 3:2, such as any value among 3:4 to 3:2, such as 3:4, 3:3, or 3:2.

[0074] Please see Figure 5 As shown, in one embodiment of the present invention, after forming the first trench 130 and the second trench 140, the fabrication of the substrate 100 further includes removing the photoresist layer 160 and the pad nitride layer 150. For example, the photoresist layer 160 can be removed by wet cleaning or ashing, and the pad nitride layer 150 can be removed by methods such as dry etching, wet etching, or a combination of both. In this embodiment, wet etching is used to remove the pad nitride layer 150.

[0075] Please see Figure 6 and Figure 7 As shown, in step S2 of the present invention, after removing the pad nitride layer 150, a first barrier is deposited in the first trench 130 and the second trench 140. The first barrier covers the substrate 100. After removing the first barrier in the horizontal direction, a first barrier layer 200 is formed on both sidewalls of the first trench 130 and the second trench 140, respectively. The first barrier layer 200 is flush with the pad oxide layer 120. The deposition method of the first barrier can be any one of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition. In this embodiment, the deposition method of the first barrier is atmospheric pressure chemical vapor deposition. When removing the first barrier in the horizontal direction, methods such as dry etching, wet etching, or a combination of dry etching and wet etching are used. In this embodiment, for example, dry etching is used to remove the first barrier in the horizontal direction. The material of the first barrier is, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), etc.

[0076] Please see Figure 8 and Figure 9As shown, in step S3 of the present invention, after the first barrier layer 200 is formed, a second barrier is deposited in the first trench 130 and the second trench 140. The second barrier covers the pad oxide layer 120, the first trench 130, the second trench 140, and the first barrier layer 200. The second barrier in the horizontal direction is removed, and a second barrier layer 300 is formed on the sidewalls of the first barrier layer 200 in the first trench 130 and the second trench 140, respectively. The second barrier layer 300 fills the first trench 130, and a groove 141 is formed between the two sides of the second barrier layer 300 in the second trench 140. The second barrier layer 300 is flush with the pad oxide layer 120. The deposition method of the second barrier can be any one of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition. In this embodiment, the deposition method of the first barrier is atmospheric pressure chemical vapor deposition. When removing the second barrier in the horizontal direction, methods such as dry etching, wet etching, or a combination of both can be used. In this embodiment, dry etching is used to remove the second barrier in the horizontal direction. The material of the second barrier is, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), etc. The material of the second barrier is different from that of the first barrier so that the etching solution has high selectivity for the first barrier layer 200 and the second barrier layer 300 when removing the second barrier layer 300, avoiding damage to the first barrier layer 200 when removing the second barrier layer 300, and preventing impact on subsequent processes. For example, if the material of the first barrier is silicon nitride, the material of the second barrier can be silicon oxynitride or silicon carbon nitride; or if the material of the first barrier is silicon carbon nitride, the material of the second barrier can be silicon nitride or silicon oxynitride; or, for example, if the material of the first barrier is silicon carbon nitride, the material of the second barrier can be silicon nitride or silicon oxynitride.

[0077] Please see Figure 10In step S4 of this invention, after forming second barrier layers 300 in the first trench 130 and the second trench 140 respectively, an insulating medium is deposited in the second trench 140. The insulating medium covers the pad oxide layer 120, the first barrier layer 200, the second barrier layer 300, and the groove 141. This invention does not limit the deposition method of the insulating medium. For example, it can be deposited by chemical vapor deposition (CVD) or high aspect ratio chemical vapor deposition (HARP CVD). In this embodiment, the isolation layer 400 is obtained, for example, by depositing tetraethyl orthosilicate (TEOS). Specifically, tetraethyl orthosilicate and an oxygen-containing precursor are introduced. The oxygen-containing precursor includes, for example, one of O2 or O3, and the deposition time is controlled to obtain the isolation layer 400. Among them, chemical vapor deposition is fast and can be deposited at low temperature. The deposited isolation layer 400 has good filling ability and is less prone to voids and other problems. After depositing the insulating medium, a high-temperature tempering process can be performed to increase the density and stress condition of the insulating layer 400. In this embodiment, the insulating medium is, for example, silicon oxide (SiO2). x In other embodiments, the insulating medium may also be other insulating materials suitable for isolation. The selection of the isolation layer 400, the first barrier layer 200, and the second barrier layer 300 is relatively broad, ensuring that the isolation layer 400 will not be damaged during subsequent removal of the first barrier layer 200 and the second barrier layer 300, thus avoiding impact on subsequent processes.

[0078] Please see Figure 11As shown, after depositing the insulating medium, the insulating medium is planarized, for example, by using Chemical Mechanical Polishing (CMP). CMP removes part of the insulating medium, obtaining an isolation layer 400 that fills the groove 141. This invention does not limit the planarization of the insulating medium to a specific location; it can be set at any position according to the semiconductor device design requirements, for example, planarizing the insulating medium to be flush with the first barrier layer 200 and the second barrier layer 300. For example, during the CMP process, Endpoint Detection (EPD) technology can be used to monitor the removal status of the insulating medium in real time and accurately, and then accurately determine whether the grinding of the insulating medium has reached a preset position based on the monitored data, thereby terminating the grinding process in a timely and accurate manner. Because the first barrier layer 200, the second barrier layer 300, and the insulating medium have different materials, their light reflection intensities are different. Based on this characteristic, the difference in reflected light intensity between the first barrier layer 200, the second barrier layer 300, and the insulating medium can be used to achieve accurate detection of the grinding endpoint. During the grinding stage of the insulating medium, the intensity of reflected light can remain relatively stable; however, when the grinding process progresses to the point where the insulating medium is gradually removed and the first barrier layer 200 and the second barrier layer 300 are exposed, the intensity of reflected light will change significantly. This change can serve as a signal to terminate the grinding process and stop the planarization treatment of the insulating medium.

[0079] The thickness of the isolation layer 400 is, for example, 150~300nm, such as any value in the range of 150nm, 200nm, 250nm or 300nm. For example, when the node is 90~65nm, the thickness of the isolation layer 400 is 250nm; when the node is 40~28nm, the thickness of the isolation layer 400 is 200nm; and when the node is 22nm / 20nm and below (especially FinFET), the isolation layer 400 is 150~200nm or shallower.

[0080] Please see Figure 12As shown, in step S5 of the present invention, in one embodiment of the present invention, the doping type of the heavily doped region 510 is P-type doping or N-type doping, and the doping type of the lightly doped region 610 is the same as that of the heavily doped region 510. In this embodiment, the number of trench groups is, for example, one. Taking the doping type of the well region 111 as P-type doping and the doping types of the heavily doped region 510 and the lightly doped region 610 as N-type doping as an example. After forming the isolation layer 400, the second barrier layer 300 is removed. The present invention does not limit the removal method of the second barrier layer 300, for example, it can be removed by dry etching, wet etching, or a combination of dry etching and wet etching. In this embodiment, the second barrier layer 300 is removed by wet etching. In this embodiment, the number of trench groups can also be multiple. When the number of trench groups is multiple, the doping type of the heavily doped region 510 is either all P-type doping or all N-type doping, and the doping type of the lightly doped region 610 is the same as that of the heavily doped region 510.

[0081] Please see Figure 13 As shown, after removing the second barrier layer 300, a first epitaxial layer 500 is formed in the first trench 130 and the second trench 140. The first epitaxial layer 500 can be formed using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), or metal-organic chemical vapor deposition (MOCVD). The lattice orientation of the first epitaxial layer 500 is the same as that of the substrate 110, and the doping type of the first epitaxial layer 500 is the same as that of the well region 111. For example, the substrate 110 is, for example, a p-type doped silicon substrate, and the first epitaxial layer 500 is also a p-type doped silicon material, with dopant ions such as boron (B) or gallium (Ga). After forming the first epitaxial layer 500, a heavily doped region 510 is formed on the first epitaxial layer 500 as the source and drain of the semiconductor structure. The heavily doped region 510 can be formed using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), or metal-organic chemical vapor deposition (MOCVD). The doping type of the heavily doped region 510 is opposite to that of the well region 111; for example, it is N-type doped, with dopant ions such as phosphorus (P) or arsenic (As). The ion concentration of the heavily doped region 510 is 1 × 10⁻⁶. 20 ~5×10 20 cm -3 For example, 1×10 20 cm -3 3×10 20cm -3 Or 5×10 20 cm -3 1×10 20 ~5×10 20 cm -3 Any value in the range. After forming a first epitaxial layer 500 with the same doping type as the well region 111, a heavily doped region 510 with the opposite doping type to the well region 111 is formed on the first epitaxial layer 500. For example, the thickness of the first epitaxial layer 500 is 100~250nm, such as any value in the range of 100~250nm, like 100nm, 200nm, or 250nm, and the thickness of the heavily doped region 510 is 50~200nm, such as any value in the range of 50~200nm, like 50nm, 100nm, or 200nm.

[0082] Please see Figure 14 As shown, after forming the heavily doped region 510, the first barrier layer 200 is removed. This invention does not limit the method of removing the first barrier layer 200; for example, it can be removed using dry etching, wet etching, or a combination of both. In this embodiment, wet etching is used to remove the first barrier layer 200.

[0083] Please see Figure 15As shown, after removing the first barrier layer 200, a second epitaxial layer 600 is formed at the corresponding positions of the first barrier layer 200 in the first trench 130 and the second trench 140. The second epitaxial layer 600 can be formed using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), or metal-organic chemical vapor deposition (MOCVD). The lattice orientation of the second epitaxial layer 600 is the same as that of the substrate 110, and the doping type of the second epitaxial layer 600 is the same as that of the well region 111. For example, the substrate 110 is, for example, a p-type doped silicon substrate 110, and the second epitaxial layer 600 is also a p-type doped silicon material, with dopant ions such as boron (B) or gallium (Ga). After forming the second epitaxial layer 600 in the trench, a lightly doped region 610 is formed on the second epitaxial layer 600. The lightly doped region 610 can be formed using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), or metal-organic chemical vapor deposition (MOCVD). The doping type of the lightly doped region 610 is opposite to that of the well region 111; for example, it is N-type doped, with dopant ions such as phosphorus (P) or arsenic (As). The ion concentration of the lightly doped region 610 is 1 × 10⁻⁶. 17 ~5×10 17 cm -3 For example, 1×10 17 cm -3 3×10 17 cm -3 Or 5×10 17 cm -3 1×10 17 ~5×10 17 cm -3Any value in the range. After forming a second epitaxial layer 600 with the same doping type as the well region 111, a lightly doped region 610 with the opposite doping type to the well region 111 is formed on the second epitaxial layer 600. For example, the thickness of the second epitaxial layer 600 is 50~280nm, such as any value in the range of 50nm, 100nm, 200nm or 280nm, and the thickness of the lightly doped region 610 is 20~100nm, such as any value in the range of 20nm, 50nm, 80nm or 100nm. The interface between the lightly doped region 610 and the second epitaxial layer 600 is higher than the interface between the heavily doped region 510 and the first epitaxial layer 500, that is, the thickness of the lightly doped region 610 is less than the thickness of the heavily doped region 510. In this invention, no additional mask and implantation process is required when forming the heavily doped region 510 and the lightly doped region 610, which can shorten the process cycle and reduce manufacturing costs.

[0084] In semiconductor structures, there is an inverse relationship between doping concentration and carrier diffusion depth. The lightly doped region 610 has a lower impurity concentration, allowing carriers to recombine with the majority carriers to achieve electrical neutrality within a shorter distance. Furthermore, the depletion region more easily penetrates the entire lightly doped layer to effectively control the channel. Conversely, the heavily doped region 510 has a higher ion concentration, requiring a thicker dimension to accommodate more carriers and reduce series resistance, while preventing excessive diffusion that could damage the device structure. Therefore, reducing the thickness of the lightly doped region 610 enhances the gate's control over the channel (e.g., suppressing short-channel effects), while increasing the thickness of the heavily doped region 510 provides lower contact resistance and mechanical stability. In the fabrication of traditional Metal Oxide Semiconductors (MOS), channel dopant ions from the lightly doped region are uniformly implanted into the channel, source, and drain regions. However, channel doping in the source and drain regions is ineffective; instead, it increases the impurity ion concentration in these regions, exacerbating GIDL leakage. On the other hand, the doping type of the lightly doped region is opposite to that of the channel doping. In order to counteract the channel doping previously performed in the source and drain regions, the concentration of the lightly doped region needs to be increased, that is, the impurity ion concentration in the source and drain regions needs to be increased, which will also exacerbate GIDL leakage current. In this application, the heavily doped region 510 and the lightly doped region 610 are formed by epitaxial doping. The ion concentration of the heavily doped region 510 and the lightly doped region 610 is not affected by the doping concentration in the channel region, which can reduce the channel doping concentration in the source and drain regions, thereby reducing the ion concentration in the subsequently formed lightly doped region 610, and reducing the gate-induced drain leakage current.

[0085] Please see Figure 16As shown, in one embodiment of this application, after forming the lightly doped region 610, the method for fabricating the semiconductor structure further includes removing the pad oxide layer 120. For example, the pad oxide layer 120 is removed by wet etching, and the etching solution used for wet etching is, for example, hydrofluoric acid or a buffer oxide etching solution.

[0086] Please see Figure 17 As shown, after removing the pad oxide layer 120, an oxide layer 170 is formed on the surface of the substrate 110. In this embodiment, taking a medium-voltage device as an example, the oxide layer 170 is formed, for example, by a dry oxygen oxidation method. For example, the substrate 100 is placed in a furnace tube, oxygen is introduced, and the exposed surface of the substrate 110 reacts with the oxygen at a high temperature to form the oxide layer 170. In this embodiment, the temperature of the thermal oxidation treatment is 1000~1200℃, for example, any value within the range of 1000~1200℃, such as 1000℃, 1100℃, or 1200℃. The time of the thermal oxidation treatment is 40~80s, for example, any value within the range of 40~80s, such as 40s, 60s, or 80s. For example, the thickness of the oxide layer 170 is 20~30Å, for example, any value within the range of 20~30Å, such as 20Å, 25Å, or 30Å. In other embodiments, wet oxygen oxidation can also be used, which uses H2 and O2 to oxidize the exposed substrate 110 surface at a preset temperature.

[0087] Please see Figure 18 As shown, in step S6 of this application, after forming an oxide layer 170 on the surface of the substrate 110, a gate structure 700 is formed on the substrate 110. Specifically, a gate oxide layer 710 is first formed on the surface of the substrate 110, and then a gate material layer 720 is formed on the surface of the gate oxide layer 710. In this embodiment, the material of the gate oxide layer 710 is, for example, silicon oxide. The gate oxide layer 710 is formed by methods such as thermal oxidation, chemical vapor deposition, or physical vapor deposition. The gate material layer 720 is, for example, a polysilicon layer, and the polysilicon layer can be P-type doped or N-type doped to ensure that the doping type of the polysilicon layer is different from the doping type of the well region 111, so as to improve the performance of the semiconductor device. In other embodiments, the material and thickness of the gate material layer 720 can be set according to actual needs. Then, the gate material layer 720 and the gate oxide layer 710 are etched by, for example, a dry etching process, a wet etching process, or a combination of dry etching and wet etching processes to form the gate structure 700. In other embodiments, the gate material layer 720 may also be, for example, a metal gate layer.

[0088] Please see Figure 18As shown, in one embodiment of the present invention, after forming the gate structure 700, sidewall structures 800 are formed on both sides of the gate structure 700. Specifically, a dielectric layer (not shown in the figure) is formed on the gate structure 700 and the substrate 110, and the dielectric layer includes, for example, a silicon oxide layer. The dielectric layer is formed, for example, by high-temperature thermal oxidation, including methods such as dry thermal oxidation, wet thermal oxidation, or in-situ steam generation (ISSG). The dielectric layer is then subjected to nitriding treatment, for example, by one or a combination of methods such as decoupled plasma nitriding (DPN), rapid thermal nitriding (RTN), or ammonia immersion, to nitrid the surface of the dielectric layer, forming a nitrided layer and improving the stability of the sidewall structure 800. By employing wet etching, dry etching, or a combination of wet and dry etching methods, the dielectric layers on both sides of the gate structure 700 are preserved, thereby forming single-layer or multi-layer sidewall structures 800 on both sides of the gate. This effectively controls the influence of parasitic capacitance and improves the performance of the semiconductor device. In this embodiment, the sidewall structure 800 is multi-layered.

[0089] Please see Figure 18 As shown, in some embodiments, after forming the sidewall structure 800, a back-end process (BEOL) for integrated circuit manufacturing is performed. An interlayer dielectric layer is covered on the surface of the substrate 100 by a metal interconnect process (e.g., including at least one of contact hole process, damask process and pad process), and contact plugs with electrical contact electrostatic protection structure and multilayer metal interconnects electrically connected to the contact plugs are formed in the interlayer dielectric layer.

[0090] Please see Figures 19 to 23As shown, in another embodiment of this application, the substrate 100 includes a plurality of trench groups. The heavily doped regions 510 of the plurality of trench groups include P-type heavily doped regions 511 and N-type heavily doped regions 512, and the lightly doped regions 610 of the plurality of trench groups include P-type lightly doped regions 611 and N-type lightly doped regions 612. For example, the well region 111 includes a P-type well region 1111 and an N-type well region 1112, and an isolation structure 180 is provided between the P-type well region 1111 and the N-type well region 1112. The N-type heavily doped regions 512 and 612 are formed within the trench group of the P-type well region 1111, and the P-type heavily doped regions 511 and 611 are formed within the trench group of the N-type well region 1112. The doping types of the first epitaxial layer 500 and the second epitaxial layer 600 are the same as those of the well region 111. Specifically, the first epitaxial layer 500 is doped with both N-type and P-type doping, and the second epitaxial layer 600 is doped with both N-type and P-type doping. When the well region 111 is an N-type well region 1112, the first epitaxial layer 500 and the second epitaxial layer 600 are doped with N-type doping, and the heavily doped region 510 and the lightly doped region 610 are doped with P-type doping. When the well region 111 is a P-type well region 1111, the first epitaxial layer 500 and the second epitaxial layer 600 are doped with P-type doping, and the heavily doped region 510 and the lightly doped region 610 are doped with N-type doping. In this embodiment, the difference between the semiconductor structure fabrication method and the method where the heavily doped region 510 and the lightly doped region 610 are both N-type and P-type doping lies in... Figures 11 to 15 .

[0091] Please see Figures 20 to 23 As shown, in some other embodiments of this application, the second barrier layer 300 is replaced by a first epitaxial layer 500 and a heavily doped region 510 arranged sequentially from bottom to top, and the first barrier layer 200 is replaced by a second epitaxial layer 600 and a lightly doped region 610 arranged sequentially from bottom to top, including the following steps: Please refer to Figure 20 As shown, a first mask layer 900 is formed on the substrate 100, exposing trench groups corresponding to the heavily doped P-type region 511 and the lightly doped P-type region 611. (See also...) Figure 21As shown, the second barrier layer 300 in the trench group corresponding to the heavily doped P-type region 511 and the lightly doped P-type region 611 is removed, and a first N-type epitaxial layer 502 and a heavily doped P-type region 511 are sequentially generated at the corresponding positions of the second barrier layer 300. The first barrier layer 200 in the trench group corresponding to the heavily doped P-type region 511 and the lightly doped P-type region 611 is removed, and a second N-type epitaxial layer 602 and a lightly doped P-type region 611 are sequentially generated at the corresponding positions of the first barrier layer 200. For example, a patterned photoresist is used as the first mask layer 900. The type of photoresist material is not limited; it can be a positive photoresist material or a negative photoresist material. The first mask layer 900 is, for example, a positive photoresist material. The removal method of the first barrier layer 200 and the second barrier layer 300 is the same as the removal method when the substrate 100 includes a trench group, and will not be described again here.

[0092] Please see Figure 22 As shown, after forming the P-type heavily doped region 511 and the P-type lightly doped region 611, the first mask layer 900 is removed, and a second mask layer 910 is formed on the substrate 100. The second mask layer 910 exposes the trench groups corresponding to the N-type heavily doped region 512 and the N-type lightly doped region 612. Please refer to [link / reference]. Figure 23 As shown, the second barrier layer 300 in the trench group corresponding to the N-type heavily doped region 512 and the N-type lightly doped region 612 is removed, and a first P-type epitaxial layer 501 and an N-type heavily doped region 512 are sequentially generated at the corresponding positions of the second barrier layer 300. The first barrier layer 200 in the trench group corresponding to the N-type heavily doped region 512 and the N-type lightly doped region 612 is removed, and a second P-type epitaxial layer 601 and an N-type lightly doped region 612 are sequentially generated at the corresponding positions of the first barrier layer 200. The removal method of the first barrier layer 200 and the second barrier layer 300 is the same as the removal method when the substrate 100 includes a trench group, and will not be described again here. For example, a patterned photoresist is used as the second mask layer 910. The type of photoresist material is not limited and can be either a positive photoresist material or a negative photoresist material. The second mask layer 910 is, for example, a negative photoresist material. The second mask layer 910 and the first mask layer 900 are made of materials with opposite photoresist properties. When patterning the second mask layer 910 and the first mask layer 900, the same set of photomasks can be used, reducing the amount of photomask fabrication and simplifying the process. The second P-type epitaxial layer 601 and the N-type lightly doped region 612 are formed, and then the second mask layer 910 is removed.

[0093] The substrate 100 includes multiple trench groups. The heavily doped regions 510 of the multiple trench groups include P-type heavily doped regions 511 and P-type lightly doped regions 512. The lightly doped regions 610 of the multiple trench groups include P-type lightly doped regions 611 and N-type lightly doped regions 612. When forming the P-type heavily doped regions 511, N-type lightly doped regions 612, and N-type lightly doped regions 612, only one photomask is needed to complete the setting of the first mask layer 900 and the second mask layer 910, and no implantation process is required, which can greatly reduce the process cycle and reduce the fabrication cost. This invention does not limit the order in which the N-type and P-type doped regions are formed. In other embodiments, the N-type heavily doped regions 512 and N-type lightly doped regions 612 can be formed first, followed by the P-type heavily doped regions 511 and P-type lightly doped regions 611.

[0094] In summary, this invention provides a method for fabricating a semiconductor structure. A first barrier layer and a second barrier layer are formed in a first trench, and a first barrier layer, a second barrier layer, and an isolation layer are formed in a second trench. The second barrier layer is replaced by a first epitaxial layer and a heavily doped region arranged sequentially from bottom to top, and the first barrier layer is replaced by a second epitaxial layer and a lightly doped region arranged sequentially from bottom to top. A gate structure is formed on the channel between the first and second trenches, and sidewalls are formed on both sides of the gate structure. An unexpected advantage of this application is that the isolation layer is formed in the second trench, eliminating the need for a separate mask fabrication. Furthermore, no additional masking or implantation processes are required when forming the source, drain, and lightly doped regions, simplifying the fabrication process, improving production efficiency, and reducing manufacturing costs.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, the substrate including a substrate, a pad oxide layer and at least one trench group, the trench group including a first trench and a second trench, the pad oxide layer being formed on the surface of the substrate, the first trench and the second trench being disposed within the substrate and having an opening formed through the pad oxide layer at the top, the width of the first trench being smaller than the width of the second trench. A first barrier layer is formed on both sides of the first trench and on both sides of the second trench. A second barrier layer is formed on the sidewall of the first barrier layer in the first trench and the second trench, respectively, and the second barrier layer fills the first trench. An isolation layer is formed between the second barrier layers on both sides of the second trench; The second barrier layer is replaced with a first epitaxial layer and a heavily doped region arranged sequentially from bottom to top, and the first barrier layer is replaced with a second epitaxial layer and a lightly doped region arranged sequentially from bottom to top. A gate structure is formed in the channel between the first trench and the second trench, and sidewall structures are formed on both sides of the gate structure.

2. The preparation method according to claim 1, characterized in that, The substrate includes a plurality of trench groups, the heavily doped regions of the plurality of trench groups include P-type heavily doped regions and N-type heavily doped regions, and the lightly doped regions of the plurality of trench groups include P-type lightly doped regions and N-type lightly doped regions. Replacing the second barrier layer with a first epitaxial layer and a heavily doped region arranged sequentially from bottom to top, and replacing the first barrier layer with a second epitaxial layer and a lightly doped region arranged sequentially from bottom to top, includes the following steps: A first mask layer is disposed on the substrate, the first mask layer exposes the trench group corresponding to the P-type heavily doped region and the P-type lightly doped region, the second barrier layer in the trench group corresponding to the P-type heavily doped region and the P-type lightly doped region is removed, and a first N-type epitaxial layer and a P-type heavily doped region are sequentially generated at the corresponding positions of the second barrier layer. Remove the first barrier layer in the trench group corresponding to the P-type heavily doped region and the P-type lightly doped region, and sequentially generate a second N-type epitaxial layer and a P-type lightly doped region at the corresponding positions of the first barrier layer; A second mask layer is disposed on the substrate, the second mask layer exposes the trench group corresponding to the N-type heavily doped region and the N-type lightly doped region, the second barrier layer in the trench group corresponding to the N-type heavily doped region and the N-type lightly doped region is removed, and a first P-type epitaxial layer and an N-type heavily doped region are sequentially generated at the corresponding positions of the second barrier layer; Remove the first barrier layer in the trench group corresponding to the N-type heavily doped region and the N-type lightly doped region, and sequentially generate a second P-type epitaxial layer and an N-type lightly doped region at the corresponding positions of the first barrier layer.

3. The preparation method according to claim 1, characterized in that, Forming a first barrier layer on both sides of the first trench and on both sides of the second trench, respectively, includes the following steps: A first barrier is deposited in the first trench and the second trench, the first barrier covering the substrate; Remove the first obstruction in the horizontal direction, and form the first obstruction layer on both side walls of the first trench and on both side walls of the second trench, respectively.

4. The preparation method according to claim 1, characterized in that, Forming second barrier layers on the sidewalls of the first barrier layer within the first trench and the second trench, respectively, and filling the first trench with the second barrier layers, includes the following steps: A second barrier is deposited in the first trench and the second trench, the second barrier covering the pad oxide layer, the first trench, the second trench and the first barrier layer; Remove the second obstruction in the horizontal direction, and form a second obstruction layer on the sidewall of the first obstruction layer in the first trench and the second trench, respectively.

5. The preparation method according to claim 1, characterized in that, The depths of the first trench and the second trench are 150~330nm.

6. The preparation method according to claim 1, characterized in that, The thickness of the lightly doped region is 20~100nm, and the thickness of the heavily doped region is 50~220nm.

7. The preparation method according to claim 1, characterized in that, The ion concentration in the heavily doped region is 1×10⁻⁶. 20 ~5×10 20 cm -3 The ion concentration of the lightly doped region is 1×10⁻⁶. 17 ~5×10 17 cm -3 .

8. The preparation method according to claim 1, characterized in that, After removing the first barrier layer and sequentially forming a second epitaxial layer and a lightly doped region at the corresponding position of the first barrier layer, the preparation method further includes removing the pad oxide layer and performing a thermal oxidation treatment on the surface of the substrate to form an oxide layer on the surface of the substrate.

9. The preparation method according to claim 8, characterized in that, The temperature of the thermal oxidation treatment is 1000~1200℃, the time of the thermal oxidation treatment is 40~80s, and the thickness of the oxide layer is 20~30Å.

10. The preparation method according to claim 1, characterized in that, Replacing the second barrier layer with a first epitaxial layer and a heavily doped region arranged sequentially from bottom to top, and replacing the first barrier layer with a second epitaxial layer and a lightly doped region arranged sequentially from bottom to top, includes the following steps: Remove the second barrier layer, and sequentially form the first epitaxial layer and the heavily doped region at the corresponding positions of the second barrier layer; Remove the first barrier layer, and sequentially form the second epitaxial layer and the lightly doped region at the corresponding positions of the first barrier layer; The removal of the first barrier layer and the removal of the second barrier layer are carried out by wet etching, and the wet etching has different selectivity ratios for the first barrier layer, the second barrier layer and the isolation layer.

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