Battery management system fault processing method, AFE chip and battery management system

Abstract

The invention provides a battery management system fault processing method, an AFE chip and a battery management system, and relates to the field of power supply or power distribution circuit devices or systems. The battery management system fault processing method provided by the invention comprises the following steps: when the battery management system is in a low power consumption mode, a bridge chip receives an abnormal signal and awakens a microcontroller unit; the bridging chip wakes up the AFE chip; each AFE chip detects the state of the AFE chip, generates a state signal of the AFE chip by combining the state signal of the previous AFE chip and sends the state signal of the AFE chip to the next AFE chip; single-point disconnection is determined, and the topological structure is divided into two parts by the single-point disconnection; and re-determining the address and the state signal transmission direction of each AFE chip and determining whether the state signals of other AFE chips need to be waited or not. According to the method provided by the invention, regular autonomous diagnosis in a low-power-consumption mode can still be performed after a single-point disconnection fault occurs, and when the fault occurs, the microcontroller unit is awakened in time for processing.

Description

Technical Field

[0001] The present application relates to the field of circuit devices or systems for power supply or distribution, and in particular to a battery management system fault handling method, an AFE chip, and a battery management system. Background Art

[0002] Abnormal battery conditions such as overcharging, over-discharging, and overheating can easily lead to thermal runaway and even explosion, placing stringent demands on the real-time monitoring and protection capabilities of the battery management system (BMS). As a core component of the BMS, the analog front-end chip (AFE) is responsible for collecting and diagnosing key parameters such as battery voltage, temperature, and current. Its reliability directly affects the safety of the entire system.

[0003] In low-power applications (such as new energy vehicles), the BMS is often placed in sleep mode to reduce energy consumption. However, during sleep, the battery may enter an abnormal state due to self-discharge, ambient temperature fluctuations, or internal short circuits. Failure to promptly wake the system for intervention could result in irreversible damage or safety incidents. Furthermore, the AFE chip itself may experience hardware aging or transient faults (such as register rollover and clock drift) due to long-term operation, requiring regular diagnostics to ensure its functional integrity. Summary of the Invention

[0004] In response to the problems existing in the prior art, the present application proposes a fault handling method for a battery management system. The battery management system includes a topology structure of multiple AFE chips electrically connected end to end via a bridge chip, and a microcontroller unit electrically connected to the bridge chip. The method is characterized in that the method includes: when the microcontroller unit in the battery management system is in shutdown mode, the bridge chip is in sleep mode or shutdown mode, and the multiple AFE chips are in sleep mode, the bridge chip wakes up the microcontroller unit when it receives an abnormal signal from the last AFE chip in the topology structure; the bridge chip sends a wake-up command to the AFE chips in the topology structure; each AFE chip in the topology structure is configured to detect its own status, and generate its own status signal based on the status signal received from the previous AFE chip, and send it to the next AFE chip; When only one AFE chip in a topology does not receive a normal signal or an abnormal signal, it is determined that a single-point break occurs between the AFE chip and the AFE chip above it, and the topology is divided into a first topology and a second topology by the single-point break. Based on the number of AFE chips in the first topology and the second topology and the location of each AFE chip, the address of each AFE chip, the status signal transmission direction, and whether it needs to wait for status signals from other AFE chips to generate its own status signal are re-determined.

[0005] In particular, the battery management system fault handling method proposed in the present application is as follows: when the AFE chip itself has no faults and receives a normal signal from the previous AFE chip, it sends a normal signal to the next AFE chip; when the AFE chip itself has no faults and receives an abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip; when the AFE chip itself has a fault and receives a normal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip; when the AFE chip itself has a fault and receives an abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip; when the AFE chip itself has a fault and receives an abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip; when the AFE chip does not receive a normal signal or an abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip.

[0006] In particular, the battery management system fault handling method proposed in this application determines that there is no line break fault in the topology structure, but a first type of fault has occurred in the AFE chip, when all other AFE chips in the topology structure have received the status signal sent by the previous AFE chip, except for the AFE chip that does not need to wait for the status signal from other AFE chips.

[0007] In particular, the battery management system fault handling method proposed in the present application determines that a multi-point disconnection fault occurs in the topology structure when two or more AFE chips in the topology structure do not receive normal signals or abnormal signals.

[0008] In particular, the battery management system fault handling method proposed in this application, when only one AFE chip in the topology structure does not receive a normal signal or an abnormal signal, detects the status of the AFE chip above the AFE chip to confirm whether the previous AFE chip itself has a second-type fault that causes it to fail to send a status signal.

[0009] The present application also proposes an AFE chip, characterized in that it includes: a normal signal register, configured to set the stored value to be valid when a normal signal is received from the previous AFE chip; an abnormal signal register, configured to set the stored value to be valid when an abnormal signal is received from the previous AFE chip; a direction register, wherein the stored value represents the propagation direction of the status signal; a wait register, wherein the stored value represents whether the AFE chip needs to wait for the status signal sent by the previous AFE chip to generate the status signal of the AFE chip; and a disconnection register, configured to set the stored value to be valid when the status signal sent by the previous AFE chip is not received within a specified time.

[0010] In particular, the AFE chip proposed in this application further includes an address register configured to store the address of the AFE chip.

[0011] In particular, the AFE chip proposed in the present application further includes a top register configured to mark whether the AFE chip is at the top of the topology structure in which it is located.

[0012] The present application also proposes a battery management system, comprising a plurality of AFE chip topology structures electrically connected end to end through a bridge chip, and a microcontroller unit electrically connected to the bridge chip, characterized in that when the microcontroller unit in the battery management system is in shutdown mode, the bridge chip is in sleep mode or shutdown mode, and the plurality of AFE chips are in sleep mode, the bridge chip is configured to receive a status signal from the last AFE chip in the topology structure, and when the status signal is an abnormal signal, the bridge chip is configured to wake up the microcontroller unit; and is configured to respectively connect the AFE chips in the topology structure in two directions. Sending a wake-up command; each AFE chip in the topology structure is configured to detect its own status and receive a status signal from the previous AFE chip to generate its own status signal and send it to the next AFE chip; the microcontroller unit is configured to read the register value of each AFE chip in the topology structure to determine whether a single-point break occurs between the AFE chip and the AFE chip above it; when a single-point break occurs, the topology structure is configured to be divided into a first topology structure and a second topology structure by the single-point break, and the register values ​​of the AFE chips in the first topology structure and the second topology structure are reset.

[0013] In particular, the battery management system proposed in the present application, the AFE chip includes a normal signal register, which is configured to set the stored value to be valid when receiving a normal signal from the previous AFE chip; an abnormal signal register, which is configured to set the stored value to be valid when receiving an abnormal signal from the previous AFE chip; a direction register, in which the stored value represents the propagation direction of the status signal; a wait register, in which the stored value represents whether the AFE chip needs to wait for the status signal sent by the previous AFE chip to generate the status signal of the AFE chip; and a disconnection register, which is configured to set the stored value to be valid when the status signal sent by the previous AFE chip is not received within a specified time.

[0014] In particular, in the battery management system proposed in the present application, the microcontroller unit reads the values ​​of the normal signal register, abnormal signal register, and disconnection register of each AFE chip in the topology structure to determine whether a single-point disconnection occurs.

[0015] In particular, in the battery management system proposed in the present application, the microcontroller unit resets the values ​​of the direction register and the wait register of the AFE chip in the first topology structure and the second topology structure.

[0016] The present application also proposes an electronic device, comprising the above-mentioned battery management system.

[0017] By using the method, AFE chip, battery management system and electronic device proposed in this application, regular autonomous diagnosis can still be performed in low-power mode after a single-point disconnection fault occurs, and when a new fault occurs, the microcontroller unit can be woken up in time for processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of a battery management system in a fault-free state according to an embodiment of the present application; Figure 2 This is a schematic diagram of the state of a battery management system after a single-point disconnection fault occurs according to an embodiment of the present application; Figure 3 This is a schematic diagram of an unconfigured state after a single-point disconnection fault occurs in a battery management system according to an embodiment of the present application; Figure 4 This is a configuration flow chart after a single point disconnection fault according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0020] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0021] Technologies, methods, and devices known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. The lines between the elements in the drawings are merely for ease of explanation, indicating that at least the elements at both ends of the line are communicating with each other, and are not intended to limit the unconnected elements from being unable to communicate. Furthermore, the number of lines between two elements is intended to indicate at least the number of signals involved in the communication between the two elements or at least the number of outputs provided, and is not intended to limit the two elements to communicating only with the signals shown in the figure.

[0022] This application provides a mechanism that can automatically wake up and perform diagnosis in low-power mode, and wake up the main control after a fault is found. In addition, in order to reduce the user's usage cost or ensure safety during the repair process, when a single-point disconnection fault occurs in the entire topology, this application provides a method to continue low-power periodic diagnosis and reverse wake-up of the entire BMS system. The user can continue to use it normally without maintenance, or ensure that the battery status can still be continuously monitored during the repair process.

[0023] Figure 1 This is a schematic diagram of the state of a battery management system when there is no fault according to an embodiment of the present application.

[0024] According to one embodiment, the battery management system may include a microcontroller unit 101 .

[0025] According to one embodiment, the battery management system may further include a bridge chip 102, which is electrically connected to the microcontroller unit 101 and receives commands from the microcontroller unit 101. According to one embodiment, the bridge chip 102 may include two interfaces, namely an L interface and an H interface. According to one embodiment, the bridge chip 102 may further include an interface register, which is configured as a forwarding interface for control commands. When the value of the interface register is 0, the command is forwarded from the H interface; when the value of the interface register is 1, the command is forwarded from the L interface. When a single-point disconnection fault occurs, the entire topology is divided into two parts. When configuring one of the parts, the value of the interface register of the bridge chip 102 needs to be set to 1. When configuring the other part, the value of the interface register of the bridge chip 102 needs to be set to 0.

[0026] According to one embodiment, the bridge chip 102 may further include a power control pin configured to reversely wake up the microcontroller unit 101 when a fault occurs, so as to handle the fault.

[0027] According to one embodiment, the battery management system may further include a plurality of analog front-end chips (AFEs), hereinafter referred to as AFE chips. Figure 1Taking a battery management system including multiple, for example, 7 AFE chips as an example, the battery management system may also include other numbers of AFE chips. Figure 1 As shown, multiple AFE chips are connected in series, and the ends are electrically connected to the bridge chip.

[0028] According to one embodiment, Figure 1 The battery management system shown can be in a low power consumption mode, which means that the microcontroller unit 101 is in a shutdown mode, all AFE chips are in a sleep mode, and the bridge chip 102 is in a shutdown mode or a sleep mode.

[0029] According to one embodiment, an AFE chip may include two interfaces, namely an L interface and an H interface. According to one embodiment, the L interface of AFE chip 103 is electrically connected to the H interface of bridge chip 102. The H interface of AFE chip 109 is electrically connected to the L interface of bridge chip 102. The L interfaces of other AFE chips are electrically connected to the H interfaces of the previous AFE chip.

[0030] According to one embodiment, the AFE chip can periodically perform self-diagnosis on its own functions and cell voltages. According to one embodiment, the status signal includes two types, namely normal signals and abnormal signals.

[0031] According to one embodiment, when the battery management system has no faults, the transmission direction of the status signal is from the AFE chip 103 to the AFE chip 109, such as Figure 1 Therefore, when the battery management system is fault-free, the previous AFE chip is the AFE chip closer to AFE chip 103 in the direction of status signal transmission, and the next AFE chip is the AFE chip farther away from AFE chip 103 in the direction of status signal transmission. For example, the previous AFE chip of AFE chip 105 is AFE chip 104, and the next AFE chip is AFE chip 106.

[0032] According to one embodiment, AFE chip failures can include both Type 1 and Type 2 failures. An AFE chip experiencing a Type 1 failure can still send an abnormality signal. An AFE chip experiencing a Type 2 failure cannot send a status signal. Hereinafter, "failure" of an AFE chip refers to a Type 1 failure. When referring to a Type 2 failure, it will be specifically stated as a Type 2 failure.

[0033] According to one embodiment, when the AFE chip itself has no faults and receives a normal signal from the previous AFE chip, it sends a normal signal to the next AFE chip; when the AFE chip itself has no faults and receives an abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip; when the AFE chip itself has a fault and receives a normal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip; when the AFE chip itself has a fault and receives an abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip; when the AFE chip does not receive a normal signal or an abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip.

[0034] According to one embodiment, the AFE chip may also include a normal signal register. Initially, the value of the normal signal register is 0. Upon receiving a normal signal from the previous AFE chip, the AFE chip sets the value of the normal signal register to 1. When a fault occurs, the microcontroller unit 101 reads the value of the normal signal register of each AFE chip and, combined with the values ​​of other registers, determines the fault type. If the fault is a single-point disconnection, this register can also be used to determine the location of the single-point disconnection fault.

[0035] According to one embodiment, the AFE chip may further include an exception signal register. Initially, the value of the exception signal register is 0. When the AFE chip receives an exception signal from the previous AFE chip, it sets the value of the exception signal register to 1. When a fault occurs, the microcontroller unit 101 reads the value of the exception signal register of each AFE chip and determines the type of fault in combination with the values ​​of other registers. If the fault type is a single-point disconnection fault, it can also be used to determine the location where the single-point disconnection fault occurred. According to one embodiment, the AFE chip may further include a period register. The value of this register is the period for the AFE chip to perform autonomous diagnosis. The period for the AFE chip to perform autonomous diagnosis can be changed by setting the value of this register.

[0036] According to one embodiment, the AFE chip may further include a direction register configured to control the direction of status signal propagation in sleep mode. When the value of the direction register is 1, the AFE chip transmits status signals from the L interface and receives status signals from the H interface. When the value of the direction register is 0, the AFE chip transmits status signals from the H interface and receives status signals from the L interface. When a single-point disconnection fault occurs, the entire topology is divided into two sections. In one section, the direction of status signal propagation is opposite to that in a normal state, so the value of the direction register of each AFE chip in this section must be changed.

[0037] According to one embodiment, the AFE chip may further include an address register configured to store an address of the AFE chip.

[0038] According to one embodiment, the AFE chip may further include a wait register configured to control the AFE chip to actively send a status signal to an adjacent AFE chip or wait for a status signal from another chip, based on the direction defined by the direction register. When the wait register value is 1, the AFE chip actively sends a status signal to the adjacent AFE chip without waiting for a status signal from the adjacent AFE chip. When the wait register value is 0, the AFE chip waits for a status signal from the adjacent AFE chip.

[0039] According to one embodiment, the AFE chip may further include a disconnection register. Initially, the disconnection register is set to 0. If an AFE chip receives neither a normal signal nor an abnormal signal within a specified time, and the wait register of that AFE chip is set to 0, the disconnection register of that AFE chip is set to 1. In this case, the AFE chip also sends an abnormality signal to the next AFE chip.

[0040] According to one embodiment, when a fault occurs, the microcontroller unit 101 reads the value of the disconnection register of each AFE chip and combines it with the values ​​of other registers to determine the type of fault. If the fault type is a single-point disconnection fault, the location of the single-point disconnection fault can also be determined.

[0041] According to one embodiment, the AFE chip may further include a top register configured to indicate whether the AFE chip is at the top of the topology, i.e., the AFE chip with the highest address in the topology. When the value of the top register is 1, the AFE chip is at the top of the topology. When the value of the top register is 0, the AFE chip is not at the top of the topology.

[0042] According to one embodiment, the working state of the battery management system when there is no fault is as follows Figure 1 As shown. At this point, AFE chips 103 through 109, along with bridge chip 102, form a head-to-tail topology. The direction register values ​​for AFE chips 103 through 109 are all 0, sending status signals from the H interface and receiving them from the L interface. Because bridge chip 102 is in shutdown mode, the wait register value for AFE chip 103 is 1, meaning AFE chip 103 does not need to wait for status signals from adjacent chips. AFE chip 109 is at the top of the topology, so its top register value is 1. Status signals are transmitted in the direction shown.

[0043] Figure 2This is a schematic diagram of the state of a battery management system after a single-point disconnection fault occurs according to an embodiment of the present application.

[0044] According to one embodiment, Figure 2 In the working state shown, the battery management system is in a low power consumption mode, which means that the microcontroller unit 201 is in a shutdown mode, all AFE chips are in a sleep mode, and the bridge chip 202 is in a shutdown mode or a sleep mode.

[0045] According to one embodiment, after a single point failure occurs in the battery management system, the configuration method proposed in this application can enable the battery management system to still perform autonomous periodic diagnosis in low power consumption mode. Figure 2 shown.

[0046] According to one embodiment, Figure 2 Taking a battery management system including 7 AFE chips as an example, the battery management system may also include other numbers of AFE chips.

[0047] According to one embodiment, Figure 2 Take for example a single-point disconnection fault between the AFE chip 206 and the AFE chip 207. Of course, the single-point disconnection fault in the battery management system may also occur at other locations.

[0048] According to one embodiment, Figure 2 As shown, when a single-point disconnection fault occurs between AFE chip 206 and AFE chip 207, the original complete topology is divided into two parts, namely the first topology connecting AFE chip 203 to AFE chip 206 and the second topology connecting AFE chip 207 to AFE chip 209.

[0049] According to one embodiment, because the original complete topology is divided into two parts, the address registers of each AFE chip are modified. In the first topology, the address register value of AFE chip 203 is 001, the address register value of AFE chip 204 is 010, the address register value of AFE chip 205 is 011, and the address register value of AFE chip 206 is 100. In the second topology, the address register value of AFE chip 209 is 001, the address register value of AFE chip 208 is 010, and the address register value of AFE chip 207 is 011.

[0050] According to one embodiment, because the line between AFE chip 206 and AFE chip 207 is disconnected, AFE chip 206 becomes the endpoint for transmitting the first topology status signal, and the value of its wait register is 1. AFE chip 207 becomes the endpoint for transmitting the second topology status signal, and the value of its wait register is 1. The values ​​of the wait registers of the remaining AFE chips are 0.

[0051] According to one embodiment, AFE chip 206 is at the top of the first topology, and the value of its top register is 1. AFE chip 207 is at the top of the second topology, and the value of its top register is 1. The values ​​of the top registers of the remaining AFE chips are 0.

[0052] According to one embodiment, in a first topology, the status signal is transmitted from AFE chip 206 to AFE chip 203, so the values ​​of the direction registers of AFE chips 203, 204, 205, and 206 in the first topology are 1. According to one embodiment, in a second topology, the status signal is transmitted from AFE chip 207 to AFE chip 209, so the values ​​of the direction registers of AFE chips 207, 208, and 209 in the second topology are 0.

[0053] According to one embodiment, after a single-point disconnect fault occurs in the battery management system and configuration is performed, the transmission direction of the status signal in the first and second topologies is as described above. Therefore, in the first topology, the previous AFE chip refers to the AFE chip closer to AFE chip 206 in the status signal transmission direction, and the next AFE chip refers to the AFE chip farther away from AFE chip 206 in the status signal transmission direction. For example, the previous AFE chip of AFE chip 205 is AFE chip 206, and the next AFE chip is AFE chip 204. In the second topology, the previous AFE chip refers to the AFE chip closer to AFE chip 207 in the status signal transmission direction, and the next AFE chip refers to the AFE chip farther away from AFE chip 207 in the status signal transmission direction. For example, the previous AFE chip of AFE chip 208 is AFE chip 207, and the next AFE chip is AFE chip 209.

[0054] According to one embodiment, Figure 2 As shown, after the line between AFE chip 206 and AFE chip 207 is disconnected, the battery management system can still perform regular autonomous diagnosis in low power mode. This autonomous diagnosis is actively initiated by the AFE chip, and the status signal is Figure 2The direction of transmission shown does not require the participation of the microcontroller unit 201. Therefore, the entire battery management system can continue to maintain normal use without the need for maintenance when a single-point disconnection fault occurs.

[0055] Figure 3 This is a schematic diagram of an unconfigured state after a single-point disconnection fault occurs in a battery management system according to an embodiment of the present application.

[0056] According to one embodiment, Figure 3 Taking a battery management system including 7 AFE chips as an example, the battery management system may also include other numbers of AFE chips.

[0057] According to one embodiment, Figure 3 Taking a single-point disconnection fault between the AFE chip 306 and the AFE chip 307 as an example, the single-point disconnection fault in the battery management system may also be located at other locations.

[0058] According to one embodiment, Figure 3 As shown, when a single-point disconnection occurs between AFE chip 306 and AFE chip 307, AFE chip 307 receives neither a normal signal nor an abnormal signal. At this time, the value of AFE chip 307's wait register is 0, so the value of AFE chip 307's disconnection register is set to 1. Furthermore, AFE chip 307 sends an abnormality signal to AFE chip 308. Upon receiving the abnormality signal, AFE chip 308 sets the value of its own abnormality signal register to 1 and sends the abnormality signal to AFE chip 309. Upon receiving the abnormality signal, AFE chip 309 sets the value of its own abnormality signal register to 1 and sends the abnormality signal to bridge chip 302. Therefore, when a single-point disconnection occurs between AFE chip 306 and AFE chip 307, the value of AFE chip 307's disconnection register is 1, and the values ​​of the abnormality signal registers of AFE chip 308 and AFE chip 309 are 1.

[0059] Figure 4 This is a configuration flow chart after a single point disconnection fault according to an embodiment of the present application.

[0060] Step 401: The bridge chip 302 receives an abnormal signal and wakes up the microcontroller unit 301 in reverse via the power control pin.

[0061] Step 402: Wake up all AFE chips. Set the values ​​of the interface registers of the bridge chip 302 to 0 and 1 respectively and send corresponding commands to wake up all AFE chips.

[0062] Step 403: Determine the type of fault. The microcontroller unit 301 reads the values ​​of the normal signal register, abnormal signal register, and disconnection register of each AFE chip, and determines the type of fault based on the read values.

[0063] When the values ​​of the disconnection registers of all AFE chips are 0, the fault type is determined to be an AFE chip fault.

[0064] When the value of the disconnection register of only one AFE chip is 1, for example, the value of the disconnection register of the AFE chip 307 is 1, it is necessary to further determine the status of the AFE chip 306 .

[0065] According to one embodiment, the AFE chip may be unable to even send an abnormal signal due to a Type II fault. In this case, it is necessary to determine whether the AFE chip 306 has a Type II fault. If not, the fault type is determined to be a single-point disconnection fault. According to one embodiment, any known method can be used to determine whether the AFE chip is unable to send a status signal due to a Type II fault.

[0066] When the value of the disconnection register of two or more AFE chips is 1, the fault type is determined to be a multi-point disconnection fault.

[0067] Step 404: When the fault type is an AFE chip fault, repair is required.

[0068] Step 406: When the fault type is a multi-point disconnection fault, maintenance is required.

[0069] Step 405: If the fault type is a single-point disconnection fault, the location of the single-point disconnection fault is determined, and the topology is divided into two parts. Because the value of the disconnection register of AFE chip 307 is 1, and AFE chip 306 does not have the second type of fault described above, the location of the single-point disconnection fault can be determined to be between AFE chip 306 and AFE chip 307. The first topology is formed from AFE chip 303 to AFE chip 306, and the second topology is formed from AFE chip 307 to AFE chip 309.

[0070] Step 407: Reallocate addresses for all AFE chips. Addresses are reallocated based on the number of AFE chips in the first and second topologies. For example, the address register value of AFE chip 303 is set to 001, the address register value of AFE chip 304 is set to 010, the address register value of AFE chip 305 is set to 011, and the address register value of AFE chip 306 is set to 100. For example, the address register value of AFE chip 309 is set to 001, the address register value of AFE chip 308 is set to 010, and the address register value of AFE chip 307 is set to 011. According to one embodiment, the address reallocation operation for the AFE chips in the two topologies can be performed sequentially based on the value of the bridge chip interface register.

[0071] Step 408: Set the top register and wait register values. Set the top register and wait register values ​​of the two AFE chips adjacent to the location where the single-point disconnection fault occurred to 1, and set the top register and wait register values ​​of the remaining AFE chips to 0. For example, AFE chip 306 becomes the top of the first topology. Furthermore, after entering sleep mode, AFE chip 306 will not wait for status signals from other AFE chips, but will instead actively send its own status signals. Therefore, the value of its wait register is set to 1.

[0072] Step 409: Set the direction register values ​​of all AFE chips in the first topology to 1. Thereafter, each AFE chip in the first topology will send status signals from the L interface and receive status signals from the H interface. For example, AFE chip 306 will send status signals to AFE chip 305 instead of AFE chip 307 if the fault is not present.

[0073] Step 410: The entire system enters a low-power mode. All AFE chips in the first and second topologies are placed in sleep mode and undergo regular self-diagnosis. The bridge chip 302 is placed in sleep mode or shutdown mode, and the microcontroller unit 301 is placed in shutdown mode, causing the entire battery management system to enter a low-power mode again.

[0074] After the above configuration process, the working status of the battery management system is as follows: Figure 2 As shown in the figure, the topology with a single-point disconnection fault is divided into two topologies, namely the first topology and the second topology. AFE chip 206 and AFE chip 207 become the endpoints for status signal transmission. With the above configuration, the battery management system can still perform regular self-diagnosis in low-power mode. Users can continue to use the battery normally without repair, or ensure that the battery status can still be continuously monitored during repair.

[0075] According to one embodiment, reference Figure 1 The battery management system can set an autonomous wake-up time based on the microcontroller's low-power strategy. After autonomous wake-up, the microcontroller wakes up the bridge chip 102 and all AFE chips and sends commands to determine whether the connection between the bridge chip and AFE chip 109 is normal. If a disconnection is detected between the AFE chip 109 and the bridge chip, the microcontroller configures the register values ​​of each AFE chip to enable the AFE chip 109 to actively transmit its status signal. This status signal is then transmitted from AFE chip 109 to AFE chip 103. AFE chip 103 then sends the status signal to the bridge chip 102.

[0076] According to one embodiment, reference Figure 1 When a single-point disconnection occurs between the AFE chip 103 and the bridge chip 102, the bridge chip 102 can still receive status signals from the AFE chip 109. Therefore, a single-point disconnection between the AFE chip 103 and the bridge chip 102 will not affect the autonomous diagnosis of the entire battery management system.

[0077] The above method is only one embodiment of the present application, and the step numbers do not limit the order in which the operations are performed. Based on the content disclosed in this application, methods that adjust the execution order of different operations still fall within the scope of this application.

[0078] The present application also provides an electronic device, comprising the above-mentioned battery management system.

[0079] In low-power application scenarios (such as new energy vehicles and energy storage devices), the battery management system is often in low-power mode to reduce energy consumption. However, during the low-power mode, the battery may enter an abnormal state due to self-discharge, ambient temperature changes, or internal short circuits. If the microcontroller unit cannot be awakened in time for intervention, irreversible damage or safety accidents will occur. In addition, the AFE chip itself may experience hardware aging or transient faults (such as register flips and clock drift) due to long-term operation, and regular diagnosis is required to ensure its functional integrity. The method, AFE chip, battery management system, and electronic device proposed in this application can still perform regular self-diagnosis in low-power mode after a single-point disconnection fault occurs, and can wake up the microcontroller unit in time to handle new faults.

[0080] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A method for troubleshooting a battery management system, wherein the battery management system comprises a topology of multiple AFE chips electrically connected end to end via a bridge chip, and a microcontroller unit electrically connected to the bridge chip, characterized in that: The method includes: when the microcontroller unit in the battery management system is in shutdown mode, the bridge chip is in sleep mode or shutdown mode, and the multiple AFE chips are in sleep mode, When the bridge chip receives an abnormal signal from the last AFE chip in the topology structure, it wakes up the microcontroller unit; The bridge chip sends a wake-up command to the AFE chip in the topology; Each AFE chip in the topology is configured to detect its own status and generate its own status signal in combination with the status signal received from the previous AFE chip and send it to the next AFE chip; When only one AFE chip in the topology structure does not receive a normal signal or an abnormal signal, it is determined that a single-point break occurs between the AFE chip and the AFE chip above it, and the topology structure is divided into a first topology structure and a second topology structure by the single-point break; According to the number of AFE chips in the first topology and the second topology and the location of each AFE chip, the address of each AFE chip, the status signal transmission direction, and whether it is necessary to wait for the status signal of other AFE chips to generate its own status signal are re-determined.

2. The battery management system fault handling method according to claim 1, characterized in that: When the AFE chip itself has no faults and receives a normal signal from the previous AFE chip, it sends a normal signal to the next AFE chip; When the AFE chip itself has no faults and receives an abnormal signal from the previous AFE chip, it sends the abnormal signal to the next AFE chip; When the AFE chip itself has a fault and receives a normal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip; When the AFE chip itself has a fault and receives an abnormal signal from the previous AFE chip, it sends the abnormal signal to the next AFE chip; When the AFE chip does not receive a normal signal or an abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip.

3. The battery management system fault handling method according to claim 1, characterized in that: When all other AFE chips in the topology structure, except for the AFE chip that does not need to wait for status signals from other AFE chips, receive status signals from the previous AFE chip, it is determined that there is no disconnection fault in the topology structure, but a first type of fault occurs in the AFE chip.

4. The battery management system fault handling method according to claim 1, characterized in that: When two or more AFE chips in the topology structure do not receive normal signals or abnormal signals, it is determined that a multi-point disconnection fault occurs in the topology structure.

5. The battery management system fault handling method according to claim 1, characterized in that: When only one AFE chip in the topology does not receive a normal signal or an abnormal signal, the status of the previous AFE chip is detected to confirm whether the previous AFE chip itself has a second type of fault and therefore fails to send a status signal.

6. An AFE chip, characterized in that: include: The normal signal register is configured to set the stored value to be valid when receiving the normal signal from the previous AFE chip; The abnormal signal register is configured to set the stored value to be valid when receiving the abnormal signal from the previous AFE chip; A direction register, in which the stored value represents the direction of propagation of the status signal; A wait register, wherein the value stored therein represents whether the AFE chip needs to wait for the status signal sent by the previous AFE chip to generate the status signal of the AFE chip; The disconnection register is configured so that when the status signal sent by the previous AFE chip is not received within a specified time, the stored value is set to be valid.

7. The AFE chip according to claim 6, wherein: The device also includes an address register configured to store the address of the AFE chip.

8. The AFE chip according to claim 6, wherein: The top register is further included and is configured to mark whether the AFE chip is at the top of the topology in which it is located.

9. A battery management system, characterized in that: The battery management system comprises a topology structure of multiple AFE chips electrically connected end to end via a bridge chip, and a microcontroller unit electrically connected to the bridge chip. The structure is characterized in that when the microcontroller unit in the battery management system is in shutdown mode, the bridge chip is in sleep mode or shutdown mode, and the multiple AFE chips are in sleep mode, The bridge chip is configured to receive a status signal from the last AFE chip in the topology structure, and when the status signal is an abnormal signal, the bridge chip is configured to wake up the microcontroller unit; and is configured to send wake-up commands to the AFE chips in the topology structure in two directions respectively; Each AFE chip in the topology is configured to detect its own state and receive a state signal from the previous AFE chip to generate its own state signal and send it to the next AFE chip; The microcontroller unit is configured to read the register value of each AFE chip in the topology structure to determine whether a single-point break occurs between the AFE chip and the AFE chip above it; when a single-point break occurs, the microcontroller unit is configured to divide the topology structure into a first topology structure and a second topology structure by the single-point break, and reset the register values ​​of the AFE chips in the first topology structure and the second topology structure.

10. The battery management system according to claim 9, characterized in that: The AFE chip includes: The normal signal register is configured to set the stored value to be valid when receiving the normal signal from the previous AFE chip; The abnormal signal register is configured to set the stored value thereof to be valid when receiving an abnormal signal from the previous AFE chip; A direction register, in which the stored value represents the direction of propagation of the status signal; A wait register, wherein the value stored therein represents whether the AFE chip needs to wait for the status signal sent by the previous AFE chip to generate the status signal of the AFE chip; The disconnection register is configured so that when the status signal sent by the previous AFE chip is not received within a specified time, the stored value is set to be valid.

11. The battery management system according to claim 10, characterized in that: The microcontroller unit reads the values ​​of the normal signal register, the abnormal signal register, and the disconnection register of each AFE chip in the topology structure to determine whether a single point disconnection occurs.

12. The battery management system according to claim 10, characterized in that: The microcontroller unit resets the values ​​of the direction register and the wait register of the AFE chips in the first topology structure and the second topology structure.

13. An electronic device, characterized in that: Comprising a battery management system as described in any one of claims 9 to 12.

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