Driving circuit for current regulation and control and negative voltage charge pump circuit

Abstract

The invention belongs to the technical field of electronic circuits, and provides a driving circuit for current regulation and control and a negative voltage charge pump circuit. The driving circuit comprises a soft start module, a control module, a driving module and a current mirror module. The control module is respectively connected with the soft start module, the driving module and a source electrode of a fourth power tube in the charge pump circuit, and the current mirror module is respectively connected with the soft start module and the driving module. The driving module is used for being connected with a grid electrode of a first power tube, a grid electrode of a second power tube, a grid electrode of a third power tube and a grid electrode of a fourth power tube in the charge pump circuit. The driving circuit provided by the invention can ensure that the current flowing through the third power tube in the initial stage of soft start is relatively small, so that the safety of the charge pump circuit is ensured; the current flowing through the third power tube is gradually increased, so that the output voltage of the charge pump circuit can be ensured to reach the target voltage after the soft start is finished, and the charge pump circuit can work normally.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuit technology, and in particular relates to a drive circuit and a negative voltage charge pump circuit for current regulation. Background Art

[0002] In today's information age, with the rapid development of LCD (Liquid Crystal Display) technology, LCD screens have become widely used in various electronic devices. In the LCD drive system, gate switching control requires VGH (high) and VGL (low) voltage signals, necessitating both positive and negative power supplies. Negative charge pumps, a common method for generating negative power, play a key role in LCD drive systems.

[0003] However, during the soft start process of the negative charge pump, when the negative charge pump operates in the second phase, the drain voltage of the NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) power tube will change (from large to small). In some processes, the linearity of the NMOS power tube is poor, causing the current flowing through the NMOS power tube to change (also from large to small) when the drain voltage changes. This can easily cause the negative charge pump to malfunction and pose safety issues. Summary of the Invention

[0004] The embodiments of the present application provide a driving circuit and a negative voltage charge pump circuit for current regulation, which can solve the problem that during the soft start process of the current negative voltage charge pump, when the negative voltage charge pump operates in the second phase, the drain voltage of the NMOS power tube changes (from large to small). In some processes, the linearity of the NMOS power tube is poor, so that when the drain voltage changes, the current flowing through the NMOS power tube also changes (also from large to small), which can easily cause the negative voltage charge pump to malfunction and pose safety issues.

[0005] In a first aspect, an embodiment of the present application provides a current-regulated drive circuit, comprising a soft-start module, a control module, a drive module, and a current mirror module; the control module is respectively connected to the soft-start module, the drive module, and the source of a fourth power tube in a charge pump circuit; the current mirror module is respectively connected to the soft-start module and the drive module; and the drive module is respectively configured to be connected to the gate of a first power tube, the gate of a second power tube, the gate of a third power tube, and the gate of a fourth power tube in the charge pump circuit; The soft start module is used to output a reference voltage, a first signal and n control signals; when the first signal is at a low level, the current mirror module is used to output a first current with a step-changing pattern according to the first signal and the n control signals, and at the same time output a second current according to the first signal; the control module is used to output a second signal according to the reference voltage and the output voltage of the charge pump circuit; when the second signal is at a high level, the drive module is used to control the first power tube to be disconnected according to the second signal, the first signal and the second current, control the second power tube to be disconnected and control the fourth power tube to be turned on according to the second signal, and at the same time control the gate voltage of the third power tube to gradually increase according to the second signal, the first signal and the first current, thereby gradually increasing the current flowing through the third power tube; wherein n is a natural number greater than 0.

[0006] In a possible implementation of the first aspect, when the first signal is at a low level and the second signal is at a low level, the driving module is further used to control the second power tube to be turned on and the fourth power tube to be turned off according to the second signal, control the third power tube to be turned off according to the second signal, the first signal and the first current, and at the same time control the gate voltage of the first power tube according to the second signal, the first signal and the second current to limit the current flowing through the first power tube.

[0007] In a possible implementation of the first aspect, the current mirror module includes a first current source, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, n current mirror branches, and n+1 inverters; the first end of the first current source, the source of the fourth transistor, the source of the sixth transistor, and the first ends of the n current mirror branches all receive a first voltage, the second end of the first current source is respectively connected to the drain of the first transistor, the gate of the first transistor, the gate of the second transistor, and the gate of the fifth transistor, the drain of the second transistor is connected to the source of the third transistor, the drain of the third transistor is connected to the driving module, and the The drain of the fifth transistor is respectively connected to the drain of the fourth transistor, the gate of the fourth transistor, the gate of the sixth transistor, and the second ends of the n current mirror branches; the third ends of the n current mirror branches are correspondingly connected to the output ends of the n inverters; the input ends of the n+1 inverters are respectively connected to the soft start module; the gate of the third transistor is connected to the output end of the (n+1)th inverter; the drain of the sixth transistor and the fourth ends of the n current mirror branches are both connected to the source of the seventh transistor; the gate of the seventh transistor is connected to the soft start module; the drain of the seventh transistor is connected to the driving module; the source of the first transistor, the source of the second transistor, and the source of the fifth transistor are all grounded; The current mirror branch includes two transistors; the source of the first transistor serves as the first end of the current mirror branch, the gate of the first transistor serves as the second end of the current mirror branch, the gate of the second transistor serves as the third end of the current mirror branch, the drain of the second transistor serves as the fourth end of the current mirror branch, and the drain of the first transistor is connected to the source of the second transistor.

[0008] In a possible implementation of the first aspect, the soft start module includes a soft start unit and a logic unit, and the logic unit is connected to the soft start unit, the current mirror module, and the driving module respectively; The soft start unit is used to output a reference voltage and a soft start signal; the logic unit is used to receive a soft start time, divide the soft start time into n time periods according to the soft start signal, and output a first signal and n control signals corresponding to the n time periods.

[0009] In a possible implementation of the first aspect, the driving module includes a clock generation unit, a first driving unit, a second driving unit, a third driving unit, and a fourth driving unit; the clock generation unit is connected to the control module, the first driving unit, the second driving unit, the third driving unit, and the fourth driving unit, respectively; the first driving unit is connected to the soft start module, the current mirror module, and the gate of the first power tube, respectively; the second driving unit is configured to be connected to the gate of the second power tube; the third driving unit is connected to the soft start module, the current mirror module, and the gate of the third power tube, respectively; and the fourth driving unit is configured to be connected to the gate of the fourth power tube; The clock generating unit is used to output a third signal and a fourth signal according to the clock signal and the second signal; when the first signal is at a low level and the second signal is at a high level, the first driving unit is used to control the first power tube to be disconnected according to the third signal, the first signal and the second current; the second driving unit is used to control the second power tube to be disconnected according to the third signal; the third driving unit is used to control the gate voltage of the third power tube to gradually increase according to the fourth signal, the first signal and the first current, thereby gradually increasing the current flowing through the third power tube; the fourth driving unit is used to control the fourth power tube to be turned on according to the fourth signal.

[0010] In a possible implementation of the first aspect, the third driving unit includes a NAND gate, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a first resistor; the first input terminal of the NAND gate is connected to the soft start module, the output terminal of the NAND gate is connected to the gate of the twentieth transistor, the source of the eighth transistor, the source of the tenth transistor, the source of the twelfth transistor, the source of the seventeenth transistor, and the source of the twentieth transistor all receive a second voltage, the gate of the eighth transistor is respectively connected to the clock generation unit, the gate of the ninth transistor, and the second input terminal of the NAND gate, the drain of the eighth transistor is respectively connected to the drain of the ninth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor, the drain of the tenth transistor is respectively connected to the drain of the eleventh transistor, the drain of the tenth transistor is respectively connected to the drain of the ten ... The gate of the second transistor is connected to the gate of the thirteenth transistor, the drain of the twelfth transistor is respectively connected to the drain of the thirteenth transistor, the gate of the seventeenth transistor and the gate of the nineteenth transistor, the drain of the seventeenth transistor is respectively connected to the drain of the eighteenth transistor, the source of the eighteenth transistor is respectively connected to the drain of the nineteenth transistor, the first end of the first resistor, the drain of the twentieth transistor and the gate of the third power tube, the gate of the eighteenth transistor is respectively connected to the drain of the fourteenth transistor, the gate of the fourteenth transistor and the current mirror module, the source of the fourteenth transistor is respectively connected to the drain of the fifteenth transistor, the gate of the fifteenth transistor and the gate of the sixteenth transistor, the source of the fifteenth transistor is connected to the drain of the sixteenth transistor, the source of the ninth transistor, the source of the eleventh transistor, the source of the thirteenth transistor, the source of the sixteenth transistor, the source of the nineteenth transistor and the second end of the first resistor are all grounded.

[0011] In a possible implementation of the first aspect, the first driving unit includes a first inverter, an AND gate, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, a thirty-first transistor, a thirty-second transistor, a thirty-third transistor, and a second resistor; the input end of the first inverter is respectively connected to the clock generating unit, the gate of the twenty-first transistor, and the gate of the twenty-second transistor, the output end of the first inverter is connected to the first input end of the AND gate, the second input end of the AND gate is connected to the soft start module, the output end of the AND gate is connected to the gate of the thirty-third transistor, the source of the twenty-first transistor, the source of the twenty-third transistor, the source of the twenty-fifth transistor, the source of the twenty-seventh transistor, the source of the thirtieth transistor, and the first end of the second resistor all receive an input voltage, the drain of the twenty-first transistor is respectively connected to the drain of the twenty-second transistor, the gate of the twenty-third transistor, and the gate of the twenty-fourth transistor. The drain of the twenty-third transistor is respectively connected to the drain of the twenty-fourth transistor, the gate of the twenty-fifth transistor and the gate of the twenty-sixth transistor, the drain of the twenty-fifth transistor is respectively connected to the drain of the twenty-sixth transistor, the gate of the 30th transistor and the gate of the thirty-second transistor, the drain of the 30th transistor is respectively connected to the source of the thirty-first transistor, the second end of the second resistor, the drain of the thirty-third transistor and the gate of the first power transistor, the drain of the thirty-first transistor is respectively connected to the drain of the thirty-second transistor, the gate of the thirty-first transistor is respectively connected to the gate of the twenty-ninth transistor, the drain of the twenty-ninth transistor and the current mirror module, the source of the twenty-ninth transistor is respectively connected to the drain of the twenty-eighth transistor, the gate of the twenty-eighth transistor and the gate of the twenty-seventh transistor, the source of the twenty-eighth transistor is connected to the drain of the twenty-seventh transistor, the source of the twenty-second transistor, the source of the twenty-fourth transistor, the source of the twenty-sixth transistor, the source of the thirty-second transistor and the source of the thirty-third transistor are all grounded.

[0012] In a possible implementation of the first aspect, the driving circuit further includes a power supply module, which is connected to the driving module and the control module respectively; When the second signal is at a high level, the power supply module is used to output a second voltage to the driving module according to the second signal; when the first signal is at a high level and the charge pump circuit is in a light-load state, the current mirror module is also used to stop outputting the first current and the second current; the driving module is also used to control the gate voltage of the third power tube according to the second signal, the first signal and the second voltage to limit the current flowing through the third power tube.

[0013] In a possible implementation of the first aspect, the power supply module includes a second inverter, a second current source, a third current source, a first capacitor and a thirty-fourth transistor; the input end of the second inverter is respectively connected to the control module, the driving module and the control end of the third current source, the output end of the second inverter is connected to the control end of the second current source, the first end of the second current source and the drain of the thirty-fourth transistor both receive a first voltage, the second end of the second current source is respectively connected to the first end of the third current source, the first end of the first capacitor and the gate of the thirty-fourth transistor, the second end of the third current source and the second end of the first capacitor are both grounded, and the source of the thirty-fourth transistor is connected to the driving module.

[0014] In a second aspect, an embodiment of the present application provides a negative voltage charge pump circuit, comprising the driving circuit described in any one of the first aspects.

[0015] In a third aspect, an embodiment of the present application provides a driving system comprising the negative voltage charge pump circuit described in any one of the second aspects.

[0016] In a fourth aspect, an embodiment of the present application provides a display screen comprising the driving system described in any one of the third aspects.

[0017] Compared with the prior art, the embodiments of the present application have the following beneficial effects: An embodiment of the present application provides a driving circuit for current regulation, including a soft start module, a control module, a driving module and a current mirror module; the control module is respectively connected to the soft start module, the driving module and the source of the fourth power tube in the charge pump circuit, the current mirror module is respectively connected to the soft start module and the driving module, and the driving module is respectively used to be connected to the gate of the first power tube, the gate of the second power tube, the gate of the third power tube and the gate of the fourth power tube in the charge pump circuit.

[0018] The soft-start module is configured to output a reference voltage, a first signal, and n control signals. When the first signal is at a low level, the charge pump circuit is in the soft-start phase. During this phase, the current mirror module is configured to output a first current in a step-wise manner based on the first signal and the n control signals, while also outputting a second current based on the first signal. The control module is configured to output a second signal based on the reference voltage and the output voltage of the charge pump circuit. When the second signal is at a high level, it indicates that the charge pump circuit is operating in the second phase. Specifically, during the soft-start process of the charge pump circuit, when the charge pump circuit is operating in the second phase, the driver module is configured to control the first power transistor to be disconnected based on the second signal, the first signal, and the second current; control the second power transistor to be disconnected and the fourth power transistor to be connected based on the second signal; and control the gate voltage of the third power transistor to gradually increase based on the second signal, the first signal, and the first current, thereby gradually increasing the current flowing through the third power transistor. n is a natural number greater than 0. In this way, the current flowing through the third power tube can be kept small in the initial stage of soft start, thereby ensuring the safety of the charge pump circuit. Since the current flowing through the third power tube will gradually increase, the output voltage of the charge pump circuit can be guaranteed to reach the target voltage after the soft start is completed, so that the charge pump circuit can operate normally.

[0019] In summary, the driving circuit provided in the embodiment of the present application can solve the problem that during the soft start process of the current negative pressure charge pump, when the negative pressure charge pump operates in the second phase, the drain voltage of the NMOS power tube will change (from large to small), and in some processes, the linearity of the NMOS power tube is poor, so that when the drain voltage changes, the current flowing through the NMOS power tube also changes (also from large to small), which can easily cause the negative pressure charge pump to malfunction and pose a safety problem.

[0020] It can be understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 is a circuit schematic diagram of an existing charge pump circuit; Figure 2 This is a principle block diagram of a driving circuit provided in one embodiment of the present application; Figure 3 is a principle block diagram of a driving circuit provided in another embodiment of the present application; Figure 4 This is the circuit connection diagram of the current mirror module; Figure 5 is a circuit connection diagram of the third drive unit; Figure 6 is a circuit diagram of the first driving unit; Figure 7 is a principle block diagram of a driving circuit provided in another embodiment of the present application; Figure 8 This is the circuit connection diagram of the power module; Figure 9 This is a circuit connection diagram of the control module.

[0023] In the figure: 1. Charge pump circuit; 2. Drive circuit; 20. Soft start module; 21. Soft start unit; 22. Logic unit; 30. Control module; 40. Drive module; 41. Clock generation unit; 42. First drive unit; 43. Second drive unit; 44. Third drive unit; 45. Fourth drive unit; 50. Current mirror module; 51. Current mirror branch; 60. Power supply module. DETAILED DESCRIPTION

[0024] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0025] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0026] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0027] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0028] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0029] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0030] Figure 1 FIG. 1 shows a circuit schematic diagram of an existing charge pump circuit 1, as shown in FIG. Figure 1 As shown, the charge pump circuit 1 primarily includes a first power transistor M1, a second power transistor M2, a third power transistor M3, a fourth power transistor M4, a flying capacitor CFLY, and an output capacitor COUT. The charge pump circuit 1 operates in two phases: the first phase and the second phase. The first power transistor M1 and the second power transistor M2 are controlled by the first phase, while the third power transistor M3 and the fourth power transistor M4 are controlled by the second phase. During the first phase, the first power transistor M1 and the second power transistor M2 are turned on, while the third power transistor M3 and the fourth power transistor M4 are turned off. The flying capacitor CFLY is charged by the input voltage Vin. During the second phase, the first power transistor M1 and the second power transistor M2 are turned off, while the third power transistor M3 and the fourth power transistor M4 are turned on. The flying capacitor CFLY is connected to the output capacitor COUT via the fourth power transistor M4. Charge is transferred from the flying capacitor CFLY to the output capacitor COUT, resulting in an output voltage Vneg, which is a negative voltage.

[0031] However, during the soft-start process of the charge pump circuit 1, when the charge pump circuit 1 operates in the second phase, the drain voltage of the third power transistor M3 gradually decreases. While the current of an ideal MOS transistor in the saturation region varies little with the drain-source voltage, in some processes, the linearity of an NMOS power transistor is poor. That is, at the same gate-source voltage, the current in the saturation region varies significantly with the drain-source voltage. Therefore, when the drain voltage of the third power transistor M3 changes (from high to low), the current flowing through the third power transistor M3 also changes (also from high to low). If the current flowing through the third power transistor M3 is not regulated, the current flowing through the NMOS power transistor in the initial soft-start phase will be excessive, resulting in safety issues for the charge pump circuit 1. If a fixed current limit is used, the output voltage of the charge pump circuit 1 will not reach the target voltage after the soft-start ends, ultimately causing the charge pump circuit 1 to malfunction.

[0032] In order to solve the above problems, the present invention provides a driving circuit for current control. Figure 2 As shown, the driving circuit 2 includes a soft start module 20, a control module 30, a driving module 40 and a current mirror module 50; the control module 30 is respectively connected to the soft start module 20, the driving module 40 and the source of the fourth power tube M4 in the charge pump circuit 1, the current mirror module 50 is respectively connected to the soft start module 20 and the driving module 40, and the driving module 40 is respectively used to be connected to the gate of the first power tube M1, the gate of the second power tube M2, the gate of the third power tube M3 and the gate of the fourth power tube M4 in the charge pump circuit 1.

[0033] Specifically, the soft-start module 20 is configured to output a reference voltage Vref, a first signal SS_END, and n control signals SS1, SS2, ..., SSn. When the first signal is at a low level, the charge pump circuit 1 is in the soft-start phase. During the soft-start phase, the reference voltage Vref gradually increases. During this phase, the current mirror module 50 is configured to output a first current IN in a step-wise manner based on the first signal SS_END and the n control signals SS1, SS2, ..., SSn, and simultaneously output a second current IP based on the first signal SS_END. The control module 30 is configured to output a second signal D based on the reference voltage Vref and the output voltage Vneg of the charge pump circuit 1. When the second signal D is at a high level, it indicates that the charge pump circuit 1 is operating in the second phase. That is, during the soft-start process of the charge pump circuit 1, when the charge pump circuit 1 operates in the second phase, the driver module 40 is configured to control the first power transistor M1 to be off based on the second signal D, the first signal SS_END, and the second current IP; control the second power transistor M2 to be off and the fourth power transistor M4 to be on based on the second signal D; and simultaneously control the gate voltage of the third power transistor M3 to gradually increase based on the second signal D, the first signal SS_END, and the first current IN, thereby gradually increasing the current flowing through the third power transistor M3. Where n is a natural number greater than 0. This ensures that the current flowing through the third power transistor M3 is relatively low during the initial soft-start phase, thereby ensuring the safety of the charge pump circuit 1. Since the current flowing through the third power transistor M3 gradually increases, after the soft-start phase ends, the output voltage Vneg of the charge pump circuit 1 is guaranteed to reach the target voltage, ensuring normal operation of the charge pump circuit 1.

[0034] In summary, the driving circuit 2 provided in the embodiment of the present application can solve the problem that during the soft start process of the current charge pump circuit 1, when the charge pump circuit 1 operates in the second phase, the drain voltage of the third power tube M3 changes (from large to small). In some processes, the linearity of the third power tube M3 is poor, so that when the drain voltage changes, the current flowing through the third power tube M3 also changes (also from large to small), which can easily cause the negative pressure charge pump to malfunction and pose a safety problem.

[0035] It should be noted that when the first signal SS_END becomes high, it indicates that the soft start of the charge pump circuit 1 ends. At this time, the current mirror module 50 stops outputting the first current IN and the second current IP, that is, no current regulation is required.

[0036] In some embodiments, during the soft start process of the charge pump circuit 1, when the charge pump circuit 1 operates in the first phase, the drain-source voltage VDS of the first power tube M1 is M1The change is small, so only basic current limiting is required for the current flowing through the first power transistor M1, without the need for segmented control. The second current IP provided by the current mirror module 50 is the current limiting current for the first power transistor M1. Specifically, when the first signal SS_END is at a low level and the second signal D is at a low level, the charge pump circuit 1 is in the soft start phase and is operating in the first phase. In this state, the driver module 40 is further configured to control the second power transistor M2 to be conductive and the fourth power transistor M4 to be disconnected based on the second signal D; control the third power transistor M3 to be disconnected based on the second signal D, the first signal SS_END, and the first current IN; and control the gate voltage of the first power transistor M1 based on the second signal D, the first signal SS_END, and the second current IP to limit the current flowing through the first power transistor M1.

[0037] In some embodiments, as Figure 3 As shown, the soft start module 20 includes a soft start unit 21 and a logic unit 22 , and the logic unit 22 is connected to the soft start unit 21 , the current mirror module 50 and the driving module 40 respectively.

[0038] Specifically, the soft-start unit 21 is configured to output a reference voltage Vref and a soft-start signal SS. The logic unit 22 is configured to receive a soft-start time TS, divide the soft-start time TS into n time periods based on the soft-start signal SS, and output a first signal SS_END and n control signals SS1, SS2, ..., SSn corresponding to the n time periods. It should be noted that the soft-start time TS is provided by the digital module, and this application does not protect the digital module; it only performs operations based on the soft-start time TS output by the digital module.

[0039] In some embodiments, as Figure 3 As shown, the driving module 40 includes a clock generating unit 41, a first driving unit 42, a second driving unit 43, a third driving unit 44 and a fourth driving unit 45; the clock generating unit 41 is respectively connected to the control module 30, the first driving unit 42, the second driving unit 43, the third driving unit 44 and the fourth driving unit 45, the first driving unit 42 is respectively connected to the soft start module 20, the current mirror module 50 and the gate of the first power tube M1, the second driving unit 43 is used to be connected to the gate of the second power tube M2, the third driving unit 44 is respectively connected to the soft start module 20, the current mirror module 50 and the gate of the third power tube M3, and the fourth driving unit 45 is used to be connected to the gate of the fourth power tube M4.

[0040] Specifically, the clock generation unit 41 is configured to output a third signal A1 and a fourth signal B1 based on the clock signal CLK and the second signal D. When the first signal SS_END is low and the second signal D is high, the charge pump circuit 1 is in the soft start phase and operating in the second phase. At this time, the third signal A1 and the fourth signal B1 are both high. In this state, the first drive unit 42 is configured to control the first power transistor M1 to be turned off based on the third signal A1, the first signal SS_END, and the second current IP. The second drive unit 43 is configured to control the second power transistor M2 to be turned off based on the third signal A1. The third drive unit 44 is configured to control the gate voltage of the third power transistor M3 to gradually increase based on the fourth signal B1, the first signal SS_END, and the first current IN, thereby gradually increasing the current flowing through the third power transistor M3. The fourth drive unit 45 is configured to control the fourth power transistor M4 to be turned on based on the fourth signal B1. In the present application, during the soft-start process of the charge pump circuit 1, the current mirror module 50 outputs a first current IN with a step-wise change, and the third driving unit 44 controls the current flowing through the third power tube M3 to gradually increase. This solves the problem caused by the poor linearity of the third power tube M3 under certain processes, and ensures that the current flowing through the third power tube M3 is relatively small in the initial stage of the soft-start, thereby ensuring the safety of the charge pump circuit 1. Since the current flowing through the third power tube M3 gradually increases, after the soft-start ends, the output voltage Vneg of the charge pump circuit 1 can be guaranteed to reach the target voltage, so that the charge pump circuit 1 can operate normally.

[0041] In some embodiments, as Figure 4As shown, the current mirror module 50 includes a first current source I1, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, n current mirror branches 51 and n+1 inverters INV; a first end of the first current source I1, a source of the fourth transistor Q4, a source of the sixth transistor Q6 and a first end of the n current mirror branches 51 all receive a first voltage VDD, a second end of the first current source I1 is respectively connected to the drain of the first transistor Q1, the gate of the first transistor Q1, the gate of the second transistor Q2 and the gate of the fifth transistor Q5, the drain of the second transistor Q2 is connected to the source of the third transistor Q3, the drain of the third transistor Q3 is connected to the driving module 40, and the fifth transistor Q5 is connected to the gate of the fifth transistor Q5. The drain of the transistor Q5 is respectively connected to the drain of the fourth transistor Q4, the gate of the fourth transistor Q4, the gate of the sixth transistor Q6, and the second ends of the n current mirror branches 51. The third ends of the n current mirror branches 51 are correspondingly connected to the output ends of the n inverters INV. The input ends of the n+1 inverters INV are respectively connected to the soft start module 20. The gate of the third transistor Q3 is connected to the output end of the (n+1)th inverter INV. The drain of the sixth transistor Q6 and the fourth ends of the n current mirror branches 51 are both connected to the source of the seventh transistor Q7. The gate of the seventh transistor Q7 is connected to the soft start module 20. The drain of the seventh transistor Q7 is connected to the driving module 40. The source of the first transistor Q1, the source of the second transistor Q2, and the source of the fifth transistor Q5 are all grounded. The current mirror branch 51 includes two transistors Qt1 and Qt2; the source of the first transistor Qt1 serves as the first end of the current mirror branch 51, the gate of the first transistor Qt1 serves as the second end of the current mirror branch 51, the gate of the second transistor Qt2 serves as the third end of the current mirror branch 51, and the drain of the second transistor Qt2 serves as the fourth end of the current mirror branch 51. The drain of the first transistor Qt1 is connected to the source of the second transistor Qt2.

[0042] Specifically, the input ends of the first n inverters INV receive n control signals SS1, SS2, ..., SSn respectively, and output n signals SS1B, SS2B, ..., SSnB after being inverted by the inverters INV.

[0043] An input terminal of the (n+1)th inverter INV receives the first signal SS_END, and after being inverted by the inverter INV, outputs a signal SS_ENDB.

[0044] During the soft start process, the first signal SS_END is at a low level, and the signal SS_ENDB is at a high level.

[0045] The first current source I1 provides current to the first transistor Q1, which is then copied to the second transistor Q2 and the fifth transistor Q5. The current flowing through the second transistor Q2 is the second current IP. The fifth transistor Q5 transmits the current to the fourth transistor Q4, which is then copied to the sixth transistor Q6 and the n current mirror branches 51.

[0046] The signal SS_ENDB is at a high level, controlling the third transistor Q3 to be turned on, so as to output the second current IP.

[0047] The first signal SS_END is at a low level, controlling the seventh transistor Q7 to conduct, thereby outputting the first current IN. When the soft start reaches the first time period, the signal SS1 becomes high, and the signal SS1B becomes low, controlling the first current mirror branch 51 to conduct. When the soft start reaches the second time period, the signal SS2 becomes high, and the signal SS2B becomes low, controlling the second current mirror branch 51 to conduct. Similarly, the first current IN increases stepwise over time.

[0048] After the soft start is finished, the first signal SS_END becomes high, controlling the seventh transistor Q7 to be turned off, thereby stopping the output of the first current IN. The signal SS_ENDB becomes low, controlling the third transistor Q3 to be turned off, thereby stopping the output of the second current IP.

[0049] In some embodiments, as Figure 5As shown, the third driving unit 44 includes a NAND gate NAND, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a fourteenth transistor Q14, a fifteenth transistor Q15, a sixteenth transistor Q16, a seventeenth transistor Q17, an eighteenth transistor Q18, a nineteenth transistor Q19, a twentieth transistor Q20 and a first resistor R1; a first input end of the NAND gate NAND is connected to the soft start module 20, and an output end of the NAND gate NAND is connected to the twentieth transistor Q20. The gate of the eighth transistor Q8 is connected to the gate of the ninth transistor Q9, the source of the tenth transistor Q10, the source of the twelfth transistor Q12, the source of the seventeenth transistor Q17 and the source of the twentieth transistor Q20 all receive the second voltage VPP, the gate of the eighth transistor Q8 is connected to the clock generating unit 41, the gate of the ninth transistor Q9 and the second input terminal of the NAND gate respectively, the drain of the eighth transistor Q8 is connected to the drain of the ninth transistor Q9, the gate of the tenth transistor Q10 and the gate of the eleventh transistor Q11 respectively, the drain of the tenth transistor Q10 is connected to the drain of the eleventh transistor Q11 respectively The drain of Q11, the gate of the twelfth transistor Q12 and the gate of the thirteenth transistor Q13 are connected, the drain of the twelfth transistor Q12 is respectively connected to the drain of the thirteenth transistor Q13, the gate of the seventeenth transistor Q17 and the gate of the nineteenth transistor Q19, the drain of the seventeenth transistor Q17 is connected to the drain of the eighteenth transistor Q18, the source of the eighteenth transistor Q18 is respectively connected to the drain of the nineteenth transistor Q19, the first end of the first resistor R1, the drain of the twentieth transistor Q20 and the gate of the third power tube M3, the gate of the eighteenth transistor Q18 is respectively connected The first end of the first resistor R1 is connected to the drain of the fourth transistor Q14, the gate of the fourth transistor Q14 and the current mirror module 50, the source of the fourth transistor Q14 is respectively connected to the drain of the fifteenth transistor Q15, the gate of the fifteenth transistor Q15 and the gate of the sixteenth transistor Q16, the source of the fifteenth transistor Q15 is connected to the drain of the sixteenth transistor Q16, the source of the ninth transistor Q9, the source of the eleventh transistor Q11, the source of the thirteenth transistor Q13, the source of the sixteenth transistor Q16, the source of the nineteenth transistor Q19 and the second end of the first resistor R1 are all grounded.

[0050] Specifically, the eighth transistor Q8, the ninth transistor Q9, the tenth transistor Q10, the eleventh transistor Q11, the twelfth transistor Q12, the thirteenth transistor Q13, the seventeenth transistor Q17, and the nineteenth transistor Q19 constitute a basic driving unit. The fourteenth transistor Q14, the fifteenth transistor Q15, the sixteenth transistor Q16, the eighteenth transistor Q18, and the first resistor R1 constitute a current mirror with resistor negative feedback, which functions to regulate current. By regulating the first current IN, the resistance value of the first resistor R1, the width-to-length ratio of the fourteenth transistor Q14 and the eighteenth transistor Q18, and the width and length of the fifteenth transistor Q15 and the sixteenth transistor Q16, the gate voltage of the third power transistor M3 can be changed.

[0051] During the soft start process, the first signal SS_END is at a low level. No matter whether the fourth signal B1 is at a high level or a low level, the signal SS_END2 output by the NAND gate NAND is always at a high level, and the twentieth transistor Q20 is controlled to be turned off. When the second signal D is at a high level (indicating that the charge pump circuit 1 is operating in the second phase) and the fourth signal B1 is also at a high level, the gate voltage of the third power transistor M3 is controlled by a current mirror with resistor negative feedback. After the resistance value of the first resistor R1 and the aspect ratio of the fourteenth transistor Q14 to the eighteenth transistor Q18 are determined, the gate voltage of the third power transistor M3 is controlled by the first current IN. As the first current IN increases in a step-like manner, the gate voltage of the third power transistor M3 also increases, thereby continuously increasing the current flowing through the third power transistor M3. This solves the problem caused by the poor linearity of the third power transistor M3 under certain processes and ensures that the current flowing through the third power transistor M3 is relatively low during the initial soft-start phase, thereby ensuring the safety of the charge pump circuit 1. Since the current flowing through the third power transistor M3 gradually increases, the output voltage Vneg of the charge pump circuit 1 is guaranteed to reach the target voltage after the soft-start ends, ensuring normal operation of the charge pump circuit 1.

[0052] After the soft start is completed, the first signal SS_END becomes high. When the second signal D is high, the fourth signal B1 is high, and the signal SS_END2 is low, controlling the twentieth transistor Q20 to be turned on, thereby releasing the current control. In this state, the gate voltage of the third power tube M3 is the second voltage VPP.

[0053] In some embodiments, as Figure 6As shown, the first driving unit 42 includes a first inverter INV1, an AND gate AND, a twenty-first transistor Q21, a twenty-second transistor Q22, a twenty-third transistor Q23, a twenty-fourth transistor Q24, a twenty-fifth transistor Q25, a twenty-sixth transistor Q26, a twenty-seventh transistor Q27, a twenty-eighth transistor Q28, a twenty-ninth transistor Q29, a thirtieth transistor Q30, a thirty-first transistor Q31, a thirty-second transistor Q32, a thirty-third transistor Q33 and a second resistor R2; the input end of the first inverter INV1 is connected to the clock generating unit 41, the gate of the twenty-first transistor Q21 and the gate of the twenty-second transistor Q24, respectively. The gate of the 33rd transistor Q33 is connected to the output terminal of the first inverter INV1, the output terminal of the AND gate AND is connected to the first input terminal of the AND gate AND, the second input terminal of the AND gate AND is connected to the soft start module 20, the output terminal of the AND gate AND is connected to the gate of the 33rd transistor Q33, the source of the 21st transistor Q21, the source of the 23rd transistor Q23, the source of the 25th transistor Q25, the source of the 27th transistor Q27, the source of the 30th transistor Q30, and the first end of the second resistor R2 all receive the input voltage VIN, the drain of the 21st transistor Q21 is connected to the drain of the 22nd transistor Q22, the gate of the 23rd transistor Q23, and the gate of the 27th transistor Q27, respectively. The gate of the fourth transistor Q24 is connected, the drain of the twenty-third transistor Q23 is respectively connected to the drain of the twenty-fourth transistor Q24, the gate of the twenty-fifth transistor Q25, and the gate of the twenty-sixth transistor Q26, the drain of the twenty-fifth transistor Q25 is respectively connected to the drain of the twenty-sixth transistor Q26, the gate of the thirtieth transistor Q30, and the gate of the thirty-second transistor Q32, the drain of the thirtieth transistor Q30 is respectively connected to the source of the thirty-first transistor Q31, the second end of the second resistor R2, the drain of the thirty-third transistor Q33, and the gate of the first power transistor M1, the drain of the thirty-first transistor Q31 is respectively connected to the drain of the thirty-second transistor Q32 The drain of the thirty-first transistor Q31 is connected to the gate of the twenty-ninth transistor Q29, the drain of the twenty-ninth transistor Q29 and the current mirror module 50 respectively, the source of the twenty-ninth transistor Q29 is connected to the drain of the twenty-eighth transistor Q28, the gate of the twenty-eighth transistor Q28 and the gate of the twenty-seventh transistor Q27 respectively, the source of the twenty-eighth transistor Q28 is connected to the drain of the twenty-seventh transistor Q27, the source of the twenty-second transistor Q22, the source of the twenty-fourth transistor Q24, the source of the twenty-sixth transistor Q26, the source of the thirty-second transistor Q32 and the source of the thirty-third transistor Q33 are all grounded.

[0054] Specifically, the twenty-first transistor Q21, the twenty-second transistor Q22, the twenty-third transistor Q23, the twenty-fourth transistor Q24, the twenty-fifth transistor Q25, the twenty-sixth transistor Q26, the thirtieth transistor Q30, and the thirty-second transistor Q32 constitute a basic drive unit. The twenty-seventh transistor Q27, the twenty-eighth transistor Q28, the twenty-ninth transistor Q29, the thirty-first transistor Q31, and the second resistor R2 form a current mirror with resistor negative feedback, which provides current limiting. The twenty-seventh transistor Q27 and the second transistor Q28 are diode-connected, while the twenty-ninth transistor Q29 and the thirty-first transistor Q31 are current mirror-connected. By adjusting the second current IP, the resistance value of the second resistor R2, the width-to-length ratio of the twenty-ninth transistor Q29 to the thirty-first transistor Q31, and the width and length of the twenty-seventh transistor Q27 and the twenty-eighth transistor Q28, the gate voltage of the first power transistor M1 can be changed, thereby changing its current limiting value.

[0055] During the soft-start process, when the first signal SS_END is low, the signal SS_END1 is also low, turning off the thirty-third transistor Q33. When the second signal D is low (indicating that the charge pump circuit 1 is operating in the first phase), the third signal A1 is also low. The gate voltage of the first power transistor M1 is controlled by a current mirror with resistor negative feedback. Once the resistance of the second resistor R2 and the aspect ratio of the twenty-ninth transistor Q29 to the thirty-first transistor Q31 are determined, the gate voltage of the first power transistor M1 is controlled by the second current IP to achieve current limiting.

[0056] After the soft start ends, the first signal SS_END becomes a high level. When the second signal D is a low level, the third signal A1 is also a low level, and the signal A2 is a high level, then the signal SS_END1 is a high level, controlling the thirty-third transistor Q33 to be turned on, thereby releasing the current limiting, and the gate voltage of the first power tube M1 is 0V.

[0057] In some embodiments, after the soft start is completed, if the charge pump circuit 1 is in a light load state and operates in the second phase, the current flowing through the third power transistor M3 exceeds the requirement of |Vneg| increase, that is, the current flowing through the third power transistor M3 is large, which increases the circuit power consumption and poses an overcurrent risk. To address this problem, the present application sets a power supply module 60 in the drive circuit 2: Figure 7 As shown, the driving circuit 2 further includes a power supply module 60, which is connected to the driving module 40 and the control module 30 respectively. Figure 7 It can be seen that the power module 60 is specifically connected to the third driving unit 44 in the driving module 40 .

[0058] Specifically, when the second signal D is at a high level, indicating that the charge pump circuit 1 is operating in the second phase, the power supply module 60 is configured to output the second voltage VPP to the driver module 40 based on the second signal D. When the first signal SS_END is at a high level (indicating the end of soft start) and the charge pump circuit 1 is in a light-load state (meaning that the load Rload in the charge pump circuit 1 has a low current demand), the current mirror module 50 stops outputting the first current IN and the second current IP. The driver module 40 controls the gate voltage of the third power transistor M3 based on the second signal D, the first signal SS_END, and the second voltage VPP to limit the current flowing through the third power transistor M3, thereby eliminating the risk of overcurrent and reducing circuit power consumption.

[0059] like Figure 8 As shown, the power supply module 60 includes a second inverter INV2, a second current source I2, a third current source I3, a first capacitor C1, and a thirty-fourth transistor Q34; the input end of the second inverter INV2 is respectively connected to the control module 30, the driving module 40, and the control end of the third current source I3; the output end of the second inverter INV2 is connected to the control end of the second current source I2; the first end of the second current source I2 and the drain of the thirty-fourth transistor Q34 both receive the first voltage VDD; the second end of the second current source I2 is respectively connected to the first end of the third current source I3, the first end of the first capacitor C1, and the gate of the thirty-fourth transistor Q34; the second end of the third current source I3 and the second end of the first capacitor C1 are both grounded; and the source of the thirty-fourth transistor Q34 is connected to the driving module 40. It should be noted that the second current source I2 and the third current source I3 are simplified versions of the current outputs of the PMOS transistor and the NMOS transistor, respectively.

[0060] Specifically, when the charge pump circuit 1 operates in the second phase, the second signal D is high, which controls the third current source I3 to be turned off and the second current source I2 to be turned on. The second current source I2 charges the first capacitor C1. The 34th transistor Q34 functions as a source follower of a high-voltage transistor. The second voltage VPP is the top plate voltage of the first capacitor C1 minus the gate-source voltage of the 34th transistor Q34. When the charge pump circuit 1 operates in the first phase, the second signal D is low, which controls the second current source I2 to be turned off and the third current source I3 to be turned on. The third current source I3 discharges the first capacitor C1. Under light load conditions, the charge pump circuit 1 enters the second phase after multiple cycles. Therefore, the first phase lasts longer, meaning that the first capacitor C1 has more time to discharge. This ensures that the second voltage VPP is lower when the charge pump circuit 1 enters the second phase. Since the gate voltage of the third power transistor M3 is the second voltage VPP after the soft start ends, the current flowing through the third power transistor M3 is lower, eliminating the risk of overcurrent and reducing circuit power consumption.

[0061] In some embodiments, as Figure 9 As shown, the control module 30 includes an error amplifier EA, a third resistor R3, a fourth resistor R4, and a comparator CMP. The first input terminal of the error amplifier EA receives a reference voltage Vref, the second input terminal of the error amplifier EA is respectively connected to the output terminal of the error amplifier EA and the first terminal of the third resistor R3, the second terminal of the third resistor R3 is respectively connected to the first terminal of the fourth resistor R4 and the first input terminal of the comparator CMP, the second input terminal of the comparator CMP is grounded, the second terminal of the fourth resistor R4 receives the output voltage Vneg, and the output terminal of the comparator CMP outputs a second signal D. In the embodiment of the present application, the first input terminal of the error amplifier EA is a positive input terminal, and the second input terminal is a negative input terminal. The first input terminal of the comparator CMP is a positive input terminal, and the second input terminal is a negative input terminal.

[0062] Specifically, the error amplifier EA receives a reference voltage Vref as an input and outputs a voltage Vref1. Assuming that the resistance ratio of the fourth resistor R4 to the third resistor R3 is K, when the charge pump circuit 1 operates in the first phase and Vneg>K×Vref1, the second signal D is at a low level. When the charge pump circuit 1 operates in the second phase and Vneg<K×Vref1, the second signal D is at a high level.

[0063] In summary, during the soft start process of the charge pump circuit 1, the drive circuit 2 provided in the embodiment of the present application outputs a first current IN with a step-wise change through the current mirror module 50, and gradually increases the current flowing through the third power transistor M3 through the control of the third drive unit 44. This solves the problem caused by the poor linearity of the third power transistor M3 under certain processes, and ensures that the current flowing through the third power transistor M3 is relatively small during the initial soft start phase, thereby ensuring the safety of the charge pump circuit 1. Since the current flowing through the third power transistor M3 gradually increases, after the soft start ends, the output voltage Vneg of the charge pump circuit 1 can be guaranteed to reach the target voltage, allowing the charge pump circuit 1 to operate normally. At the same time, the power supply module 60 outputs a second voltage VPP, which reduces the gate voltage of the third power transistor M3 when the charge pump circuit 1 is in a light load state, thereby reducing the current flowing through the third power transistor M3, eliminating the risk of overcurrent and reducing circuit power consumption.

[0064] The present invention also provides a negative charge pump circuit, including the aforementioned drive circuit. Because the negative charge pump circuit provided by the present invention includes the aforementioned drive circuit, the negative charge pump circuit provided by the present invention has the advantages of being safe, reliable, stable in operation, and having low power consumption.

[0065] The present application also provides a drive system including the negative charge pump circuit described above. Since the drive system provided in the present application utilizes all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be detailed here.

[0066] The present application also provides a display screen including the aforementioned drive system. Since the display screen provided by the present application adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0067] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0068] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A driving circuit for current regulation, characterized in that: The circuit comprises a soft start module, a control module, a drive module and a current mirror module; the control module is respectively connected to the soft start module, the drive module and the source of the fourth power tube in the charge pump circuit; the current mirror module is respectively connected to the soft start module and the drive module; the drive module is respectively used to connect to the gate of the first power tube, the gate of the second power tube, the gate of the third power tube and the gate of the fourth power tube in the charge pump circuit; The soft start module is used to output a reference voltage, a first signal and n control signals; when the first signal is at a low level, the current mirror module is used to output a first current with a step-changing pattern according to the first signal and the n control signals, and at the same time output a second current according to the first signal; the control module is used to output a second signal according to the reference voltage and the output voltage of the charge pump circuit; when the second signal is at a high level, the drive module is used to control the first power tube to be disconnected according to the second signal, the first signal and the second current, control the second power tube to be disconnected and control the fourth power tube to be turned on according to the second signal, and at the same time control the gate voltage of the third power tube to gradually increase according to the second signal, the first signal and the first current, thereby gradually increasing the current flowing through the third power tube; wherein n is a natural number greater than 0.

2. The driving circuit according to claim 1, wherein: When the first signal is at a low level and the second signal is at a low level, the driving module is further used to control the second power tube to be turned on and the fourth power tube to be turned off according to the second signal, control the third power tube to be turned off according to the second signal, the first signal and the first current, and at the same time control the gate voltage of the first power tube according to the second signal, the first signal and the second current to limit the current flowing through the first power tube.

3. The driving circuit according to claim 1 or 2, characterized in that: The current mirror module includes a first current source, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, n current mirror branches and n+1 inverters; The first end of the first current source, the source of the fourth transistor, the source of the sixth transistor, and the first ends of the n current mirror branches all receive a first voltage. The second end of the first current source is respectively connected to the drain of the first transistor, the gate of the first transistor, the gate of the second transistor, and the gate of the fifth transistor. The drain of the second transistor is connected to the source of the third transistor, the drain of the third transistor is connected to the driving module, and the drain of the fifth transistor is respectively connected to the drain of the fourth transistor, the gate of the fourth transistor, the gate of the sixth transistor, and the gate of the fifth transistor. The second ends of the n current mirror branches are connected, the third ends of the n current mirror branches are correspondingly connected to the output ends of the n inverters, the input ends of the n+1 inverters are respectively connected to the soft start module, the gate of the third transistor is connected to the output end of the (n+1)th inverter, the drain of the sixth transistor and the fourth ends of the n current mirror branches are both connected to the source of the seventh transistor, the gate of the seventh transistor is connected to the soft start module, the drain of the seventh transistor is connected to the driving module, and the source of the first transistor, the source of the second transistor, and the source of the fifth transistor are all grounded; The current mirror branch includes two transistors; The source of the first transistor serves as the first end of the current mirror branch, the gate of the first transistor serves as the second end of the current mirror branch, the gate of the second transistor serves as the third end of the current mirror branch, the drain of the second transistor serves as the fourth end of the current mirror branch, and the drain of the first transistor is connected to the source of the second transistor.

4. The driving circuit according to claim 1 or 2, characterized in that: The soft start module includes a soft start unit and a logic unit, and the logic unit is connected to the soft start unit, the current mirror module and the driving module respectively; The soft start unit is used to output a reference voltage and a soft start signal; the logic unit is used to receive a soft start time, divide the soft start time into n time periods according to the soft start signal, and output a first signal and n control signals corresponding to the n time periods.

5. The driving circuit according to claim 1 or 2, characterized in that: The driving module includes a clock generating unit, a first driving unit, a second driving unit, a third driving unit and a fourth driving unit; the clock generating unit is respectively connected to the control module, the first driving unit, the second driving unit, the third driving unit and the fourth driving unit; the first driving unit is respectively connected to the soft start module, the current mirror module and the gate of the first power tube; the second driving unit is used to be connected to the gate of the second power tube; the third driving unit is respectively connected to the soft start module, the current mirror module and the gate of the third power tube; the fourth driving unit is used to be connected to the gate of the fourth power tube; The clock generating unit is used to output a third signal and a fourth signal according to the clock signal and the second signal; when the first signal is at a low level and the second signal is at a high level, the first driving unit is used to control the first power tube to be disconnected according to the third signal, the first signal and the second current; the second driving unit is used to control the second power tube to be disconnected according to the third signal; the third driving unit is used to control the gate voltage of the third power tube to gradually increase according to the fourth signal, the first signal and the first current, thereby gradually increasing the current flowing through the third power tube; the fourth driving unit is used to control the fourth power tube to be turned on according to the fourth signal.

6. The driving circuit according to claim 5, wherein: The third driving unit includes a NAND gate, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor and a first resistor; the first input terminal of the NAND gate is connected to the soft start module, the output terminal of the NAND gate is connected to the gate of the twentieth transistor, the source of the eighth transistor, the source of the tenth transistor, the source of the twelfth transistor, the source of the seventeenth transistor and the source of the twentieth transistor all receive a second voltage, the gate of the eighth transistor is respectively connected to the clock generating unit, the gate of the ninth transistor and the second input terminal of the NAND gate, the drain of the eighth transistor is respectively connected to the drain of the ninth transistor, the gate of the tenth transistor and the gate of the eleventh transistor, the drain of the tenth transistor is respectively connected to the drain of the eleventh transistor, the gate of the twelfth transistor and the gate of the The gate of the thirteenth transistor is connected, the drain of the twelfth transistor is respectively connected to the drain of the thirteenth transistor, the gate of the seventeenth transistor and the gate of the nineteenth transistor, the drain of the seventeenth transistor is respectively connected to the drain of the eighteenth transistor, the source of the eighteenth transistor is respectively connected to the drain of the nineteenth transistor, the first end of the first resistor, the drain of the twentieth transistor and the gate of the third power tube, the gate of the eighteenth transistor is respectively connected to the drain of the fourteenth transistor, the gate of the fourteenth transistor and the current mirror module, the source of the fourteenth transistor is respectively connected to the drain of the fifteenth transistor, the gate of the fifteenth transistor and the gate of the sixteenth transistor, the source of the fifteenth transistor is connected to the drain of the sixteenth transistor, the source of the ninth transistor, the source of the eleventh transistor, the source of the thirteenth transistor, the source of the sixteenth transistor, the source of the nineteenth transistor and the second end of the first resistor are all grounded.

7. The driving circuit according to claim 5, wherein: The first driving unit includes a first inverter, an AND gate, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, a thirty-first transistor, a thirty-second transistor, a thirty-third transistor and a second resistor; the input end of the first inverter is respectively connected to the clock generating unit, the gate of the twenty-first transistor and the gate of the twenty-second transistor, the output end of the first inverter is connected to the first input end of the AND gate, the second input end of the AND gate is connected to the soft start module, the output end of the AND gate is connected to the gate of the thirty-third transistor, the source of the twenty-first transistor, the source of the twenty-third transistor, the source of the twenty-fifth transistor, the source of the twenty-seventh transistor, the source of the thirtieth transistor and the first end of the second resistor all receive an input voltage, the drain of the twenty-first transistor is respectively connected to the drain of the twenty-second transistor, the gate of the twenty-third transistor and the gate of the twenty-fourth transistor, the drain of the twenty-third transistor is respectively connected to the drain of the twenty-second transistor, the gate of the twenty-third transistor and the gate of the twenty-fourth transistor, The drains are respectively connected to the drain of the twenty-fourth transistor, the gate of the twenty-fifth transistor and the gate of the twenty-sixth transistor; the drain of the twenty-fifth transistor is respectively connected to the drain of the twenty-sixth transistor, the gate of the thirtieth transistor and the gate of the thirty-second transistor; the drain of the thirtieth transistor is respectively connected to the source of the thirty-first transistor, the second end of the second resistor, the drain of the thirty-third transistor and the gate of the first power tube; the drain of the thirty-first transistor is connected to the drain of the thirty-second transistor; the gate of the thirty-first transistor is respectively connected to the gate of the twenty-ninth transistor, the drain of the twenty-ninth transistor and the current mirror module; the source of the twenty-ninth transistor is respectively connected to the drain of the twenty-eighth transistor, the gate of the twenty-eighth transistor and the gate of the twenty-seventh transistor; the source of the twenty-eighth transistor is connected to the drain of the twenty-seventh transistor; the source of the twenty-second transistor, the source of the twenty-fourth transistor, the source of the twenty-sixth transistor, the source of the thirty-second transistor and the source of the thirty-third transistor are all grounded.

8. The driving circuit according to claim 1 or 2, characterized in that: The driving circuit further includes a power supply module, which is connected to the driving module and the control module respectively; When the second signal is at a high level, the power supply module is used to output a second voltage to the driving module according to the second signal; when the first signal is at a high level and the charge pump circuit is in a light-load state, the current mirror module is also used to stop outputting the first current and the second current; the driving module is also used to control the gate voltage of the third power tube according to the second signal, the first signal and the second voltage to limit the current flowing through the third power tube.

9. The driving circuit according to claim 8, wherein: The power supply module includes a second inverter, a second current source, a third current source, a first capacitor and a thirty-fourth transistor; the input end of the second inverter is respectively connected to the control module, the driving module and the control end of the third current source, the output end of the second inverter is connected to the control end of the second current source, the first end of the second current source and the drain of the thirty-fourth transistor both receive a first voltage, the second end of the second current source is respectively connected to the first end of the third current source, the first end of the first capacitor and the gate of the thirty-fourth transistor, the second end of the third current source and the second end of the first capacitor are both grounded, and the source of the thirty-fourth transistor is connected to the driving module.

10. A negative voltage charge pump circuit, characterized in that: The drive circuit comprises the drive circuit according to any one of claims 1 to 9.

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