Circuit board and manufacturing method thereof

Abstract

The invention provides a circuit board and a manufacturing method thereof. Specifically, the circuit board comprises a circuit area and a non-circuit area; the circuit board comprises a dielectric layer, a first circuit layer, a second circuit layer and a conduction column which is in conduction connection with the first circuit layer and the second circuit layer. Wherein the first circuit layer and the conduction column are embedded in the dielectric layer located in the circuit area, and the second circuit layer is arranged on the dielectric layer located in the circuit area; in the direction perpendicular to the circuit board, the surface, close to the first circuit layer, of the dielectric layer has a height difference in the circuit area and the non-circuit area. According to the technical scheme, the circuit board can have a three-dimensional shape matched with the shape of a product shell, and the effects of effectively utilizing the internal space and improving the integration level of the product are achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a circuit board and a manufacturing method thereof. Background Art

[0002] With the development and progress of electronic technology, electronic products are evolving towards being shorter, lighter and thinner, and the functional requirements of electronic products are becoming more and more powerful, which has promoted the packaging structure of electronic products to develop in the direction of high integration and miniaturization, making it an inevitable trend for electronic components and circuit board substrates to be refined, integrated, smaller, thinner and more multifunctional. Summary of the Invention

[0003] In view of this, the present disclosure aims to provide a circuit board and a method for manufacturing the same.

[0004] Based on the above objectives, in a first aspect, the present disclosure provides a circuit board, comprising a circuit area and a non-circuit area; the circuit area and the non-circuit area both comprising a dielectric layer; wherein the circuit area further comprises a first circuit layer, a second circuit layer, and a conductive column conductively connecting the first circuit layer and the second circuit layer;

[0005] Wherein, the first circuit layer and the conductive pillar are embedded in the dielectric layer of the circuit area, and the second circuit layer is formed on the surface of the dielectric layer of the circuit area;

[0006] Wherein, in the thickness direction of the circuit board, there is a height difference between the surface of the dielectric layer in the circuit area and the surface of the dielectric layer in the non-circuit area.

[0007] In some embodiments, the dielectric layer includes a curved structure; the curved structure is located in the non-circuit area.

[0008] In some embodiments, the curved structure includes an opening.

[0009] In some embodiments, in the thickness direction of the circuit board, the second circuit layer is partially embedded in the dielectric layer and partially exposed outside the dielectric layer.

[0010] In some embodiments, a surface treatment layer is further included; wherein the surface treatment layer is located on the surface of at least one of the first circuit layer and the second circuit layer.

[0011] In some embodiments, the dielectric layer is made of a thermosetting resin material.

[0012] In a second aspect, the present disclosure provides a method for manufacturing a circuit board, comprising:

[0013] (a) providing a carrier plate;

[0014] (b) forming a first circuit layer on the carrier board;

[0015] (c) forming a conductive column on the first circuit layer;

[0016] (d) pressing a semi-cured dielectric material and exposing the end of the conductive column;

[0017] (e) forming a second circuit layer on the semi-cured dielectric material;

[0018] (f) removing the carrier plate;

[0019] (g) Using a mold to heat-press and cure the semi-cured dielectric material to form a dielectric layer, wherein a portion of the dielectric layer forms a curved structure in the thickness direction of the circuit board, and a portion of the second circuit layer is embedded in the dielectric layer.

[0020] In a third aspect, the present disclosure provides another method for manufacturing a circuit board, comprising:

[0021] (a) providing a carrier plate;

[0022] (b) forming a first circuit layer on the carrier board;

[0023] (c) laminating a semi-cured dielectric material on the first circuit layer;

[0024] (d) forming a via hole in the semi-cured dielectric material exposing a portion of the first circuit layer;

[0025] (e) forming a conductive column and a second circuit layer on the semi-cured dielectric material; wherein the conductive column is located in the conductive hole;

[0026] (f) removing the carrier plate;

[0027] (g) Using a mold to heat-press and cure the semi-cured dielectric material to form a dielectric layer, wherein a portion of the dielectric layer forms a curved structure in the thickness direction of the circuit board, and a portion of the second circuit layer is embedded in the dielectric layer.

[0028] In some embodiments, further comprising:

[0029] (h) Cutting the curved structure.

[0030] In some embodiments, before step (h), the method further comprises:

[0031] A surface treatment layer is formed on at least one of the first circuit layer and the second circuit layer.

[0032] In some embodiments, the semi-cured dielectric material is selected from at least one of PP, ABF, epoxy resin, and polyimide resin.

[0033] In some embodiments, the curing degree of the semi-cured dielectric material is 50% to 80%.

[0034] As can be seen from the above, the circuit board and its manufacturing method provided by the present disclosure can form a dielectric layer structure with a height difference and / or a bendable and / or opening in the non-circuit area of ​​the circuit board by setting a non-circuit area on the circuit board, so that the circuit board can form a three-dimensional morphology that matches the shape of the product shell, thereby achieving the effect of effectively utilizing the internal space and improving the integration of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 A schematic structural diagram of a circuit board provided in an embodiment of the present disclosure;

[0037] Figure 2(a) to Figure 2(l) A schematic cross-sectional view of intermediate structures of some steps in a method for manufacturing a circuit board provided by an embodiment of the present disclosure;

[0038] Figure 3(a) to Figure 3(e) A cross-sectional schematic diagram of intermediate structures of some steps in another method for manufacturing a circuit board provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0040] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

[0041] In the drawings, the thickness and shapes of some layers and regions may be exaggerated for better understanding and ease of description.

[0042] In related technologies, rigid or flexible planar circuit substrates and rigid-flexible circuit boards are typically used to manufacture miniaturized and compact electronic devices. However, these have certain limitations in terms of product thinness and appearance design, and cannot maximize the utilization of the internal space of electronic products. This has been unable to meet the development needs of highly integrated and miniaturized intelligent electronic devices. Therefore, the development of electronic technology requires that circuit boards, as component carriers, can better adapt to three-dimensional spatial structures to achieve a more optimized layout within a limited space, providing more design possibilities for miniaturized and compact electronic devices.

[0043] In view of this, the present disclosure provides a circuit board and a method for manufacturing the same, wherein the circuit board includes a circuit area and a non-circuit area; the circuit area and the non-circuit area both include a dielectric layer; wherein the circuit area also includes a first circuit layer, a second circuit layer, and conductive pillars that connect the first circuit layer and the second circuit layer; wherein the first circuit layer and the conductive pillars are embedded in the dielectric layer of the circuit area, and the second circuit layer is formed on the surface of the dielectric layer of the circuit area; wherein in the thickness direction of the circuit board, there is a height difference between the surface of the dielectric layer of the circuit area and the surface of the dielectric layer of the non-circuit area. Such a technical solution, through the height difference between the dielectric layers of the circuit area and the non-circuit area, gives the circuit board a three-dimensional shape, facilitating the formation of a three-dimensional morphology that matches the shape of the product housing, thereby achieving the effect of effectively utilizing the internal space and improving the integration of the product.

[0044] Figure 1 This is a schematic diagram of the structure of a circuit board provided in an embodiment of the present disclosure. Figure 1As shown, the circuit board includes a circuit area M1 and a non-circuit area M2; the circuit area M1 and the non-circuit area M2 include a dielectric layer 303. The circuit area M1 includes a first circuit layer 202, a second circuit layer 401, and a conductive column 302 that connects the first circuit layer 202 and the second circuit layer 401; wherein the dielectric layer 303 located in the circuit area M1 is embedded with the first circuit layer 202 and the conductive column 302, and the second circuit layer 401 is arranged on the dielectric layer 303 in the circuit area M1; in a direction perpendicular to the circuit board ( Figure 1 In the z-axis thickness direction, a height difference h exists between the surface of the dielectric layer 303 close to the first circuit layer 202 in the circuit region M1 and the non-circuit region M2.

[0045] It can be seen that compared with the planar circuit board in the related art, the technical solution of the embodiment of the present disclosure has a height difference h between the dielectric layer 303 in the circuit area M1 and the non-circuit area M2, so that the circuit board has a three-dimensional shape, which is convenient for forming a three-dimensional morphology that matches the shape of the product shell, thereby achieving the effect of effectively utilizing the internal space and improving the integration of the product.

[0046] In some embodiments, dielectric layer 303 includes curved structures 3031 located in non-circuit region M2. Using curved structures 3031, a three-dimensional circuit board can be created that matches the product housing, facilitating better adaptation to three-dimensional spatial structures, achieving a more optimized layout within a limited space, improving product integration, and providing more design possibilities for electronic products.

[0047] In some embodiments, the curved structure 3031 includes an opening 3032. The provision of opening 3032 facilitates the insertion of other components and structures of the electronic product through the circuit board, providing more options for the structural design of the electronic product. Furthermore, opening 3032 facilitates adjusting the shape of the curved structure 3031 to facilitate matching with the housing of the electronic product.

[0048] Related art circuit structures include non-embedded and embedded types. The finer the non-embedded circuit, the lower its bonding strength with the dielectric material, making it difficult to fabricate fine circuits. Embedded circuit structures, on the other hand, can improve bonding strength between the circuit and the dielectric layer, but small pads are prone to poor solderability. To address the contradiction between the low bonding strength between fine circuits and dielectric materials and the poor solderability of small pads, the present disclosure employs a semi-embedded approach in some embodiments.

[0049] like Figure 1 As shown, in the direction perpendicular to the circuit board (eg Figure 1In the z-direction, second circuit layer 401 is partially embedded in dielectric layer 303 and partially exposed outside dielectric layer 303. The semi-buried circuit structure can enhance the bonding strength between the circuit layer and the dielectric layer, facilitating the production of fine circuits. It can also improve the poor solderability problem of small pads in buried circuit structures.

[0050] In some embodiments, a surface treatment layer 402 is further included. Optionally, the surface treatment layer 402 is located on the surface of at least one of the first circuit layer 202 and the second circuit layer 401. For example, Figure 1 A surface treatment layer 402 is provided on the surfaces of the first circuit layer 202 and the second circuit layer 401 .

[0051] In some embodiments, the dielectric layer 303 is made of a thermosetting resin material, such as a semi-cured prepreg, an ABF (Ajinomoto Build-up) film, an epoxy resin, or a polyimide resin, which is not limited in the present disclosure.

[0052] The use of thermosetting resin material helps to form a height difference between the circuit area and the non-circuit area during the curing process of the dielectric layer 303 with the help of a mold, thereby obtaining a circuit board with a three-dimensional shape.

[0053] Based on the same inventive concept, the embodiments of the present disclosure also provide a method for manufacturing any of the above-mentioned circuit boards. Figure 2(a) to Figure 2(l) This is a cross-sectional diagram of the intermediate structure of some steps of a method for manufacturing a circuit board provided by an embodiment of the present disclosure. The manufacturing method includes the following steps:

[0054] First, a carrier plate 100 is provided (step a), as shown in FIG2( a ). Optionally, the carrier plate 100 has a first metal seed layer 101 thereon.

[0055] It should be noted that the first metal seed layer 101 can be used to make the first circuit layer 202. When there is no first metal seed layer 101 on the carrier board 100, the first metal seed layer 101 needs to be formed on the carrier board 100 in step b.

[0056] Next, a first circuit layer 202 is formed on the carrier board 100—step b, as shown in FIG. 2( a ) and FIG. 2( b ).

[0057] In some embodiments, step b specifically includes:

[0058] Referring to FIG2(a), a first circuit pattern layer 201 is formed on a carrier board 100. Exemplarily, the process steps for forming the first circuit pattern layer 201 may include: forming a photosensitive dry film on the carrier board 100, followed by exposure and development to obtain the first circuit pattern layer 201. Next, referring to FIG2(b), a first circuit layer 202 is formed by electroplating on the first metal seed layer 101 exposed in the first circuit pattern layer 201.

[0059] Then, a conductive column 302 is formed on the first circuit layer 202 (step c). Figure 2(c) to Figure 2(e) shown.

[0060] In some embodiments, step c specifically includes:

[0061] Referring to Figure 2(c), a conductive pillar pattern layer 301 is formed on the first circuit pattern layer 201 and the first circuit layer 202. Here, the manufacturing process of the conductive pillar pattern layer 301 is similar to the manufacturing process of the first circuit pattern layer 201 and will not be repeated here. Next, referring to Figure 2(d), a conductive pillar 302 is formed by electroplating on the first circuit layer 202 exposed by the conductive pillar pattern layer 301. Optionally, the material of the conductive pillar 302 may be copper. It should be noted that, usually, the end of the electroplating is higher than the surface of the conductive pillar pattern layer 301, and the end of the conductive pillar 302 is smoothed by mechanical grinding so that the end of the conductive pillar 302 is flush with the surface of the conductive pillar pattern layer 301. Finally, as shown in Figure 2(e), the first circuit pattern layer 201 and the conductive pillar pattern layer 301 are removed.

[0062] Next, the semi-cured dielectric material 305 is pressed and the end of the conductive pillar 302 is exposed—step d, as shown in FIG. 2( f ).

[0063] Optionally, the semi-cured dielectric material is a thermosetting dielectric material. Exemplarily, the thermosetting dielectric material is selected from at least one of semi-cured prepreg (PP), ABF (Ajinomoto Build-up), epoxy resin, and polyimide resin.

[0064] Here, the curing degree of the semi-cured dielectric material 305 is 50% to 80%. It should be noted that for different semi-cured dielectric materials, the corresponding curing degrees may vary to a certain extent, and this disclosure does not make any specific limitation on this.

[0065] It should be noted that after lamination, the semi-cured dielectric material 305 completely covers the end of the conductive pillar 302 to ensure that the semi-cured dielectric material 305 completely covers the first circuit layer 202 and the conductive pillar 302; the semi-cured dielectric material on the surface is removed by grinding, so that the end of the conductive pillar 302 is exposed to the semi-cured dielectric material 305.

[0066] Then, a second circuit layer 401 is formed on the semi-cured dielectric material 305—step e, as shown in FIG. 2( g ).

[0067] In some embodiments, the process steps for forming the second circuit layer 401 include: forming a second metal seed layer on the semi-cured dielectric material 305; then forming a second circuit pattern layer on the second metal seed layer; then electroplating and stripping; and finally etching the exposed second metal seed layer to obtain the second circuit layer 401. The process steps for forming the second circuit pattern layer are similar to those for the first circuit pattern layer and are not further described.

[0068] Next, the carrier plate 100 is removed (step f), as shown in Figures 2(h) and 2(i). It should be noted that, as shown in Figure 2(i), both the first metal seed layer 101 of the carrier plate 100 and the first metal seed layer 101 formed when the first circuit layer 202 is formed can be removed by etching, and this disclosure does not limit this.

[0069] Then, a mold is used to heat-press and solidify the semi-cured dielectric material 305 to form a dielectric layer 303. Part of the dielectric layer 303 forms a curved structure 3031 in a direction perpendicular to the circuit board (z-axis direction), and the second circuit layer 401 is partially embedded in the dielectric layer 303 - step g, as shown in Figure 2(j).

[0070] As shown in FIG. 2( j ), the semi-cured dielectric material 305 is cured by hot pressing with a mold, so that the semi-cured dielectric material 305 is completely cured and forms a three-dimensional shape corresponding to the mold, for example, the dielectric layer 303 forms a curved structure 3031 .

[0071] As can be clearly seen in the dashed box A in Figure 2(j), the pressure during the hot pressing process causes the second circuit layer 401 to be partially embedded in the dielectric layer 303 and partially exposed. This semi-buried circuit structure helps to improve the bonding strength between the second circuit layer 401 and the dielectric layer 303, while effectively avoiding the problem of poor solderability caused by small pads in the fully buried circuit structure.

[0072] Next, a surface treatment layer 402 is formed on at least one of the first circuit layer 202 and the second circuit layer 401—step h, as shown in FIG. 2( k ).

[0073] Finally, the curved structure 3031 is cut to form an opening 3032—step i, as shown in FIG2(l).

[0074] Optionally, the curved structure 3031 may be cut by laser cutting or mechanical cutting, which is not limited in the present disclosure.

[0075] The circuit board obtained through the above steps has a three-dimensional shape and meets the diverse needs of electronic products.

[0076] Figure 3(a) to Figure 3(e) A cross-sectional view of the intermediate structure of some steps of another circuit board manufacturing method provided by an embodiment of the present disclosure. The manufacturing method includes the following steps:

[0077] First, a carrier plate 100 is provided—step a, as shown in FIG3( a ). Here, step a is the same as step a in the previous embodiment and will not be described in detail.

[0078] Next, a first circuit layer 202 is formed on the carrier board 100—step b′, as shown in FIG. 3( a ) and FIG. 3( b ).

[0079] Here, the difference between step b′ and step b of the aforementioned embodiment is that after the first circuit layer 202 is formed by electroplating on the first metal seed layer 101 exposed by the first circuit pattern layer 201 , the first circuit pattern layer 201 is etched away.

[0080] Then, a pre-cured dielectric material 305 is laminated on the first circuit layer 202 (step c'), as shown in Figure 3(c). Here, the definition of the pre-cured dielectric material 305 is as described above and will not be repeated here.

[0081] Optionally, a second metal seed layer 304 , such as copper foil, is laminated on the semi-cured dielectric material 305 .

[0082] Next, a via hole 306 is formed on the semi-cured dielectric material 305 to expose a portion of the first circuit layer—step d′, as shown in FIG. 3( d ).

[0083] Here, the via hole 306 may be formed by laser drilling.

[0084] Then, a conductive pillar 302 and a second circuit layer 401 are formed on the semi-cured dielectric material 305 ; wherein the conductive pillar 302 is located in the conductive hole 306 —step e′, as shown in FIG. 3( e ).

[0085] In some embodiments, step e′ specifically includes: forming a second circuit pattern layer on the second metal seed layer 304 ; then performing via-filling electroplating and film stripping; and finally etching the exposed second metal seed layer 304 to obtain the conductive pillars 302 and the second circuit layer 401 .

[0086] The subsequent processes from step f to step i are the same as those in the above embodiment and will not be described in detail.

[0087] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Within the scope of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0088] The embodiments of the present disclosure are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A circuit board, characterized in that: The circuit board includes a circuit area and a non-circuit area; the circuit area and the non-circuit area both include a dielectric layer; wherein the circuit area further includes a first circuit layer, a second circuit layer, and a conductive column conductively connecting the first circuit layer and the second circuit layer; Wherein, the first circuit layer and the conductive pillar are embedded in the dielectric layer of the circuit area, and the second circuit layer is formed on the surface of the dielectric layer of the circuit area; Wherein, in the thickness direction of the circuit board, there is a height difference between the surface of the dielectric layer in the circuit area and the surface of the dielectric layer in the non-circuit area.

2. The circuit board according to claim 1, wherein: The dielectric layer includes a curved structure; the curved structure is located in the non-circuit area.

3. The circuit board according to claim 2, characterized in that The curved structure includes an opening.

4. The circuit board according to claim 1, wherein: In the thickness direction of the circuit board, the second circuit layer is partially embedded in the dielectric layer and partially exposed outside the dielectric layer.

5. The circuit board according to claim 1, wherein: It also includes a surface treatment layer; wherein the surface treatment layer is located on the surface of at least one of the first circuit layer and the second circuit layer.

6. The circuit board according to claim 1, wherein: The dielectric layer includes thermosetting resin material.

7. A method for manufacturing a circuit board, characterized in that: include: (a) providing a carrier plate; (b) forming a first circuit layer on the carrier board; (c) forming a conductive column on the first circuit layer; (d) pressing a semi-cured dielectric material and exposing the end of the conductive column; (e) forming a second circuit layer on the semi-cured dielectric material; (f) removing the carrier plate; (g) Using a mold to heat-press and cure the semi-cured dielectric material to form a dielectric layer, wherein a portion of the dielectric layer forms a curved structure in the thickness direction of the circuit board, and a portion of the second circuit layer is embedded in the dielectric layer.

8. A method for manufacturing a circuit board, characterized in that: include: (a) providing a carrier plate; (b) forming a first circuit layer on the carrier board; (c) laminating a semi-cured dielectric material on the first circuit layer; (d) forming a via hole in the semi-cured dielectric material exposing a portion of the first circuit layer; (e) forming a conductive column and a second circuit layer on the semi-cured dielectric material; wherein the conductive column is located in the conductive hole; (f) removing the carrier plate; (g) Using a mold to heat-press and cure the semi-cured dielectric material to form a dielectric layer, wherein a portion of the dielectric layer forms a curved structure in the thickness direction of the circuit board, and a portion of the second circuit layer is embedded in the dielectric layer.

9. The production method according to claim 7 or 8, characterized in that: Also includes: (h) Cutting the curved structure.

10. The manufacturing method according to claim 9, characterized in that: Before step (h), the method further comprises: A surface treatment layer is formed on at least one of the first circuit layer and the second circuit layer.

11. The production method according to claim 7 or 8, characterized in that: The semi-cured dielectric material is selected from at least one of PP, ABF, epoxy resin and polyimide resin.

12. The production method according to claim 7 or 8, characterized in that: The curing degree of the semi-cured medium material is 50% to 80%.

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