A method of manufacturing a semiconductor device

Abstract

The application relates to the technical field of semiconductor manufacturing, in particular to a preparation method of a semiconductor device, the semiconductor device comprising a substrate, the substrate having a plurality of grooves, the substrate between adjacent grooves forming a fin part, and the upper end of the fin part having a mask layer; the preparation method comprises the following steps: a first deposition step: depositing a first dielectric layer in the grooves, the thickness of the first dielectric layer being less than the depth of the grooves; and a first annealing step: performing annealing treatment on the semiconductor device with the deposited first dielectric layer. Taking a fin field effect transistor as an example, the preparation method of the semiconductor device provided by the application can reduce the contact area between the first dielectric layer and the sidewall surface of the groove, reduce the stress of the first dielectric layer on the fin part, reduce or even avoid the bending deformation of the fin part, thereby improving the electrical performance of the fin field effect transistor and improving the yield of the fin field effect transistor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a method for fabricating a semiconductor device. Background Technology

[0002] As the size of semiconductor devices continues to shrink, the size of the isolation regions between semiconductor devices also decreases accordingly. FinFET (Fin Field-Effect Transistor) is a new type of complementary metal-semiconductor transistor, where reducing the width of the fins is a primary goal. This is because the fin width directly affects the transistor's leakage current and on-resistance. For example, a narrower fin width results in lower losses during current flow, significantly reducing chip heat generation and improving energy efficiency.

[0003] In related technologies, semiconductor devices include a substrate, a mask layer, and a trench formed by sequentially etching the mask layer and part of the substrate from bottom to top. The trench isolation is usually achieved by the following techniques: first, an oxide layer is filled into the trench, wherein the oxide layer covers the mask layer; then, the oxide layer is annealed; and finally, the oxide layer is planarized so that the oxide layer is flush with the surface of the mask layer.

[0004] However, the fin width of fin field-effect transistors is less than or equal to 10 nm, and the trench aspect ratio is increasing. If related technologies are used to isolate the trenches of fin field-effect transistors, the thermal stress on the fins during annealing and the shrinkage of the oxide layer itself can cause the fins to bend and deform. Therefore, there is an urgent need to propose a semiconductor device fabrication method to reduce or even avoid fin bending and deformation, thereby improving the electrical performance and yield of semiconductor devices. Summary of the Invention

[0005] The present invention aims to at least solve the technical problems existing in the related art, and proposes a method for fabricating semiconductor devices that can reduce or even avoid bending deformation of the fins, thereby improving the electrical performance of semiconductor devices and increasing the yield of semiconductor devices.

[0006] The present invention provides a method for fabricating a semiconductor device, the semiconductor device including a substrate having a plurality of trenches, a fin being formed between adjacent trenches on the substrate, and a mask layer being provided at the upper end of the fin;

[0007] The preparation method includes the following steps:

[0008] First deposition step: Deposit a first dielectric layer in the trench, the thickness of the first dielectric layer being less than the depth of the trench;

[0009] First annealing step: Annealing the semiconductor device on which the first dielectric layer is deposited.

[0010] Optionally, after the first annealing step, the preparation method further includes the following steps:

[0011] Second deposition step: Deposit a second dielectric layer in the trench, the second dielectric layer covering the upper surface of the first dielectric layer and being higher than the upper surface of the mask layer;

[0012] Second annealing step: Annealing the semiconductor device on which the second dielectric layer is deposited.

[0013] Optionally, the ratio of the thickness of the first dielectric layer to the depth of the trench is between 20% and 80%.

[0014] And / or, the size of the upper end of the fin is smaller than the size of the lower end of the fin, and the size of the upper end of the fin is much smaller than the opening size of the upper end of the groove.

[0015] Optionally, the first annealing step includes:

[0016] Curing pretreatment stage: Under an inert gas atmosphere, ultraviolet light is used for the first curing time;

[0017] Stress relief and structural reorganization stage: Under a water vapor atmosphere, the temperature is increased from a first temperature to a second temperature at a first heating rate, and held at that temperature for a second duration;

[0018] Densification stage: Under an inert gas atmosphere, the temperature is increased from the second temperature to the third temperature at a second heating rate, and held at that temperature for a third duration.

[0019] Optionally, the second annealing step includes:

[0020] Curing pretreatment stage: Under an inert gas atmosphere, ultraviolet light is used for the first curing time;

[0021] Stress relief and structural reorganization stage: Under a water vapor atmosphere, the temperature is increased from a first temperature to a second temperature at a first heating rate, and held at that temperature for a second duration;

[0022] Densification stage: Under an inert gas atmosphere, the temperature is increased from the second temperature to the third temperature at a second heating rate, and held at that temperature for a third duration.

[0023] Optionally, the stress release and structural reorganization stage is a stepped heating stage, which has N sub-heating stages, where N≥2.

[0024] Optionally, the sub-heating stage includes the following steps:

[0025] For each increase in sub-temperature, the temperature is maintained for a fourth time; wherein, the sub-temperature = (second temperature - first temperature) / N.

[0026] Optionally, the process parameters of the curing pretreatment stage include: a first duration, power, ambient pressure, and inert gas flow rate; wherein the first duration is between 10s and 1000s, the power is between 0% and 80%, the ambient pressure is between 0 and 500 torr, and the inert gas flow rate is between 0 and 50000 sccm.

[0027] And / or, the value of the first temperature is between 150℃ and 250℃;

[0028] And / or, the second temperature ranges from 550℃ to 800℃; the second duration ranges from 10min to 120min;

[0029] And / or, the value of the third temperature is between 800℃ and 1200℃; the value of the third duration is between 10min and 120min.

[0030] Optionally, a transition layer is provided between the substrate and the mask layer;

[0031] And / or, the first deposition step employs a fluid chemical vapor deposition process;

[0032] And / or, both the first deposition step and the first annealing step have one or more steps. When there are multiple steps, the first deposition step and the first annealing step are performed alternately in sequence.

[0033] And / or, the first dielectric layer is a silicon oxide layer.

[0034] Optionally, the distance between the upper surface of the second dielectric layer and the upper surface of the mask layer is between 500 Å and 600 Å; after the second annealing step, the preparation method further includes the following step: planarization treatment: performing planarization treatment on the second dielectric layer;

[0035] And / or, the second deposition step employs a fluid chemical vapor deposition process;

[0036] And / or, both the second deposition step and the second annealing step have one or more steps. When there are multiple steps, the second deposition step and the second annealing step are performed alternately in sequence.

[0037] And / or, the second dielectric layer is a silicon oxide layer.

[0038] Taking a finned field-effect transistor as an example, the method for fabricating a semiconductor device provided by this invention has at least the following beneficial technical effects:

[0039] By first depositing a first dielectric layer of a certain thickness at the bottom of the trench, and then annealing the fin field-effect transistor with the deposited first dielectric layer, the shrinkage of the first dielectric layer causes stress to form between the first dielectric layer and the fin. By limiting the thickness of the first dielectric layer to be less than the depth of the trench, the contact area between the first dielectric layer and the sidewall of the trench can be reduced, while the stress of the first dielectric layer on the fin can be reduced, reducing or even avoiding the bending deformation of the fin, thereby improving the electrical performance of the fin field-effect transistor and increasing the yield of the fin field-effect transistor. Attached Figure Description

[0040] Figure 1(a)-Figure 1(c) This is a schematic diagram of the process structure of a semiconductor device fabrication method in related technologies;

[0041] Figures 2(a)-2(c) A schematic diagram of the process structure of a semiconductor device fabrication method provided in an embodiment of the present invention;

[0042] Figure 3 A flowchart of a method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0043] Figure 4 A flowchart of a method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0044] Figure 5 A process flow for fabricating a semiconductor device provided in an embodiment of the present invention. Figure 3 .

[0045] Explanation of reference numerals in the attached figures:

[0046] 100 - Substrate; 101 - Mask layer; 102 - Transition layer; 200 - Trench; 201 - Oxide layer; 202 - First dielectric layer; 203 - Second dielectric layer; 204 - Fin;

[0047] h1 - Thickness of the first dielectric layer; h2 - Depth of the trench; X - Width of the fin; K - Ratio of the thickness h1 of the first dielectric layer to the depth h2 of the trench. Detailed Implementation

[0048] For related technologies, please refer to the appendix. Figure 1a-1c, a semiconductor device includes a substrate 100, a mask layer 101, and trenches 200 formed by sequentially etching the mask layer 101 and a portion of the substrate 100, arranged from bottom to top. The area between adjacent trenches 200 is an active region. The fabrication method of the semiconductor device includes the following steps: first, filling the mask layer 101 and the surface of the trenches 200 with an oxide layer 201, wherein the oxide layer 201 covers the mask layer 101; then annealing the oxide layer 201; and finally planarizing the oxide layer 201 to the surface of the mask layer 101. This related technology, by annealing the oxide layer 201 filling the trenches 200, can improve the density of the oxide layer 201, reduce defects within the oxide layer 201, and improve the isolation effect of the oxide layer 201. In the semiconductor devices of the related technology, the width of the active region is comparable to or greater than the width of the trench 200. This allows for greater resistance to stress from the oxide layer 201 on the active region, preventing bending issues. However, the fin width of a fin field-effect transistor is less than or equal to 10 nm, which is much smaller than the width of the active region in the related technology. If the trench 200 of the fin field-effect transistor is isolated using the related technology, the thermal stress on the fin from the oxide layer during annealing, as well as the fin's own shrinkage, can cause bending deformation of the fin. Therefore, the fabrication method of the semiconductor devices in the related technology is not suitable for fin field-effect transistors with a fin width less than or equal to 10 nm.

[0049] To address the technical problem that the aforementioned semiconductor device fabrication methods are not applicable to fin field-effect transistors with fin widths less than or equal to 10 nm, and that the thermal stress of the oxide layer on the fin and its own shrinkage can lead to fin bending deformation, this invention proposes a semiconductor device fabrication method. This method primarily reduces the stress of the first dielectric layer 202 on the fin 204 by controlling the thickness of the deposited first dielectric layer 202 to be less than the depth of the trench 200. This reduces or even eliminates fin bending deformation, thereby improving the electrical performance and yield of the semiconductor device.

[0050] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the following description is provided in conjunction with the accompanying drawings. Figures 2(a)-2(c) The figures and diagrams provide a detailed description of specific embodiments of the present invention.

[0051] Please refer to Figure 2(a). This embodiment of the invention provides a method for fabricating a semiconductor device. The semiconductor device includes a substrate 100, which has a plurality of trenches 200. The number of trenches 200 can be one, two, or other; for example, as shown in Figure 2, the number of trenches 200 is nine. Fins 204, also known as active regions, are formed on the substrate 100 between adjacent trenches 200. That is, fins 204 are formed on the sidewalls of the trenches 200, and a mask layer 101 is provided at the upper end of the fins 204. The plurality of trenches 200 are formed by sequentially etching the mask layer 101 and a portion of the thickness of the substrate 100. See Figure 2(b) and... Figure 3 The preparation method includes the following steps:

[0052] S100, First deposition step: Deposit a first dielectric layer 202 in the trench 200. The thickness h1 of the first dielectric layer 202 is less than the depth h2 of the trench 200. It should be noted that the first dielectric layer 202 can be a silicon oxide layer. The first deposition step can be carried out using a fluid chemical vapor deposition process. The thickness h1 of the first dielectric layer 202 depends on the width X of the fin 204, and the thickness h1 of the first dielectric layer 202 can be selected based on the width X of the fin 204.

[0053] S200, First Annealing Step: Annealing is performed on the semiconductor device with the first dielectric layer 202 deposited thereon to improve the density of the first dielectric layer 202, reduce the internal defects of the first dielectric layer 202, and improve the isolation effect of the first dielectric layer 202.

[0054] Taking a fin field-effect transistor as an example, this embodiment of the invention provides a method for fabricating a semiconductor device. First, a first dielectric layer 202 of a certain thickness is deposited at the bottom of a trench 200. Then, the fin field-effect transistor with the deposited first dielectric layer 202 is annealed. The shrinkage of the first dielectric layer 202 causes stress to form between the first dielectric layer 202 and the fin 204. By limiting the thickness of the first dielectric layer 202 to be less than the depth of the trench 200, the contact area between the first dielectric layer 202 and the sidewall of the trench 200 can be reduced, while simultaneously reducing the stress of the first dielectric layer 202 on the fin 204. This reduces or even avoids bending deformation of the fin 204, thereby improving the electrical performance of the semiconductor device and increasing its yield.

[0055] In this embodiment of the invention, both the first deposition step and the first annealing step have one or more steps. When there are multiple steps, the first deposition step and the first annealing step are performed alternately. With this configuration, the alternating first deposition step and the first annealing step can release the residual stress of the first dielectric layer 202 layer by layer.

[0056] During the annealing process of the fin field-effect transistor with the first dielectric layer 202 deposited at the bottom of the trench 200, the first dielectric layer 202 shrinks, which can cause gaps to form between the first dielectric layer 202 and the fin 204 or inside the first dielectric layer 202. To eliminate these gaps, this embodiment of the invention performs a second deposition step and a second annealing step after the first annealing step, as follows:

[0057] In this embodiment of the invention, see Figure 2(c) and Figure 3 After the first annealing step, the preparation method also includes the following steps:

[0058] S300, Second deposition step: Deposit a second dielectric layer 203 in the trench 200. The second dielectric layer 203 covers the upper surface of the first dielectric layer 202 and is higher than the upper surface of the mask layer 101, that is, the second dielectric layer 203 covers the mask layer 101. It should be noted that the second deposition step can be carried out using a fluid chemical vapor deposition process, and the second dielectric layer 203 can be a silicon oxide layer.

[0059] S400, Second Annealing Step: Annealing is performed on the semiconductor device with the second dielectric layer 203 deposited thereon to improve the density of the second dielectric layer 203, reduce the internal defects of the second dielectric layer 203, and improve the isolation effect of the second dielectric layer 203.

[0060] In this embodiment of the invention, both the second deposition step and the second annealing step have one or more steps. When there are multiple steps, the second deposition step and the second annealing step are performed alternately. With this configuration, the alternating second deposition step and the second annealing step can release the residual stress of the second dielectric layer 203 layer by layer.

[0061] This invention provides a method for fabricating a semiconductor device. Based on a first deposition step and a first annealing step, a second deposition step and a second annealing step are performed. The second dielectric layer 203 can fill the voids between the first dielectric layer 202 and the fin 204, or fill the voids inside the first dielectric layer 202. This improves the density of the interface between the first dielectric layer 202 and the fin 204, or improves the density inside the first dielectric layer 202, thereby suppressing the diffusion of doped ions from the substrate 100 into the trenches through the voids. The first dielectric layer 202 in 200 reduces leakage current, thereby improving the electrical performance of the fin field-effect transistor. In addition, the fin field-effect transistor with the first dielectric layer 202 deposited is first annealed to release the stress on the bottom end of the fin 204 by the first dielectric layer 202. Then, the fin field-effect transistor with the second dielectric layer 203 deposited is annealed to reduce the stress on the fin 204 by the first dielectric layer 202 and the second dielectric layer 203, thereby reducing or even avoiding bending deformation of the fin 204.

[0062] In this embodiment of the invention, the ratio K of the thickness h1 of the first dielectric layer 202 to the depth h2 of the trench 200 is between 20% and 80%. It should be noted that the ratio K of the thickness h1 of the first dielectric layer 202 to the depth h2 of the trench 200 depends on the width X of the fin 204; for example, the smaller the width X of the fin 204, the smaller the ratio K of the thickness h1 of the first dielectric layer 202 to the depth h2 of the trench 200.

[0063] In this embodiment of the invention, the upper end of the fin 204 is smaller than the lower end of the fin 204, and the upper end of the fin 204 is much smaller than the opening size of the upper end of the trench 200. With this configuration, when the fin field-effect transistor with the first dielectric layer 202 deposited is annealed, the first dielectric layer 202 shrinks, generating stress on the bottom end of the fin 204. Because the lower end of the fin 204 is large, the structural rigidity of the fin field-effect transistor can be increased, reducing the risk of deformation of the fin 204 due to the stress on the bottom end of the fin 204 caused by the first dielectric layer 202 during annealing.

[0064] In this embodiment of the invention, referring to Figure 2(a), from top to bottom, the size of the fin 204 remains constant initially and then gradually increases; that is, the fin 204 includes a straight segment and an arc segment. Correspondingly, from top to bottom, the size of the groove 200 remains constant initially and then gradually decreases; that is, the groove 200 is a U-shaped groove, and the bottom of the U-shaped groove is an arc groove. This configuration, with the arc segment of the fin 204, can reduce stress concentration at the bottom of the fin 204, thereby reducing the risk of fracture at the bottom of the fin 204; correspondingly, the bottom of the U-shaped groove is an arc groove, which can reduce the probability of void formation during the filling of the first dielectric layer 202, improving the quality of the isolation interface between the first dielectric layer 202 and the groove 200.

[0065] See appendix Figure 4 In this embodiment of the invention, S200, the first annealing step includes:

[0066] S210, Curing Pretreatment Stage: Under an inert gas atmosphere, UV light is used to cure for the first duration t1;

[0067] S220, Stress relief and structural reorganization stage: Under a water vapor atmosphere, the temperature is raised from the first temperature T1 to the second temperature T2 at a first heating rate K1, and held for a second duration t2.

[0068] S230, Densification Stage: Under an inert gas atmosphere, the temperature is increased from a second temperature T2 to a third temperature T3 at a second heating rate K2, and held at that temperature for a third time t3. This setup first cures the first dielectric layer 202 with ultraviolet light; then annealing is performed in a moisture atmosphere to eliminate residual stress in the first dielectric layer 202 inside the fin field-effect transistor; finally, annealing is performed in an inert gas atmosphere to promote grain boundary migration and macroscopic densification inside the fin field-effect transistor, releasing residual stress from macroscopic densification, enabling the fin field-effect transistor to reach a steady-state densified structure, suppressing subsequent deformation or stress rebound, improving the mechanical properties of the fin field-effect transistor, and reducing the stress of the first dielectric layer 202 on the fin 204.

[0069] See appendix Figure 5 In this embodiment of the invention, S400, the second annealing step includes:

[0070] S410, Curing Pretreatment Stage: Under an inert gas atmosphere, such as argon, nitrogen or other inert gases, air and oxygen in the annealing chamber can be effectively removed to prevent the semiconductor device from being oxidized. The first curing time is achieved using ultraviolet light.

[0071] S420, Stress Relief and Structural Reorganization Stage: Under a water vapor atmosphere, the temperature is increased from a first temperature to a second temperature at a first heating rate, and held at that temperature for a second duration;

[0072] S430, Densification Stage: Under an inert gas atmosphere, the temperature is increased from the second temperature to the third temperature at a second heating rate, and held at that temperature for a third duration. This setup first cures the second dielectric layer 203 with ultraviolet light; then annealing is performed in a moisture atmosphere to eliminate residual stress inside the fin field-effect transistor; finally, annealing is performed in an inert gas atmosphere to promote grain boundary migration and macroscopic densification inside the fin field-effect transistor, releasing residual stress from macroscopic densification, enabling the fin field-effect transistor to reach a steady-state densified structure, suppressing subsequent deformation or stress rebound, improving the mechanical properties of the fin field-effect transistor, and reducing or even avoiding stress on the fin 204 caused by the second dielectric layer 203.

[0073] In this embodiment of the invention, for the first and second annealing steps, the stress release and structural reorganization stage is a stepped heating stage, which has N sub-heating stages, where N ≥ 2. For example, N can be 2, 3, 4, or other numbers. For example, as shown in the figure, N is 4. This configuration, through stepped heating, avoids lattice abrupt changes caused by sudden temperature variations, thus homogenizing the temperature gradient inside the fin field-effect transistor, effectively reducing thermal stress concentration, and thereby reducing the risk of cracking in the fin field-effect transistor.

[0074] In this embodiment of the invention, the sub-heating stage includes the following steps:

[0075] For each sub-temperature increase ΔT, a fourth holding time t4 is performed; where sub-temperature = second temperature - first temperature / N. For example, the second temperature T2 is 600℃, the first temperature T1 is 200℃, N is 2, and the sub-temperature ΔT is 200℃. This setup ensures that each sub-temperature increase stage is held for a fourth time t4, resulting in a more uniform temperature within the annealing chamber, reducing internal temperature differences in the fin field-effect transistor, and improving the consistency of fin field-effect transistor performance.

[0076] In this embodiment of the invention, the process parameters of the curing pretreatment stage include: first duration, power, ambient pressure and inert gas flow rate; wherein, the first duration t1 is between 10s and 1000s, the power P is between 0 and 80%, the ambient pressure p is between 0 and 500 torr, and the inert gas flow rate Q is between 0 and 50000 sccm.

[0077] In this embodiment of the invention, the first temperature T1 ranges from 150°C to 250°C. Preferably, the first temperature T1 can be 200°C.

[0078] In this embodiment of the invention, the second temperature T2 ranges from 550℃ to 800℃; the second duration t2 ranges from 10min to 120min. Preferably, the second temperature T1 can be 600℃.

[0079] In this embodiment of the invention, the third temperature T3 ranges from 800℃ to 1200℃; the third duration t3 ranges from 10min to 120min. Preferably, the second temperature T3 can be 1000℃.

[0080] In this embodiment of the invention, the first heating rate K1 ranges from 3 to 15 °C / min.

[0081] In this embodiment of the invention, the second heating rate K2 ranges from 3 to 15 °C / min.

[0082] Referring to Figure 2(a), in this embodiment of the invention, a transition layer 102 is provided between the substrate 100 and the mask layer 101. This arrangement is used to balance the stress between the substrate 100 and the mask layer 101.

[0083] In this embodiment of the invention, the distance d between the upper surface of the second dielectric layer 203 and the upper surface of the mask layer 101 is between 500 Å and 600 Å; after the second annealing step, the preparation method further includes the following steps: planarization treatment: the second dielectric layer 203 is planarized.

[0084] In this embodiment of the invention, the process parameters of the fluid chemical vapor deposition process include: deposition pressure, deposition temperature, argon flow rate, oxygen flow rate, helium flow rate, ammonia flow rate, and trimethylsilylamine flow rate; wherein, the deposition pressure ranges from 0.1 to 200 torr; the deposition temperature ranges from 20°C to 200°C; the argon flow rate ranges from 0 to 10000 sccm; the oxygen flow rate ranges from 0 to 1000 sccm; the trimethylsilylamine flow rate ranges from 0 to 1800 sccm; the helium flow rate ranges from 0 to 9000 sccm; and the ammonia flow rate ranges from 0 to 2000 sccm.

[0085] In summary, compared with the related techniques that involve covering the mask layer 101 with a first dielectric layer 202, then annealing the first dielectric layer 202, and finally planarizing the first dielectric layer 202 to the surface of the mask layer 101 to isolate fin field-effect transistors with a fin width less than or equal to 10 nm using trench 200, the semiconductor device fabrication method provided in this embodiment of the invention, through step-by-step deposition and annealing, first anneals the fin field-effect transistor with the first dielectric layer 202 deposited thereon, and then planarizes the first dielectric layer 202 to the surface of the mask layer 101 to isolate the fin field-effect transistor with a fin width less than or equal to 10 nm using trench 200. The stress at the bottom of 204 is released; then, the fin field-effect transistor with the second dielectric layer 203 deposited is annealed, and the stress on the fin 204 by the first dielectric layer 202 and the second dielectric layer 203 is reduced, thereby reducing or even avoiding bending deformation of the fin 204; in addition, the second dielectric layer 203 can fill the gap between the first dielectric layer 202 and the fin 204 or the gap inside the first dielectric layer 202 to improve the compactness inside the first dielectric layer 202, thereby improving the electrical performance of the fin field-effect transistor.

[0086] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The semiconductor device includes a substrate (100) having a plurality of trenches (200), the trenches (200) being U-shaped trenches with a circular arc bottom, the substrate (100) between adjacent trenches (200) forming fins (204), the upper end of the fins (204) being smaller than the lower end of the fins (204), and the upper end of the fins (204) being much smaller than the opening size of the upper end of the trenches (200), the upper end of the fins (204) having a mask layer (101). The preparation method includes the following steps: First deposition step: Deposit a first dielectric layer (202) in the trench (200), wherein the thickness of the first dielectric layer (202) is less than the depth of the trench (200); First annealing step: Annealing the semiconductor device on which the first dielectric layer (202) is deposited; Second deposition step: Deposit a second dielectric layer (203) in the trench (200), the second dielectric layer (203) covering the upper surface of the first dielectric layer (202) and being higher than the upper surface of the mask layer (101); Second annealing step: Annealing the semiconductor device on which the second dielectric layer (203) is deposited.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The ratio of the thickness of the first dielectric layer (202) to the depth of the trench (200) is between 20% and 80%.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first annealing step includes: Curing pretreatment stage: Under an inert gas atmosphere, ultraviolet light is used for the first curing time; Stress relief and structural reorganization stage: Under a water vapor atmosphere, the temperature is increased from a first temperature to a second temperature at a first heating rate, and held at that temperature for a second duration; Densification stage: Under an inert gas atmosphere, the temperature is increased from the second temperature to the third temperature at a second heating rate, and held at that temperature for a third duration.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The second annealing step includes: Curing pretreatment stage: Under an inert gas atmosphere, ultraviolet light is used for the first curing time; Stress relief and structural reorganization stage: Under a water vapor atmosphere, the temperature is increased from a first temperature to a second temperature at a first heating rate, and held at that temperature for a second duration; Densification stage: Under an inert gas atmosphere, the temperature is increased from the second temperature to the third temperature at a second heating rate, and held at that temperature for a third duration.

5. The method for fabricating a semiconductor device according to claim 3 or 4, characterized in that, The stress release and structural reorganization stage is a stepped heating stage, which has N sub-heating stages, where N≥2.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The sub-heating stage includes the following steps: For each increase in sub-temperature, the temperature is maintained for a fourth time; wherein, the sub-temperature = (second temperature - first temperature) / N.

7. The method for fabricating a semiconductor device according to claim 3 or 4, characterized in that, The process parameters of the curing pretreatment stage include: first duration, power, ambient pressure, and inert gas flow rate; wherein, the first duration is between 10s and 1000s, the power is between 0 and 80%, the ambient pressure is between 0 and 500 torr, and the inert gas flow rate is between 0 and 50000 sccm. And / or, the value of the first temperature is between 150℃ and 250℃; And / or, the second temperature ranges from 550℃ to 800℃; the second duration ranges from 10min to 120min; And / or, the value of the third temperature is between 800℃ and 1200℃; the value of the third duration is between 10min and 120min.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, A transition layer (102) is provided between the substrate (100) and the mask layer (101). And / or, the first deposition step employs a fluid chemical vapor deposition process; And / or, both the first deposition step and the first annealing step have one or more steps. When there are multiple steps, the first deposition step and the first annealing step are performed alternately in sequence. And / or, the first dielectric layer (202) is a silicon oxide layer.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The distance between the upper surface of the second dielectric layer (203) and the upper surface of the mask layer (101) is between 500 Å and 600 Å; after the second annealing step, the preparation method further includes the following steps: planarization treatment: the second dielectric layer (203) is planarized; And / or, the second deposition step employs a fluid chemical vapor deposition process; And / or, both the second deposition step and the second annealing step have one or more steps. When there are multiple steps, the second deposition step and the second annealing step are performed alternately in sequence. And / or, the second dielectric layer (203) is a silicon oxide layer.

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