Power switch device structure and preparation method thereof

Abstract

The invention provides a power switch device structure and a preparation method thereof, a device electrode structure and an edge terminal structure surrounding the device electrode structure are arranged in a first conductive type drift region, and a first polycrystalline silicon layer in the device electrode structure and a potential fixing layer in the edge terminal structure are correspondingly arranged; the first polycrystalline silicon layer is electrically connected with the corresponding potential fixing layer, so that the potential of each first polycrystalline silicon layer in the device electrode structure is determined through the potential of the potential fixing layer in the edge terminal structure; each potential fixing layer is connected with one edge electrode structure, and the arrangement of the second polycrystalline silicon layer below the second polycrystalline silicon layer at the top in the edge electrode structure is the same as the arrangement of the first polycrystalline silicon layer below the first polycrystalline silicon layer corresponding to the potential fixing layer connected with the edge electrode structure, so that the two-dimensional electric field effect can be enhanced; and the process is simple and feasible.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power switch device structure and a preparation method thereof. Background Art

[0002] The structure of all power switching devices includes a drift region that can withstand a blocking voltage. Research has found that a two-dimensional electric field can be generated by setting segmented electrodes in the trench, which can be applied to high-voltage devices. However, in order to ensure that the required potential in each electrode segment is fixed under the condition of a certain blocking voltage, the area of ​​each electrode segment (referring to the surface area of ​​the electrode segment perpendicular to the thickness direction) needs to be much larger than the thickness of the isolation oxide layer between two adjacent electrode segments. This will increase the size of the device and thus increase the device cost. In order to reduce the size of the device, a solution can be adopted that combines a segmented electrode structure in the device trench with a PN junction. The potential of the PN junction determines the potential at each electrode segment in the device trench structure. However, because this solution reduces the two-dimensional electric field effect used to increase the breakdown voltage, this structure requires reducing the doping concentration in the drift region in the PN junction area to reduce the impact on the two-dimensional electric field effect. This will result in different doping concentrations in the drift region in the device trench structure and the PN junction area. Since the drift region is relatively thick, it needs to be formed through multiple deposition and ion implantation processes. Therefore, when the doping concentrations in the drift region where the device trench structure is located and the PN junction are located are different, the process becomes very difficult. Summary of the Invention

[0003] The object of the present invention is to provide a power switch device structure and a preparation method thereof, so as to reduce the size of the power switch device structure, enhance the two-dimensional electric field effect, and have a simple and easy process.

[0004] In order to achieve the above-mentioned object and other related objects, the present invention provides a power switch device structure, comprising:

[0005] a first metal layer;

[0006] a semiconductor substrate, located on the first metal layer;

[0007] A first conductive type drift region is located on the semiconductor substrate;

[0008] At least one device electrode structure is spaced apart and arranged in the first conductive type drift region, each of the device electrode structures includes a device trench structure and at least two first polysilicon layers spaced apart and arranged in the device trench structure along a direction perpendicular to the semiconductor substrate;

[0009] an edge terminal structure disposed around all device electrode structures, the edge terminal structure comprising a plurality of potential fixing layers spaced apart along a direction pointing from the center of the semiconductor substrate toward the edge, and a plurality of edge electrode structures located in the first conductivity type drift region, the potential fixing layers corresponding to the first polysilicon layers in the device trench structures, each of the potential fixing layers being connected to one of the edge electrode structures, each of the edge electrode structures comprising an edge trench structure and at least one second polysilicon layer spaced apart in the edge trench structure along a direction perpendicular to the semiconductor substrate, the second polysilicon layer below the top second polysilicon layer in the edge electrode structure being arranged in the same manner as the first polysilicon layer below the first polysilicon layer corresponding to the potential fixing layer connected to the edge electrode structure;

[0010] an electrical connection layer, located between the first polysilicon layer in the device trench structure and the corresponding potential fixing layer, so as to achieve electrical connection between the first polysilicon layer in the device trench structure and the corresponding potential fixing layer;

[0011] The second metal layer is located on the first polysilicon layer at the top of each device trench structure.

[0012] Optionally, in the power switching device structure, the device electrode structure also includes a first isolation oxide layer, which is located between adjacent first polysilicon layers and between the first polysilicon layer and the device trench structure; the edge electrode structure also includes a second isolation oxide layer, which is located between adjacent second polysilicon layers and between the second polysilicon layer and the edge trench structure; the isolation oxide layer under the top second polysilicon layer in the edge electrode structure is set the same as the isolation oxide layer under the first polysilicon layer corresponding to the potential fixed layer connected to the edge electrode structure.

[0013] Optionally, in the power switching device structure, the power switching device structure also includes a top oxide layer located on the first conductive type drift region on one side of each edge trench structure and connected to the second isolation oxide layer, and the second polysilicon layer at the top of the edge trench structure also extends to a portion of the surface of the top oxide layer.

[0014] Optionally, in the power switch device structure, the longer the distance between two adjacent potential fixing layers is, the greater the potential difference therebetween is.

[0015] Optionally, in the power switch device structure, each of the potential fixing layers is annular and surrounds all device trench structures.

[0016] Optionally, in the power switching device structure, the potential fixing layer includes a top structure or a combination of a top structure and a second conductive type injection region, the top structure includes at least one of a third polysilicon layer, a first Schottky contact structure, and an ohmic contact metal layer, and the potential of each of the potential fixing layers is equal to the potential required by the corresponding first polysilicon layer in the device trench structure.

[0017] Optionally, in the power switching device structure, the second conductive type injection region is located on the first conductive type drift region and is adjacent to the edge trench structure, and the top structure is located on the second polysilicon layer at the top of the edge trench structure. When the potential fixing layer is a combination of the top structure and the second conductive type injection region, the top structure also extends to a portion of the surface of the second conductive type injection region; when the potential fixing layer is the top structure, the top structure also extends to a portion of the surface of the first conductive type drift region.

[0018] Optionally, in the power switch device structure, the first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.

[0019] Optionally, in the power switching device structure, when there are multiple device trench structures, the multiple device trench structures are arranged in parallel along the first direction, and at least one side of each first polysilicon layer in each device trench structure in the second direction is electrically connected to the potential fixing layer in the corresponding edge terminal structure, the first direction is perpendicular to the second direction, and the plane in which the first direction and the second direction are located is parallel to the upper surface of the semiconductor substrate.

[0020] Optionally, in the power switching device structure, the electrical connection layer electrically connects the first polysilicon layer to all second polysilicon layers having the same potential as that required by the first polysilicon layer.

[0021] Optionally, in the power switch device structure, the power switch device structure further includes a second conductivity type doped region located on the first conductivity type drift region between adjacent device trench structures.

[0022] Optionally, in the power switching device structure, the power switching device structure also includes a second conductive type doped region located on the first conductive type drift region between adjacent device trench structures, a first conductive type source region located on the second conductive type doped region, and a gate oxide layer, a gate electrode, and a dielectric layer located in sequence between the polysilicon layer at the top of each device trench structure and the second metal layer.

[0023] Optionally, in the power switching device structure, the power switching device structure also includes a second Schottky contact structure and an insulating dielectric layer located on the first conductive type drift region between adjacent device trench structures, and the insulating dielectric layer also covers the side of the second Schottky contact structure.

[0024] Optionally, in the power switching device structure, the electrical connection layer includes a polysilicon wire of a first conductivity type and an insulating layer wrapping the polysilicon wire of the first conductivity type.

[0025] In order to achieve the above-mentioned object and other related objects, the present invention further provides a method for preparing a power switching device structure, comprising the following steps:

[0026] providing a semiconductor substrate;

[0027] forming a first conductivity type drift region on the semiconductor substrate;

[0028] forming at least one device electrode structure and an edge termination structure surrounding all device trench structures in the first conductive type drift region, each device electrode structure comprising a device trench structure and at least two first polysilicon layers spaced apart in each device trench structure along a direction perpendicular to the semiconductor substrate; the edge termination structure comprising a plurality of potential fixing layers spaced apart in a direction from the center to the edge of the semiconductor substrate and a plurality of edge electrode structures located in the first conductive type drift region, the potential fixing layers corresponding to the first polysilicon layers in the device trench structures, each of the potential fixing layers being connected to one edge electrode structure; each edge electrode structure comprising an edge trench structure and at least one second polysilicon layer spaced apart in the edge trench structure along a direction perpendicular to the semiconductor substrate, the second polysilicon layer below the top second polysilicon layer in the edge electrode structure being arranged in the same manner as the first polysilicon layer below the first polysilicon layer corresponding to the potential fixing layer connected to the edge electrode structure;

[0029] forming an electrical connection layer between the first polysilicon layer in the device trench structure and the corresponding potential fixing layer to achieve electrical connection between the first polysilicon layer in the device trench structure and the corresponding potential fixing layer;

[0030] A second metal layer is formed on the first polysilicon layer, and a first metal layer is formed on the lower surface of the semiconductor substrate.

[0031] Optionally, in the method for preparing the power switching device structure, the device electrode structure further includes a first isolation oxide layer, the first isolation oxide layer being located between adjacent first polysilicon layers and between the first polysilicon layer and the device trench structure; the edge electrode structure further includes a second isolation oxide layer, the second isolation oxide layer being located between adjacent second polysilicon layers and between the second polysilicon layer and the edge trench structure; and the step of forming at least one device electrode structure and an edge terminal structure surrounding all device trench structures includes:

[0032] forming at least one device trench structure and an edge trench structure in the first conductive type drift region, wherein the edge trench structure surrounds all the device trench structures;

[0033] Alternatingly forming the first polysilicon layer and the first isolation oxide layer on the bottom surface of each of the device trench structures, and simultaneously alternatingly forming the second polysilicon layer and the second isolation oxide layer on the bottom surface of each of the edge trench structures;

[0034] A potential fixing layer is formed corresponding to the first polysilicon layer in the device trench structure.

[0035] Optionally, in the method for preparing the power switching device structure, in the step of alternately forming the second polysilicon layer and the second isolation oxide layer on the bottom surface of each of the edge trench structures, a top oxide layer is also formed on the first conductive type drift region on one side of each of the edge trench structures, and the top oxide layer is connected to the second isolation oxide layer.

[0036] Optionally, in the method for preparing the power switching device structure, a reactive ion etching process is used to form the device trench structure and the edge trench structure; and a thermal oxidation process or a CVD process is used to form the first isolation oxide layer, the second isolation oxide layer and the top oxide layer.

[0037] Optionally, in the preparation method of the power switching device structure, after the step of forming at least one device electrode structure and an edge terminal structure surrounding all device trench structures in the first conductive type drift region, the preparation method also includes: forming a second Schottky contact structure and an insulating dielectric layer on the first conductive type drift region between adjacent device trench structures, and the insulating dielectric layer also covers the side of the second Schottky contact structure.

[0038] Optionally, in the preparation method of the power switching device structure, after the step of forming at least one device electrode structure and an edge terminal structure surrounding all device trench structures in the first conductive type drift region, the preparation method also includes: forming a second conductive type doping region on the first conductive type drift region between adjacent device trench structures.

[0039] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0040] In a power switching device structure and preparation method provided by the present invention, a device electrode structure and an edge terminal structure are provided simultaneously. The first polysilicon layer in the device electrode structure and the potential fixing layer in the edge terminal structure are provided correspondingly, and the first polysilicon layer and the corresponding potential fixing layer are electrically connected via an electrical connection layer. The potential of each first polysilicon layer in the device electrode structure is determined by the potential of the potential fixing layer in the edge terminal structure. This can reduce the area of ​​the first polysilicon layer in the device electrode structure, thereby reducing the size of the power switching device structure and reducing its cost.

[0041] Furthermore, the edge termination structure of the present invention also includes an edge electrode structure connected to each of the potential-fixed layers. This edge electrode structure is used to generate a two-dimensional electric field, ensuring uniform distribution of the two-dimensional electric field in the vertical direction. As a result, the doping concentration of the first conductivity type drift region in the region where the edge termination structure and the device electrode structure are located can be the same, simplifying the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a schematic structural diagram of a power switch device structure in an embodiment of the present invention, in which the top structure is a third polysilicon layer;

[0043] Figure 2 This is a schematic structural diagram of a power switch device structure in an embodiment of the present invention, in which the top structure is an ohmic contact metal layer;

[0044] Figure 3 This is a schematic structural diagram of a power switch device structure in an embodiment of the present invention, in which the top structure is a combination of an ohmic contact metal layer and a Schottky contact structure;

[0045] Figure 4 This is a schematic structural diagram of a power switch device structure according to an embodiment of the present invention in which a second conductive type injection region is not provided;

[0046] Figure 5 A schematic structural diagram of a power switch device structure according to another embodiment of the present invention;

[0047] Figure 6This is a schematic structural diagram of a power switch device structure according to another embodiment of the present invention in which a second conductive type injection region is not provided;

[0048] Figure 7 FIG. 1 is a schematic structural diagram of a power switch device structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following is a detailed description of a power switching device structure proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0050] See Figures 1 to 7 , the power switch device structure of this embodiment may include:

[0051] a first metal layer 131;

[0052] a semiconductor substrate 11 located on the first metal layer 131;

[0053] A first conductive type drift region 12 is located on the semiconductor substrate 11;

[0054] At least one device electrode structure is spaced apart in the first conductive type drift region 12, each of the device electrode structures comprising a device trench structure 141 and at least two first polysilicon layers 151 spaced apart in the device trench structure 141 along a direction perpendicular to (the upper surface of) the semiconductor substrate 11 (i.e., the y-direction);

[0055] an edge terminal structure disposed around all device electrode structures, and comprising a plurality of potential fixing layers spaced apart in a direction from the center of the semiconductor substrate 11 to the edge thereof, and a plurality of edge electrode structures located in the first conductive type drift region 12, wherein the potential fixing layers correspond to the first polysilicon layer 151 in the device trench structure 141, and each of the potential fixing layers is connected to one of the edge electrode structures. Each of the edge electrode structures comprises an edge trench structure 142 and at least one second polysilicon layer 152 spaced apart in the edge trench structure 142 along a direction perpendicular to the semiconductor substrate 11 (y direction), wherein the arrangement of the second polysilicon layer 152 below the top second polysilicon layer 152 in the edge electrode structure is the same as the arrangement of the first polysilicon layer 151 below the first polysilicon layer 151 corresponding to the potential fixing layer connected to the edge electrode structure;

[0056] an electrical connection layer, located between the first polysilicon layer 151 in the device trench structure 141 and the corresponding potential fixing layer, so as to achieve electrical connection between the first polysilicon layer 151 in the device trench structure 141 and the corresponding potential fixing layer;

[0057] The second metal layer 132 is located on the first polysilicon layer 151 at the top of each device trench structure 141 .

[0058] In this embodiment, the first metal layer 131 may be a drain metal layer, and the material of the first metal layer 131 may be a conventional electrode material, such as Ti (titanium), Ni (nickel) and Pt (platinum), but is not limited thereto.

[0059] The second metal layer 132 is electrically connected to the first polysilicon layer 151 at the top of the device trench structure 141. The second metal layer 132 can be a source metal layer, but is not limited thereto. The material of the second metal layer 132 can be a conventional electrode material, such as Ti (titanium), Ni (nickel), and Pt (platinum), but is not limited thereto.

[0060] In this embodiment, the first metal layer 131 and the second metal layer 132 can be prepared by using a conventional electrode formation process, which will not be described in detail here.

[0061] The semiconductor substrate 11 is located on the first metal layer 131, and the semiconductor substrate 11 is preferably a semiconductor substrate of the first conductivity type. In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type; alternatively, the first conductivity type is p-type and the second conductivity type is n-type. The following content is explained using the example of the first conductivity type being n-type and the second conductivity type being p-type. That is, in this embodiment, the semiconductor substrate of the first conductivity type is an n-type semiconductor substrate, and is preferably a heavily doped n-type semiconductor substrate. Its doping concentration can be set according to the semiconductor substrate of the power switching device in the prior art, which is not described in detail here.

[0062] The first conductive type drift region 12 is located on the semiconductor substrate 11. The material of the first conductive type drift region 12 is preferably single crystal silicon, but is not limited thereto. The thickness of the first conductive type drift region 12 depends on the blocking voltage. The higher the required blocking voltage, the greater the thickness of the first conductive type drift region 12. For example, the thickness of the first conductive type drift region 12 required to achieve a blocking voltage of 400V is at least 20 microns. Therefore, the thickness of the first conductive type drift region 12 can be set according to the blocking voltage requirement. In this embodiment, the first conductive type drift region 12 is an n-type drift region, which is doped with n-type ions, such as phosphorus. Since this embodiment forms an edge electrode structure connected to the potential fixing layer while forming the potential fixing layer, it does not cause a reduction in the two-dimensional electric field effect, nor does it need to reduce the doping concentration of the first conductive type drift region 12 in the area where the potential fixing layer is located. Therefore, the ion doping concentration in the first conductive type drift region of this embodiment is the same, and the problem of reducing the two-dimensional electric field effect does not occur. The doping concentration and formation process of the n-type ions in the first conductive type drift region in this embodiment can adopt the doping concentration and formation process in the drift region of the power switch device in the prior art, which will not be described in detail here.

[0063] The number of the device electrode structures is at least one, preferably multiple. All the device trench structures 14 are spaced apart in the first conductive type drift region 12. When the number of the device electrode structures is multiple, the multiple device trench structures 14 are arranged in parallel along the first direction (i.e., the x-direction). Each of the device electrode structures includes a device trench structure 141 and at least two first polysilicon layers 151 spaced apart in the device trench structure 141 along a direction perpendicular to the semiconductor substrate 11 (i.e., the y-direction). The depths of all device trench structures 14 are preferably the same; the lengths in the second direction can be the same or different, preferably the same; the lengths in the first direction can be the same or different, preferably the same; and the spacing distances between adjacent device trench structures are also preferably the same. The first direction (x-direction) is perpendicular to the second direction, and the planes in which the first and second directions lie are parallel to the upper surface of the semiconductor substrate 11, and the y-direction is perpendicular to the upper surface of the semiconductor substrate 11.

[0064] In this embodiment, the depth of each device trench structure 14 is less than the depth of the first conductive type drift region 12, that is, there is a small space between the bottom surface of each device trench structure 14 and the bottom surface of the first conductive type drift region 12. The depth of each device trench structure 14 can be obtained according to the following formula: each trench structure depth t = BV / Ec, where BV is the breakdown voltage and Ec is the critical electric field. The critical electric field (Ec) is a set value, which can be set according to process requirements, for example, 2×10 5 The depth of each device trench structure 14 in this embodiment must be adjusted to achieve the required breakdown voltage.

[0065] In this embodiment, a plurality of the first polysilicon layers 151 are spaced apart in each of the device trench structures 141 along a direction perpendicular to the semiconductor substrate (i.e., the y direction). At least two first polysilicon layers 151 are spaced apart in each of the device trench structures 141, and the first polysilicon layers 151 in each of the device trench structures 141 are spaced apart along a direction perpendicular to the semiconductor substrate 11. For example Figure 1 In the embodiment, four first polysilicon layers 151 are provided in each of the device trench structures 141 .

[0066] In this embodiment, the first polysilicon layer 151 can serve as an electrode segment, that is, one first polysilicon layer 151 can serve as an electrode segment. The first polysilicon layer 151 is preferably doped with first conductive type ions. That is, the material of the first polysilicon layer 151 in this embodiment is preferably highly doped n-type polysilicon, and its doping concentration can adopt the doping concentration of polysilicon layers in power switching devices in the prior art, which is not further described here.

[0067] In this embodiment, the device electrode structure may further include a first isolation oxide layer 181, and the first isolation oxide layer 181 is located between adjacent first polysilicon layers 151 and between the first polysilicon layer 151 and the device trench structure 141. Specifically, the first isolation oxide layer 181 is disposed between adjacent first polysilicon layers 151, on the bottom surface of the device trench structure 141 (i.e., between the first polysilicon layer 151 at the bottom of the device trench structure 141 and the bottom surface of the device trench structure 141), and on the side surfaces of the device trench structure 141. The first isolation oxide layer 181 located on the side surfaces and bottom surface of the device trench structure 141 isolates the first polysilicon layer 141 from the first conductivity type drift region 12.

[0068] In this embodiment, the thickness of the first isolation oxide layer 181 between two adjacent first polysilicon layers 151 is proportional to the potential difference between the two adjacent first polysilicon layers 151 to avoid exceeding the maximum electric field strength in the first isolation oxide layer 181. For example, if the required potential difference between two adjacent first polysilicon layers is 100V, the thickness of the first isolation oxide layer 181 therebetween can be 0.5μm to keep the electric field strength in the first isolation oxide layer 181 no more than 2×10 6 The potential difference between the bottom first polysilicon layer 151 and the bottom surface of the device trench structure 141 is also in the same proportional relationship as the thickness of the first isolation oxide layer 181 on the bottom surface of the device trench structure 141 .

[0069] The potential difference V between the two adjacent first polysilicon layers 151 in the device trench structure 141 (or the bottom first polysilicon layer 151 and the bottom surface of the device trench structure 141) 器 =h 器 / h 器总 ×V 器阻总 , where h 器 h is the thickness of the first isolation oxide layer 181 between the two adjacent first polysilicon layers 151 (or the bottom first polysilicon layer 151 and the bottom surface of the device trench structure 141); 器总 V is the sum of the thickness of the first isolation oxide layer 181 between all two adjacent first polysilicon layers 151 in the device trench structure 141 and the thickness of the first isolation oxide layer 181 on the bottom surface of the device trench structure 141; 器阻总is the blocking voltage of the device electrode structure. In this embodiment, under the condition of a certain blocking voltage, equidistant potential lines are evenly distributed in the first isolation oxide layer 181 between two adjacent first polysilicon layers 151 and in the first isolation oxide layer 181 on the bottom surface of the device trench structure 141. For example, for a blocking voltage of 400V and a desired potential difference between two adjacent first polysilicon layers 151 equal to 200V, two first polysilicon layers 151 need to be provided in the device trench structure 141. This means that the desired potential difference between the two first polysilicon layers 151 in the device trench structure 141 and between the bottom first polysilicon layer 151 and the bottom surface of the device trench structure 141 are the same and equal to 200V, then the thickness of the first isolation oxide layer 181 therebetween should be 1 micron, and the thickness of the first isolation oxide layer 181 on the side surfaces of the device trench structure 141 can also be 1 micron. In addition, the thickness of the first isolation oxide layer 181 on the side of the device trench structure 141 is proportional to the maximum potential difference between the two adjacent first polysilicon layers 151 to avoid exceeding the maximum electric field strength in the first isolation oxide layer 181 on the side of the device trench structure 141. For example, if the potential difference between the two adjacent first polysilicon layers 151 is exactly the same and equal to 100V, the thickness of the first isolation oxide layer 181 on the side of the device trench structure 141 can be equal to 0.5 microns to ensure that the electric field strength in the first isolation oxide layer 181 at each point on the side of the device trench structure 141 does not exceed 2×10 6 V / cm.

[0070] In this embodiment, the potential difference between the bottom first polysilicon layer 151 and the bottom surface of the device trench structure 141 is actually the potential difference between the bottom first polysilicon layer 151 and the first conductivity type drift region 12. However, the potential drop in the first conductivity type drift region 12 below the bottom surface of the device trench structure 141 is very small and can be ignored. In this embodiment, the greater the number of first polysilicon layers 151, the greater the reduction in the thickness of the first isolation oxide layer 181 therebetween.

[0071] In order to further reduce the thickness and specific on-resistance of the first isolation oxide layer 181 on the side surface of the device trench structure 141 , more first polysilicon layers 151 may be provided in the device trench structure 141 .

[0072] In this embodiment, the thinner the thickness of the first isolation oxide layer 181, the thinner the thickness of the first polysilicon layer 151 immediately adjacent to the first isolation oxide layer 181, thereby achieving a more uniform electric field distribution. This embodiment utilizes the aforementioned design scheme of providing multiple first polysilicon layers 151 in each device trench structure 141, easily generating a two-dimensional charge coupling effect without increasing the thickness of the first isolation oxide layer 181 on the side and bottom surfaces of the device trench structure. This embodiment does not increase the thickness of the first isolation oxide layer 181 on the side and bottom surfaces of the device trench structure 141 as the blocking voltage increases, thereby not increasing the specific on-resistance. Furthermore, as the number of first polysilicon layers 151 in the device trench structure 141 increases, the thickness of the first isolation oxide layer 181 on the side and bottom surfaces of the device trench structure 141 decreases, thereby reducing stress at the interface between the first conductivity type drift region 12 and the first isolation oxide layer 181, lowering the specific on-resistance, and reducing cell pitch. Therefore, the present invention can obtain a power switch device structure with high blocking voltage and low specific on-resistance.

[0073] In this embodiment, the edge termination structure is arranged in the first conductive type drift region 12 around all device electrode structures. In a top view (i.e., in a direction from the semiconductor substrate 11 to the first metal layer 131), all device trench structures 141 are arranged in the middle of the first conductive type drift region 12, and the edge termination structure is arranged at the edge of the first conductive type drift region 12. The edge termination structure may include a plurality of potential fixing layers arranged in a direction from the center of the semiconductor substrate 11 (upper surface) to the edge (upper surface of the semiconductor substrate 11) and a plurality of edge electrode structures located in the first conductive type drift region 12. The potential fixing layer corresponds to the first polysilicon layer 151 in the device trench structure 141. Each of the potential fixing layers is connected to one of the edge electrode structures, specifically, to the second polysilicon layer 152 at the top of the edge trench structure 142.

[0074] In this embodiment, different potential fixing layers have different potentials. The potential fixing layer can be a top structure or a combination of a top structure and a second conductive type injection region 161. The top structure can include at least one of a third polysilicon layer 162, a first Schottky contact structure 164, and an ohmic contact metal layer 163. The doping type and concentration in the third polysilicon layer 162 are preferably the same as those in the second polysilicon layer 152; the material of the ohmic contact metal layer 163 is preferably the same as that of the first metal layer 131, and the material of the first Schottky contact structure 164 is preferably the same as that of the second Schottky contact structure 21. The top structure is located on the second polysilicon layer 152 at the top of the edge trench structure 142. For example Figure 1 In the embodiment, the top structure is the third polysilicon layer 162, and one third polysilicon layer 162 is provided on the top second polysilicon layer 152 in each edge trench structure 142. Figure 2 In the embodiment, the top structure is an ohmic contact metal layer 163, and one ohmic contact metal layer 163 is provided on the top second polysilicon layer 152 in each edge trench structure 142. Figure 3 In the embodiment, the top structure is a combination of an ohmic contact metal layer 163 and a first Schottky contact structure 164. An ohmic contact metal layer 163 is provided on the second polysilicon layer 152 at the top of each edge trench structure 142, and the first Schottky contact structure 164 is provided on the first conductive type drift region 12 and is adjacent to the ohmic contact metal layer 163.

[0075] In this embodiment, the second conductive type injection region 161 may be provided or not provided. When the potential fixing layer is a combination of the top structure and the second conductive type injection region 161, the top structure also extends to a portion of the surface of the second conductive type injection region 161; when the potential fixing layer only includes the top structure, the top structure also extends to a portion of the surface of the first conductive type drift region 12. For example Figure 1 and Figure 2 In the embodiment, a second conductive type injection region 161 is provided on the first conductive type drift region 12, and the top structure further extends to a portion of the surface of the second conductive type injection region 161. For another example, Figure 3 and Figure 4 No second conductivity type injection region 161 is provided on the first conductivity type drift region 12, and the top structure also extends onto a portion of the surface of the first conductivity type drift region 12. In this embodiment, the second conductivity type injection region 161 is preferably provided because each second conductivity type injection region 161 forms a PN junction at its interface with the first conductivity type drift region 12, which has stronger anti-interference capabilities than the top structure.

[0076] When setting the second conductive type injection region 161, the second conductive type injection region 161 can be set on the first conductive type drift region 12, specifically on the first conductive type drift region 12 on one side of the edge trench structure 142, and adjacent to the edge trench structure 142. In this embodiment, the second conductive type injection region 161 is electrically connected to the adjacent top structure and the second polysilicon layer 152 at the top of the edge trench structure 142, and their potentials are the same. The potential of the potential fixing layer can be the potential of the PN junction. The potential of each PN junction is equal to the potential required by the first polysilicon layer 151 in the corresponding device trench structure 141. For example Figure 1 In the embodiment, the PN junction with a potential of 100 V corresponds to the first polysilicon layer 151 with a required potential of 100 V in the device trench structure 141; the PN junction with a potential of 200 V corresponds to the first polysilicon layer 151 with a required potential of 200 V in the device trench structure 141; and the PN junction with a potential of 300 V corresponds to the first polysilicon layer 151 with a required potential of 300 V in the device trench structure 141.

[0077] In this embodiment, the second conductive type implantation region 161 is doped with second conductive type ions, such as boron ions, and the ion doping concentration of the second conductive type implantation region 161 is preferably 10 18 cm -3 ~10 20 cm -3 The depth of each second conductive type injection region 161 is preferably in the range of 1 μm to 5 μm; the width (ring width) of each second conductive type injection region 161 is preferably 1 μm, but is not limited thereto. In this embodiment, the second conductive type injection region 161 can be formed by ion implantation and annealing processes, but is not limited thereto.

[0078] In this embodiment, the potential difference between adjacent potential-fixed layers is proportional to the distance between the two potential-fixed layers, and is related to the positions of the two potential-fixed layers relative to zero potential (the potential of the first polysilicon layer 151 at the top of the device trench structure 141 is zero potential). Specifically, the potential of the potential-fixed layer = (q×ND / es)×(WD×χ-χ×χ / 2), where q = electron charge, which is a known constant; ND = doping concentration of the first conductive type drift region; es = dielectric constant of Si, which is a known constant; WD = depletion layer depth of the first conductive type drift region, which refers to the depth of the depletion layer formed in the first conductive type drift region due to the potential difference between the first metal layer and the second metal layer. When the potential difference between the first metal layer and the second metal layer is determined, the depth of the depletion layer formed in the first conductive type drift region is also determined; and χ = distance from the potential fixation to zero potential. The potential of each potential-fixed layer is equal to the required potential of the corresponding first polysilicon layer 151 in the device trench structure 141. The higher the required potential difference between two adjacent first polysilicon layers 151 in the device trench structure 141, the longer the distance between the corresponding two adjacent potential-fixed layers.

[0079] Each of the potential-fixed layers is annular, and multiple potential-fixed layers are formed into multiple annular shapes, surrounding all of the device trench structures 141. Specifically, the second conductivity-type implant region 161, the third polysilicon layer 162, the first Schottky contact structure 164, and the ohmic contact metal layer 163 are all arranged in annular shapes, surrounding all of the device trench structures 141.

[0080] In this embodiment, the potential fixing layer is electrically connected to the first polysilicon layer having the same required potential in the device trench structure 141. Figure 1 In the embodiment, the potential-fixed layer with a potential of 100 V is electrically connected to the first polysilicon layer 151 with a required potential of 100 V in the device trench structure 141; the potential-fixed layer with a potential of 200 V is electrically connected to the first polysilicon layer 151 with a required potential of 200 V in the device trench structure 141; and the potential-fixed layer with a potential of 300 V is electrically connected to the first polysilicon layer 151 with a required potential of 300 V in the device trench structure 141.

[0081] In this embodiment, the potential fixing layer is electrically connected to each corresponding first polysilicon layer 151. At least one side surface of each first polysilicon layer 151 in each device trench structure 141 in the second direction is electrically connected to the potential fixing layer in the corresponding edge terminal structure. For example, one side surface of each first polysilicon layer 151 in each device trench structure 141 in the second direction is electrically connected to the potential fixing layer in the corresponding edge terminal structure. In other embodiments, both side surfaces of each first polysilicon layer 151 in each device trench structure 141 in the second direction are electrically connected to the potential fixing layer in the corresponding edge terminal structure. The two side surfaces of each first polysilicon layer 151 in the device trench structure 141 in the second direction are electrically connected to the corresponding potential fixing layer, which can make the transient potential difference on the first polysilicon layer 151 in the device trench structure 141 more uniform and less affected by its own resistance.

[0082] In this embodiment, each of the edge electrode structures may include an edge trench structure 142 and at least one second polysilicon layer 152 spaced apart in the edge trench structure 142 along a direction perpendicular to the semiconductor substrate 11 (ie, the y direction).

[0083] The length of each edge trench structure 142 in the first direction and the length in the second direction may be the same as or different from those of the device trench structure 141, but are preferably the same. The depth of each edge trench structure 142 is preferably the same as that of the device trench structure 141. The number of edge trench structures 142 is the same as the number of potential pinning layers.

[0084] The edge electrode structure may further include a second isolation oxide layer 182, which is located between adjacent second polysilicon layers 152 and between the second polysilicon layer 152 and the edge trench structure 142. Specifically, the second isolation oxide layer 182 is disposed between adjacent second polysilicon layers 152, on the bottom surface of the edge trench structure 142 (i.e., between the second polysilicon layer 152 at the bottom of the edge trench structure 142 and the bottom surface of the edge trench structure 142), and on the side surfaces of the edge trench structure 142. The second isolation oxide layer 182 located on the side surfaces and bottom surface of the edge trench structure 142 isolates the second polysilicon layer 142 from the first conductive type drift region 12.

[0085] In this embodiment, the arrangement of the second polysilicon layer 152 and the second isolation oxide layer 182 below the top second polysilicon layer 152 in the edge electrode structure is the same as the arrangement of the first polysilicon layer 151 and the first isolation oxide layer 181 below the first polysilicon layer 151 corresponding to the potential fixed layer connected to the edge electrode structure. Figure 1 In the device trench structure 141, two first polysilicon layers are spaced apart below the first polysilicon layer 151 with a required potential of 100V, and the potential of the top second polysilicon layer 152 in the edge trench structure connected to the corresponding potential fixed layer with a potential of 100V is also 100V. Two second polysilicon layers are set below the top second polysilicon layer 152, and the thickness of the two second polysilicon layers, the thickness of the second isolation oxide layer between the two second polysilicon layers, and the thickness of the second isolation oxide layer between the bottom second polysilicon layer and the bottom surface of the edge trench structure are all the same as the first polysilicon layer and the first isolation oxide layer below the first polysilicon layer 151 with a required potential of 100V in the device trench structure 141.

[0086] In this embodiment, the first polysilicon layer 151 can be electrically connected to all second polysilicon layers 152 having the same potential as the first polysilicon layer, so as to realize the electrical connection between the first polysilicon layer 151 and the corresponding potential fixed layer, and also make the two-dimensional electric field uniformly distributed in the vertical direction, which is conducive to enhancing the two-dimensional electric field effect. Figure 1 In the embodiment, the first polysilicon layer 151 having a desired potential of 300 V is electrically connected to the second polysilicon layer 152 having a desired potential of 300 V in the first edge trench structure. The second polysilicon layer 152 having a desired potential of 300 V in the first edge trench structure is further electrically connected to the second polysilicon layer 152 having a desired potential of 300 V in the second edge trench structure. The second polysilicon layer 152 having a desired potential of 300 V in the second edge trench structure is further electrically connected to the second polysilicon layer 152 having a desired potential of 300 V in the third edge trench structure. The second polysilicon layer 152 having a desired potential of 300 V in the third edge trench structure is the top second polysilicon layer and is electrically connected to the potential-fixed layer having a potential of 300 V. In other words, the first polysilicon layer 151 is electrically connected to the corresponding potential-fixed layer by being electrically connected to all second polysilicon layers 152 having the same desired potential as the first polysilicon layer.

[0087] In this embodiment, the edge termination structure may further include a top oxide layer 183 located on the first conductivity type drift region 12 on a side of each edge trench structure 142 away from the device trench structure 141 and connected to the second isolation oxide layer 182, and the top structure further extends onto a portion of the surface of the top oxide layer 183 to improve electric field shielding, thereby further preventing a reduction in breakdown voltage on the surface. The top oxide layer 183 may also be located on the first conductivity type drift region 12 between the device trench structure 141 and the edge trench structure 142, and connected to the first isolation oxide layer 181 in the device trench structure 141.

[0088] In this embodiment, the top oxide layer 183 may also extend to cover a portion of the surface of the adjacent second conductive type implantation region 161. The material of the top oxide layer 183 is preferably the same as that of the second isolation oxide layer 182, and the thickness of the top oxide layer 183 is preferably 0.5 μm, but is not limited thereto.

[0089] The electrical connection layer (not shown in the figure) is located between the first polysilicon layer 151 in the device trench structure 141 and the corresponding potential fixing layer to achieve electrical connection between the first polysilicon layer 151 in the device trench structure 141 and the corresponding potential fixing layer, that is, the potential fixing layer will be electrically connected to the first polysilicon layer 151 in the device trench structure 141 with the same required potential, and the potential of each first polysilicon layer 151 in the device trench structure 141 is determined by the potential of the corresponding potential fixing layer position. Specifically, the electrical connection layer can be located respectively between the first polysilicon layer and the second polysilicon layer 152 having the same required potential as the first polysilicon layer, and the polysilicon layers with the same required potential are connected in sequence to realize the electrical connection between the first polysilicon layer 151 and the corresponding potential fixed layer, and the potential of the first polysilicon layer can be determined according to the potential of the potential fixed layer, and the potential of the second polysilicon layer can also be determined, thereby making the two-dimensional electric field of the first conductive type drift region in the area where the edge terminal structure is located uniformly distributed.

[0090] Due to the presence of the electrical connection layer, this embodiment can determine the potential of each first polysilicon layer 151 in the device trench structure 141 by the potential of each potential-fixing layer in the edge terminal structure. The first polysilicon layer 151 does not need to be arranged to have a large area to achieve potential fixing. Therefore, this embodiment can reduce the area of ​​the first polysilicon layer in the device trench structure, thereby reducing the size of the power switching device structure and reducing its cost. This embodiment can reduce the area of ​​the first polysilicon layer in the device trench structure by reducing the width of the first polysilicon layer in the first direction. The width of the first polysilicon layer in the device trench structure in the first direction is preferably greater than or equal to 0.1 μm, which can ensure process feasibility while also ensuring conductivity.

[0091] In this embodiment, the electrical connection layer may include a conductive layer. In other embodiments, the electrical connection layer may include a conductive layer and an insulating layer wrapping the conductive layer. The conductive layer may be a metal layer or a polysilicon wire of the first conductivity type, but is not limited thereto. Preferably, the conductive layer is a polysilicon wire of the first conductivity type. The material of the insulating layer is preferably the same as the material of the first isolation oxide layer. In this embodiment, the electrical connection layer may be formed by etching and deposition processes, but is not limited thereto. The shape and thickness of the electrical connection layer of this embodiment are not limited, as long as the first polysilicon layer 151 can be electrically connected to the corresponding potential fixing layer.

[0092] Continue reading Figures 1 to 4 The power switching device structure may further include: a second Schottky contact structure 21 and an insulating dielectric layer 22 located on the first conductive type drift region 12 between adjacent device trench structures 141, and the insulating dielectric layer 22 also covers the side surfaces of the second Schottky contact structure 21, that is, the upper surfaces of the second Schottky contact structure 21 and the insulating dielectric layer 22 are flush. The second metal layer 132 also extends to cover the second Schottky contact structure 21 and the insulating dielectric layer 22. In this embodiment, the junction on the surface of the first conductive type drift region 12 between the device trench structures 141 is a Schottky junction formed by the second Schottky contact structure 21 through Schottky contact. The material of the second Schottky contact structure 21 is preferably metal. In this embodiment, the second Schottky contact structure 21 can be set and prepared by the Schottky contact structure in the power switching device structure of the prior art, and will not be described in detail here. The material of the insulating dielectric layer 22 is preferably the same as the material of the top oxide layer 183. The upper surface of the insulating dielectric layer 22 is preferably flush with the upper surface of the first polysilicon layer 151 at the top of the device trench structure 141 .

[0093] See Figure 5 and Figure 6In another embodiment, a second conductive type doped region 31 is formed on the first conductive type drift region 12 between adjacent device trench structures 141, rather than a second Schottky contact structure 21 and an insulating dielectric layer 22. The junction on the surface of the first conductive type drift region 12 between the device trench structures 141 is a PN junction formed by the second conductive type doped region 31 through second conductive type doping. For example, if the first conductive type drift region 12 is an n-type drift region, the junction on the surface of the n-type drift region can be a PN junction formed by a p-type doped region. For another example, if the first conductive type drift region 12 is a p-type drift region, the junction on the surface of the p-type drift region can be a PN junction formed by an n-type doped region.

[0094] See Figure 7 In another embodiment, a second conductivity type doped region 41 is formed on the first conductivity type drift region 12 between adjacent device trench structures 141, a first conductivity type source region 42 is formed on the second conductivity type doped region 41, and a gate oxide layer (not shown), a gate electrode 43, and a dielectric layer 44 are sequentially formed between the first polysilicon layer 151 at the top of each device trench structure 141 and the second metal layer 132. The second Schottky contact structure 21 and the insulating dielectric layer 22 are not formed. The junction on the surface of the first conductivity type drift region 12 is a PN junction formed by the second conductivity type doping of the second conductivity type doped region 41. For example, if the first conductivity type drift region 12 is an n-type drift region, the junction on the surface of the n-type drift region can be a PN junction formed by a p-type doped region. For another example, if the first conductivity type drift region 12 is a p-type drift region, the junction on the surface of the p-type drift region can be a PN junction formed by an n-type doped region. The second metal layer 132 is electrically connected to the first polysilicon layer 151 at the top of the device trench structure 141. The gate electrode 43 is isolated from the first polysilicon layer 151 by the gate oxide layer. The dielectric layer 44 is located between the gate electrode 43 and the second metal layer 132. The material of the gate electrode 43 is preferably the same as that of the first polysilicon layer 151. The material of the dielectric layer 44 and the gate oxide layer is preferably silicon oxide, but is not limited thereto. The thicknesses of the gate electrode 43, the dielectric layer 44, and the gate oxide layer can adopt the thicknesses of the gate electrode, dielectric layer, and gate oxide layer of the power switching device structure in the prior art, and are not further described here.

[0095] In the area where the device trench structure is located, the present invention can adopt a scheme of forming a second Schottky contact structure 21 and an insulating dielectric layer 22 on the first conductive type drift region 12 between adjacent device trench structures 141, or a scheme of forming a second conductive type doped region 31 on the first conductive type drift region 12 between adjacent device trench structures 141, or a technical scheme of forming a second conductive type doped region 41 on the first conductive type drift region 12 between adjacent device trench structures 141, forming a first conductive type source region 42 on the second conductive type doped region 41, and sequentially forming a gate oxide layer, a gate electrode 43 and a dielectric layer 44 between the first polysilicon layer 151 and the second metal layer 132 at the top of each device trench structure 141; and in the area where the edge trench structure is located, a scheme of combining the second conductive type injection region 161 and the top structure as a potential fixing layer can be adopted, or a scheme of using the top structure alone as the potential fixing layer can be adopted. The technical solution in the region where the device trench structure of the present invention is located can be matched with the technical solution in the region where the edge trench structure is located to obtain more power switch device structures.

[0096] In addition, the present invention provides a method for preparing the above-mentioned power switch device structure, which specifically includes:

[0097] Step S1: providing a semiconductor substrate 11;

[0098] Step S2: forming a first conductive type drift region 12 on the semiconductor substrate 11;

[0099] Step S3: forming at least one device electrode structure and an edge terminal structure surrounding all device trench structures in the first conductive type drift region 12, each of the device electrode structures including a device trench structure 141 and at least two first polysilicon layers 151 spaced apart in each of the device trench structures 141 along a direction perpendicular to the semiconductor substrate 11, the edge terminal structure including a plurality of potential fixing layers spaced apart in a direction from the center to the edge of the semiconductor substrate 11 and a plurality of edge electrode structures located in the first conductive type drift region 12, the potential fixing layers and the first conductive type drift region 12. The first polysilicon layer 151 in the device trench structure 141 corresponds to each of the potential fixing layers, and each of the edge electrode structures is connected to one of the edge electrode structures. Each of the edge electrode structures includes an edge trench structure 142 and at least one second polysilicon layer 152 spaced apart in the edge trench structure 142 in a direction perpendicular to the semiconductor substrate 11. The second polysilicon layer 152 below the top second polysilicon layer 152 in the edge electrode structure is arranged in the same manner as the first polysilicon layer 151 below the first polysilicon layer 151 corresponding to the potential fixing layer connected to the edge electrode structure.

[0100] Step S4: forming an electrical connection layer between the first polysilicon layer 151 in the device trench structure 141 and the corresponding potential fixing layer to achieve electrical connection between the first polysilicon layer in the device trench structure 141 and the corresponding potential fixing layer;

[0101] Step S5 : forming a second metal layer 132 on the first polysilicon layer, and simultaneously forming a first metal layer 131 on the lower surface of the semiconductor substrate 11 .

[0102] In step S1 , the semiconductor substrate 11 is preferably a heavily doped semiconductor substrate of the first conductivity type, such as a heavily doped n-type semiconductor substrate.

[0103] In step S2, epitaxial growth is performed on the semiconductor substrate 11 to form a first conductive type drift region 12. The first conductive type drift region 12 is, for example, an n-type drift region.

[0104] In step S3, forming at least one device electrode structure and an edge termination structure surrounding all device trench structures may specifically include:

[0105] Step S31 : forming at least one device trench structure 141 and an edge trench structure 151 in the first conductive type drift region 12 , wherein the edge trench structure 142 surrounds all the device trench structures 141 ;

[0106] Step S32: alternately forming the first polysilicon layer 151 and the first isolation oxide layer 181 on the bottom surface of each of the device trench structures 141 , and alternately forming the second polysilicon layer 152 and the second isolation oxide layer 182 on the bottom surface of each of the edge trench structures 142 ;

[0107] Step S33 : forming a potential fixed layer corresponding to the first polysilicon layer 151 in the device trench structure 141 .

[0108] In step S31 , reactive ion etching is performed using a mask to form a device trench structure 141 and an edge trench structure 142 in the first conductive type drift region 12 .

[0109] In this embodiment, while forming the device trench structure 141 and the edge trench structure 142, a connection trench structure may also be formed in the first conductive type drift region 12 to form an electrical connection layer. In other embodiments, the connection trench structure may also be performed after step S3. The connection trench structure may be arranged according to the position of the electrical connection layer. The method for forming the connection trench structure is preferably reactive ion etching, but is not limited thereto.

[0110] In step S32, during the step of alternately forming the first polysilicon layer 151 and the first isolation oxide layer 181 on the bottom surface of each device trench structure 141, a layer of isolation oxide layer is grown on the bottom surface of each device trench structure 141 by a thermal oxidation or CVD process, and then a highly doped n-type polysilicon layer is used as an electrode segment to fill the trench structure 141 and the edge trench structure 142; another layer of isolation oxide layer is grown on the polysilicon layer; and then a highly doped n-type polysilicon layer is used again to fill the trench structure 141 and the edge trench structure 142 until all polysilicon layers are formed, and the last layer of polysilicon layer is electrically connected to the second metal layer. In this embodiment, each time an isolation oxide layer is grown in the device trench structure 141, the isolation oxide layer also covers the side surfaces of the device trench structure 141. After each time the device trench structure 141 is filled with a highly doped n-type polysilicon layer, a portion of the polysilicon layer needs to be removed so that the thickness of the polysilicon layer formed each time can meet the corresponding potential requirements. Each time a portion of the polysilicon layer is removed, a portion of the isolation oxide layer on the side of the device trench structure 141 is also removed, so that the isolation oxide layer on the side of the device trench structure 141 is flush with the top of the polysilicon layer.

[0111] The step of alternately forming the second polysilicon layer 152 and the second isolation oxide layer 182 on the bottom surface of each edge trench structure 142 is similar to the step of alternately forming the first polysilicon layer 151 and the first isolation oxide layer 181 on the bottom surface of each device trench structure 141, and will not be repeated here.

[0112] In this embodiment, the second polysilicon layer 152 and the second isolation oxide layer 182 in different edge trench structures 142 can be formed separately in sequence, that is, the second polysilicon layer 152 and the second isolation oxide layer 182 in one edge trench structure 142 are formed first, and then the second polysilicon layer 152 and the second isolation oxide layer 182 in the next edge trench structure 142 are formed. In addition, part of the second polysilicon layer 152 and the second isolation oxide layer 182 in different edge trench structures 142 can also be formed simultaneously. For example, the second polysilicon layer and the second isolation oxide layer below the top second polysilicon layer in each edge trench structure 142 can be formed simultaneously with the first polysilicon layer and the first isolation oxide layer in the device trench structure, and the top second polysilicon layer in each edge trench structure 142 is formed separately, and the upper surface of the top second polysilicon layer in each edge trench structure 142 is flush with the upper surface of the top first polysilicon layer in the device trench structure.

[0113] In the step of alternately forming the second polysilicon layer 152 and the second isolation oxide layer 182 on the bottom surface of each of the edge trench structures 142 in this embodiment, a top oxide layer 183 is also formed on the first conductive type drift region 12 on one side of each of the edge trench structures 142, and the top oxide layer 183 is connected to the second isolation oxide layer 182.

[0114] In step S33, a potential fixing layer is formed corresponding to the first polysilicon layer phase 151 in the device trench structure 141. When the potential fixing layer includes a second conductive type injection region 161, it can be directly formed using an ion implantation process. When the potential fixing layer includes a first Schottky contact structure 164, the first Schottky contact structure 164 can adopt a Schottky contact structure formation process in the prior art, which will not be described in detail here. The first Schottky contact structure 164 is preferably formed simultaneously with the second Schottky contact structure 21. When the potential fixing layer includes an ohmic contact metal layer 163, the ohmic contact metal layer 163 is preferably formed using the same formation process as the first metal layer 131 and the second metal layer 132, and is preferably formed simultaneously with the first metal layer 131 and the second metal layer 132. When the potential fixed layer includes the third polysilicon layer 162 , the third polysilicon layer 162 is preferably formed using the same process as the first polysilicon layer 151 and the second polysilicon layer 152 , and is preferably prepared during the formation of the second polysilicon layer 152 .

[0115] In step S4, an electrical connection layer is formed in the connection trench structure. In this embodiment, an insulating layer can be first grown on the bottom surface of the connection trench structure using a thermal oxidation or CVD process in the connection trench structure, and then a polysilicon line is formed using a highly doped n-type polysilicon layer, and then the insulating layer is formed, and the electrical connection layer is obtained in sequence. The polysilicon line is located between a side surface of the first polysilicon layer in the second direction and a second polysilicon layer in the edge trench structure having the same desired potential as the first polysilicon layer, as well as between all second polysilicon layers having the same desired potential. That is, the polysilicon line sequentially connects the first polysilicon layer and all second polysilicon layers having the same desired potential as the first polysilicon layer in series.

[0116] In other embodiments, the electrical connection layer may also be prepared during the formation of the isolation oxide layer and the polysilicon layer in the device electrode structure and the edge terminal structure.

[0117] After step S4, when a second Schottky contact structure 21 and an insulating dielectric layer 22 are provided on the first conductivity type drift region between adjacent device trench structures, the method for preparing the power switch device structure further includes forming the second Schottky contact structure 21 and the insulating dielectric layer 22. The second Schottky contact structure 21 is formed using a conventional Schottky contact structure forming process, which will not be described in detail herein. The insulating dielectric layer 22 may be formed using, but is not limited to, a thermal oxidation or CVD process.

[0118] When the second conductive type doping region 31 is provided on the first conductive type drift region between adjacent device trench structures, the method for preparing the power switch device structure further includes: forming the second conductive type doping region 31 by an ion implantation process.

[0119] When forming a second conductivity type doped region 41 on the first conductivity type drift region 12 between adjacent device trench structures 141, forming a first conductivity type source region 42 on the second conductivity type doped region 41, and sequentially forming a gate oxide layer, a gate electrode 43, and a dielectric layer 44 between the first polysilicon layer 151 at the top of each device trench structure 141 and the second metal layer 132, the method for preparing the power switching device structure further includes: forming the second conductivity type doped region 41 on the first conductivity type drift region 12 by implanting boron ions, then ion implanting phosphorus and subsequently performing an annealing process to produce the first conductivity type source region 42. In step S3, a gate oxide layer, a gate electrode 43, and a dielectric layer 44 are also formed sequentially on the second polysilicon layer 252. That is, an additional polysilicon layer is deposited and planarized to serve as a gate electrode, and then an intermetallic dielectric is deposited to form a dielectric layer 27, and contact windows for the second conductive type doped region 41 and the first conductive type source region 42 are etched, and finally the device manufacturing is completed by depositing and patterning the second metal layer.

[0120] In step S5 , a second metal layer 132 is formed on the first polysilicon layer 151 , and at the same time, the second metal layer 132 is formed on a surface of the semiconductor substrate 11 away from the first conductive type drift region 12 .

[0121] In summary, the present invention simultaneously provides a device trench structure and an edge termination structure. The first polysilicon layer in the device trench structure and the potential fixing layer in the edge termination structure are provided in correspondence with each other, and the first polysilicon layer and the corresponding potential fixing layer are electrically connected via an electrical connection layer. The potential of each first polysilicon layer in the device trench structure is determined by the potential of the potential fixing layer in the edge termination structure. This can reduce the area of ​​the first polysilicon layer in the device trench structure, thereby reducing the size of the power switching device structure and reducing its cost. Furthermore, the edge termination structure of the present invention also includes an edge electrode structure connected to each potential fixing layer, and the edge electrode structure is used to generate a two-dimensional electric field so that the two-dimensional electric field is uniformly distributed in the vertical direction. As a result, the doping concentration in the first conductive type drift region in the region where the edge termination structure is located and the region where the device electrode structure is located can be the same, which can simplify the process.

[0122] In addition, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

[0123] It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which may vary. It should also be understood that the terminology described herein is used only to describe specific embodiments and is not intended to limit the scope of the present invention. It should be noted that the singular forms "a," "an," and "the" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in their broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or," not a logical "exclusive or," unless the context clearly indicates otherwise. Structures described herein are to be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximating should be so interpreted unless the context clearly indicates otherwise.

Claims

1. A power switching device structure, characterized in that: include: a first metal layer; a semiconductor substrate, located on the first metal layer; A first conductive type drift region is located on the semiconductor substrate; At least one device electrode structure is spaced apart and arranged in the first conductive type drift region, each of the device electrode structures includes a device trench structure and at least two first polysilicon layers spaced apart and arranged in the device trench structure along a direction perpendicular to the semiconductor substrate; an edge terminal structure disposed around all device electrode structures, the edge terminal structure comprising a plurality of potential fixing layers spaced apart along a direction pointing from the center of the semiconductor substrate toward the edge, and a plurality of edge electrode structures located in the first conductivity type drift region, the potential fixing layers corresponding to the first polysilicon layers in the device trench structures, each of the potential fixing layers being connected to one of the edge electrode structures, each of the edge electrode structures comprising an edge trench structure and at least one second polysilicon layer spaced apart in the edge trench structure along a direction perpendicular to the semiconductor substrate, the second polysilicon layer below the top second polysilicon layer in the edge electrode structure being arranged in the same manner as the first polysilicon layer below the first polysilicon layer corresponding to the potential fixing layer connected to the edge electrode structure; an electrical connection layer, located between the first polysilicon layer in the device trench structure and the corresponding potential fixing layer, so as to achieve electrical connection between the first polysilicon layer in the device trench structure and the corresponding potential fixing layer; The second metal layer is located on the first polysilicon layer at the top of each device trench structure.

2. The power switch device structure according to claim 1, wherein: The device electrode structure also includes a first isolation oxide layer, which is located between adjacent first polysilicon layers and between the first polysilicon layer and the device trench structure; the edge electrode structure also includes a second isolation oxide layer, which is located between adjacent second polysilicon layers and between the second polysilicon layer and the edge trench structure; the isolation oxide layer below the top second polysilicon layer in the edge electrode structure is set the same as the isolation oxide layer below the first polysilicon layer corresponding to the potential fixed layer connected to the edge electrode structure.

3. The power switch device structure according to claim 2, wherein: The power switch device structure further includes a top oxide layer located on the first conductivity type drift region on one side of each edge trench structure and connected to the second isolation oxide layer.

4. The power switch device structure according to claim 1, wherein: The longer the distance between two adjacent potential fixed layers, the greater the potential difference therebetween.

5. The power switch device structure according to claim 1, wherein: Each of the potential fixing layers is annular and surrounds all the device trench structures.

6. The power switch device structure according to claim 1, wherein: The potential-fixed layer includes a top structure or a combination of a top structure and a second conductive type injection region, wherein the top structure includes at least one of a third polysilicon layer, a first Schottky contact structure, and an ohmic contact metal layer. The potential of each of the potential-fixed layers is equal to the potential required by the corresponding first polysilicon layer in the device trench structure.

7. The power switch device structure according to claim 6, wherein: The second conductive type injection region is located on the first conductive type drift region and is adjacent to the edge trench structure. The top structure is located on the second polysilicon layer at the top of the edge trench structure. When the potential fixing layer is a combination of the top structure and the second conductive type injection region, the top structure also extends to a portion of the surface of the second conductive type injection region; when the potential fixing layer is only the top structure, the top structure also extends to a portion of the surface of the first conductive type drift region.

8. The power switch device structure according to claim 6, wherein: The first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.

9. The power switch device structure according to claim 1, wherein: When there are multiple device trench structures, the multiple device trench structures are arranged in parallel along the first direction, and at least one side surface of each first polysilicon layer in each device trench structure in the second direction is electrically connected to the potential fixed layer in the corresponding edge terminal structure, the first direction is perpendicular to the second direction, and the plane where the first direction and the second direction are located is parallel to the upper surface of the semiconductor substrate.

10. The power switch device structure according to claim 1, wherein: The electrical connection layer electrically connects the first polysilicon layer to all second polysilicon layers having the same desired electrical potential as that of the first polysilicon layer.

11. The power switch device structure according to claim 1, characterized in that: The power switch device structure further includes a second conductivity type doping region located on the first conductivity type drift region between adjacent device trench structures.

12. The power switch device structure according to claim 1, characterized in that: The power switching device structure also includes a second conductive type doped region located on the first conductive type drift region between adjacent device trench structures, a first conductive type source region located on the second conductive type doped region, and a gate oxide layer, a gate electrode, and a dielectric layer located in sequence between the polysilicon layer at the top of each device trench structure and the second metal layer.

13. The power switch device structure according to claim 1, characterized in that: The power switch device structure further includes a second Schottky contact structure and an insulating dielectric layer located on the first conductive type drift region between adjacent device trench structures. The insulating dielectric layer also covers side surfaces of the second Schottky contact structure.

14. The power switch device structure according to claim 1, wherein: The electrical connection layer includes a polysilicon line of a first conductivity type and an insulating layer wrapping the polysilicon line of the first conductivity type.

15. A method for preparing a power switching device structure, characterized in that: The following steps are involved: providing a semiconductor substrate; forming a first conductivity type drift region on the semiconductor substrate; forming at least one device electrode structure and an edge termination structure surrounding all device trench structures in the first conductive type drift region, each device electrode structure comprising a device trench structure and at least two first polysilicon layers spaced apart in each device trench structure along a direction perpendicular to the semiconductor substrate; the edge termination structure comprising a plurality of potential fixing layers spaced apart in a direction from the center to the edge of the semiconductor substrate and a plurality of edge electrode structures located in the first conductive type drift region, the potential fixing layers corresponding to the first polysilicon layers in the device trench structures, each of the potential fixing layers being connected to one edge electrode structure; each edge electrode structure comprising an edge trench structure and at least one second polysilicon layer spaced apart in the edge trench structure along a direction perpendicular to the semiconductor substrate, the second polysilicon layer below the top second polysilicon layer in the edge electrode structure being arranged in the same manner as the first polysilicon layer below the first polysilicon layer corresponding to the potential fixing layer connected to the edge electrode structure; forming an electrical connection layer between the first polysilicon layer in the device trench structure and the corresponding potential fixing layer to achieve electrical connection between the first polysilicon layer in the device trench structure and the corresponding potential fixing layer; A second metal layer is formed on the first polysilicon layer, and a first metal layer is formed on the lower surface of the semiconductor substrate.

16. The method for preparing a power switch device structure according to claim 15, wherein: The device electrode structure further includes a first isolation oxide layer, the first isolation oxide layer being located between adjacent first polysilicon layers and between the first polysilicon layer and the device trench structure; the edge electrode structure further includes a second isolation oxide layer, the second isolation oxide layer being located between adjacent second polysilicon layers and between the second polysilicon layer and the edge trench structure; The step of forming at least one device electrode structure and an edge termination structure surrounding all device trench structures comprises: forming at least one device trench structure and an edge trench structure in the first conductive type drift region, wherein the edge trench structure surrounds all the device trench structures; Alternatingly forming the first polysilicon layer and the first isolation oxide layer on the bottom surface of each of the device trench structures, and simultaneously alternatingly forming the second polysilicon layer and the second isolation oxide layer on the bottom surface of each of the edge trench structures; A potential fixing layer is formed corresponding to the first polysilicon layer in the device trench structure.

17. The method for preparing a power switch device structure according to claim 16, wherein: In the step of alternately forming the second polysilicon layer and the second isolation oxide layer on the bottom surface of each of the edge trench structures, a top oxide layer is also formed on the first conductive type drift region on one side of each of the edge trench structures, and the top oxide layer is connected to the second isolation oxide layer.

18. The method for preparing a power switch device structure according to claim 17, wherein: The device trench structure and the edge trench structure are formed by a reactive ion etching process; the first isolation oxide layer, the second isolation oxide layer and the top oxide layer are formed by a thermal oxidation process or a CVD process.

19. The method for preparing a power switch device structure according to claim 15, wherein: After the step of forming at least one device electrode structure and an edge terminal structure surrounding all device trench structures in the first conductive type drift region, the preparation method further includes: forming a second Schottky contact structure and an insulating dielectric layer on the first conductive type drift region between adjacent device trench structures, and the insulating dielectric layer also covers the side surfaces of the second Schottky contact structure.

20. The method for preparing a power switch device structure according to claim 15, wherein: After the step of forming at least one device electrode structure and an edge terminal structure surrounding all device trench structures in the first conductive type drift region, the preparation method further includes: forming a second conductive type doping region on the first conductive type drift region between adjacent device trench structures.

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