Power switch device and preparation method thereof

Abstract

The invention provides a power switch device and a preparation method thereof, a device groove structure and an edge groove structure are arranged in a first conductive type drift region at intervals, polycrystalline silicon layers arranged in the device groove structure and the edge groove structure correspond to each other, and the corresponding polycrystalline silicon layers are electrically connected through an electric connection layer. The potential of each polycrystalline silicon layer in the device groove structure can be determined through the potential of each polycrystalline silicon layer in the edge groove structure, the area of the polycrystalline silicon layers in the device groove structure can be reduced, the size of the power switch device can be reduced, and meanwhile the cost can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power switching device and a preparation method thereof. Background Art

[0002] The structure of all power switching devices includes a drift region that can withstand a blocking voltage. The inventors have discovered that a two-dimensional electric field can be generated by setting segmented electrodes in the grooves, which can be applied to high-voltage devices. However, in order to ensure that the required potential in each electrode segment is fixed under the condition of a certain blocking voltage, the area of ​​each electrode segment (referring to the surface area of ​​the electrode segment perpendicular to the thickness direction) needs to be much larger than the thickness of the isolation oxide layer between two adjacent electrode segments, which will increase the size of the device and thus increase the device cost. For example, if the thickness of the isolation oxide layer is 0.5 microns, the area of ​​the electrode segment needs to be at least greater than 4 square microns. Summary of the Invention

[0003] An object of the present invention is to provide a power switching device and a method for manufacturing the same, so as to reduce the size of the power switching device and lower the cost thereof.

[0004] In order to achieve the above-mentioned object and other related objects, the present invention provides a power switching device, comprising:

[0005] a first metal layer;

[0006] a semiconductor substrate, located on the first metal layer;

[0007] A first conductive type drift region is located on the semiconductor substrate;

[0008] a device trench structure and an edge trench structure arranged at intervals, wherein the edge trench structure surrounds the device trench structure, and both the device trench structure and the edge trench structure are located in the first conductive type drift region;

[0009] a plurality of polysilicon layers, spaced apart in the device trench structure and the edge trench structure along a direction perpendicular to the semiconductor substrate, wherein the polysilicon layers in the edge trench structure correspond to the polysilicon layers in the device trench structure;

[0010] an isolation oxide layer, located between adjacent polysilicon layers, between the polysilicon layer and the device trench structure, and between the polysilicon layer and the edge trench structure;

[0011] an electrical connection layer, located between the polysilicon layer in the device trench structure and the corresponding polysilicon layer in the edge trench structure, to achieve electrical connection between the polysilicon layer in the device trench structure and the corresponding polysilicon layer in the edge trench structure;

[0012] The second metal layer is located on the polysilicon layer.

[0013] Optionally, in the power switching device, the polysilicon layer and the isolation oxide layer in the device trench structure constitute a device electrode structure, and the polysilicon layer and the isolation oxide layer in the edge trench structure constitute an edge electrode structure. The blocking voltage of the device electrode structure is equal to the blocking voltage of the edge electrode structure, and the blocking voltage of the device electrode structure is equal to the sum of the potential difference between all adjacent two polysilicon layers in the device trench structure and the potential difference between the bottom polysilicon layer and the bottom surface of the device trench structure; the blocking voltage of the edge electrode structure is equal to the sum of the potential difference between all adjacent two polysilicon layers in the edge trench structure and the potential difference between the bottom polysilicon layer and the bottom surface of the edge trench structure.

[0014] Optionally, in the power switching device, the potential difference V between two adjacent polysilicon layers in the edge trench structure is 边 =h 边 / h 边总 ×V 边阻总 , where h 边 h is the thickness of the isolation oxide layer between the two adjacent polysilicon layers; 边总 V is the sum of the thickness of the isolation oxide layer between all two adjacent polysilicon layers in the edge trench structure and the thickness of the isolation oxide layer on the bottom surface of the edge trench structure; 边阻总 is the blocking voltage of the edge electrode structure.

[0015] Optionally, in the power switching device, the second metal layer includes a device metal layer located on the polysilicon layer in the device trench structure and an edge metal layer located on the polysilicon layer in the edge trench structure; the power switching device also includes: a top oxide layer on the first conductive type drift region adjacent to the edge trench structure, the top oxide layer is connected to the isolation oxide layer in the edge trench structure, and the edge metal layer extends onto a portion of the top oxide layer.

[0016] Optionally, in the power switching device, the power switching device further includes: a Schottky contact structure or a second conductive type doped region on the first conductive type drift region adjacent to the device trench structure.

[0017] Optionally, in the power switching device, when the power switching device includes a second conductive type doped region, the power switching device also includes a first conductive type source region located on the second conductive type doped region and a gate oxide layer, a gate electrode and a dielectric layer located in sequence between the polysilicon layer at the top of the device trench structure and the second metal layer.

[0018] Optionally, in the power switching device, the first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.

[0019] Optionally, in the power switching device, the electrical connection layer includes a polysilicon wire of a first conductivity type and an insulating layer wrapping the polysilicon wire of the first conductivity type.

[0020] Optionally, in the power switching device, the number of the device trench structures is one or more, and the edge trench structure surrounds all the device trench structures.

[0021] Optionally, in the power switching device, when there are multiple device trench structures, the multiple device trench structures are arranged in parallel along a first direction, and at least one side of each polysilicon layer in each device trench structure in a second direction is electrically connected to the polysilicon layer in the corresponding edge trench structure, and the first direction is perpendicular to the second direction.

[0022] In order to achieve the above-mentioned object and other related objects, the present invention further provides a method for preparing a power switching device, comprising the following steps:

[0023] providing a semiconductor substrate;

[0024] forming a first conductivity type drift region on the semiconductor substrate;

[0025] forming a spaced device trench structure and an edge trench structure in the first conductive type drift region, wherein the edge trench structure surrounds the device trench structure;

[0026] A plurality of polysilicon layers and an isolation oxide layer are formed in the device trench structure and the edge trench structure, and an electrical connection layer is formed in the first conductive type drift region, wherein the plurality of polysilicon layers are spaced apart in the device trench structure and the edge trench structure along a direction perpendicular to the semiconductor substrate, and the polysilicon layer in the edge trench structure corresponds to the polysilicon layer in the device trench structure; the isolation oxide layer is arranged between adjacent polysilicon layers, between the polysilicon layer and the device trench structure, and between the polysilicon layer and the edge trench structure; the electrical connection layer is arranged between the polysilicon layer in the device trench structure and the corresponding polysilicon layer in the edge trench structure, so as to realize electrical connection between the polysilicon layer in the device trench structure and the corresponding polysilicon layer in the edge trench structure;

[0027] A second metal layer is formed on the polysilicon layer, and a first metal layer is formed on the lower surface of the semiconductor substrate.

[0028] Optionally, in the preparation method of the power switching device, the polysilicon layer and the isolation oxide layer in the device trench structure constitute a device electrode structure, and the polysilicon layer and the isolation oxide layer in the edge trench structure constitute an edge electrode structure. The blocking voltage of the device electrode structure is equal to the blocking voltage of the edge electrode structure. The blocking voltage of the device electrode structure is equal to the sum of the potential difference between all adjacent two polysilicon layers in the device trench structure and the potential difference between the bottom polysilicon layer and the bottom surface of the device trench structure; the blocking voltage of the edge electrode structure is equal to the sum of the potential difference between all adjacent two polysilicon layers in the edge trench structure and the potential difference between the bottom polysilicon layer and the bottom surface of the edge trench structure.

[0029] Optionally, in the method for preparing the power switching device, the potential difference V between two adjacent polysilicon layers in the edge trench structure is 边 =h 边 / h 边总 ×V 阻总 , where h 边 h is the thickness of the isolation oxide layer between two adjacent polysilicon layers; 边总 V is the sum of the thickness of the isolation oxide layer between all two adjacent polysilicon layers in the edge trench and the thickness of the isolation oxide layer on the bottom surface of the edge trench structure; 阻总 is the blocking voltage of the edge electrode structure.

[0030] Optionally, in the preparation method of the power switching device, the number of the device groove structures is one or more. When the number of the device groove structures is multiple, the multiple device groove structures are arranged in parallel along the first direction, and the edge groove structure surrounds all the device groove structures.

[0031] Optionally, in the method for preparing the power switching device, the electrical connection layer includes a polysilicon wire of a first conductivity type and an insulating layer wrapping the polysilicon wire of the first conductivity type.

[0032] Optionally, in the preparation method of the power switching device, in the step of forming the spaced device trench structure and the edge trench structure in the first conductive type drift region, a connection trench structure is also formed in the first conductive type drift region, and the connection trench structure is located between at least one side surface of each of the device trench structures in the second direction and the edge trench structure; the step of forming an electrical connection layer in the first conductive type drift region is: forming an electrical connection layer in the connection trench structure in the first conductive type drift region, and the first direction is perpendicular to the second direction.

[0033] Optionally, in the preparation method of the power switching device, the electrical connection layer in the connection groove structure corresponds to the polysilicon layer in the device groove structure, and at least one side of each polysilicon layer in the device groove structure in the second direction is electrically connected to the polysilicon layer in the corresponding edge groove through the electrical connection layer.

[0034] Optionally, in the method for preparing the power switching device, the step of forming a plurality of polysilicon layers and an isolation oxide layer in the device trench structure and the edge trench structure includes:

[0035] Isolation oxide layers and polysilicon layers are alternately formed on the bottom surfaces of the edge trench structure and the device trench structure.

[0036] Optionally, in the preparation method of the power switching device, the second metal layer includes a device metal layer located on the polysilicon layer in the device trench structure and an edge metal layer located on the polysilicon layer in the edge trench structure; in the step of forming multiple polysilicon layers and isolation oxide layers in the device trench structure and the edge trench structure, a top oxide layer is also formed on the first conductive type drift region adjacent to the edge trench structure; in the step of forming the second metal layer on the polysilicon layer, the edge metal layer extends onto a portion of the top oxide layer.

[0037] Optionally, in the method for preparing the power switching device, a reactive ion etching process is used to form the device trench structure and the edge trench structure; and a thermal oxidation process or a CVD process is used to form the isolation oxide layer and the top oxide layer.

[0038] Optionally, in the preparation method of the power switching device, after the step of forming spaced device trench structures and edge trench structures in the first conductive type drift region, the preparation method also includes: forming a Schottky contact structure or a second conductive type doping region on the first conductive type drift region adjacent to the device trench structure.

[0039] Optionally, in the method for preparing the power switching device, the first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.

[0040] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0041] In the power switching device provided by the present invention, a device trench structure and an edge trench structure are provided simultaneously. The polysilicon layers in the device trench structure and the edge trench structure are provided correspondingly, and the corresponding polysilicon layers are electrically connected through an electrical connection layer, so that the potential of each polysilicon layer in the device trench structure is determined by the potential of each polysilicon layer in the edge trench structure. This can reduce the area of ​​the polysilicon layer in the device trench structure, thereby reducing the size of the power switching device and reducing its cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic structural diagram of a power switch device according to an embodiment of the present invention;

[0043] Figure 2 This is a schematic structural diagram of another power switch device according to an embodiment of the present invention;

[0044] Figure 3a for Figure 2 A side view of the polysilicon layer and the electrical connection layer arrangement;

[0045] Figure 3b for Figure 2 A top view of the polysilicon layer and the electrical connection layer arrangement;

[0046] Figure 4a for Figure 2 A side view of another arrangement of a polysilicon layer and an electrical connection layer;

[0047] Figure 4b for Figure 2 A top view of another arrangement of the polysilicon layer and the electrical connection layer;

[0048] Figure 5 A schematic structural diagram of a power switch device according to another embodiment of the present invention;

[0049] Figure 6 A schematic structural diagram of the power switch device of the present invention;

[0050] Figure 7a for Figure 6 A side view of the polysilicon layer and the electrical connection layer arrangement;

[0051] Figure 7b for Figure 6 A top view of the polysilicon layer and the electrical connection layer arrangement;

[0052] Figure 8a for Figure 6 A side view of another arrangement of a polysilicon layer and an electrical connection layer;

[0053] Figure 8b for Figure 6 A top view of another arrangement of the polysilicon layer and the electrical connection layer in FIG. DETAILED DESCRIPTION

[0054] The power switching device and its manufacturing method proposed in the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0055] See Figures 1 to 4b , the power switching device of the present invention may include:

[0056] a first metal layer 131;

[0057] a semiconductor substrate 11 located on the first metal layer 131;

[0058] A first conductive type drift region 12 is located on the semiconductor substrate 11;

[0059] a device trench structure 141 and an edge trench structure 142 arranged at intervals, wherein the edge trench structure 142 surrounds the device trench structure 141 , and both the device trench structure 141 and the edge trench structure 142 are located in the first conductive type drift region 12 ;

[0060] a plurality of polysilicon layers, spaced apart in the device trench structure 141 and the edge trench structure 142 along a direction perpendicular to the semiconductor substrate 11 , wherein the polysilicon layers in the edge trench structure 142 correspond to the polysilicon layers in the device trench structure 141 ;

[0061] an isolation oxide layer 16 , located between the polysilicon layers, between the polysilicon layer and the device trench structure 141 , and between the polysilicon layer and the edge trench structure 142 ;

[0062] An electrical connection layer 19 is located between the polysilicon layer in the device trench structure 141 and the polysilicon layer in the corresponding edge trench structure 142 to achieve electrical connection between the polysilicon layer in the device trench structure 141 and the polysilicon layer in the corresponding edge trench structure 142;

[0063] The second metal layer 132 is located on the polysilicon layer.

[0064] In this embodiment, the first metal layer 131 may be a drain metal layer, and the material of the first metal layer 131 may be a conventional electrode material, such as Ti (titanium), Ni (nickel) and Pt (platinum), but is not limited thereto.

[0065] The second metal layer 132 includes a device metal layer 1321 located on the polysilicon layer in the device trench structure 141 and an edge metal layer 1322 located on the polysilicon layer in the edge trench structure 142. The device metal layer 1321 is electrically connected to the polysilicon layer at the top of the device trench structure 141, and the edge metal layer 1322 is electrically connected to the polysilicon layer at the top of the edge trench structure 142. The device metal layer 1321 can be a source metal layer, and the edge metal layer 1322 can be an electric field plate, but are not limited thereto. The materials of the device metal layer 1321 and the edge metal layer 1322 can both be conventional electrode materials, such as Ti (titanium), Ni (nickel) and Pt (platinum), but are not limited thereto. The materials of the device metal layer 1321 and the edge metal layer 1322 can be the same or different. Furthermore, the materials of the device metal layer 1321 and the edge metal layer 1322 are preferably the same. In this embodiment, the device metal layer 1321 may only cover the polysilicon layer of the device trench structure 141, or may extend to cover the first conductive type drift region 12, and the specific configuration may be based on the process requirements. Figure 1 In the embodiment, when the power switch device further includes a Schottky contact structure 17 located on the first conductive type drift region 12, the device metal layer 1321 may only cover the polysilicon layer of the device trench structure 141. Figure 2 In the power switch device, the second conductive type doping region ( Figure 2(not shown), that is, the Schottky contact structure 17 is not provided, the device metal layer 1321 can cover the polysilicon layer of the device trench structure 141 and can also extend to the first conductive type drift region 12.

[0066] The semiconductor substrate 11 is located on the first metal layer 131, and the semiconductor substrate 11 is preferably a semiconductor substrate of the first conductivity type. The first conductivity type is n-type, and the second conductivity type is p-type; alternatively, the first conductivity type is p-type, and the second conductivity type is n-type. The following description is based on the example of the first conductivity type being n-type and the second conductivity type being p-type. That is, in this embodiment, the semiconductor substrate of the first conductivity type is an n-type semiconductor substrate, and is preferably a heavily doped n-type semiconductor substrate. Its doping concentration can be set according to the semiconductor substrate of the power switching device in the prior art, and will not be described in detail here.

[0067] The first conductive type drift region 12 is located on the semiconductor substrate 11. The material of the first conductive type drift region 12 is preferably single crystal silicon, but is not limited thereto. The thickness of the first conductive type drift region 12 depends on the blocking voltage. The higher the required blocking voltage, the greater the thickness of the first conductive type drift region 12. For example, the thickness of the first conductive type drift region 12 required to achieve a blocking voltage of 400V is at least 20 microns. Therefore, the thickness of the first conductive type drift region 12 can be set according to the blocking voltage requirement. In this embodiment, the first conductive type drift region 12 is an n-type drift region, which is doped with n-type ions, such as phosphorus. The doping concentration of the n-type ions can adopt the doping concentration in the drift region of the power switching device in the prior art, which will not be elaborated here.

[0068] The device trench structure 141 and the edge trench structure 142 are spaced apart in the first conductive type drift region 12. In this embodiment, the depths of the device trench structure 141 and the edge trench structure 142 are both less than the depth of the first conductive type drift region 12, that is, there is a very small space between the bottom surfaces of the device trench structure 141 and the edge trench structure 142 and the bottom surface of the first conductive type drift region 12. The depths of the device trench structure 141 and the edge trench structure 142 can be obtained according to the following formula: trench structure depth t = BV / Ec, where BV is the breakdown voltage and Ec is the critical electric field. The critical electric field (Ec) is a set value, which can be set according to process requirements, for example, 2×10 5 V / cm. The depths of the device trench structure 141 and the edge trench structure 142 of this embodiment must be adjusted to achieve the desired breakdown voltage. In this embodiment, the depth of the device trench structure 141 and the depth of the edge trench structure 142 are preferably the same.

[0069] The number of the device trench structures 141 is one or more, preferably more than one. When there are multiple device trench structures 141, the multiple device trench structures 141 are arranged in parallel along the first direction (i.e., the x-direction). The number of the edge trench structure 142 is one, and the edge trench structure 142 surrounds all the device trench structures 141.

[0070] In this embodiment, a plurality of polysilicon layers are spaced apart in the device trench structure 141 and the edge trench structure 142. The polysilicon layer in the device trench structure 141 is the device polysilicon layer 151, and the polysilicon layer in the edge trench structure 142 is the edge polysilicon layer 152. At least two polysilicon layers are provided in each of the device trench structure 141 and the edge trench structure 142, and at least two polysilicon layers in the device trench structure 141 and the edge trench structure 142 are spaced apart along a direction perpendicular to the semiconductor substrate 11 (i.e., the third direction). In this embodiment, the polysilicon layer in the device trench structure 141 corresponds to the polysilicon layer in the edge trench structure 142. Specifically, the number of polysilicon layers in each of the device trench structures 141 is the same as the number of polysilicon layers in the edge trench structure 142, and the thickness and material of the polysilicon layers at corresponding positions are the same. For example Figure 1 In the embodiment, two polysilicon layers are provided in each of the device trench structures 141, and two polysilicon layers are also provided in the edge trench structure 142, and the thickness of the top polysilicon layer in the device trench structure 141 is the same as the thickness of the top polysilicon layer in the edge trench structure 142, and the thickness of the bottom polysilicon layer 141 in the device trench structure is also the same as the thickness of the bottom polysilicon layer in the edge trench structure 142.

[0071] The polysilicon layer in this embodiment can be used as an electrode segment, that is, a polysilicon layer can be used as an electrode segment. Specifically, the polysilicon layer in the edge trench structure 142 can be used as an edge trench electrode segment, and the polysilicon layer in the device trench structure 141 can be used as a device trench electrode segment. This embodiment uses a segmented electrode to perform edge field termination in the edge trench structure to determine the potential of each segmented electrode. The polysilicon layer is preferably doped with first conductive type ions, that is, the material of the polysilicon layer in this embodiment is preferably highly doped n-type polysilicon, and its doping concentration can adopt the doping concentration of the polysilicon layer in the power switching device in the prior art, which will not be elaborated here.

[0072] The isolation oxide layer 16 is disposed between adjacent polysilicon layers, between the polysilicon layer and the device trench structure 141, and between the polysilicon layer and the edge trench structure 142. Specifically, the isolation oxide layer 16 is disposed between adjacent polysilicon layers, on the bottom surface of the device trench structure 141 (i.e., between the polysilicon layer at the bottom of the device trench structure 141 and the bottom surface of the device trench structure 141), on the bottom surface of the edge trench structure 142 (i.e., between the polysilicon layer at the bottom of the edge trench structure 142 and the bottom surface of the edge trench structure 142), on the side surfaces of the device trench structure 141, and on the side surfaces of the edge trench structure 142. The isolation oxide layer 16 located on the side surfaces and bottom surfaces of the device trench structure 141 and the edge trench structure 142 isolates the polysilicon layer from the first conductive type drift region 12.

[0073] In this embodiment, the isolation oxide layer 16 in the device trench structure 141 corresponds to the isolation oxide layer 16 in the edge trench structure 142, and the corresponding isolation oxide layers have the same thickness. The material of the isolation oxide layer 16 is preferably silicon dioxide, but is not limited thereto. The polysilicon layer and the isolation oxide layer 16 in the device trench structure 141 constitute a device electrode structure; the polysilicon layer and the isolation oxide layer 16 in the edge trench structure 142 constitute an edge electrode structure.

[0074] The blocking voltage of the edge electrode structure is equal to the blocking voltage of the device electrode structure, and the blocking voltage of the device electrode structure is equal to the sum of the potential difference between all adjacent polysilicon layers in the device trench structure 141 and the potential difference between the bottom polysilicon layer and the bottom surface of the device trench structure 141. The blocking voltage of the edge electrode structure is equal to the sum of the potential difference between all adjacent polysilicon layers in the edge trench structure 142 and the potential difference between the bottom polysilicon layer and the bottom surface of the edge trench structure 142. The potential difference between two adjacent polysilicon layers in the device trench structure 141 is the same as the potential difference between the corresponding two adjacent polysilicon layers in the edge trench structure 142. The thickness of the isolation oxide layer 16 between two adjacent polysilicon layers is proportional to the potential difference between the two adjacent polysilicon layers to avoid exceeding the maximum electric field strength in the isolation oxide layer 16. For example, if the required potential difference between two adjacent polysilicon layers is 100 V, the thickness of the isolation oxide layer 16 therebetween is 0.5 μm to keep the field strength in the isolation oxide layer 16 no greater than 2×10 6The potential difference between the bottom polysilicon layer and the bottom surface of the device trench structure 141 (or edge trench structure 142 ) is proportional to the thickness of the isolation oxide layer 16 on the bottom surface of the device trench structure 141 (or edge trench structure 142 ).

[0075] The potential difference V between the two adjacent polysilicon layers in the edge trench structure 142 (or the bottom polysilicon layer and the bottom surface of the edge trench structure 142) is 边 =h 边 / h 边总 ×V 边阻总 , where h 边 h is the thickness of the isolation oxide layer 16 between the two adjacent polysilicon layers (or the bottom polysilicon layer and the bottom surface of the edge trench structure 142); 边总 V is the sum of the thickness of the isolation oxide layer 16 between all two adjacent polysilicon layers in the edge trench structure 142 and the thickness of the isolation oxide layer 16 on the bottom surface of the edge trench structure 142; 边阻总 is the blocking voltage of the edge electrode structure. In this embodiment, the area of ​​each polysilicon layer in the edge trench structure 142 is designed to be larger than the thickness of the isolation oxide therebetween, so that the potential of each polysilicon layer in the edge trench structure 142 is fixed. Under this condition, the two adjacent polysilicon layers of the isolation oxide layer 16 act like an ideal planar capacitor. The potential difference V between the two adjacent polysilicon layers in the device trench structure 141 (or the bottom polysilicon layer and the bottom surface of the device trench structure 141) is 器 =h 器 / h 器总 ×V 器阻总 , where h 器 h is the thickness of the isolation oxide layer 16 between the two adjacent polysilicon layers (or the bottom polysilicon layer and the bottom surface of the device trench structure 141); 器总 V is the sum of the thickness of the isolation oxide layer 16 between all two adjacent polysilicon layers in the device trench structure 141 and the thickness of the isolation oxide layer 16 on the bottom surface of the device trench structure 141; 器阻总 The potential difference between the two adjacent polysilicon layers in the device trench structure 141 is the same as the potential difference between the two adjacent polysilicon layers in the corresponding edge trench structure 142. Figure 2 , Figure 2 The dashed lines in the figure are equipotential lines.

[0076] In this embodiment, the thickness of the isolation oxide layer 16 between adjacent polysilicon layers in the same trench structure (device trench structure 141 or edge trench structure 142) can be the same or different. The thickness of the isolation oxide layer 16 between two adjacent polysilicon layers can be the same as or different from the thickness of the isolation oxide layer 16 on the bottom surface of the trench structure. When the thickness of the isolation oxide layer 16 between the two adjacent polysilicon layers is equal to the thickness of the isolation oxide layer 16 on the bottom surface of the trench structure, the corresponding potential differences are the same, that is, the potential difference between the two adjacent polysilicon layers is equal to the potential difference between the bottom polysilicon layer and the bottom surface of the trench structure. In this embodiment, under the condition of a certain blocking voltage, equidistant potential lines are evenly distributed in the spacer oxide layer 16 between the two adjacent polysilicon layers, in the spacer oxide layer 16 on the bottom surface of the device trench structure 141, and in the spacer oxide layer 16 on the bottom surface of the edge trench structure 142. For example, for a blocking voltage of 400V and a desired potential difference between two adjacent polysilicon layers of 200V, two polysilicon layers are required in both the device trench structure 141 and the edge trench structure 142. This means that the potential difference between the two polysilicon layers in the device trench structure 141, as well as between the bottom polysilicon layer and the bottom surface of the device trench structure 141, is the same and equal to 200V. Therefore, the thickness of the isolation oxide layer therebetween should be 1 micron. The potential difference between the two polysilicon layers in the edge trench structure 142, as well as between the bottom polysilicon layer and the bottom surface of the edge trench structure 142, is the same and equal to 200V. Therefore, the thickness of the isolation oxide layer therebetween should also be 1 micron. Furthermore, the thickness of the isolation oxide layer on the side surfaces of both the device trench structure 141 and the edge trench structure 142 can be 1 micron. Furthermore, the thickness of the isolation oxide layer 16 on the side surfaces of the trench structures is proportional to the maximum potential difference between the two adjacent polysilicon layers to avoid exceeding the maximum field strength in the isolation oxide layer on the side surfaces of the trench structures. For example, if the potential difference between two adjacent polysilicon layers is exactly the same, both equal to 100 V, then the thickness of the isolation oxide layer 16 on the side of the trench structure is equal to 0.5 microns, so as to keep the electric field strength in the isolation oxide layer 16 at each point on the side of the trench structure no more than 2×10 6 V / cm.

[0077] In this embodiment, the potential difference between the bottom polysilicon layer and the bottom surface of the device trench structure 141 (or edge trench structure 142) is actually the potential difference between the bottom polysilicon layer and the first conductive type drift region 12. However, the potential drop in the first conductive type drift region 12 below the bottom surface of the device trench structure 141 (or edge trench structure 142) is very small and can be ignored. In this embodiment, the greater the number of polysilicon layers, the greater the reduction in the thickness of the isolation oxide layer 16 therebetween.

[0078] In order to further reduce the thickness and specific on-resistance of the isolation oxide layer 16 on the side of the trench structure, more polysilicon layers may be provided in the device trench structure and the edge trench structure.

[0079] In this embodiment, the smaller the thickness of the isolation oxide layer 16, the smaller the thickness of the polysilicon layer immediately adjacent to the isolation oxide layer 16, so that the distribution of the electric field will be more uniform. This embodiment utilizes the above-mentioned design of the polysilicon layer, which can easily produce a two-dimensional charge coupling effect without increasing the thickness of the isolation oxide layer on the side and bottom surface of the trench structure. This embodiment does not increase the thickness of the isolation oxide layer on the side and bottom of the trench structure as the blocking voltage increases, and thus does not increase the specific on-resistance. Moreover, as the number of polysilicon layers in the trench structure increases, the thickness of the isolation oxide layer on the side and bottom surface of the trench structure will decrease, which can reduce the stress at the interface between the first conductive type drift region and the isolation oxide layer, reduce the specific on-resistance, and also reduce the cell spacing. Therefore, the present invention can obtain a power switching device with high blocking voltage and low specific on-resistance.

[0080] The electrical connection layer 19 is located between the polysilicon layer in the device trench structure 141 and the polysilicon layer in the corresponding edge trench structure 142, realizing electrical connection between the polysilicon layer in the device trench structure 141 and the polysilicon layer in the corresponding edge trench structure 142, so that the potential difference between the two adjacent polysilicon layers in the device trench structure is the same as the potential difference between the two adjacent polysilicon layers in the corresponding edge trench structure, and the potentials of the corresponding polysilicon layers are also the same. In this embodiment, the area of ​​the polysilicon layer in the edge trench structure 142 can be set to a large area (the area of ​​the polysilicon layer of the existing power switching device). Therefore, the potential of each polysilicon layer in the edge trench structure 142 is fixed. Due to the presence of the electrical connection layer 19, this embodiment can determine the potential of each polysilicon layer in the device trench structure 141 by the potential of each polysilicon layer in the edge trench structure 142. Each polysilicon layer in the device trench structure 141 does not need to be set to a large area to achieve fixed potential. Therefore, this embodiment can reduce the area of ​​the polysilicon layer in the device trench structure, thereby reducing the size of the power switching device and reducing its cost. This embodiment can reduce the area of ​​the polysilicon layer by reducing the width of the polysilicon layer in the device trench structure in the first direction. The width of the polysilicon layer in the device trench structure in the first direction is preferably greater than or equal to 0.1 μm, which can ensure process feasibility while also ensuring conductivity.

[0081] In this embodiment, the electrical connection layer 19 may include a conductive layer and an insulating layer wrapping the conductive layer. The conductive layer may be a metal layer or a polysilicon line of the first conductivity type, but is not limited thereto. Preferably, the conductive layer is a polysilicon line of the first conductivity type to simplify the process and save process time and cost. The material of the insulating layer is preferably the same as the material of the isolation oxide layer. The material of the conductive layer is preferably the same as the material of the polysilicon layer. In this embodiment, a polysilicon layer in the device trench structure 141 is electrically connected to the polysilicon layer in the corresponding edge trench structure 142 through one or two electrical connection layers 19, so the electrical connection layer 19 corresponds to the polysilicon layer in the device trench structure 141.

[0082] In this embodiment, at least one side surface of each polysilicon layer in the device trench structure 141 in the second direction (ie, the y direction) is electrically connected to the polysilicon layer in the corresponding edge trench structure 142. Figure 3a and Figure 3b In the embodiment, one side surface of the polysilicon layer in the device trench structure 141 in the second direction is electrically connected to the polysilicon layer in the corresponding edge trench structure 142. Figure 4a and Figure 4b In the embodiment, the two side surfaces of the polysilicon layer in the device trench structure 141 in the second direction are electrically connected to the polysilicon layer in the corresponding edge trench structure 142. The first direction is perpendicular to the second direction, and the third direction is perpendicular to the plane containing the first and second directions. In this embodiment, the two side surfaces of the polysilicon layer in the device trench structure 141 in the second direction are electrically connected to the polysilicon layer in the corresponding edge trench structure 142, which can make the transient potential difference on the polysilicon layer in the device trench structure 141 more uniform and less affected by its own resistance.

[0083] Continuing with reference to 1, the power switch device may further include: a Schottky contact structure 17 or a second conductive type doped region on the first conductive type drift region 12 adjacent to the device trench structure 141. The junction on the surface of the first conductive type drift region 12 may be a Schottky junction formed by the Schottky contact structure 17 through the Schottky contact (see Figure 1), or a PN junction formed by the second conductive type doping region through the second conductive type doping. For example, if the first conductive type drift region 12 is an n-type drift region, the junction on the surface of the n-type drift region can be a Schottky junction or a PN junction formed by a p-type doping region. For another example, if the first conductive type drift region 12 is a p-type drift region, the junction on the surface of the p-type drift region can be a Schottky junction or a PN junction formed by an n-type doping region. The material of the Schottky contact structure 17 is preferably metal. In this embodiment, the Schottky contact structure 17 or the second conductive type doping region can be set and prepared by the Schottky contact structure and the second conductive type doping region in the power switching device of the prior art, which will not be elaborated here. For example, when the power switching device is a MOSFET, the junction on the surface of the first conductive type drift region 12 is a PN junction.

[0084] In another embodiment, some semiconductor structure layers may be provided between the polysilicon layer at the top of the device trench structure and the device metal layer 1321, and may be provided according to specific applications. Figure 5 In the embodiment, when the power switching device includes a second conductivity type doped region (i.e., a second conductivity type body region 22), the power switching device may further include a first conductivity type source region 23 located on the second conductivity type doped region and a gate oxide layer (not shown in the figure) located between the polysilicon layer at the top of the device trench structure and the second metal layer, a gate electrode 21, and a dielectric layer 24. In this embodiment, the device metal layer 1321 is electrically connected to the polysilicon layer at the top of the device trench structure. The gate electrode 21 is isolated from the polysilicon layer by the gate oxide layer, and the dielectric layer 24 is located between the gate electrode 21 and the device metal layer 1321. The material of the gate electrode 21 is preferably the same as that of the polysilicon layer. The material of the dielectric layer 24 and the gate oxide layer is preferably silicon oxide, but is not limited thereto. The thicknesses of the gate electrode 21, the dielectric layer 24, and the gate oxide layer can adopt the thicknesses of the gate electrode, dielectric layer, and gate oxide layer of power switching devices in the prior art, which will not be described in detail here. The second conductivity type body region 22 is located on the first conductivity type drift region 12 on both sides of the gate electrode 21. The first conductivity type source region 23 is located on the second conductivity type body region 22 on both sides of the gate electrode 21 and is adjacent to the gate electrode 21. The device metal layer 1321 sequentially covers the second conductivity type body region 22, the first conductivity type source region 23, the dielectric layer 24, the first conductivity type source region 23, and the second conductivity type body region 22 along a first direction. In this embodiment, the power switching device is a MOSFET.

[0085] Continuing to refer to 1, the power switching device may further include: a top oxide layer 18 on the first conductive type drift region 12 adjacent to the edge trench structure 142. Specifically, the top oxide layer 18 may be provided on the first conductive type drift region 12 on the side of the edge trench structure 142 away from the device trench structure 141, and the top oxide layer 18 is connected to the isolation oxide layer 16 in the edge trench structure 142, and the edge metal layer 1322 extends to part of the top oxide layer 18 to improve the shielding of the electric field, thereby further avoiding the reduction of the breakdown voltage on the surface. In this embodiment, the top oxide layer 18 may extend to cover the side of the edge metal layer 1322, or may not cover the side of the edge metal layer 1322. For example, Figure 1 The top oxide layer 18 in the embodiment covers the side surfaces of the edge metal layer 1322. For another example, Figure 2 The top oxide layer 18 in the embodiment does not cover the side surfaces of the edge metal layer 1322 .

[0086] In this embodiment, the top oxide layer 17 is preferably made of the same material as the isolation oxide layer 16. The thickness of the top oxide layer 17 can be set by the thickness of the top oxide layer of the power switch device in the prior art, which will not be described in detail here.

[0087] In addition, the present invention also provides a method for preparing the power switching device described above, which specifically includes:

[0088] Step S1: providing a semiconductor substrate 11;

[0089] Step S2: forming a first conductive type drift region 12 on the semiconductor substrate 11;

[0090] Step S3: forming a spaced device trench structure 141 and an edge trench structure 142 in the first conductive type drift region 12 , wherein the edge trench structure 142 surrounds the device trench structure 141 ;

[0091] Step S4: forming a plurality of polysilicon layers and an isolation oxide layer 16 in the device trench structure 141 and the edge trench structure 142, and forming an electrical connection layer 19 in the first conductive type drift region 12, wherein the plurality of polysilicon layers are spaced apart in the device trench structure 141 and the edge trench structure 142 along a direction perpendicular to the semiconductor substrate 11, and the polysilicon layer in the edge trench structure 142 corresponds to the polysilicon layer in the device trench structure 141; the isolation oxide layer 16 is arranged between adjacent polysilicon layers, between the polysilicon layer and the device trench structure 141, and between the polysilicon layer and the edge trench structure 142; the electrical connection layer 19 is located between the polysilicon layer in the device trench structure 141 and the corresponding polysilicon layer in the edge trench structure 142, to achieve electrical connection between the polysilicon layer in the device trench structure 141 and the corresponding polysilicon layer in the edge trench structure 142;

[0092] Step S5 : forming a second metal layer on the polysilicon layer, and simultaneously forming a first metal layer 131 on the lower surface of the semiconductor substrate 11 .

[0093] In step S1 , the semiconductor substrate 11 is preferably a heavily doped semiconductor substrate of the first conductivity type, such as a heavily doped n-type semiconductor substrate.

[0094] In step S2, epitaxial growth is performed on the semiconductor substrate 11 to form a first conductive type drift region 12. The first conductive type drift region 12 is, for example, an n-type drift region.

[0095] After step S2 , the preparation method may further include: forming a Schottky contact structure 17 or a second conductive type doped region on the first conductive type drift region 12 .

[0096] In step S3 , reactive ion etching is performed using a mask to form a device trench structure 141 and an edge trench structure 142 in the first conductive type drift region 12 .

[0097] In this embodiment, while forming the device trench structures 141 and the edge trench structures 142, a connection trench structure may also be formed in the first conductive type drift region 12 to form the electrical connection layer 19. The connection trench structure is located between at least one side surface of each device trench structure 141 in the second direction and the edge trench structure 142. The connection trench structure may be specifically arranged according to the number of the device trench structures 141 and the electrical connection method. For example, when it is required that one side surface of each polysilicon layer in the device trench structure 141 in the second direction be electrically connected to the polysilicon layer in the corresponding edge trench structure 142, a connecting trench structure is provided between the one side surface of the device trench structure 141 in the second direction and the edge trench structure 142, and the number of the connecting trench structures is the same as that of the device trench structure 141. When it is required that both sides of each polysilicon layer in the device trench structure 141 in the second direction be electrically connected to the polysilicon layer in the corresponding edge trench structure 142, a connecting trench structure is provided between both sides of the device trench structure 141 in the second direction and the edge trench structure 142, and the number of the connecting trench structures is twice the number of the device trench structure 141. The depth of the connecting trench structure is preferably the same as that of the edge trench structure 142 or the device trench structure 141, and the forming method of the connecting trench structure is also preferably the same as that of the device trench structure 141 and the edge trench structure 142.

[0098] In step S4 , the polysilicon layer and the isolation oxide layer are formed in the device trench structure 141 and the edge trench structure 142 , and an electrical connection layer 19 is formed in the connection trench.

[0099] The step of forming a plurality of polysilicon layers and isolation oxide layers in the device trench structure and the edge trench structure includes: alternately forming isolation oxide layers and polysilicon layers on the bottom surfaces of the edge trench structure 142 and the device trench structure 141 .

[0100] In this step, an isolation oxide layer is grown on the bottom surface of the device trench structure 141 and the edge trench structure 142 by a thermal oxidation or CVD process. Then, a highly doped n-type polysilicon layer is used as an electrode segment to fill the trench structure 141 and the edge trench structure 142. Another isolation oxide layer is grown on the polysilicon layer. Then, a highly doped n-type polysilicon layer is used again to fill the layer until all polysilicon layers are formed. The last polysilicon layer is electrically connected to the second metal layer. In this embodiment, each time an isolation oxide layer is grown in the device trench structure 141 and the edge trench structure 142, the isolation oxide layer also covers the side surfaces of the device trench structure 141 and the edge trench structure 142. After each time the device trench structure 141 and the edge trench structure 142 are filled with a highly doped n-type polysilicon layer, a portion of the polysilicon layer needs to be removed so that the thickness of the polysilicon layer formed each time can meet the corresponding potential requirements. Each time a portion of the polysilicon layer is removed, a portion of the isolation oxide layer on the side of the device trench structure 141 and the side of the edge trench structure 142 will also be removed, so that the isolation oxide layer on the side of the device trench structure 141 and the side of the edge trench structure 142 is flush with the top of the polysilicon layer.

[0101] When the electrical connection layer 19 is composed of a polysilicon line of the first conductivity type and an insulating layer wrapping the polysilicon line of the first conductivity type, in step S4, the electrical connection layer 19 can also be formed in the connection trench structure in the first conductivity type drift region 12. Specifically, an isolation oxide layer is grown on the bottom surface of the device trench structure 141 and the edge trench structure 142 by thermal oxidation or CVD, and an insulating layer is also grown at the bottom of the connection trench structure; while a highly doped n-type polysilicon layer is used as an electrode segment to fill the device trench structure 141 and the edge trench structure 142, a highly doped n-type polysilicon layer is also used as a conductive layer to fill the connection trench; while an isolation oxide layer is grown on the polysilicon layer, another isolation oxide layer is grown on the conductive layer; while a highly doped n-type polysilicon layer is again used to fill the device trench structure 141 and the edge trench structure 142, a highly doped n-type polysilicon layer is again used to fill the connection trench structure, until all electrical connection layers are formed. In this embodiment, the isolation oxide layer 16 does not need to be formed where the polysilicon layer in the device trench structure 141 and the edge trench structure 142 is electrically connected to the conductive layer of the connection trench to ensure electrical connection.

[0102] In other embodiments, the electrical connection layer may not be completed in the same process as the polysilicon layer and the isolation oxide layer, as long as the electrical connection layer is connected to the corresponding polysilicon layer.

[0103] In step S5, a second metal layer 132 is formed on the polysilicon layer, and a first metal layer 131 is simultaneously formed on a surface of the semiconductor substrate 11 away from the first conductivity type drift region 12. The second metal layer 132 may include a device metal layer 1321 located on the polysilicon layer in the device trench structure 141 and an edge metal layer 1322 located on the polysilicon layer in the edge trench structure 142. In this embodiment, the device metal layer 1321 and the edge metal layer 1322 are preferably formed simultaneously.

[0104] In step S4, while growing the isolation oxide layer 16 in the trench structure using a thermal oxidation or CVD process, a top oxide layer 18 is also formed on the first conductive type drift region 12 adjacent to the edge trench structure 142; and in step S5, while forming a second metal layer on the polysilicon layer, the edge metal layer 1322 also extends onto a portion of the top oxide layer 18.

[0105] When the power switching device further includes a first conductivity type source region 23 located on the second conductivity type doped region, and a gate oxide layer, a gate electrode 21, and a dielectric layer 24 located sequentially between the polysilicon layer and the second metal layer at the top of the device trench structure, after step S2, the following additional steps are required: after forming the second conductivity type body region 22 (second conductivity type doped region) on the first conductivity type drift region 12 by implanting boron ions, the first conductivity type source region 23 is formed by implanting phosphorus ions and then performing an annealing process; in step S4, a gate oxide layer is further formed on the polysilicon layer at the top of the device trench structure 141, as well as a gate electrode 21 and a dielectric layer 24 located on the gate oxide layer. The dielectric layer 24 is used to isolate the gate electrode from the second metal layer. Specifically, an additional polysilicon layer is deposited and planarized to serve as the gate electrode, followed by deposition of a dielectric material to form the dielectric layer 24, and etching contact windows for the first conductivity type source region 23 and the second conductivity type body region 22. Finally, the device is fabricated by depositing and patterning the second metal layer.

[0106] The power switching device fabricated using the above-described method for fabricating a power switching device in this embodiment can reduce the size of the power switching device and easily determine the potential of each electrode segment (polysilicon layer) in the device trench structure. Furthermore, by segmenting the electrodes in the device trench structure and edge trench structure (by providing multiple polysilicon layers), scalability and adaptability are achieved, making it easy to implement applications with different high blocking voltages.

[0107] Figure 6 A specific embodiment of a power switching device is shown for determining the potential of each electrode segment (polysilicon layer) in a MOSFET having a breakdown voltage of 400V. Figure 6 The power switching devices in Figure 5 The power switching devices in Figure 6 The polysilicon layer in each trench structure is divided into four sections, namely, the first polysilicon layer, the second polysilicon layer, the third polysilicon layer, and the fourth polysilicon layer from bottom to top. The potential of the fourth polysilicon layer in the edge trench structure 142 is 0V, the potential of the third polysilicon layer is 100V, the potential of the second polysilicon layer is 200V, the potential of the first polysilicon layer is 300V, and the potential of the first conductivity type drift region below the first polysilicon layer is 400V. The potential of the fourth polysilicon layer in the device trench structure 141 is 0V, the potential of the third polysilicon layer is 100V, the potential of the second polysilicon layer is 200V, the potential of the first polysilicon layer is 300V, and the potential of the first conductivity type drift region below the first polysilicon layer is 400V. That is, the potential difference between adjacent polysilicon layers and the potential difference between the bottom polysilicon layer and the bottom of the trench are both 100V. At least one side surface of each polysilicon layer in the device trench structure 141 in the second direction is electrically connected to the polysilicon layer in the corresponding edge trench structure 142 through the electrical connection layer 19. Figure 7a and Figure 7b In the embodiment, the first polysilicon layer in the device trench structure 141 is electrically connected to the first polysilicon layer in the edge trench structure 142 via an electrical connection layer 19 on one side in the second direction; the second polysilicon layer in the device trench structure 141 is electrically connected to the second polysilicon layer in the edge trench structure 142 via an electrical connection layer 19 on one side in the second direction; the third polysilicon layer in the device trench structure 141 is electrically connected to the third polysilicon layer in the edge trench structure 142 via an electrical connection layer 19 on one side in the second direction; and the fourth polysilicon layer in the device trench structure 141 is electrically connected to the fourth polysilicon layer in the edge trench structure 142 via an electrical connection layer 19 on one side in the second direction. For another example Figure 8a and Figure 8bIn the embodiment, the first polysilicon layer in the device trench structure 141 is electrically connected to the first polysilicon layer in the edge trench structure 142 via two electrical connection layers 19 on both sides in the second direction; the second polysilicon layer in the device trench structure 141 is electrically connected to the second polysilicon layer in the edge trench structure 142 via two electrical connection layers 19 on both sides in the second direction; the third polysilicon layer in the device trench structure 141 is electrically connected to the third polysilicon layer in the edge trench structure 142 via two electrical connection layers 19 on both sides in the second direction; and the fourth polysilicon layer in the device trench structure 141 is electrically connected to the fourth polysilicon layer in the edge trench structure 142 via two electrical connection layers 19 on both sides in the second direction. Both of the above connection methods can electrically connect the corresponding polysilicon layers (i.e., electrode segments) in the device trench structure 141 and the edge trench structure 142 with the same required potential, and can design all polysilicon layers in the device trench structure to have a smaller area, thereby saving space for the power switching device and simplifying the manufacturing process.

[0108] In addition, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

[0109] It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which may vary. It should also be understood that the terminology described herein is used only to describe specific embodiments and is not intended to limit the scope of the present invention. It should be noted that the singular forms "a," "an," and "the" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in their broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or," not a logical "exclusive or," unless the context clearly indicates otherwise. Structures described herein are to be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximating should be so interpreted unless the context clearly indicates otherwise.

Claims

1. A power switching device, characterized in that: include: a first metal layer; a semiconductor substrate, located on the first metal layer; A first conductive type drift region is located on the semiconductor substrate; a device trench structure and an edge trench structure arranged at intervals, wherein the edge trench structure surrounds the device trench structure, and both the device trench structure and the edge trench structure are located in the first conductive type drift region; a plurality of polysilicon layers, spaced apart in the device trench structure and the edge trench structure along a direction perpendicular to the semiconductor substrate, wherein the polysilicon layers in the edge trench structure correspond to the polysilicon layers in the device trench structure; an isolation oxide layer, located between adjacent polysilicon layers, between the polysilicon layer and the device trench structure, and between the polysilicon layer and the edge trench structure; an electrical connection layer, located between the polysilicon layer in the device trench structure and the corresponding polysilicon layer in the edge trench structure, to achieve electrical connection between the polysilicon layer in the device trench structure and the corresponding polysilicon layer in the edge trench structure; The second metal layer is located on the polysilicon layer.

2. The power switching device according to claim 1, wherein: The polysilicon layer and the isolation oxide layer in the device trench structure constitute a device electrode structure, the polysilicon layer and the isolation oxide layer in the edge trench structure constitute an edge electrode structure, the blocking voltage of the device electrode structure is equal to the blocking voltage of the edge electrode structure, and the blocking voltage of the device electrode structure is equal to the sum of the potential difference between all two adjacent polysilicon layers in the device trench structure and the potential difference between the bottom polysilicon layer and the bottom surface of the device trench structure; The blocking voltage of the edge electrode structure is equal to the sum of the potential difference between all two adjacent polysilicon layers in the edge trench structure and the potential difference between the bottom polysilicon layer and the bottom surface of the edge trench structure.

3. The power switching device according to claim 2, wherein: The potential difference V between two adjacent polysilicon layers in the edge trench structure 边 =h 边 / h 边总 ×V 边阻总 , where h 边 h is the thickness of the isolation oxide layer between the two adjacent polysilicon layers; 边总 V is the sum of the thickness of the isolation oxide layer between all two adjacent polysilicon layers in the edge trench structure and the thickness of the isolation oxide layer on the bottom surface of the edge trench structure; 边阻总 is the blocking voltage of the edge electrode structure.

4. The power switching device according to claim 1, wherein: The second metal layer includes a device metal layer located on the polysilicon layer in the device trench structure and an edge metal layer located on the polysilicon layer in the edge trench structure; the power switching device also includes: a top oxide layer on the first conductive type drift region adjacent to the edge trench structure, the top oxide layer is connected to the isolation oxide layer in the edge trench structure, and the edge metal layer extends onto a portion of the top oxide layer.

5. The power switching device according to claim 1, wherein: The power switch device further includes: a Schottky contact structure or a second conductive type doped region on the first conductive type drift region adjacent to the device trench structure.

6. The power switching device according to claim 5, wherein: When the power switching device includes a second conductive type doped region, the power switching device also includes a first conductive type source region located on the second conductive type doped region and a gate oxide layer, a gate electrode and a dielectric layer located in sequence between the polysilicon layer at the top of the device trench structure and the second metal layer.

7. The power switching device according to claim 5, wherein: The first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.

8. The power switching device according to claim 1, wherein: The electrical connection layer includes a polysilicon line of a first conductivity type and an insulating layer wrapping the polysilicon line of the first conductivity type.

9. The power switching device according to claim 1, wherein: The number of the device trench structures is one or more, and the edge trench structure surrounds all the device trench structures.

10. The power switching device according to claim 1, wherein: When there are multiple device trench structures, the multiple device trench structures are arranged in parallel along a first direction, and at least one side of each polysilicon layer in each device trench structure in a second direction is electrically connected to the polysilicon layer in the corresponding edge trench structure, and the first direction is perpendicular to the second direction.

11. A method for preparing a power switching device, characterized in that: The following steps are involved: providing a semiconductor substrate; forming a first conductivity type drift region on the semiconductor substrate; forming a spaced device trench structure and an edge trench structure in the first conductive type drift region, wherein the edge trench structure surrounds the device trench structure; forming a plurality of polysilicon layers and an isolation oxide layer in the device trench structure and the edge trench structure, and forming an electrical connection layer in the first conductive type drift region, wherein the plurality of polysilicon layers are spaced apart in the device trench structure and the edge trench structure along a direction perpendicular to the semiconductor substrate, and the polysilicon layer in the edge trench structure corresponds to the polysilicon layer in the device trench structure; The isolation oxide layer is arranged between adjacent polysilicon layers, between the polysilicon layer and the device trench structure, and between the polysilicon layer and the edge trench structure; the electrical connection layer is arranged between the polysilicon layer in the device trench structure and the corresponding polysilicon layer in the edge trench structure to achieve electrical connection between the polysilicon layer in the device trench structure and the corresponding polysilicon layer in the edge trench structure; A second metal layer is formed on the polysilicon layer, and a first metal layer is formed on the lower surface of the semiconductor substrate.

12. The method for preparing a power switching device according to claim 11, wherein: The polysilicon layer and the isolation oxide layer in the device trench structure constitute a device electrode structure, the polysilicon layer and the isolation oxide layer in the edge trench structure constitute an edge electrode structure, the blocking voltage of the device electrode structure is equal to the blocking voltage of the edge electrode structure, and the blocking voltage of the device electrode structure is equal to the sum of the potential difference between all two adjacent polysilicon layers in the device trench structure and the potential difference between the bottom polysilicon layer and the bottom surface of the device trench structure; The blocking voltage of the edge electrode structure is equal to the sum of the potential difference between all two adjacent polysilicon layers in the edge trench structure and the potential difference between the bottom polysilicon layer and the bottom surface of the edge trench structure.

13. The method for preparing a power switching device according to claim 12, wherein: The potential difference V between two adjacent polysilicon layers in the edge trench structure 边 =h 边 / h 边总 ×V 阻总 , where h 边 h is the thickness of the isolation oxide layer between two adjacent polysilicon layers; 边总 V is the sum of the thickness of the isolation oxide layer between all two adjacent polysilicon layers in the edge trench and the thickness of the isolation oxide layer on the bottom surface of the edge trench structure; 阻总 is the blocking voltage of the edge electrode structure.

14. The method for preparing a power switching device according to claim 11, wherein: The number of the device trench structures is one or more. When the number of the device trench structures is more than one, the multiple device trench structures are arranged in parallel along the first direction, and the edge trench structure surrounds all the device trench structures.

15. The method for preparing a power switching device according to claim 14, wherein: The electrical connection layer includes a polysilicon line of a first conductivity type and an insulating layer wrapping the polysilicon line of the first conductivity type.

16. The method for preparing a power switching device according to claim 15, wherein: In the step of forming the spaced device trench structure and the edge trench structure in the first conductive type drift region, a connection trench structure is also formed in the first conductive type drift region, and the connection trench structure is located between at least one side surface of each of the device trench structures in the second direction and the edge trench structure; the step of forming an electrical connection layer in the first conductive type drift region is: forming an electrical connection layer in the connection trench structure in the first conductive type drift region, and the first direction is perpendicular to the second direction.

17. The method for preparing a power switching device according to claim 16, wherein: The electrical connection layer in the connection trench structure corresponds to the polysilicon layer in the device trench structure, and at least one side surface of each polysilicon layer in the device trench structure in the second direction is electrically connected to the polysilicon layer in the corresponding edge trench through the electrical connection layer.

18. The method for preparing a power switching device according to claim 11, wherein: The step of forming a plurality of polysilicon layers and isolation oxide layers in the device trench structure and the edge trench structure includes: alternately forming isolation oxide layers and polysilicon layers on the bottom surfaces of the edge trench structure and the device trench structure.

19. The method for preparing a power switching device according to claim 11, wherein: The second metal layer includes a device metal layer located on the polysilicon layer in the device trench structure and an edge metal layer located on the polysilicon layer in the edge trench structure; in the step of forming a plurality of polysilicon layers and an isolation oxide layer in the device trench structure and the edge trench structure, a top oxide layer is also formed on the first conductive type drift region adjacent to the edge trench structure; In the step of forming a second metal layer on the polysilicon layer, the edge metal layer extends onto a portion of the top oxide layer.

20. The method for preparing a power switching device according to claim 19, wherein: The device trench structure and the edge trench structure are formed by a reactive ion etching process; and the isolation oxide layer and the top oxide layer are formed by a thermal oxidation process or a CVD process.

21. The method for preparing a power switching device according to claim 11, wherein: After the step of forming spaced device trench structures and edge trench structures in the first conductive type drift region, the preparation method further includes: forming a Schottky contact structure or a second conductive type doped region on the first conductive type drift region adjacent to the device trench structure.

22. The method for preparing a power switching device according to claim 21, wherein: The first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.

Images