Power switch device structure and preparation method thereof

Abstract

The invention provides a power switch device structure and a preparation method thereof. The power switch device structure comprises a drain metal layer; the semiconductor substrate is located on the drain metal layer; the first conduction type drift region is located on the semiconductor substrate; a trench structure located in the first conductive type drift region; the at least two polycrystalline silicon layers are arranged in the groove structure at intervals in the direction perpendicular to the semiconductor substrate; the isolation oxide layers are located between the adjacent polycrystalline silicon layers, between the polycrystalline silicon layer at the bottom and the bottom surface of the groove structure and on the side wall of the groove structure; and the source electrode metal layer is positioned on the polycrystalline silicon layer. According to the invention, a power switch device structure with high blocking voltage and low specific on-resistance can be obtained through the arrangement of the plurality of polycrystalline silicon layers and the isolation oxide layers in the groove structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power switch device structure and a preparation method thereof. Background Art

[0002] The structure of all power switching devices includes a drift region (Drift Region), which can withstand a blocking voltage (Blocking Voltage). Figure 1a The structure of a power switch device with a traditional drift region is shown, which includes a drain metal layer 0132, an n-type substrate 011 located on the drain metal layer 0132, a drift region 012 located on the n-type substrate 011, and a source metal layer 0131 located on the drift region 012. Figure 1b , the voltage results in a triangular electric field distribution in the uniformly doped drift region 012, where the slope of the field distribution is determined by the doping concentration of the drift region 012. The maximum voltage (breakdown voltage, BV) that the drift region 012 can withstand is determined by the maximum electric field (Em) that reaches the critical electric field (Ec) at which the semiconductor material breaks down. The critical electric field and the doping concentration of the drift region 012 determine the maximum depletion width (WD), i.e.

[0003] WD=2×BV / Ec (1)

[0004] The ideal specific on-resistance (Ron.sp, resistance per unit area) of the drift region 012 can be given by the following formula:

[0005] Ron.sp=WD / (q×μn×ND) (2)

[0006] Where q is the charge, μn is the electron mobility, and ND is the doping concentration in the drift region.

[0007] The doping concentration in the drift region 012 required to obtain the breakdown voltage can be given by the following formula:

[0008] ND=εs×Ec×Ec / (2×q×BV) (3)

[0009] Where εs is the dielectric constant of the semiconductor material.

[0010] Combining formulas (1), (2) and (3), we get the ideal drift region specific on-resistance:

[0011] Ron.sp=4×BV×BV / (εs×μn×Ec×Ec×Ec) (4)

[0012] It can be seen from the above formula that the specific on-resistance has a strong dependence on the critical electric field, and the specific on-resistance is proportional to the cube of the critical electric field.

[0013] Figure 2a A charge-coupled structure with a two-dimensional electric field (i.e., the power switching device structure is a charge-coupled structure with a two-dimensional electric field) is shown, and its drift region has a trench electrode, specifically including a drain metal layer 0232, an n-type substrate 021 located on the drain metal layer 0232, a drift region 022 located on the n-type substrate 021, a Schottky contact structure 024 located on the drift region 022, a trench structure (not marked in the figure) located in the drift region 022, a polysilicon layer (i.e., a trench electrode) 025 located in the trench structure, an isolation oxide layer 026 located between the polysilicon layer 025 and the trench structure (bottom surface and sidewalls), and a source metal layer 0231 located on the polysilicon layer 025. The charge-coupled structure exhibits a two-dimensional charge coupling effect, namely, a junction in the x-direction (e.g., a junction formed by a Schottky contact) and another junction in the y-direction (e.g., a junction formed by the polysilicon layer 025, the isolation oxide layer 026, and the drift region 022 beneath the source metal layer 0231) generate depletion layers in two directions within the drift region 022 and interact with each other, enhancing voltage blocking capability by extending the depletion layer in two dimensions. A horizontal PN junction can also be used in the charge-coupled structure instead of a Schottky junction. The horizontal PN junction promotes the extension of the depletion region along the y-direction, while the vertical trench structure with the trench electrode inside promotes the extension of the depletion region in the x-direction. Figure 2b Shown Figure 2a The electric field distribution corresponding to the charge coupling structure in the circuit. It has been found that the highest breakdown voltage generated by the charge can be given by the following formula:

[0014] Qoptimum=q×ND×WN / 2=εs×Ec (5)

[0015] Wherein, Qoptimum is the optimal charge coupling amount per unit area, and WN is the width of the drift region 022 between the two trench structures.

[0016] The depth of the trench structure can be given by the following formula:

[0017] t=BV / Ec (6)

[0018] Wherein, t is the depth of the trench structure.

[0019] The specific on-resistance (RD.sp, resistance per unit area) of the ideal drift region 022 can be given by the following formula:

[0020] RD.sp=t×p / (q×μn×ND×WN) (7)

[0021] Where p is the unit pitch.

[0022] Combining equations (5), (6) and (7), the specific on-resistance of the ideal drift region with a two-dimensional electric field structure is obtained:

[0023] RD.sp=BV×p / (2×es×μn×Ec×Ec)(8)

[0024] By comparing formula (8) with formula (4) in the one-dimensional case, it can be observed that the specific on-resistance in the one-dimensional electric field structure is proportional to the square of the breakdown voltage, while the specific on-resistance of the charge-coupled device increases linearly with the breakdown voltage. Although the charge-coupled device increases the blocking voltage capability and reduces the on-resistance, it requires a thick isolation oxide layer on the sidewall of the trench structure and the bottom surface of the trench structure, and the equidistant potential lines in the isolation oxide layer on the bottom surface of the trench structure are very dense (see Figure 2a ).

[0025] For high blocking voltage applications, the above-mentioned charge coupling structure needs to increase the thickness of the isolation oxide layer (since the maximum electric field strength of the isolation oxide layer is limited to 2×10 6 For voltages below 200 V / cm, the thickness of the isolation oxide layer on the sidewalls and bottom of the trench structure needs to increase by 0.5 microns for every 100 V increase. This results in a very thick isolation oxide layer in the trench structure, which creates strong stress at the interface between the drift region (silicon) and the isolation oxide layer (silicon oxide), increases the cell pitch, and further increases the specific on-resistance. Therefore, the aforementioned charge-coupled structure is currently limited to applications with blocking voltages below 200 V.

[0026] See Figure 3 The above structure can also be used in an edge termination structure to avoid a drop in blocking voltage at the edge. The edge termination structure may include a drain metal layer 0332, an n-type substrate 031 located on the drain metal layer 0332, a drift region 032 located on the n-type substrate 031, a trench structure (not shown) located in the drift region 032, a polysilicon layer (i.e., a trench electrode) 035 located in the trench structure, an isolation oxide layer 036 located between the polysilicon layer 035 and the trench structure (sidewalls and bottom surface), and a source metal layer 0331 located on the polysilicon layer 035. The isolation oxide layer 036 also extends from the sidewalls of the trench structure to the drift region 032, and the source metal layer 0331 extends to cover a portion of the isolation oxide layer 036. In this structure, the surface at the edge is covered by the isolation oxide layer 036 and connected to the isolation oxide layer 036 on the sidewall of the trench structure, and the source metal layer 0331 is expanded to cover a portion of the isolation oxide layer 036 at the edge. However, due to the same reasons mentioned above, this edge termination structure is also limited to a blocking voltage below 200V.

[0027] In patent application US6110804A, a floating field conductor is placed on the top surface of the FET drift region to provide field shaping for the lateral MOSFET at the surface of the drift region. Charge is injected into the floating field conductor, causing a depletion region to form in the drift region. However, the two-dimensional charge coupling is not effective, especially in regions far from the surface, so the improvement in blocking voltage is not significant. In addition, the gate electrode transfer capacitance and output capacitance are not improved, and the current density is also low.

[0028] Patent application US8592906A describes a lateral MOSFET having a source and drain extending along the top surface of a semiconductor substrate, with an active region disposed between the source and drain regions within the semiconductor substrate. The active region is disposed adjacent to a segmented field plate extending from the source region to the drain region, thereby also achieving a two-dimensional charge coupling effect. This structure is easy to implement. However, it has low current density, high specific on-resistance, and high transfer capacitance, making it unsuitable for high-power and high-voltage applications. Summary of the Invention

[0029] The object of the present invention is to provide a power switch device structure and a preparation method thereof, so as to obtain a power switch device structure with high blocking voltage and low specific on-resistance.

[0030] In order to achieve the above-mentioned object and other related objects, the present invention provides a power switch device structure, comprising:

[0031] drain metal layer;

[0032] a semiconductor substrate, located on the drain metal layer;

[0033] A first conductive type drift region is located on the semiconductor substrate;

[0034] a trench structure located in the first conductive type drift region;

[0035] At least two polysilicon layers are spaced apart and arranged in the trench structure along a direction perpendicular to the semiconductor substrate;

[0036] an isolation oxide layer, located between adjacent polysilicon layers, between the bottom polysilicon layer and the bottom surface of the trench structure, and on the sidewalls of the trench structure;

[0037] The source metal layer is located on the polysilicon layer.

[0038] Optionally, in the power switching device structure, the blocking voltage of the power switching device structure is equal to the sum of the potential differences between all two adjacent polysilicon layers and the potential difference between the bottom polysilicon layer and the bottom surface of the trench structure.

[0039] Optionally, in the power switching device structure, the potential difference between the two adjacent polysilicon layers is obtained according to the thickness of the isolation oxide layer between the two adjacent polysilicon layers, and the potential difference between the bottom polysilicon layer and the bottom surface of the trench structure is obtained according to the thickness of the isolation oxide layer between the bottom polysilicon layer and the bottom surface of the trench structure, and when the thickness of the isolation oxide layer between the two adjacent polysilicon layers is equal to the thickness of the isolation oxide layer between the bottom polysilicon layer and the bottom surface of the trench structure, the corresponding potential differences are the same.

[0040] Optionally, in the power switch device structure, the power switch device structure further includes a Schottky contact structure or a second conductive type doped region located on the first conductive type drift region.

[0041] Optionally, in the power switching device structure, when the power switching device structure includes a second conductive type doped region, the power switching device structure also includes a first conductive type source region located on the second conductive type doped region and a gate oxide layer, a gate electrode and a dielectric layer located in sequence between the polysilicon layer at the top of the trench structure and the source metal layer.

[0042] Optionally, in the power switch device structure, the first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.

[0043] Optionally, in the power switching device structure, the power switching device structure further includes a top oxide layer located on the first conductive type drift region, the top oxide layer is connected to the isolation oxide layer, and the source metal layer extends onto a portion of the top oxide layer.

[0044] Optionally, in the power switch device structure, the smaller the thickness of the isolation oxide layer between the two adjacent polysilicon layers, the smaller the thickness of the polysilicon layer on the isolation oxide layer.

[0045] In order to achieve the above-mentioned object and other related objects, the present invention further provides a method for preparing a power switching device structure, comprising the following steps:

[0046] providing a semiconductor substrate;

[0047] forming a first conductivity type drift region on the semiconductor substrate;

[0048] A trench structure is formed in the first conductive type drift region.

[0049] forming at least two polysilicon layers and an isolation oxide layer spaced apart in a direction perpendicular to the semiconductor substrate in the trench structure, wherein the isolation oxide layer is located between adjacent polysilicon layers, between the bottom polysilicon layer and the bottom surface of the trench structure, and on the sidewalls of the trench structure;

[0050] A source metal layer is formed on the polysilicon layer, and a drain metal layer is formed on the lower surface of the semiconductor substrate.

[0051] Optionally, in the method for preparing the power switching device structure, the blocking voltage of the power switching device structure is equal to the sum of the potential differences between all two adjacent polysilicon layers and the potential differences between the bottom polysilicon layer and the bottom surface of the trench structure.

[0052] Optionally, in the preparation method of the power switching device structure, the potential difference between the two adjacent polysilicon layers is obtained according to the thickness of the isolation oxide layer between the two adjacent polysilicon layers, and the potential difference between the bottom polysilicon layer and the bottom surface of the trench structure is obtained according to the thickness of the isolation oxide layer between the bottom polysilicon layer and the bottom surface of the trench structure, and when the thickness of the isolation oxide layer between the two adjacent polysilicon layers is equal to the thickness of the isolation oxide layer between the bottom polysilicon layer and the bottom surface of the trench structure, the corresponding potential differences are the same.

[0053] Optionally, in the method for preparing the power switching device structure, in the step of forming at least two polysilicon layers and an isolation oxide layer spaced apart in a direction perpendicular to the semiconductor substrate in the trench structure, a top oxide layer is also formed on the first conductive type drift region, and the top oxide layer is connected to the isolation oxide layer; in the step of forming a source metal layer on the polysilicon layer, the source metal layer extends onto a portion of the top oxide layer.

[0054] Optionally, in the method for preparing the power switching device structure, the trench structure is formed by a reactive ion etching process; and the isolation oxide layer and the top oxide layer are formed by a thermal oxidation process or a CVD process.

[0055] Optionally, in the preparation method of the power switching device structure, after the step of forming a trench structure in the first conductive type drift region, the preparation method further includes: forming a Schottky contact structure or a second conductive type doping region on the first conductive type drift region.

[0056] Optionally, in the method for preparing the power switch device structure, the first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.

[0057] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0058] In the power switching device structure provided by the present invention, at least two polysilicon layers are spaced apart in a direction perpendicular to the semiconductor substrate within the trench structure, and the blocking voltage is divided. This allows the present invention to prevent the thickness of the isolation oxide layer on the sidewalls and bottom surface of the trench structure from increasing as the blocking voltage of the power switching device structure increases. Furthermore, the potential difference between two adjacent polysilicon layers and the potential difference between the bottom polysilicon layer and the bottom surface of the trench structure are both less than the blocking voltage of the power switching device structure. This reduces the thickness of the isolation oxide layer on the bottom surface of the trench structure and the isolation oxide layer on the sidewalls of the trench structure, thereby reducing stress at the interface between the first conductive type drift region and the isolation oxide layer, and thereby reducing the specific on-resistance. Therefore, the present invention can provide a power switching device structure with a high blocking voltage and a low specific on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1a Schematic diagram of the structure of a power switch device with a traditional drift region;

[0060] Figure 1b for Figure 1a The electric field distribution diagram under the blocking voltage corresponding to the power switching device in;

[0061] Figure 2a A schematic diagram of a charge-coupled structure with a two-dimensional electric field and a distribution diagram of equidistant potential lines under blocking voltage;

[0062] Figure 2b for Figure 2a The electric field distribution diagram under blocking voltage corresponding to the charge coupling structure in FIG;

[0063] Figure 3 A schematic diagram of an edge terminal structure and a distribution diagram of equidistant potential lines under blocking voltage;

[0064] Figure 4 A schematic diagram of the structure of a power switch device according to an embodiment of the present invention and a distribution diagram of equidistant potential lines under blocking voltage;

[0065] Figure 5 A schematic diagram of the structure of a power switch device and a distribution diagram of equidistant potential lines under blocking voltage according to another embodiment of the present invention;

[0066] Figure 6 A schematic diagram of the structure of a vertical MOSFET used in the power switch device structure of the present invention and a distribution diagram of equidistant potential lines under blocking voltage;

[0067] Figure 7This is a schematic diagram of the structure of the power switch device structure in the present invention applied to an edge terminal structure MOSFET. DETAILED DESCRIPTION

[0068] The power switching device structure and its manufacturing method proposed in the present invention are further described in detail below, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0069] See Figure 4 The present invention provides a power switching device structure, comprising:

[0070] drain metal layer 132;

[0071] A semiconductor substrate 11 is located on the drain metal layer 132;

[0072] A first conductive type drift region 12 is located on the semiconductor substrate 11;

[0073] The trench structure (not marked in the figure) is located in the first conductive type drift region 12 .

[0074] At least two polysilicon layers 15 are spaced apart and arranged in the trench structure along a direction perpendicular to the semiconductor substrate 11;

[0075] an isolation oxide layer 16, located between adjacent polysilicon layers 15, between the bottom polysilicon layer 15 and the bottom surface of the trench structure, and on the sidewalls of the trench structure;

[0076] The source metal layer 131 is located on the polysilicon layer 15 .

[0077] In this embodiment, the drain metal layer 132 and the source metal layer 131 may be made of conventional electrode materials, such as Ti (titanium), Ni (nickel), and Pt (platinum), but are not limited thereto. The source metal layer 131 is electrically connected to the polysilicon layer 15 .

[0078] The semiconductor substrate 11 is located on the drain metal layer 132, and the semiconductor substrate 11 is preferably a semiconductor substrate of the first conductivity type. The first conductivity type is n-type, and the second conductivity type is p-type; alternatively, the first conductivity type is p-type, and the second conductivity type is n-type. The following content is described using the example of the first conductivity type being n-type and the second conductivity type being p-type. That is, in this embodiment, the semiconductor substrate of the first conductivity type is an n-type semiconductor substrate, and is preferably a heavily doped n-type semiconductor substrate. Its doping concentration can be set according to the semiconductor substrate of the power switching device in the prior art, which is not described in detail here.

[0079] The first conductive type drift region 12 is located on the semiconductor substrate 11. The material of the first conductive type drift region 12 is preferably single crystal silicon, but is not limited thereto. The thickness of the first conductive type drift region 12 depends on the blocking voltage. The higher the required blocking voltage, the greater the thickness of the first conductive type drift region 12. For example, the thickness of the first conductive type drift region 12 required to achieve a blocking voltage of 400V is at least 20 microns. Therefore, the thickness of the first conductive type drift region 12 can be set according to the blocking voltage requirement. In this embodiment, the first conductive type drift region 12 is an n-type drift region, which is doped with n-type ions, such as phosphorus. The doping concentration of the n-type ions can adopt the doping concentration in the drift region of the power switching device in the prior art, which will not be elaborated here.

[0080] The trench structure is located in the first conductive type drift region 12. In this embodiment, the depth of the trench structure is less than the depth of the first conductive type drift region 12, that is, there is a small space between the bottom surface of the trench structure and the bottom surface of the first conductive type drift region 12. The depth of the trench structure can be set according to formula (6), where the critical electric field (Ec) is a set value, which can be set according to process requirements, for example, 2×10 5 The depth of the trench structure of this embodiment must be adjusted to achieve the desired breakdown voltage.

[0081] In this embodiment, at least two polysilicon layers 15 are spaced apart in the trench structure along a direction perpendicular to the semiconductor substrate 11 (the y-direction). Isolation oxide layers 16 are disposed between adjacent polysilicon layers 15, between the bottom polysilicon layer 15 and the bottom surface of the trench structure, and on the sidewalls of the trench structure. The isolation oxide layers 16 located on the sidewalls and bottom surface of the trench structure isolate the polysilicon layers 15 from the first conductivity type drift region 12. The polysilicon layers 15 in this embodiment can serve as trench electrodes. The polysilicon layers 15 are preferably doped with ions of the first conductivity type. Specifically, the polysilicon layers 15 in this embodiment are preferably made of highly doped n-type polysilicon, and their doping concentration can be the same as that of polysilicon layers in conventional power switching devices, which will not be described in detail here. The isolation oxide layers 16 are preferably made of silicon dioxide, but are not limited thereto. Compared to the entire polysilicon layer in conventional trench structures, this embodiment divides the entire polysilicon layer in the trench structure into at least two segments.

[0082] The blocking voltage of the power switch device structure is equal to the sum of the potential differences between all two adjacent polysilicon layers 15 and the potential difference between the bottom polysilicon layer 15 and the bottom surface of the trench structure. The potential difference between the two adjacent polysilicon layers 15 is determined by the thickness of the isolation oxide layer 16 between the two adjacent polysilicon layers 15 (i.e., the potential difference between the two adjacent polysilicon layers 15 is obtained based on the thickness of the isolation oxide layer 16 between the two adjacent polysilicon layers 15). The potential difference between the bottom polysilicon layer 15 and the bottom surface of the trench structure is determined by the thickness of the isolation oxide layer 16 on the bottom surface of the trench structure (i.e., the potential difference between the bottom polysilicon layer 15 and the bottom surface of the trench structure is obtained based on the thickness of the isolation oxide layer 16 between the bottom polysilicon layer 15 and the bottom surface of the trench structure). In this embodiment, the thickness of the isolation oxide layer 16 between adjacent polysilicon layers 15 can be the same or different. The thickness of the isolation oxide layer 16 between two adjacent polysilicon layers 15 and the thickness of the isolation oxide layer 16 on the bottom surface of the trench structure (i.e., the isolation oxide layer 16 between the bottom polysilicon layer 15 and the bottom surface of the trench structure) can be the same or the same. When the thickness of the isolation oxide layer 16 between the two adjacent polysilicon layers 15 is equal to the thickness of the isolation oxide layer 16 between the bottom polysilicon layer 15 and the bottom surface of the trench structure, the corresponding potential differences are the same, i.e., the potential difference between the two adjacent polysilicon layers 15 is equal to the potential difference between the bottom polysilicon layer 15 and the bottom surface of the trench structure. For example, Figure 4The power switching device structure in the embodiment includes two polysilicon layers 15, namely a first polysilicon layer 151 and a second polysilicon layer 152. When the thickness of the spacer oxide layer 16 between the first polysilicon layer 151 and the second polysilicon layer 152 is equal to the thickness of the spacer oxide layer 16 between the first polysilicon layer 151 and the bottom surface of the trench structure, the potential difference between the first polysilicon layer 151 and the second polysilicon layer 152 is equal to the potential difference between the first polysilicon layer 151 and the bottom surface of the trench structure, and both are equal to half the blocking voltage. In this embodiment, under a constant blocking voltage, equidistant potential lines are evenly distributed in the spacer oxide layer 16 between the first polysilicon layer 151 and the second polysilicon layer 152, and in the spacer oxide layer 16 between the first polysilicon layer 151 and the bottom surface of the trench structure. For another example, for a blocking voltage of 400V and a desired potential difference of 200V between two adjacent polysilicon layers 15, two polysilicon layers are required. This means that the potential difference between the two polysilicon layers and between the bottom polysilicon layer and the bottom surface of the trench structure is the same and equal to 200V, so the thickness of the isolation oxide layer therebetween should be 1 micron. In addition, the thickness of the isolation oxide layer on the sidewalls of the trench structure can also be 1 micron. In the case of a trench structure without trench electrode separation in the prior art, the thickness of the isolation oxide layer on the bottom surface and sidewalls of the trench structure should be 2 microns. Therefore, compared with the prior art, the thickness of the isolation oxide layer on the bottom surface of the trench structure and the sidewalls of the trench structure in this embodiment is reduced, which will reduce the stress between the isolation oxide layer and the first conductivity type drift region, thereby reducing the specific on-resistance.

[0083] In this embodiment, the potential difference between the first polysilicon layer 151 and the bottom surface of the trench structure should actually be the potential difference between the first polysilicon layer 151 and the first conductive type drift region 12. However, the potential drop in the first conductive type drift region 12 below the bottom surface of the trench structure is very small and can be ignored. Therefore, the electric field strength in the isolation oxide layer 16 does not exceed 2×10 6 V / cm, the thickness of the isolation oxide layers therebetween (the isolation oxide layer 16 between the second polysilicon layer 152 and the first polysilicon layer 151, and the isolation oxide layer 16 between the first polysilicon layer 151 and the bottom surface of the trench structure) can also be reduced to half the thickness required for the same blocking voltage in the prior art. In this embodiment, the greater the number of polysilicon layers 15, the greater the reduction in the thickness of the isolation oxide layers 16 therebetween. At the same time, for the same blocking voltage, the thickness of the isolation oxide layer 16 on the sidewalls of the trench structure can also be reduced to approximately half the thickness required in the prior art.

[0084] In this embodiment, the isolation oxide layer 16 between the polysilicon layers 15 and the isolation oxide layer 16 between the bottom polysilicon layer 15 and the bottom surface of the trench structure (i.e., the middle oxide layer) can withstand the potential difference that the isolation oxide layer 16 on the side wall of the trench structure also needs to be able to withstand. Therefore, the thickness of the isolation oxide layer 16 on the side wall of the trench can be greater than or equal to the thickness of the middle isolation oxide layer 16, and of course it can also be slightly smaller than the thickness of the middle isolation oxide layer 16, mainly because the first conductive type drift region 12 can withstand a very small part of the voltage.

[0085] To further reduce the isolation oxide thickness and specific on-resistance on the trench structure's sidewalls, more polysilicon layers 15 can be provided. For example, for a 400V blocking voltage application, if four polysilicon layers are provided in the trench structure, with the potential difference between adjacent polysilicon layers equal to 100V, the isolation oxide thickness between the polysilicon layers and the thickness between the bottom polysilicon layer and the bottom surface of the trench structure are both 0.5 microns. Furthermore, the isolation oxide thickness on each trench sidewall is also 0.5 microns, and the thickness of each polysilicon layer is equal to (20 – 4 × 0.5) / 4 = 18 / 4 = 4.5 microns, where 20 is the depth of the trench structure. Compared to the case where the potential difference between adjacent polysilicon layers is 200V (two polysilicon layers are provided), the isolation oxide thickness corresponding to the case where the potential difference between adjacent polysilicon layers is 100V is further reduced. However, this structure also increases the number of manufacturing process steps. In applications, it is necessary to balance the contradiction between improving performance by reducing the thickness of the isolation oxide layer and increasing the number of manufacturing process steps and increasing manufacturing costs to achieve the best effect.

[0086] In this embodiment, the smaller the thickness of the isolation oxide layer 16, the smaller the thickness of the polysilicon layer 15 adjacent to the isolation oxide layer 16, so that the distribution of the electric field will be more uniform. This embodiment utilizes the design of the above-mentioned polysilicon layer to easily produce a two-dimensional charge coupling effect, and will not increase the thickness of the isolation oxide layer on the sidewalls and bottom surface of the trench structure. This embodiment does not increase the thickness of the isolation oxide layer on the sidewalls and bottom of the trench structure as the blocking voltage increases, and thus does not increase the specific on-resistance. Moreover, as the number of polysilicon layers in the trench structure increases, the thickness of the isolation oxide layer on the sidewalls and bottom surface of the trench structure will decrease, which can reduce the stress at the interface between the first conductive type drift region and the isolation oxide layer, reduce the cell spacing, and reduce the specific on-resistance. Therefore, the present invention can obtain a power switching device structure with high blocking voltage and low specific on-resistance.

[0087] Continuing with reference to 4, the power switch device structure is a two-dimensional electric field charge coupling structure, and the power switch device structure further includes: a Schottky contact structure 14 or a second conductive type doped region located on the first conductive type drift region 12. The junction on the surface of the first conductive type drift region 12 can be a Schottky junction formed by the Schottky contact structure 14 through the Schottky contact (see Figure 4 ), or a PN junction formed by the second conductive type doping region through the second conductive type doping. For example, if the first conductive type drift region 12 is an n-type drift region, the junction on the surface of the n-type drift region can be a Schottky junction or a PN junction formed by a p-type doping region. For another example, if the first conductive type drift region 12 is a p-type drift region, the junction on the surface of the p-type drift region can be a Schottky junction or a PN junction formed by an n-type doping region. The material of the Schottky contact structure 14 is preferably metal. In this embodiment, the Schottky contact structure 14 or the second conductive type doping region can be set and prepared by the Schottky contact structure and the second conductive type doping region in the power switching device structure of the prior art, which will not be elaborated here. For example, when the power switching device structure is applied to a vertical MOSFET, the junction on the surface of the first conductive type drift region 12 is a PN junction. When the power switching device structure is a charge coupling structure of a two-dimensional electric field, and when the power switching device structure includes a second conductive type doped region, the power switching device structure may further include a first conductive type source region located on the second conductive type doped region and a gate oxide layer, a gate electrode, and a dielectric layer located in sequence between the polysilicon layer 15 at the top of the trench structure and the source metal layer 131.

[0088] See Figure 5 In another embodiment, the power switch device structure is an edge terminal structure to improve the blocking voltage capability of the trench structure edge. Figure 4 The difference between the charge coupling structure in the embodiment and the embodiment is that the edge terminal structure grows a top oxide layer 17 on the surface of the first conductive type drift layer 12 on one side of the trench structure, instead of growing a Schottky contact structure 14 or a second conductive type doped region, and there is no need to set a gate oxide layer, a gate electrode and a dielectric layer. In addition, the source metal layer 131 is extended to cover part of the top oxide layer 17 to improve the shielding of the electric field, thereby further avoiding the reduction of the breakdown voltage on the surface.

[0089] In this embodiment, the top oxide layer 17 is connected to the isolation oxide layer 16. The top oxide layer 17 and the isolation oxide layer 16 are preferably made of the same material. The thickness of the top oxide layer 17 can be set by the thickness of the top oxide layer of the power switching device in the prior art, which will not be described in detail here.

[0090] This embodiment utilizes the above-mentioned design of the polysilicon layer, which easily generates a two-dimensional charge coupling effect without increasing the thickness of the isolation oxide layer on the sidewalls and bottom surface of the trench structure.

[0091] In addition, the present invention also provides a method for preparing the above-mentioned power switch device structure, which specifically includes:

[0092] Step S1: providing a semiconductor substrate 11;

[0093] Step S2: forming a first conductive type drift region 12 on the semiconductor substrate 11;

[0094] Step S3: forming a trench structure in the first conductive type drift region 12;

[0095] Step S4: forming at least two polysilicon layers 15 and an isolation oxide layer 16 spaced apart in a direction perpendicular to the semiconductor substrate 11 in the trench structure, wherein the isolation oxide layer 16 is located between adjacent polysilicon layers 15, between the bottom polysilicon layer 15 and the bottom surface of the trench structure, and on the sidewalls of the trench structure;

[0096] Step S5 : forming a source metal layer 131 on the polysilicon layer, and forming a drain metal layer 132 on the lower surface of the semiconductor substrate 11 .

[0097] In step S1 , the semiconductor substrate 11 is preferably a heavily doped semiconductor substrate of the first conductivity type, such as a heavily doped n-type semiconductor substrate.

[0098] In step S2, epitaxial growth is performed on the semiconductor substrate 11 to form a first conductive type drift region 12. The first conductive type drift region 12 is, for example, an n-type drift region.

[0099] In step S3 , reactive ion etching is performed using a mask to form a trench structure in the first conductive type drift region 12 .

[0100] In step S4, an isolation oxide layer is grown on the bottom surface of the trench structure by thermal oxidation or CVD, and then a highly doped n-type polysilicon layer is used as a trench electrode to fill the trench structure. Another isolation oxide layer is grown on the polysilicon layer. Then, a highly doped n-type polysilicon layer is used to fill the trench structure again until all polysilicon layers are formed, and the last polysilicon layer is connected to the source metal layer 131. In this embodiment, each time an isolation oxide layer is grown, the isolation oxide layer also covers the sidewalls of the trench structure. After each time a highly doped n-type polysilicon layer is used as a trench electrode to fill the trench structure, a portion of the polysilicon layer needs to be removed to ensure that the thickness of the polysilicon layer formed each time can meet the corresponding potential requirements. Each time a portion of the polysilicon layer is removed, a portion of the isolation oxide layer on the sidewalls of the trench structure is also removed, so that the isolation oxide layer on the sidewalls of the trench structure is flush with the top of the polysilicon layer.

[0101] In step S5 , a source metal layer 131 is formed on the polysilicon layer 15 , and a drain metal layer 132 is formed on a surface of the semiconductor substrate 11 away from the first conductive type drift region 12 .

[0102] When the power switching device structure is a charge coupling structure with a two-dimensional electric field, after step S2 , the preparation method may further include: forming a Schottky contact structure 14 or a second conductive type doped region on the first conductive type drift region 12 .

[0103] When the power switching device structure is an edge terminal structure, in step S4, while growing the isolation oxide layer 16 in the trench structure using a thermal oxidation or CVD process, a top oxide layer 17 is also formed on the first conductive type drift region 12; and in step S5, while forming the source metal layer 131 on the polysilicon layer 15, the source metal layer 131 also extends to a portion of the top oxide layer 17.

[0104] Figure 6A specific embodiment of the power device described above being applied to a vertical MOSFET is shown, which is a trench MOSFET structure combining electrode segmentation with a vertical MOSFET, i.e., an example of the application of a 400V blocking voltage vertical power MOSFET with two polysilicon layers in the trench. The device structure of this embodiment includes: a drain metal layer 232; a semiconductor substrate 21, located on the drain metal layer 232; an n-type drift region 22, located on the semiconductor substrate 21; a trench structure, located in the n-type drift region 22; two polysilicon layers, namely a first polysilicon layer 251 and a second polysilicon layer 252, spaced apart in the trench structure along a direction perpendicular to the semiconductor substrate 21; an isolation oxide layer 26, located between the first polysilicon layer 251 and the second polysilicon layer 252, between the first polysilicon layer 251 and the bottom surface of the trench structure, and on the sidewalls of the trench structure, and the potential difference between the first polysilicon layer 251 and the second polysilicon layer 252 is equal to the potential difference between the first polysilicon layer 251 and the bottom surface of the trench structure, both of which are 200V; a source metal layer 231, electrically connected to the second polysilicon layer 252. The device structure of this embodiment may further include: a gate electrode 210, a gate oxide layer 29, and a dielectric layer 27. The gate electrode 210 is isolated from the second polysilicon layer 252 by the gate oxide layer 29. The dielectric layer 27 is located between the gate electrode 210 and the source metal layer 231. The material of the gate electrode 210 is preferably the same as that of the polysilicon layer. The material of the dielectric layer 27 and the gate oxide layer 29 is preferably silicon oxide, but is not limited thereto. The thickness of the gate electrode 210, the dielectric layer 27, and the gate oxide layer 29 can adopt the thickness of the gate electrode 210, the dielectric layer 27, and the gate oxide layer 29 of the power switching device structure in the prior art, and will not be described in detail here.

[0105] The device structure of this embodiment may further include a p-type body region 24 (i.e., a second conductive type doped region) and an n-type source region 28 (i.e., a first conductive type source region), and the p-type body region 24 is located on the n-type drift region 22 on both sides of the gate electrode 210, and the n-type source region 28 is located on the p-type body region 24 on both sides of the gate electrode 210 and is adjacent to the gate electrode 210, and the source metal layer 231 sequentially covers the p-type body region 24, the n-type source region 28, the dielectric layer 27, the n-type source region 28, and the p-type body region 24 along a direction parallel to the semiconductor substrate 21 (upper surface).

[0106] After the step of growing the n-type drift region 22 on the semiconductor substrate 21, Figure 6The method for preparing the device structure in the embodiment of the present invention requires the following additional steps: forming a p-type body region 24 on the active region (n-type drift region 22) of the device by implanting boron ions, and then generating an n-type source region 28 by implanting phosphorus ions and then performing an annealing process. A mask needs to be set when implanting the n-type source region 28. Figure 6 In the method for preparing the device structure, during the step of forming two polysilicon layers spaced apart and perpendicular to the semiconductor substrate 21 and the isolation oxide layer 26, a gate oxide layer 29 is formed on the second polysilicon layer 252, a gate electrode 210 is formed on the gate oxide layer 29, and a dielectric layer 27 is formed. The dielectric layer 27 is used to isolate the gate electrode and the source metal layer in the trench. Specifically, an additional polysilicon layer is deposited and planarized to serve as the gate electrode, followed by deposition of an intermetallic dielectric to form the dielectric layer 27, and etching of contact windows for the n-type source region and the p-type body region. Finally, the device is fabricated by depositing and patterning the source metal layer.

[0107] Figure 7 This is a specific embodiment of the application of a power switching device structure to an edge-terminated MOSFET, that is, an example of the application of an edge-terminated MOSFET with a blocking voltage of 400V having two polysilicon layers in a trench. The structure of this embodiment includes: a drain metal layer 332; a semiconductor substrate 31, located on the drain metal layer 332; an n-type drift region 32, located on the semiconductor substrate 31; a trench structure, located in the n-type drift region 32; two polysilicon layers, namely a first polysilicon layer 351 and a second polysilicon layer 352, spaced apart in the trench structure along a direction perpendicular to the semiconductor substrate 31; an isolation oxide layer 36, located between the first polysilicon layer 351 and the second polysilicon layer 352, between the first polysilicon layer 351 and the bottom surface of the trench structure, and on the sidewalls of the trench structure, and the potential difference between the first polysilicon layer 351 and the second polysilicon layer 352 is equal to the potential difference between the first polysilicon layer 351 and the bottom surface of the trench structure, both of which are 200V; a source metal layer 331, electrically connected to the second polysilicon layer 352. Figure 7 The device structure may further include: a top oxide layer 37 on the n-type drift region 32 on one side of the polysilicon layer, and the top oxide layer 37 is connected to the isolation oxide layer 36. Figure 7The device structure further includes a p-type body region 34 and an n-type source region 38, wherein the p-type body region 34 is located on the n-type drift region 32 on the side of the polysilicon layer away from the top oxide layer 37. The n-type source region 38 is located on the p-type body region 34 and away from the polysilicon layer. The source metal layer 331 sequentially covers the n-type source region 38, the p-type body region 34, the second polysilicon layer 352, and a portion of the top oxide layer 37 along a direction parallel to the semiconductor substrate 31. The material of the top oxide layer 37 is preferably silicon dioxide, but is not limited thereto. The thickness of the top oxide layer 37 can adopt the thickness of the top oxide layer of the power switching device structure in the prior art, which is not further described here.

[0108] Figure 7 In the preparation method of the device structure, in the step of forming the isolation oxide layer 36 in the trench structure, a top oxide layer 37 is also formed on the n-type drift region 32 on one side of the polysilicon layer, and the top oxide layer 37 is connected to the isolation oxide layer 36. After the step of forming the n-type drift region 32 on the semiconductor substrate 31, the preparation method may further include: injecting p-type dopant ions (such as boron) into the n-type drift region 32 on the side of the polysilicon layer away from the top oxide layer 37 to form a p-type body region 34; and injecting n-type dopant ions (such as phosphorus) into the p-type body region 34 to form an n-type source region 38 away from the polysilicon layer. Figure 6 Compared with the preparation method of the device structure in Figure 7 The device structure fabrication method in the embodiment additionally grows a top oxide layer 37 on the surface of the n-type drift region 32, and no gate electrode is required in the trench structure. Furthermore, the p-type body region 34 is not required on the right side of the trench structure (i.e., where the top oxide layer is provided), and the source metal layer 331 is extended to cover a portion of the top oxide layer 37 on the right side of the trench to improve electric field shielding, thereby further preventing a reduction in the breakdown voltage at the surface.

[0109] Existing techniques for increasing the blocking voltage through two-dimensional field generation in vertical MOSFETs with trench electrodes cannot be applied to high blocking voltages due to excessive stress between the isolation oxide layer and the first-conductivity-type drift region, which increases specific on-resistance. However, providing at least two polysilicon layers on the bottom surface of the trench structure enables a reduction in the thickness of the isolation oxide layer on the sidewalls and bottom surface of the trench structure, while achieving the same effect as the prior art in generating a two-dimensional field in the first-conductivity-type drift region to increase the blocking voltage.

[0110] The fabrication method of the power switching device structure of the present invention enables applications with varying high blocking voltages by arranging multiple polysilicon layers with fewer manufacturing processes. The vertical segmentation, combined with the vertical current flow from the source metal layer to the drain metal layer, achieves optimal current density and improved on-resistance. Similarly, the edge termination structure of the present invention also provides optimal breakdown voltage with greater compactness and fewer process steps.

[0111] In addition, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

[0112] It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which may vary. It should also be understood that the terminology described herein is used only to describe specific embodiments and is not intended to limit the scope of the present invention. It should be noted that the singular forms "a," "an," and "the" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in their broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or," not a logical "exclusive or," unless the context clearly indicates otherwise. Structures described herein are to be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximating should be so interpreted unless the context clearly indicates otherwise.

Claims

1. A power switching device structure, characterized in that: include: drain metal layer; a semiconductor substrate, located on the drain metal layer; A first conductive type drift region is located on the semiconductor substrate; a trench structure located in the first conductive type drift region; At least two polysilicon layers are spaced apart and arranged in the trench structure along a direction perpendicular to the semiconductor substrate; an isolation oxide layer, located between adjacent polysilicon layers, between the bottom polysilicon layer and the bottom surface of the trench structure, and on the sidewalls of the trench structure; The source metal layer is located on the polysilicon layer.

2. The power switch device structure according to claim 1, wherein: The blocking voltage of the power switch device structure is equal to the sum of the potential differences between all two adjacent polysilicon layers and the potential difference between the bottom polysilicon layer and the bottom surface of the trench structure.

3. The power switch device structure according to claim 2, wherein: The potential difference between the two adjacent polysilicon layers is obtained according to the thickness of the isolation oxide layer between the two adjacent polysilicon layers, and the potential difference between the bottom polysilicon layer and the bottom surface of the trench structure is obtained according to the thickness of the isolation oxide layer between the bottom polysilicon layer and the bottom surface of the trench structure, and when the thickness of the isolation oxide layer between the two adjacent polysilicon layers is equal to the thickness of the isolation oxide layer between the bottom polysilicon layer and the bottom surface of the trench structure, the corresponding potential differences are the same.

4. The power switch device structure according to claim 1, wherein: The power switch device structure further includes a Schottky contact structure or a second conductive type doped region located on the first conductive type drift region.

5. The power switch device structure according to claim 4, wherein: When the power switching device structure includes a second conductive type doped region, the power switching device structure also includes a first conductive type source region located on the second conductive type doped region and a gate oxide layer, a gate electrode and a dielectric layer located in sequence between the polysilicon layer at the top of the trench structure and the source metal layer.

6. The power switch device structure according to claim 4, wherein: The first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.

7. The power switch device structure according to claim 1, wherein: The power switch device structure further includes a top oxide layer located on the first conductive type drift region, the top oxide layer is connected to the isolation oxide layer, and the source metal layer extends onto a portion of the top oxide layer.

8. The power switch device structure according to claim 1, wherein: The smaller the thickness of the isolation oxide layer between the two adjacent polysilicon layers, the smaller the thickness of the polysilicon layer on the isolation oxide layer.

9. A method for preparing a power switching device structure, characterized in that: The following steps are involved: providing a semiconductor substrate; forming a first conductivity type drift region on the semiconductor substrate; A trench structure is formed in the first conductive type drift region. forming at least two polysilicon layers and an isolation oxide layer spaced apart in a direction perpendicular to the semiconductor substrate in the trench structure, wherein the isolation oxide layer is located between adjacent polysilicon layers, between the bottom polysilicon layer and the bottom surface of the trench structure, and on the sidewalls of the trench structure; A source metal layer is formed on the polysilicon layer, and a drain metal layer is formed on the lower surface of the semiconductor substrate.

10. The method for preparing a power switch device structure according to claim 9, wherein: The blocking voltage of the power switch device structure is equal to the sum of the potential differences between all two adjacent polysilicon layers and the potential difference between the bottom polysilicon layer and the bottom surface of the trench structure.

11. The method for preparing a power switch device structure according to claim 10, wherein: The potential difference between the two adjacent polysilicon layers is obtained according to the thickness of the isolation oxide layer between the two adjacent polysilicon layers, and the potential difference between the bottom polysilicon layer and the bottom surface of the trench structure is obtained according to the thickness of the isolation oxide layer between the bottom polysilicon layer and the bottom surface of the trench structure, and when the thickness of the isolation oxide layer between the two adjacent polysilicon layers is equal to the thickness of the isolation oxide layer between the bottom polysilicon layer and the bottom surface of the trench structure, the corresponding potential differences are the same.

12. The method for preparing a power switch device structure according to claim 9, wherein: In the step of forming at least two polysilicon layers and an isolation oxide layer spaced apart in a direction perpendicular to the semiconductor substrate in the trench structure, a top oxide layer is further formed on the first conductive type drift region, the top oxide layer being connected to the isolation oxide layer; In the step of forming a source metal layer on the polysilicon layer, the source metal layer extends onto a portion of the top oxide layer.

13. The method for preparing a power switch device structure according to claim 12, wherein: The trench structure is formed by adopting a reactive ion etching process; and the isolation oxide layer and the top oxide layer are formed by adopting a thermal oxidation process or a CVD process.

14. The method for preparing a power switch device structure according to claim 9, wherein: After the step of forming a trench structure in the first conductive type drift region, the preparation method further includes: forming a Schottky contact structure or a second conductive type doping region on the first conductive type drift region.

15. The method for preparing a power switch device structure according to claim 14, wherein: The first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.

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