Cell structure of semiconductor device, method of manufacturing, and semiconductor device

Abstract

The application provides a cell structure of a semiconductor device, a preparation method and the semiconductor device. The cell structure comprises: a substrate, a plurality of first implantation regions, which are spaced apart in the substrate below a first surface along a first direction and extend along a second direction, the first implantation regions having a second doping type; a plurality of second implantation regions, which are spaced apart in the substrate below the first surface along the second direction and extend along the first direction, at least two of the second implantation regions and part of the at least two first implantation regions having a first projection on a side surface of the substrate, the first projection being a closed pattern, the substrate surrounded by the implantation regions corresponding to the first projection being defined as a first region, the implantation regions corresponding to the first projection and the first region constituting an ohmic unit, the second implantation regions having the second doping type; and an ohmic contact metal layer, which is located on the substrate and in contact with the ohmic unit. The problem that a semiconductor device cannot simultaneously have a low forward conduction voltage drop and a high surge resistance is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a cellular structure, fabrication method, and semiconductor device. Background Technology

[0002] In existing semiconductor devices, such as MPS devices, to improve surge capability within the same chip area, the proportion of the P+ region is typically increased to generate more conductance modulation under forward bias. However, this leads to an increase in the forward voltage drop Vf, as a larger P+ region implies a larger series resistance. Conversely, if a lower forward voltage drop Vf is desired, the proportion of the P+ region needs to be reduced, but this sacrifices the device's conductance modulation capability, thus affecting its surge current withstand capability and high-voltage reliability. Therefore, it is difficult to simultaneously achieve a low forward voltage drop Vf while pursuing high surge capability or high-voltage withstand capability in semiconductor devices.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a cellular structure, fabrication method, and semiconductor device to solve the problem that existing semiconductor devices cannot simultaneously achieve both low forward voltage drop and high surge protection.

[0005] To achieve the above objectives, according to one aspect of this application, a cellular structure for a semiconductor device is provided, comprising: a substrate having a first doping type, the substrate having a first surface along the thickness direction of the device; a plurality of first implantation regions spaced apart along a first direction perpendicular to the thickness direction of the device in the substrate below the first surface and extending along a second direction, the first implantation regions being regions formed by ion implantation of a portion of one side surface of the substrate, the first direction and the second direction forming an angle, the first implantation regions having a second doping type; a plurality of second implantation regions spaced apart along the second direction in the substrate below the first surface and extending along the first direction, the second implantation regions being regions formed by ion implantation of any adjacent first implantation regions in the substrate, at least two second implantation regions and portions of at least two first implantation regions having a first projection on one side surface of the substrate, the first projection being a closed pattern, the substrate surrounded by the implantation regions corresponding to the first projection being defined as a first region, the implantation regions corresponding to the first projection and the first region constituting an ohmic cell, the second implantation regions having the second doping type; and an ohmic contact metal layer located on the substrate and in contact with the ohmic cell.

[0006] Optionally, the ohmic unit has a first thickness in the thickness direction of the device, and at least the first injection region where the ohmic unit is located has a second thickness in the thickness direction of the device, wherein the first thickness is greater than the second thickness.

[0007] Optionally, the first injection region has a second surface, the second injection region has a third surface, and both the second surface and the third surface are located within the first surface.

[0008] Optionally, the projection of the ohmic contact metal layer on the first surface is located inside the projection of the ohmic unit on the first surface.

[0009] Optionally, the width of the first region in the first direction is smaller than the width between adjacent first injection regions.

[0010] Optionally, the cell structure further includes a Schottky metal layer that covers the ohmic contact metal layer, the substrate, and the first implantation region, with adjacent portions of the Schottky metal layer located between adjacent ohmic cells.

[0011] Optionally, the shape of the first projection includes at least one of the following: a square shape, a sun shape, an eye shape, and a field shape.

[0012] According to another aspect of this application, a method for fabricating a cellular structure of a semiconductor device is provided. The method includes: providing a substrate having a first doping type and a first surface along the thickness direction of the device; performing ion implantation on one side surface of the substrate to form a plurality of first implantation regions, the plurality of first implantation regions being spaced apart along a first direction perpendicular to the thickness direction of the device in the substrate below the first surface and extending along a second direction, wherein each first implantation region is a region formed by ion implantation on a portion of one side surface of the substrate, the first direction and the second direction forming an angle, and the first implantation region having a second doping type. The substrate is subjected to ion implantation between any two adjacent first implantation regions to form a plurality of second implantation regions. The plurality of second implantation regions are spaced apart along the second direction in the substrate below the first surface and extend along the first direction. At least two second implantation regions and portions of at least two first implantation regions have a first projection on one side surface of the substrate. The first projection is a closed pattern. The substrate surrounded by the implantation regions corresponding to the first projection is defined as a first region. The implantation regions corresponding to the first projection and the first region constitute an ohmic cell. The second implantation regions have the second doping type. An ohmic contact metal layer is formed on the ohmic cell.

[0013] Optionally, the step of forming the ohmic contact metal layer includes: etching a portion of the first implantation region other than the ohmic cell and the substrate located between a plurality of first implantation regions, such that the thickness of the ohmic cell is greater than the thickness of the etched first implantation region, thereby forming the ohmic contact metal layer covering the ohmic cell; or, forming the ohmic contact metal layer covering the ohmic cell, wherein the projection of the ohmic contact metal layer on the surface of the substrate is located inside the projection of the ohmic cell on the surface of the substrate.

[0014] According to another aspect of this application, a semiconductor device is provided, which is obtained by combining the cellular structures of a plurality of said semiconductor devices.

[0015] Using the technical solution of this application, a semiconductor device includes a substrate, a first implantation region, a second implantation region, and an ohmic contact metal layer. Multiple first implantation regions and multiple second implantation regions, together with a first region of the substrate surrounded by them, form an ohmic cell. The ohmic contact metal layer is disposed on the ohmic cell, so that the ohmic contact metal layer simultaneously contacts the first region with a first doping type and the first and second implantation regions with second doping types. Since the first region does not contact the Schottky metal, no Schottky contact is generated, reducing the area of ​​Schottky contact at the device substrate, lowering the overall Schottky barrier of the device, and thus reducing the voltage drop of the device during forward conduction. The two types of implantation regions with second doping types (the first and second implantation regions) can form a PN junction with the substrate. The implantation of minority carriers into the substrate by the implantation regions generates a conductivity modulation effect, which can reduce resistance, improve the device's conduction capability under high current, and enhance the device's surge protection capability. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A top view schematic diagram of the cell structure of a first semiconductor device according to an embodiment of this application is shown;

[0018] Figure 2 A kind of Figure 1 A schematic diagram of the cross-sectional structure of the mesocellular structure along the A-A' direction;

[0019] Figure 3 Another one is shown Figure 1 A schematic diagram of the cross-sectional structure of the mesocellular structure along the A''-A''' direction;

[0020] Figure 4 The diagram shows a top view and a cross-sectional view of the cell structure of a second semiconductor device according to an embodiment of this application.

[0021] Figure 5 The diagram shows a top view and a cross-sectional view of the cell structure of a third semiconductor device according to an embodiment of this application.

[0022] Figure 6 A top view schematic diagram of the cell structure of a fourth semiconductor device according to an embodiment of this application is shown;

[0023] Figure 7 A schematic flowchart of a method for fabricating a cellular structure of a semiconductor device according to an embodiment of this application is shown;

[0024] Figure 8 This diagram illustrates a cross-sectional structure of the substrate after the formation of the first pre-implantation region in a method for fabricating the cellular structure of a semiconductor device.

[0025] Figure 9 It shows the Figure 8 The first pre-implantation region in the middle is etched to form the front and back ohmic contact metal layers and the Schottky metal layer. This is a schematic diagram of the cross-sectional structure of the substrate.

[0026] Figure 10 This diagram illustrates a cross-sectional structure of the substrate after the formation of the first implantation region in a method for fabricating the cellular structure of a semiconductor device.

[0027] Figure 11 It shows in Figure 10 A schematic diagram of the cross-sectional structure of the substrate after the formation of the ohmic contact metal layer and the Schottky metal layer on the front and back sides in the structure;

[0028] Figure 12 A cross-sectional structural schematic diagram of a semiconductor device according to an embodiment of this application is shown.

[0029] The above figures include the following reference numerals:

[0030] 1. Cell structure; 10. Substrate; 11. First region; 12. Substrate; 13. Epitaxial layer; 20. First implantation region; 21. First pre-implantation region; 30. Second implantation region; 40. Ohmic cell; 50. Ohmic contact metal layer; 60. Schottky metal layer; 70. Backside ohmic contact metal layer. Detailed Implementation

[0031] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0032] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0035] As described in the background section, in the prior art, semiconductor devices, while pursuing high surge capability or high voltage withstand, are difficult to simultaneously achieve a low forward conduction voltage drop Vf. To solve the problem that semiconductor devices cannot simultaneously achieve a low forward conduction voltage drop and a high surge resistance, embodiments of this application provide a cellular structure of a semiconductor device, a fabrication method, and a semiconductor device.

[0036] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0037] According to one embodiment of this application, a cellular structure for a semiconductor device is provided, such as... Figures 1 to 3As shown, the device includes: a substrate 10 having a first doping type, the substrate 10 having a first surface along the device thickness direction; a plurality of first implantation regions 20, spaced apart along a first direction X perpendicular to the device thickness direction, located below the first surface in the substrate 10, and extending along a second direction Y, the first implantation regions 20 being regions formed by ion implantation of a portion of one side surface of the substrate 10, the first direction X and the second direction Y forming an angle, the first implantation regions 20 having a second doping type; and a plurality of second implantation regions 30, spaced apart along the second direction Y, located below the first surface in the substrate 10, and extending along the first direction X. The second implantation region 30 is a region formed by ion implantation between any two adjacent first implantation regions 20 in the substrate 10. At least two second implantation regions 30 and portions of at least two first implantation regions 20 have a first projection on one side surface of the substrate 10. The first projection is a closed pattern. The substrate 10 surrounded by the implantation region corresponding to the first projection is defined as the first region 11. The implantation region corresponding to the first projection and the first region 11 constitute an ohmic unit 40. The second implantation region 30 has a second doping type. The ohmic contact metal layer 50 is located on the substrate 10 and is in contact with the ohmic unit 40.

[0038] The semiconductor device proposed in this application includes a substrate, a first implantation region, a second implantation region, and an ohmic contact metal layer. Multiple first implantation regions and multiple second implantation regions, together with a first region of the substrate surrounded by them, form an ohmic cell. The ohmic contact metal layer is disposed on the ohmic cell, simultaneously contacting the first region with a first doping type and the first and second implantation regions with second doping types. Since the first region does not contact the Schottky metal, no Schottky contact is generated, reducing the area of ​​Schottky contact at the device substrate, lowering the overall Schottky barrier of the device, and thus reducing the voltage drop during forward conduction. Furthermore, when the device is turned on, a depletion layer is generated at the PN junction formed by the first implantation region and the substrate. The depletion layer generated by adjacent first implantation regions can reduce leakage current and ensure the device's withstand voltage. The two types of implantation regions (first and second implantation regions) with second doping types can form a PN junction with the substrate. The implantation of minority carriers into the substrate by the implantation regions generates a conductivity modulation effect, which can reduce resistance, improve the device's conduction capability under high current, and enhance the device's surge protection capability.

[0039] In the above embodiments, the substrate material can be silicon carbide, which allows the device to have high thermal conductivity and high breakdown field strength, making it suitable for manufacturing high-performance devices that can operate under high temperature and high pressure environments. Figure 2 and Figure 3As shown, the substrate 10 includes a substrate 12 and an epitaxial layer 13. The doping concentration of the substrate 12 is higher than that of the epitaxial layer 13. The higher doping concentration of the substrate 12 can increase the depth of the depletion layer, thereby increasing the reverse breakdown voltage and reducing the risk of device breakdown. Furthermore, the substrate 12 can absorb carriers from the epitaxial layer 13, further reducing the on-resistance. The lower doping concentration of the epitaxial layer 13 can provide greater carrier mobility when the device is turned on, thereby reducing the on-resistance.

[0040] In the above embodiments, the first doping type can be N-type doping or P-type doping, and the second doping type can be P-type doping or N-type doping. For example, the first doping type is N-type doping and the second doping type is P-type doping, or the first doping type is P-type doping and the second doping type is N-type doping. The N-type doping element can be any one of pentavalent elements, including phosphorus (P), arsenic (As), and antimony (Sb), and the P-type doping element can be any one of trivalent elements, including boron (B), aluminum (Al), and gallium (Ga). This application does not impose specific limitations.

[0041] In the above embodiments, the material of the ohmic contact metal layer can be any one or more of Ni, Cu, Ag, Mo, Ta, and Au, and this application does not specifically limit it. The ohmic contact metal layer, through its contact with the first injection region, the second injection region, and the substrate, provides a low-impedance current path, promoting current transport in the device and reducing on-resistance. In this embodiment, the direct contact between the ohmic contact metal layer and the N-type substrate eliminates the Schottky barrier at the substrate, thereby improving current transport efficiency. This allows the semiconductor device to conduct more effectively under high current conditions, enhancing current injection efficiency and significantly improving the device's surge capability.

[0042] To further reduce leakage current in the device, in some alternative implementations, such as Figure 2 As shown, the ohmic cell 40 has a first thickness h1 in the device thickness direction, and at least the first injection region 20 where the ohmic cell 40 is located has a second thickness h2 in the device thickness direction, with the first thickness h1 being greater than the second thickness h2. The ohmic cell 40 is designed as a fin-like structure as shown in the figure. The first region is a JFET region, and adjacent first injection regions and JFET regions form a PN junction, generating a depletion effect, reducing the carrier concentration, thereby reducing the leakage risk and improving the device's withstand voltage. The difference between the first thickness h1 and the second thickness h2 can be reasonably set according to the surge performance and forward voltage drop required by the device. For example, if the device needs to have a higher surge resistance when it needs to operate again, the difference between the first thickness h1 and the second thickness h2 should be set smaller; if the device needs to have a lower forward voltage drop when it needs to operate again, the difference between the first thickness h1 and the second thickness h2 should be set larger. This application does not specifically limit the adjustment method.

[0043] Furthermore, by making the ohmic unit a fin structure, the contact surface between the first injection region and the substrate can be increased, thus increasing the contact area. Therefore, under high current conditions such as surge current, the PIN parasitic diode of the device conducts, resulting in stronger injection efficiency and stronger surge capability.

[0044] In some alternative implementations, such as Figure 3 As shown, the first implantation region 20 has a second surface, and the second implantation region 30 has a third surface, both of which are located within the first surface. This planar structure allows for shallow implantation depths in both the first and second implantation regions 20 and 30, eliminating the need for further etching. This simplifies the process, reduces the amount of material used for ion implantation, and saves costs. The planar ohmic cell 40 also features an ohmic contact metal layer 50 that simultaneously covers both the second-doped implantation region and the first-doped substrate, eliminating the Schottky barrier at the substrate and improving current transmission efficiency. This allows the semiconductor device to conduct more effectively under high current conditions, enhancing current injection efficiency and significantly improving the device's surge capability.

[0045] To further reduce leakage current in planar cellular structures, in some alternative implementations, such as Figure 3 As shown, the projection of the ohmic contact metal layer 50 on the first surface is located inside the projection of the ohmic cell 40 on the first surface. The size of the ohmic contact metal layer 50 is smaller than the size of the ohmic cell 40, which means that the closed injection region formed by the first injection region 20 and the second injection region 30 surrounds the ohmic contact metal layer 50. This prevents the ohmic contact metal layer 50 from directly contacting the substrate 10. This avoids the rapid increase in leakage current and rapid decrease in breakdown voltage caused by the low barrier (low contact resistance), effectively reducing leakage current. Furthermore, the ohmic contact metal layer 50 is surrounded by injection regions with the second doping type, which can also effectively control the current path, reduce leakage current caused by edge effects, and ensure the high breakdown voltage performance of the device.

[0046] In some alternative implementations, such as Figure 2 As shown, in the direction A-A', the width d1 of the first region 11 in the first direction X is smaller than the width d2 between adjacent first injection regions 20. Figure 3 As shown, in the direction A''-A''', the width d1 of the second injection region 30 is smaller than the width d2 between adjacent first injection regions 20. d1 can be much smaller than d2. By setting the width d1 of the first region 11 in the first direction X to be small, the width of the first region 11 can be basically the same as the width of the depletion layer generated by the adjacent second injection region, which can meet the requirements of device withstand voltage and leakage current.

[0047] In some alternative implementations, such as Figures 2 to 4 As shown, the cell structure also includes a Schottky metal layer 60, which covers the ohmic contact metal layer 50, the substrate 10, and the first implantation region 20, with a portion of the Schottky metal layer 60 located between adjacent ohmic cells 40. Figure 4 As shown, Figure 4 (a) contains two ohmic units 40. When the ohmic unit 40 has a fin-like structure, the cross-sectional view along the B-B' direction is as follows. Figure 4 As shown in (b). Figure 4 As shown in (b), when the ohmic unit 40 is a fin structure, the height of other regions besides the ohmic unit 40 is lower than the height of the ohmic unit 40. During the formation of the Schottky metal layer 60, part of the Schottky metal layer 60 fills the space between two ohmic units 40, forming a Schottky contact with the substrate 10 located between the two ohmic units 40. The Schottky metal layer 60 also forms a Schottky contact with the substrate 10 in the region where the ohmic unit 40 is not formed. This can create an effective barrier height when the device is reverse biased, reducing leakage current and increasing breakdown voltage. During forward conduction, the synergistic effect of the Schottky metal layer 60 and the ohmic contact metal layer 50 can reduce the forward conduction voltage drop and improve the device's conduction efficiency. This design balances the requirements of high withstand voltage and low forward conduction voltage drop, further optimizing the overall performance of the device. The ohmic unit 40 can also be planar, as shown in the cross-sectional view along the B-B' direction. Figure 4 As shown in (c).

[0048] In the above optional implementations, such as Figure 5 As shown, Figure 5 (a) contains two ohmic units 40, and the cross-sectional view along the B-B' direction is shown below. Figure 5 As shown in (b), when the ohmic element 40 is planar, the cross-sectional view along the A-A' direction is as follows. Figure 5 As shown in (c). When the ohmic unit 40 is a fin structure, the height of the first injection region 20 with the ohmic unit 40 can also be the same ( Figure 5 (b) The height of the first injection zone is the same. Figure 4 (b) different), so that the Schottky metal layer 60 will be located between adjacent ohmic contact metal layers 50 and cover the ohmic contact metal layer 50 and the second injection region 30 and the substrate 10. Figure 5 Structural references not mentioned in the text Figures 1 to 4 The description in the text will not be repeated.

[0049] In the above embodiments, the Schottky metal material can be any one of Au, Ag, Al, and Mo.

[0050] In the above optional implementations, such as Figures 2 to 5As shown, the cell structure further includes a back ohmic contact metal layer 70, which can reduce the contact resistance on the back of the device and achieve stable current transmission. The material of the back ohmic contact metal layer can be any one or more of Ni, Cu, Ag, Mo, Ta, and Au, and the present application does not make specific limitations.

[0051] In some optional embodiments, the first projection shape includes at least one of the following: a square shape, a rectangle with a vertical bar in the middle, a rectangle with two vertical bars, and a square with a cross in the middle. As Figure 1 shown, the first projection shape is a square shape, as Figure 4 (a) and Figure 5 (a) shown, the first projection shape is a rectangle with two vertical bars, as Figure 6 (a) shown, the first projection shape is a rectangle with a vertical bar in the middle, and Figure 6 (b) shown, the first projection shape is a square with a cross in the middle. The designs of these different shapes can optimize the geometric layout of the first injection region 20 and the second injection region 30 that make up the ohmic unit 40, so as to improve the conductance modulation effect of the device, thereby reducing the forward conduction voltage drop, while ensuring the high breakdown voltage performance of the device. For example, the injection unit configuration of a rectangle with a vertical bar in the middle can provide good control of the current path and reduce the influence of edge effects; the configuration of a rectangle with two vertical bars is more suitable for increasing the effective working area of the Schottky junction and reducing the forward conduction voltage drop; the configuration of a square with a cross in the middle may provide more PIN structures while ensuring breakdown voltage, enhancing the conduction ability and surge ability of the device. Figure 6 Other structures involved in Figures 1 to 5 are the same as those introduced in

[0052] Figure 7 is a flowchart of a method for manufacturing a cell structure of a semiconductor device according to an embodiment of the present application. As Figure 7 shown, the method includes the following steps:

[0053] Step S1, providing a substrate, the substrate having a first doping type, and the substrate having a first surface along the device thickness direction.

[0054] Specifically, the material of the substrate can be silicon carbide, which can endow the device with high thermal conductivity and high breakdown field strength. The substrate having a substrate and an epitaxial layer with different doping concentrations can increase the reverse breakdown voltage, reduce the risk of the device being broken down, and reduce the on-resistance.

[0055] Step S2: Ion implantation is performed on one side surface of the substrate to form multiple first implantation regions. The multiple first implantation regions are spaced apart in the substrate below the first surface along a first direction perpendicular to the thickness direction of the device, and extend along a second direction. The first implantation region is a region formed by ion implantation on a portion of one side surface of the substrate. The first direction and the second direction have an angle. The first implantation region has a second doping type.

[0056] Specifically, the first injection region can enhance the conductivity modulation effect of the device and reduce resistance, thereby improving the device's conduction capability under high current conditions. At the same time, through the specific arrangement of the first and second directions, the arrangement of the first injection region can optimize the electric field distribution of the device, reduce electric field hotspots, and further improve the device's surge capability and withstand voltage.

[0057] Step S3: Ion implantation is performed on the surface between any adjacent first implantation regions in the substrate to form a plurality of second implantation regions. The plurality of second implantation regions are spaced apart along a second direction in the substrate below the first surface and extend along a first direction. At least two second implantation regions and portions of at least two first implantation regions have a first projection on one side surface of the substrate. The first projection is a closed pattern. The substrate surrounded by the implantation region corresponding to the first projection is defined as a first region. The implantation region corresponding to the first projection and the first region constitute an ohmic unit. The second implantation regions have a second doping type.

[0058] Specifically, the implantation cells allow the subsequently formed ohmic contact metal layer to directly contact the N-type substrate, thereby reducing the additional voltage drop caused by the Schottky barrier when the device is forward-biased, while maintaining the device's breakdown voltage and reducing leakage current. By controlling the thickness of the second and first implantation regions to be the same, the electric field distribution can be further optimized, making the electric field distribution more uniform. This allows both the second and first implantation regions to effectively participate in conduction when the device is forward-biased, improving its bipolar conduction capability. At the same time, when reverse-biased, the first implantation region can shield the high electric field, reducing leakage current at the Schottky junction and ensuring the device's high breakdown voltage performance.

[0059] Step S4: Form an ohmic contact metal layer on the ohmic unit.

[0060] Specifically, the material of the ohmic contact metal layer can be any one or more of Ni, Cu, Ag, Mo, Ta, and Au. The direct contact between the ohmic contact metal layer and the N-type substrate eliminates the Schottky barrier at the substrate, thereby improving the current transmission efficiency. This allows the semiconductor device to conduct more effectively under high current conditions, enhancing the current injection efficiency and significantly improving the surge capability of the device.

[0061] The semiconductor device fabricated by the above method includes a substrate, a first implantation region, a second implantation region, and an ohmic contact metal layer. Multiple first implantation regions and multiple second implantation regions, together with a first region of the substrate surrounded by them, form an ohmic cell. The ohmic contact metal layer is disposed on the ohmic cell, simultaneously contacting the first region with a first doping type and the first and second implantation regions with second doping types. Since the first region does not contact the Schottky metal, no Schottky contact is generated, reducing the area of ​​Schottky contact at the device substrate, lowering the overall Schottky barrier of the device, and thus reducing the voltage drop during forward conduction. Furthermore, when the device is turned on, a depletion layer is generated at the PN junction formed by the first implantation region and the substrate. The depletion layer generated by adjacent first implantation regions can reduce leakage current and ensure the device's withstand voltage. The two types of implantation regions (first and second implantation regions) with second doping types can form a PN junction with the substrate. The injection of minority carriers into the substrate by the implantation regions generates a conductivity modulation effect, which can reduce resistance, improve the device's conduction capability under high current, and enhance the device's surge resistance.

[0062] In some alternative implementations, step S3, forming the ohmic contact metal layer, includes:

[0063] like Figures 8 to 11 As shown, Figures 8 to 11 The cross-sectional view along the A-A' direction shows that the portion of the first implantation region 20 excluding the ohmic cell 40 and the substrate 10 located between the plurality of first implantation regions 20 are etched to make the thickness of the ohmic cell 40 greater than the thickness of the etched first implantation region 20, forming an ohmic contact metal layer 50 covering the ohmic cell 40; or, forming an ohmic contact metal layer 50 covering the ohmic cell 40, wherein the projection of the ohmic contact metal layer 50 on the surface of the substrate 10 is located inside the projection of the ohmic cell 40 on the surface of the substrate 10. According to the above fabrication method, two cell structures can be fabricated, resulting in more diverse forms of the final semiconductor device and a wider range of applications.

[0064] Specifically, such as Figure 8 As shown, deep ion implantation is performed on the epitaxial layer 13 to form a first pre-implantation region 21. Additional control is applied to the spacing between adjacent first pre-implantation regions 21 where the ohmic unit 40 needs to be formed, so that this spacing matches the width of the depletion layer generated between the first pre-implantation region 21 and the epitaxial layer 13. For example... Figure 9As shown, the first pre-implantation region and epitaxial layer 13, where no ohmic cell 40 is formed, are etched to obtain the first implantation region 20. Then, an ohmic contact metal material is deposited on the ohmic cell 40 to form an ohmic contact metal layer 50. Next, a Schottky metal material is deposited to form a Schottky metal layer 60. Finally, an ohmic contact metal material is deposited on one side of the substrate 12 to form a back ohmic contact metal layer 70.

[0065] Specifically, such as Figure 10 As shown, shallow ion implantation is performed on the epitaxial layer 13 to form a first implantation region 20. Additional control is applied to the spacing between adjacent first implantation regions 20 where ohmic units 40 need to be formed, so that this spacing matches the width of the depletion layer generated between the first implantation region 20 and the epitaxial layer 13. For example... Figure 11 As shown, an ohmic contact metal layer 50 is formed by depositing an ohmic contact metal material on the ohmic unit 40, and then a Schottky metal material is deposited to form a Schottky metal layer 60. An ohmic contact metal material is deposited on one side of the substrate 12 to form a back ohmic contact metal layer 70. Figures 8 to 11 Structural references not mentioned in the text Figures 1 to 6 The description in the text will not be repeated.

[0066] According to another embodiment of this application, such as Figure 12 As shown, a semiconductor device is provided, which is obtained by combining multiple semiconductor device cell structures 1.

[0067] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0068] Based on the cellular structure, fabrication method, and semiconductor device proposed in the above embodiments of this application, the following technical effects can be achieved:

[0069] 1) The semiconductor device proposed in this application includes a substrate, a first implantation region, a second implantation region, and an ohmic contact metal layer. Multiple first implantation regions and multiple second implantation regions, together with a first region of the substrate surrounded by them, form an ohmic cell. The ohmic contact metal layer is disposed on the ohmic cell, so that the ohmic contact metal layer simultaneously contacts the first region with a first doping type and the first and second implantation regions with second doping types. Since the first region does not contact the Schottky metal, no Schottky contact is generated, reducing the area of ​​Schottky contact at the device substrate, lowering the overall Schottky barrier of the device, and thus reducing the voltage drop of the device during forward conduction. Furthermore, when the device is turned on, a depletion layer is generated at the PN junction formed by the first implantation region and the substrate. The depletion layer generated by adjacent first implantation regions can reduce the leakage current of the device and ensure the withstand voltage of the device. The two types of implantation regions (first and second implantation regions) with second doping types can form a PN junction with the substrate. The implantation regions inject minority carriers into the substrate, generating a conductivity modulation effect, which can reduce resistance, improve the device's conduction capability under high current, and enhance the device's surge protection capability.

[0070] 2) Setting the ohmic unit as a fin structure can increase the contact area between the first injection region and the substrate, thus increasing the contact area. Therefore, under high current conditions such as surge current, the PIN parasitic diode of the device will conduct, resulting in stronger injection efficiency and stronger surge capability.

[0071] 3) The size of the planar cellular ohmic contact metal layer is designed to be smaller than the size of the ohmic cell. This is equivalent to the closed injection region formed by the first and second injection regions surrounding the ohmic contact metal layer. This prevents the ohmic contact metal layer from directly contacting the substrate. This avoids the rapid increase in leakage current and rapid decrease in breakdown voltage caused by the low barrier (low contact resistance). It can effectively reduce leakage current. Furthermore, the ohmic contact metal layer is surrounded by injection regions with the second doping type, which can also effectively control the current path, reduce leakage current caused by edge effects, and ensure the high breakdown voltage performance of the device.

[0072] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A cellular structure for a semiconductor device, characterized in that, include: A substrate having a first doping type, the substrate having a first surface along the thickness direction of the device; Multiple first implantation regions are spaced apart in the substrate below the first surface along a first direction perpendicular to the thickness direction of the device, and extend along a second direction. Each first implantation region is a region formed by ion implantation on one side surface of a portion of the substrate. The first direction and the second direction form an angle. Each first implantation region has a second doping type. Multiple second implantation regions are spaced apart along the second direction in the substrate below the first surface and extend along the first direction. Each second implantation region is a region formed by ion implantation of any adjacent first implantation regions in the substrate. At least two second implantation regions and portions of at least two first implantation regions have a first projection on one side surface of the substrate. The first projection is a closed pattern. The substrate surrounded by the implantation region corresponding to the first projection is defined as a first region. The implantation region corresponding to the first projection and the first region constitute an ohmic cell. The second implantation region has a second doping type. The ohmic cell has a first thickness in the device thickness direction. At least the first implantation region where the ohmic cell is located has a second thickness in the device thickness direction. The first thickness is greater than the second thickness. An ohmic contact metal layer is located on the substrate and is in contact with the ohmic unit.

2. The cellular structure according to claim 1, characterized in that, The first injection region has a second surface, and the second injection region has a third surface, both of which are located within the first surface.

3. The cellular structure according to claim 1, characterized in that, The projection of the ohmic contact metal layer onto the first surface is located inside the projection of the ohmic unit onto the first surface.

4. The cellular structure according to claim 1, characterized in that, The width of the first region in the first direction is smaller than the width between adjacent first injection regions.

5. The cellular structure according to claim 1, characterized in that, The cell structure further includes a Schottky metal layer that covers the ohmic contact metal layer, the substrate, and the first implantation region, with adjacent portions of the Schottky metal layer located between adjacent ohmic cells.

6. The cellular structure according to claim 1, characterized in that, The shape of the first projection includes at least one of the following: a square shape, a sun shape, an eye shape, and a field shape.

7. A method for fabricating the cellular structure of a semiconductor device, characterized in that, The method for preparing the cell structure of the semiconductor device according to any one of claims 1 to 6 includes: A substrate is provided, the substrate having a first doping type, the substrate having a first surface along the thickness direction of the device; Ion implantation is performed on one side surface of the substrate to form a plurality of first implantation regions. The plurality of first implantation regions are spaced apart in the substrate below the first surface along a first direction perpendicular to the thickness direction of the device and extend along a second direction. The first implantation region is a region formed by ion implantation on a portion of one side surface of the substrate. The first direction and the second direction have an angle. The first implantation region has a second doping type. Ion implantation is performed on the surface between any adjacent first implantation regions in the substrate to form a plurality of second implantation regions. The plurality of second implantation regions are spaced apart along a second direction in the substrate below the first surface and extend along the first direction. At least two second implantation regions and portions of at least two first implantation regions have a first projection on one side surface of the substrate. The first projection is a closed shape. The substrate surrounded by the implantation region corresponding to the first projection is defined as a first region. The implantation region corresponding to the first projection and the first region constitute an ohmic cell. The second implantation region has a second doping type. The ohmic cell has a first thickness in the device thickness direction. At least the first implantation region where the ohmic cell is located has a second thickness in the device thickness direction. The first thickness is greater than the second thickness. An ohmic contact metal layer is formed on the ohmic unit.

8. The method for preparing the cellular structure according to claim 7, characterized in that, The steps for forming the ohmic contact metal layer include: The portion of the first implantation region excluding the ohmic cell and the substrate located between the plurality of first implantation regions are etched to make the thickness of the ohmic cell greater than the thickness of the etched first implantation region, forming the ohmic contact metal layer covering the ohmic cell; or, An ohmic contact metal layer is formed covering the ohmic unit, wherein the projection of the ohmic contact metal layer on the surface of the substrate is located inside the projection of the ohmic unit on the surface of the substrate.

9. A semiconductor device, characterized in that, It is obtained by combining the cell structures of the semiconductor devices according to any one of claims 1 to 6.

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