A method for manufacturing a semiconductor device

Abstract

The application discloses a semiconductor device manufacturing method and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming a side wall structure on both sides of the dummy gate; forming a contact hole etching stop layer on the substrate, the side wall structure and the dummy gate, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to a preset thickness of the hard mask layer; oxidizing the hard mask layer, part of the contact hole etching stop layer and part of the side wall structure to form a surface oxide layer; synchronously removing the surface oxide layer and part of the interlayer dielectric layer, so that the surface of the dummy gate and the surface of the interlayer dielectric layer on both sides of the dummy gate are flush; and removing the dummy gate to form a metal gate. The semiconductor device manufacturing method provided by the application can ensure the height of the formed metal gate, and the manufacturing process is simple and controllable.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a method for manufacturing a semiconductor device. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, in order to achieve faster computing speeds, larger data storage capacity, and more functions, integrated circuit chips are developing towards higher semiconductor device density and higher integration. As the feature size of semiconductor devices continues to shrink, polysilicon gate technology can no longer meet the requirements of semiconductor devices. Metal gates are used to replace polysilicon gates to solve problems such as threshold voltage drift, polysilicon gate depletion effect, excessively high gate resistance, and Fermi level pinning.

[0003] In the fabrication of metal gates, a post-gate process is used. During the removal of the polysilicon dummy gate, the polysilicon dummy gate is typically chemically and mechanically polished to remove the hard mask layer that stops on it. Then, a dry / wet etching process is used to remove the hard mask layer and the polysilicon dummy gate. However, during the etching process to remove the hard mask, defects such as contact hole etching stop layers or sidewall structures being etched can occur, creating depressions. In subsequent processes, these depressions will be filled with work function metal, requiring increased polishing of the metal gate to remove the metal within the depressions. This can lead to insufficient metal gate height or insufficient polishing, resulting in metal residue. Excessive depressions can even cause gate leakage. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device provided by this invention can ensure the height of the formed metal gate, avoid problems such as gate leakage current, and the manufacturing process is simple and highly controllable.

[0005] To address the aforementioned technical problems, this invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0006] A substrate is provided, on which a dummy gate is formed, and a hard mask layer is formed on the dummy gate;

[0007] Sidewall structures are formed on both sides of the dummy gate;

[0008] A contact hole etch stop layer is formed on the substrate, the sidewall structure, and the dummy gate, wherein the material of the contact hole etch stop layer is the same as the material of the hard mask layer;

[0009] An interlayer dielectric layer is formed on the contact hole etching stop layer.

[0010] Planarize the interlayer dielectric layer down to the remaining preset thickness of the hard mask layer;

[0011] Oxidize the hard mask layer, part of the contact hole etching stop layer, and part of the sidewall structure to form a surface oxide layer;

[0012] Simultaneously remove the surface oxide layer and part of the interlayer dielectric layer, making the surface of the dummy gate flush with the surfaces of the interlayer dielectric layers on both sides; and

[0013] Remove the dummy gate to form a metal gate.

[0014] In one embodiment of the present invention, the hard mask layer comprises silicon nitride, and the interlayer dielectric layer comprises silicon oxide.

[0015] In one embodiment of the present invention, the sidewall structure includes a first sublayer, a second sublayer, a third sublayer and a fourth sublayer stacked from the side closest to the dummy gate, wherein the first sublayer and the third sublayer are silicon nitride layers, and the second sublayer and the fourth sublayer are silicon oxide layers.

[0016] In one embodiment of the present invention, the fabrication step of making the surface of the dummy gate flush with the surfaces of the interlayer dielectric layers on both sides includes:

[0017] A first interlayer dielectric layer and a second interlayer dielectric layer are sequentially formed on the contact hole etching stop layer;

[0018] After planarizing the first interlayer dielectric layer, the second interlayer dielectric layer, the contact hole etching stop layer, and part of the hard mask layer, the hard mask layer and the first interlayer dielectric layer and the second interlayer dielectric layer on both sides are flush.

[0019] The hard mask layer, a portion of the contact hole etching stop layer, and a portion of the sidewall structure are oxidized to form a surface oxide layer, which protrudes from the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer.

[0020] A leveling layer is formed on the first interlayer dielectric layer, the second interlayer dielectric layer, and the surface oxide layer, wherein the leveling layer, the first interlayer dielectric layer, and the second interlayer dielectric layer are made of the same material; and

[0021] The leveling layer, the surface oxide layer, part of the first interlayer dielectric layer, and part of the second interlayer dielectric layer are removed simultaneously, and the surface of the dummy gate is flush with the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides.

[0022] In one embodiment of the present invention, the first interlayer dielectric layer and the second interlayer dielectric layer are silicon oxide. The first interlayer dielectric layer is obtained by high aspect ratio chemical vapor deposition, and the second interlayer dielectric layer is obtained by high density plasma chemical vapor deposition. The second interlayer dielectric layer has compressive stress.

[0023] In one embodiment of the present invention, the fabrication step of making the surface of the dummy gate flush with the surfaces of the interlayer dielectric layers on both sides includes:

[0024] A first interlayer dielectric layer and a second interlayer dielectric layer are sequentially formed on the contact hole etching stop layer;

[0025] The first interlayer dielectric layer, the second interlayer dielectric layer, the contact hole etch stop layer, and a portion of the hard mask layer are planarized, with the surfaces of the hard mask layer, a portion of the sidewall structure, and the contact hole etch stop layer being lower than the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides.

[0026] Oxidizing the hard mask layer, a portion of the contact hole etch stop layer, and a portion of the sidewall structure to form a surface oxide layer, the surface of which is flush with the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer; and

[0027] The surface oxide layer, part of the first interlayer dielectric layer, and part of the second interlayer dielectric layer are removed simultaneously, and the surface of the dummy gate is flush with the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides.

[0028] In one embodiment of the present invention, the method for fabricating the surface oxide layer includes:

[0029] The substrate, after planarizing the interlayer dielectric layer, is placed inside a plasma chamber; and

[0030] The chamber is controlled to be circulated with oxygen-containing gas and auxiliary gas for oxidation at a preset temperature and preset power.

[0031] In one embodiment of the present invention, the preset temperature is 350℃~550℃ and the preset power is 3000W~14000W.

[0032] In one embodiment of the present invention, the total flow rate of the oxygen-containing gas and the auxiliary gas is 300 sccm to 900 sccm, and the flow rate ratio of the oxygen-containing gas and the auxiliary gas is 1:1 to 2:1.

[0033] In one embodiment of the present invention, the remaining preset thickness of the hard mask layer is 3nm~5nm.

[0034] In summary, this invention provides a method for fabricating a semiconductor device. The unexpected technical advantages of this application are: it ensures that after removing the hard mask layer, the interlayer dielectric layer, sidewall structure, and contact hole etch stop layer do not experience depressions, thereby ensuring the height of the formed metal gate and avoiding problems such as gate leakage current; it can control the thickness of the surface oxide layer to obtain surface oxide layers of different depths, and the oxidation rate decreases significantly after the surface oxide layer reaches a certain thickness, without affecting the underlying sidewall structure and contact hole etch stop layer; it can ensure the height of the final formed metal gate and improve the height consistency of subsequent metal gates; it can neutralize the lateral stress generated during the formation of the surface oxide layer, reducing the impact of the lateral stress generated by the surface oxide layer on device performance; the fabrication process has high controllability and is simple, thus easily controlling the height of the metal gate and improving the electrical performance of the semiconductor device.

[0035] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of a pad oxide layer and a pad nitride layer formed on a substrate in one embodiment of the present invention.

[0038] Figure 2 This is a schematic diagram of the formation of a first photoresist layer in one embodiment of the present invention.

[0039] Figure 3 This is a schematic diagram of a shallow trench isolation structure formed in one embodiment of the present invention.

[0040] Figure 4 This is a schematic diagram of the formation of a trap region in one embodiment of the present invention.

[0041] Figure 5 This is a schematic diagram of the formation of a gate material layer and a hard mask layer in one embodiment of the present invention.

[0042] Figure 6 This is a schematic diagram of forming a dummy gate in one embodiment of the present invention.

[0043] Figure 7 This is a schematic diagram of the formation of a lightly doped region in one embodiment of the present invention.

[0044] Figure 8 This is a schematic diagram of the formation of the sidewall structure and the heavily doped region in one embodiment of the present invention.

[0045] Figure 9 This is a schematic diagram of the formation of a metal silicide layer, a contact hole etching stop layer, and an interlayer dielectric layer in one embodiment of the present invention.

[0046] Figure 10 This is a schematic diagram of the planarized interlayer dielectric layer and part of the hard mask layer in one embodiment of the present invention.

[0047] Figure 11 This is a schematic diagram of the surface oxide layer after its formation in one embodiment of the present invention.

[0048] Figure 12 This is a schematic diagram illustrating the effect of oxidation time on the thickness of the surface oxide layer in one embodiment of the present invention.

[0049] Figure 13 This is a schematic diagram of a leveling layer formed on the surface oxide layer and the interlayer dielectric layer in one embodiment of the present invention.

[0050] Figure 14 This is a schematic diagram of a solution after removing the leveling layer, surface oxide layer, and part of the interlayer dielectric layer in one embodiment of the present invention.

[0051] Figure 15 This is a schematic diagram of removing the dummy gate in one embodiment of the present invention.

[0052] Figure 16 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0053] Figure 17 This is a schematic diagram of the planarized interlayer dielectric layer in another embodiment of the present invention.

[0054] Figure 18 This is a schematic diagram of the surface oxide layer after it has been formed in another embodiment of the present invention.

[0055] Figure 19 This is a schematic diagram of another embodiment of the present invention after removing the surface oxide layer and part of the interlayer dielectric layer.

[0056] Label Explanation:

[0057] 10. Substrate; 101. Well region; 11. Pad oxide layer; 12. Pad nitride layer; 13. First photoresist layer; 131. Opening; 14. Shallow trench isolation structure; 15. Gate oxide layer; 16. Gate dielectric layer; 17. Barrier layer; 18. Gate material layer; 181. Dummy gate; 182. Recess; 19. Hard mask layer; 20. Second photoresist layer; 21. Lightly doped region; 22. Sidewall structure; 221. First sublayer; 222. Second sublayer; 223. Third sublayer; 224. Fourth sublayer; 23. Heavily doped region; 24. Metal silicide layer; 25. Contact hole etch stop layer; 26. First interlayer dielectric layer; 27. Second interlayer dielectric layer; 28. Surface oxide layer; 29. ​​Leveling layer; 30. Metal gate. Detailed Implementation

[0058] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0060] In the description of this specification, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing this solution and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this solution. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0061] This invention provides a method for fabricating a semiconductor device that, during the formation of the metal gate, ensures that the interlayer dielectric layer, sidewall structure, and contact hole etch stop layer do not experience depressions. This ensures the height of the formed metal gate, avoids problems such as gate leakage current, guarantees the final height of the metal gate, improves the height consistency of subsequent metal gates, and enhances the electrical performance of the semiconductor device. Furthermore, the semiconductor device prepared by this invention can be widely used in various fields such as optical communication, digital display, image reception, optical integration, transportation, energy, medicine, home appliances, and aerospace.

[0062] Please see Figure 1 As shown, in one embodiment of the present invention, a substrate 10 is first provided. The substrate 10 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafers, or other III / V compound semiconductor materials. It also includes a stacked structure composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanide-on-insulator, and germanium-on-insulator. In this embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate, and the substrate 10 can be an N-type substrate or a P-type substrate. In other embodiments, the type of substrate 10 is selected according to the semiconductor device being fabricated. The present invention does not limit the type of semiconductor device; the semiconductor device may be, for example, a semiconductor device including a gate structure. In this embodiment, a MOS transistor is selected as an example to illustrate the fabrication method of the semiconductor device.

[0063] Please see Figure 1 As shown, in one embodiment of the present invention, a pad oxide layer 11 is formed on a substrate 10. The pad oxide layer 11 serves as a buffer layer to improve the stress between the substrate 10 and the subsequently formed pad nitride layer 12. The pad oxide layer 11 is, for example, a dense silicon oxide material, and can be formed by any one of the following methods: dry oxygen oxidation, wet oxygen oxidation, or in-situ steam generation (ISSG). In this embodiment, the pad oxide layer 11 is formed, for example, by dry oxygen oxidation. Specifically, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen is introduced. The surface of the substrate 10 reacts with the oxygen at a high temperature to generate a dense pad oxide layer 11, and the generated pad oxide layer 11 has good quality. The pad oxide layer 11 is, for example, silicon oxide, and the thickness of the pad oxide layer 11 is, for example, 10nm to 40nm, specifically, 10nm, 20nm, 30nm, or 40nm.

[0064] Please see Figures 1 to 3As shown, in one embodiment of the present invention, a pad nitride layer 12 is formed on the pad oxide layer 11. The pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. In this embodiment, the pad nitride layer 12 is, for example, silicon nitride, and can be formed, for example, by a method such as low-pressure chemical vapor deposition (LPCVD). Specifically, for example, a substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia, and reacted at a pressure of, for example, 2T to 10T and a temperature of, for example, 700°C to 900°C to deposit the pad nitride layer 12. The thickness of the pad nitride layer 12 can be adjusted by controlling the heating time. The thickness of the pad nitride layer 12 is, for example, 50 nm to 80 nm, specifically 50 nm, 60 nm, or 70 nm. By providing the pad nitride layer 12, the substrate 10 can be protected from the planarization processes such as chemical mechanical polishing (CMP) involved in the fabrication of the shallow trench isolation structure 14. Furthermore, the pad nitride layer 12 can act as a mask during the subsequent formation of the shallow trench isolation structure, protecting the substrate 10 outside the shallow trench isolation structure from damage during etching.

[0065] Please see Figures 1 to 3 As shown, in one embodiment of the present invention, after forming the pad nitride layer 12, a first photoresist layer 13 is formed on the pad nitride layer 12. Through exposure and development processes, a plurality of openings 131 are formed on the first photoresist layer 13, which define the positions of the shallow trench isolation structure 14. Using the first photoresist layer 13 as a mask, etching is performed to remove the pad nitride layer 12, the pad oxide layer 11, and a portion of the substrate 10 exposed by the openings 131, thereby forming a shallow trench. In this embodiment, for example, dry etching is used to form the shallow trench (not shown in the figure). After etching is completed, the first photoresist layer 13 is removed. After forming the shallow trench, an insulating medium is deposited in the shallow trench until the insulating medium in the shallow trench protrudes from the surface of the pad nitride layer 12. This invention does not limit the deposition method of the insulating medium. For example, high-density plasma chemical vapor deposition (HDP-CVD) or high aspect ratio process chemical vapor deposition (HARP-CVD) can be used to form a high-quality insulating medium. In this embodiment, the insulating medium is, for example, silicon oxide. In other embodiments, the insulating medium can also be other insulating materials suitable for insulation.

[0066] Please see Figures 1 to 3As shown, in one embodiment of the present invention, after preparing the insulating dielectric, the insulating dielectric is planarized, for example, using CMP to planarize the insulating dielectric. For example, grinding removes part of the insulating dielectric and part of the pad nitride layer 12, and then removing the pad nitride layer 12 to obtain a shallow trench isolation structure 14, wherein the shallow trench isolation structure 14 is, for example, higher than the pad oxide layers 11 on both sides. The present invention does not limit the method of removing the pad nitride layer 12, for example, dry etching, wet etching, or a combination of dry etching and wet etching can be used for removal. In this embodiment, for example, thermal phosphoric acid is used to remove the pad nitride layer 12 to form the shallow trench isolation structure 14 to isolate adjacent semiconductor devices.

[0067] Please see Figures 3 to 4 As shown, in one embodiment of the present invention, after the shallow trench isolation structure 14 is fabricated, the substrate 10 is ion implanted using the pad oxide layer 11 as an ion implantation buffer layer to form a well region 101. In one embodiment of the present invention, the semiconductor device is, for example, a PMOS transistor, and the dopant ions in the well region 101 are, for example, N-type dopant ions, or phosphorus (P) or arsenic (As). In another embodiment of the present invention, the semiconductor device is, for example, an NMOS transistor, and the dopant ions in the well region 101 are, for example, P-type dopant ions, or boron (B) or gallium (Ga). After ion implantation, the well region 101 is subjected to a rapid thermal annealing (RTA) process to allow the ion implantation to diffuse to a suitable depth, while improving the avalanche breakdown resistance of the semiconductor device. Alternatively, wet etching can be used to remove the pad oxide layer 11, and the etching solution used for wet etching can be, for example, hydrofluoric acid or buffered oxide etch (BOE).

[0068] Please see Figures 4 to 5As shown, in one embodiment of the present invention, after removing the pad oxide layer, a gate oxide layer 15 is formed on the substrate 10. The gate oxide layer 15 is, for example, a silicon oxide layer, and is formed, for example, by in-situ water vapor growth. The thickness of the gate oxide layer 15 is, for example, 8 Å to 15 Å. After forming the gate oxide layer 15, a gate dielectric layer 16 is deposited on the gate oxide layer 15 and the shallow trench isolation structure 14. The gate dielectric layer 16 is, for example, one or a mixture of several high dielectric constant media such as hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), zirconium oxynitride (ZrSiON), hafnium silicate (HfSiO), hafnium oxynitride (HfSiON), lanthanum hafnium oxynitride (HfLaON), or hafnium aluminum oxide (HfAlO). The thickness of the gate dielectric layer 16 is, for example, 12 Å to 20 Å. The gate dielectric layer 16 can be formed, for example, using atomic layer deposition (ALD). By forming the gate oxide layer 15, the poor interface quality between the gate dielectric layer 16 and the substrate 10 can be improved, thereby enhancing the performance of the semiconductor device.

[0069] Please see Figure 5 As shown, in one embodiment of the present invention, after forming the gate dielectric layer 16, a barrier layer 17 is formed on the gate dielectric layer 16. The barrier layer 17 is, for example, titanium nitride or titanium, and is prepared by, for example, DC magnetron sputtering or atomic layer deposition. The thickness of the barrier layer 17 is, for example, 15 Å to 25 Å. By setting the barrier layer 17, it can serve as a barrier layer for dummy gate etching and a work function layer for the metal gate in subsequent fabrication processes, preventing the gate dielectric layer 16 from being contaminated or damaged, and improving the performance of the subsequently fabricated metal gate. Then, a gate material layer 18 is formed on the barrier layer 17. The gate material layer 18 is, for example, polysilicon. In this embodiment, the gate material layer 18 is prepared by, for example, chemical vapor deposition, and the thickness of the gate material layer 18 is, for example, 50 nm to 200 nm, selected according to the final thickness of the metal gate.

[0070] Please see Figure 5 As shown, in one embodiment of the present invention, after forming the gate material layer 18, a hard mask layer 19 is formed on the gate material layer 18. The hard mask layer 19 is, for example, a silicon nitride layer, and its thickness is, for example, 15 nm to 30 nm. By setting the hard mask layer, it prevents premature etching of the dummy gate during subsequent formation of sidewall structures, heavily doped regions, or contact hole etching stop layers, which would lead to loss of dummy gate height and affect the final metal gate height. This ensures the height of the dummy gate, thereby ensuring the height of the final metal gate and improving the height consistency of subsequent metal gates.

[0071] Please see Figures 5 to 6As shown, in one embodiment of the present invention, after the hard mask layer 19 is formed, a second photoresist layer 20 is formed on the hard mask layer 19. Then, the second photoresist layer 20 is exposed and developed to remove the area of ​​the second photoresist layer 20 that needs to be formed except for the dummy gate. Then, using the second photoresist layer 20 as a mask and the gate oxide layer 15 as an etch stop layer, the hard mask layer 19, the gate material layer 18, the barrier layer 17, and the gate dielectric layer 16 are etched, for example, by a dry etching process, a wet etching process, or a combination of dry etching and wet etching processes. The remaining gate material layer 18 is defined as the dummy gate 181.

[0072] Please see Figures 6 to 7 As shown, in one embodiment of the present invention, after forming the dummy gate 181, a lightly doped region 21 is formed in the well region 101 on both sides of the dummy gate 181. The dopant ions in the lightly doped region 21 are formed, for example, by ion implantation, and the type of implanted ions is opposite to the type of ions in the well region 101. In this embodiment, when the semiconductor device is a PMOS transistor, the dopant ions in the lightly doped region 21 are, for example, P-type impurities such as boron or gallium; when the semiconductor device is an NMOS transistor, the dopant ions in the lightly doped region 21 are, for example, N-type impurities such as phosphorus or arsenic. During the dopant ion implantation process, the formed lightly doped region 21 overlaps with the dummy gate portion.

[0073] Please see Figures 7 to 8 As shown, in one embodiment of the present invention, after forming the lightly doped region 21, sidewall structures 22 are formed on both sides of the dummy gate, wherein the sidewall structure 22 is, for example, a stacked structure. In this embodiment, the sidewall structure 22, starting from the side closest to the dummy gate 181, includes, for example, a stacked first sublayer 221, a second sublayer 222, a third sublayer 223, and a fourth sublayer 224, wherein the first sublayer 221 and the third sublayer 223 are, for example, silicon nitride layers, and the second sublayer 222 and the fourth sublayer 224 are, for example, silicon oxide layers. By setting the first sublayer 221 as a silicon nitride layer, during the subsequent formation of the heavily doped region, the occurrence of gaps in the sidewall structure during patterning can be reduced, and the stability of the sidewall structure 22 after the dummy gate is removed can be improved. In other embodiments, the sidewall structure 22 is, for example, other stacked structures. By setting the sidewall structure 22 as a stacked structure, the uniformity of the dummy gate is improved, thereby improving the stability of the threshold voltage of the semiconductor device.

[0074] Please see Figure 8As shown, in one embodiment of the present invention, after forming the sidewall structure 22, a heavily doped region 23 is formed in the substrate 10 on the side of the sidewall structure 22 away from the dummy gate 181. The edge of the heavily doped region 23 is aligned with the side of the sidewall structure 22 away from the dummy gate 181. The region where the heavily doped region 23 needs to be formed is exposed by photoresist processing, for example, by ion implantation to form the heavily doped region 23. The type of implanted ions is opposite to that in the well region 101, i.e., the same as that in the lightly doped region 21. The doping concentration of the heavily doped region 23 is greater than that of the lightly doped region 21, and the doping depth of the heavily doped region 23 is greater than that of the lightly doped region 21. After forming the heavily doped region 23, the heavily doped region 23 and the lightly doped region 21 are activated, for example, by rapidly thermally annealing the substrate 10. Rapid thermal annealing can repair lattice defects generated during fabrication and activate dopants, thereby activating the heavily doped region 23 and the lightly doped region 21.

[0075] Please see Figures 8 to 9 As shown, in one embodiment of the present invention, after forming the heavily doped region 23, for example, the gate oxide layer 15 outside the dummy gate 181 and sidewall structure 22 is removed by etching, and a fully covered metal layer (not shown) is formed on the substrate 10. Through heat treatment, the metal reacts with the exposed substrate 10, forming a metal silicide layer 24 on the heavily doped region 23. The unreacted metal layer is then removed. The formed metal silicide layer 24 is used to improve the contact resistance of the conductive plugs subsequently formed on the source and drain. After forming the metal silicide layer 24, a contact etch stop layer (CESL) 25 is formed on the substrate 10. The contact etch stop layer 25 is made of the same material as the hard mask layer 19, such as silicon nitride. The contact etch stop layer 25 is formed, for example, by chemical vapor deposition, and its thickness is, for example, 5 nm to 25 nm. The contact hole etching stop layer 25 covers, for example, the sidewall structure 22, the dummy gate 181, the metal silicide layer 24, and the shallow trench isolation structure 14, to prevent damage to the substrate 10 during subsequent fabrication processes, thereby improving the performance of the semiconductor device. In this application, during the formation of the lightly doped region 21, the sidewall structure 22, the heavily doped region 23, and the metal silicide layer 24, the hard mask layer 19 is partially removed. In one specific embodiment, after the formation of the metal silicide layer 24, for example, one-third to two-thirds of the hard mask layer 19 is removed.

[0076] Please see Figures 9 to 10As shown, in one embodiment of the present invention, after forming the contact hole etch stop layer 25, an interlayer dielectric layer is formed on the contact hole etch stop layer 25. The interlayer dielectric layer includes a first interlayer dielectric layer 26 and a second interlayer dielectric layer 27. The first interlayer dielectric layer 26 covers, for example, the dummy gate 181, the sidewall structure 22, the shallow trench isolation structure 14, and the substrate 10. The second interlayer dielectric layer 27 is formed on the first interlayer dielectric layer 26. The first interlayer dielectric layer 26 and the second interlayer dielectric layer 27 are, for example, silicon oxide. The first interlayer dielectric layer 26 is obtained, for example, by HARP-CVD to improve deposition quality and filling performance, and to avoid voids in the interlayer dielectric layer. The second interlayer dielectric layer 27 is obtained, for example, by HDP-CVD to obtain an oxide layer with compressive stress. After forming the second interlayer dielectric layer 27, the second interlayer dielectric layer 27 and the first interlayer dielectric layer 26 are planarized, for example, by chemical mechanical polishing. During the polishing process, for example, non-selective polishing is used to control the polishing time and remove the second interlayer dielectric layer 27, the first interlayer dielectric layer 26, the contact hole etch stop layer 25, and part of the hard mask layer 19 on the dummy gate 181. Polishing is stopped when the hard mask layer 19 has a remaining preset thickness. After planarization, the surface of the hard mask layer 19 is flush with the surfaces of the second interlayer dielectric layer 27, the first interlayer dielectric layer 26, and the contact hole etch stop layer 25 on both sides. In this embodiment, after polishing, the remaining preset thickness of the hard mask layer 19 is, for example, 3nm to 5nm. By stopping the planarization process on the hard mask layer 19, it is possible to prevent the partial exposure of the dummy gate due to uneven polishing during the polishing process, while the partial exposure of the dummy gate further leads to incomplete removal of the dummy gate. It also avoids the problem of large depressions in the interlayer dielectric layer and prevents residual metal in the interlayer dielectric layer during subsequent processes.

[0077] Please see Figures 10 to 11As shown, in one embodiment of the present invention, after planarizing the interlayer dielectric layer, the hard mask layer 19, the contact hole etching stop layer 25, and part of the sidewall structure 22 are oxidized to obtain a surface oxide layer 28. In this embodiment, for example, a high-density plasma processing technology is used for oxidation, wherein the substrate after planarizing the interlayer dielectric layer is placed in a plasma chamber, and the chamber is controlled to be oxidized by introducing oxygen-containing gas and auxiliary gas at a preset temperature and preset power, and the oxidation time is, for example, 30s to 60s. In this embodiment, the preset temperature is, for example, 350℃ to 550℃, the preset power is, for example, 3000W to 14000W, the total flow rate of oxygen-containing gas and auxiliary gas is, for example, 300sccm to 900sccm, and the flow rate ratio of oxygen-containing gas and auxiliary gas is, for example, 1:1 to 2:1. The oxygen-containing gas includes, for example, oxygen or nitrous oxide, and the auxiliary gas includes, for example, an inert gas such as argon. The oxygen-containing gas and the auxiliary gas are plasma-ionized within the chamber. The auxiliary gas increases the excited plasma density, improving the processing effect. During the oxidation process, in the sidewall structure 22, the first sub-layer 221 and the third sub-layer 223 of the surface layer are oxidized from silicon nitride to silicon oxide. The contact hole etching stop layer 25 of the surface layer is oxidized to silicon oxide, and the hard mask layer 19 is oxidized to silicon oxide, thereby forming a surface oxide layer 28. During the oxidation process, when the silicon nitride layer is oxidized to form a silicon oxide layer, the surface oxide layer 28 protrudes from the surface of the first interlayer dielectric layer 26 and the second interlayer dielectric layer 27, and the thickness of the surface oxide layer 28 increases by 40% to 80% compared to the thickness of the hard mask layer 19 before oxidation. Furthermore, the expansion of the surface oxide layer 28 formed by oxidation generates lateral stress, and the stress generated by the second interlayer dielectric layer 27 can neutralize the lateral stress, reducing the impact of the lateral stress generated by the surface oxide layer 28 on the device performance.

[0078] Please see Figures 11 to 12 As shown, in one embodiment of the present invention, the temperature and power of the plasma chamber are fixed, and a fixed flow rate of oxygen-containing gas and auxiliary gas are introduced, which affects the oxidation depth. Figure 12 This indicates the effect of oxidation time on oxidation depth under conditions such as an O2 flow rate of, for example, 300 sccm, an argon flow rate of, for example, 250 sccm, and a chamber temperature of, for example, 400°C. From... Figure 12As can be seen, the thickness of the contact hole etch stop layer 25 tends to stabilize with increasing oxidation time, i.e., the oxidation depth tends to stabilize. Therefore, by controlling the remaining thickness of the hard mask layer 19 and controlling the oxidation conditions, it is possible to ensure that the hard mask layer 19 is completely oxidized, while the oxidation depth of the sidewall structure 22 and the contact hole etch stop layer 25 is consistent with the oxidation depth of the hard mask layer 19. On the one hand, this avoids incomplete oxidation of the hard mask layer 19 on the dummy gate, which would lead to incomplete removal. On the other hand, it allows control of the thickness of the surface oxide layer, obtaining surface oxide layers of different depths. Moreover, when the surface oxide layer reaches a certain thickness, the oxidation rate decreases significantly, preventing the oxidation depth of the sidewall structure 22 and the contact hole etch stop layer 25 from being too large, thus not affecting the underlying sidewall structure and the contact hole etch stop layer. This also avoids problems such as excessive removal of the sidewall structure and the contact hole etch stop layer in subsequent processes, which could lead to depressions. This ensures the height of the formed metal gate and avoids problems such as gate leakage current.

[0079] Please see Figure 11 and Figure 13 As shown, in one embodiment of the present invention, after forming the surface oxide layer 28, a leveling layer 29 is formed on the interlayer dielectric layer and the surface oxide layer 28. The leveling layer 29 is, for example, a silicon oxide layer, and is deposited, for example, by a method such as HARP-CVD. After deposition, planarization is performed by CMP to obtain a leveling layer 29 with a smooth surface, so as to avoid the situation where the height of the dummy gate 181 and the interlayer dielectric layer are inconsistent during subsequent etching.

[0080] Please see Figure 13 and Figure 14 As shown, in one embodiment of the present invention, after the leveling layer 29 is formed, the leveling layer 29, the surface oxide layer 28 and part of the interlayer dielectric layer are removed simultaneously. Since the leveling layer 29, the surface oxide layer 28 and the interlayer dielectric layer are made of the same material, there is no difference in etching rate caused by material difference. Therefore, after removal, the surface of the dummy gate 181 is flush with the surfaces of the sidewall structures 22 on both sides, the contact hole etching stop layer 25, the first interlayer dielectric layer 26 and the second interlayer dielectric layer 27. The leveling layer 29, surface oxide layer 28, and interlayer dielectric layer are removed using processes such as wet etching, dry etching, or a combination of both. In this embodiment, wet etching is used for removal, and the etching solution is, for example, dilute hydrofluoric acid or buffered oxide etching solution. The mass fraction of the dilute hydrofluoric acid is, for example, 5% to 15%. By controlling the etching time, the surface oxide layer 28 is ensured to be removed just in time, and the etching rate is controlled to prevent the interlayer dielectric layer from sinking due to excessive etching, thereby improving the performance of the semiconductor device. By first performing oxidation, the top layer material is standardized, simplifying the removal process. The fabrication process is highly controllable and simple, making it easy to control the height of the metal gate and improving the electrical performance of the semiconductor device.

[0081] Please see Figure 14 and Figure 15 As shown, in one embodiment of the present invention, after removing the surface oxide layer 28, the gate material layer of the dummy gate 181 is removed to form a recess 182 at the location of the dummy gate 181. When removing the dummy gate 181, dry etching, wet etching, or a combination of both can be used. When using dry etching, chlorine, bromine, helium, or hydrogen bromide, or a mixture of at least one of these gases and oxygen, can be selected. Dry etching exhibits good anisotropy, selectivity, and etching efficiency, ensuring that no dummy gate 181 remains. During the etching process, etching stops after exposing the barrier layer 17, and the sidewall structure 22 is retained as the sidewall structure for the metal gate to be fabricated later.

[0082] Please see Figure 15 and Figure 16 As shown, in one embodiment of the present invention, after forming the recess 182, multiple layers of metal work function layers and metal conductive layers (not shown in the figure) are deposited on the second interlayer dielectric layer 27, the first interlayer dielectric layer 26, and the bottom and sidewalls of the recess 182. The metal conductive layers are disposed on the multiple layers of metal work function layers until the recess 182 is completely filled. Then, the metal conductive layers and metal work function layers are planarized until they are flush with the surfaces of the first interlayer dielectric layer 26 and the second interlayer dielectric layer 27 to form a metal gate 30. The material of the metal work function layer is, for example, one or more stacks of tantalum nitride (TaN), titanium nitride, titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), or tungsten nitride (WN), and the metal work function layer is formed, for example, by plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition, or physical vapor deposition. The number of metal work function layers and the material are selected according to the type of semiconductor device to meet the threshold voltage requirements of different semiconductor devices. The conductive metal layer can be made of metals with good conductivity, such as aluminum, tungsten, copper, or silver, and can be a single-layer metal, a multi-layer metal, or a stack of metal compounds. After the metal gate 30 is formed, conductive plugs and metal wiring layers are fabricated, which will not be elaborated here. In this application, the metal gate formation process can be applied to the fabrication of any semiconductor device containing a metal gate to stabilize the height of the metal gate, prevent gate leakage current, and improve the performance of the semiconductor device.

[0083] Please participate Figure 9 and Figure 17In another embodiment of the present invention, after the second interlayer dielectric layer 27 is formed, the second interlayer dielectric layer 27 and the first interlayer dielectric layer 26 are planarized, for example, by chemical mechanical polishing. During the planarization process, the polishing process is controlled to increase the polishing speed of the silicon nitride layer. After polishing stops, the surfaces of the second interlayer dielectric layer 27 and the first interlayer dielectric layer 26 are flush, and the surfaces of the silicon nitride in the hard mask layer 19, the contact hole etch stop layer 25, and the sidewall structure 22 are lower than the surface of the interlayer dielectric layer. The height difference between silicon oxide and silicon nitride is controlled to be equal to the expansion height during the subsequent silicon nitride oxidation process. In this embodiment, after polishing, the remaining preset thickness of the hard mask layer 19 is, for example, 3 nm to 5 nm.

[0084] Please participate Figures 17 to 19 In another embodiment of the present invention, after planarization, the hard mask layer 19, the contact hole etching stop layer 25, and part of the sidewall structure 22 are oxidized to obtain a surface oxide layer 28. In this embodiment, the oxidation conditions are the same as in the previous embodiment, and will not be elaborated further. During planarization, since the surface of silicon nitride in the hard mask layer 19, the contact hole etching stop layer 25, and the sidewall structure 22 is lower than the surface of the interlayer dielectric layer, the volume expansion of silicon nitride during oxidation can compensate for the height difference, and the surface of the obtained surface oxide layer 28 is flush with the surface of the interlayer dielectric layer. After obtaining the surface oxide layer 28, the surface oxide layer 28 and part of the interlayer dielectric layer can be directly etched away, making the dummy gate 181 flush with the structures on both sides. The subsequent fabrication of the metal gate is the same as in the previous embodiment, and will not be elaborated further. In this embodiment, the fabrication of a leveling layer can be avoided, further simplifying the fabrication process and improving the process speed.

[0085] In summary, this invention provides a method for fabricating a semiconductor device. By improving this method, the unexpected technical effect is that it ensures no depressions occur in the interlayer dielectric layer, sidewall structure, and contact hole etch stop layer after removing the hard mask layer, thereby ensuring the height of the formed metal gate and avoiding problems such as gate leakage current. It can control the thickness of the surface oxide layer, obtaining surface oxide layers of different depths. Once the surface oxide layer reaches a certain thickness, the oxidation rate decreases significantly without affecting the underlying sidewall structure and contact hole etch stop layer. It can ensure the height of the final formed metal gate and improve the height consistency of subsequent metal gates. It can neutralize the lateral stress generated during the formation of the surface oxide layer, reducing the impact of this lateral stress on device performance. The fabrication process is highly controllable and simple, making it easy to control the height of the metal gate and improve the electrical performance of the semiconductor device.

[0086] The above description of the embodiments shown in this invention (including the content set forth in the abstract of the specification) is not intended to be an exhaustive enumeration or to limit the invention to the precise forms disclosed herein. Although specific embodiments and examples of the invention have been described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the invention, as will be recognized and understood by those skilled in the art. As indicated, these modifications can be made to the invention in accordance with the above description of the embodiments described herein, and such modifications will be within the spirit and scope of the invention.

[0087] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by specific combinations of the above-described technical features. It should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application. Except for the technical features described in the specification, the remaining technical features are known to those skilled in the art. To highlight the innovative features of this invention, the remaining technical features will not be described further here.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, on which a dummy gate is formed, and a hard mask layer is formed on the dummy gate; Sidewall structures are formed on both sides of the dummy gate; A contact hole etch stop layer is formed on the substrate, the sidewall structure, and the dummy gate, wherein the material of the contact hole etch stop layer is the same as the material of the hard mask layer; An interlayer dielectric layer is formed on the contact hole etching stop layer; The interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer formed sequentially on the contact hole etching stop layer; The first interlayer dielectric layer and the second interlayer dielectric layer are silicon oxide. The first interlayer dielectric layer is obtained by high aspect ratio chemical vapor deposition, and the second interlayer dielectric layer is obtained by high density plasma chemical vapor deposition. The second interlayer dielectric layer has compressive stress. Planarize the interlayer dielectric layer down to the remaining preset thickness of the hard mask layer, where the preset thickness is 3nm~5nm; The hard mask layer, a portion of the contact hole etching stop layer, and a portion of the sidewall structure are oxidized to obtain a surface oxide layer, the thickness of which is increased by 40% to 80% relative to the preset thickness; the second interlayer dielectric layer neutralizes the lateral stress generated by the expansion during the formation of the surface oxide layer; Simultaneously remove the surface oxide layer and part of the interlayer dielectric layer, making the surface of the dummy gate flush with the surfaces of the interlayer dielectric layers on both sides; and Remove the dummy gate to form a metal gate.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The hard mask layer comprises silicon nitride, and the interlayer dielectric layer comprises silicon oxide.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The sidewall structure, starting from the side closest to the dummy gate, includes a first sublayer, a second sublayer, a third sublayer, and a fourth sublayer stacked together, wherein the first sublayer and the third sublayer are silicon nitride layers, and the second sublayer and the fourth sublayer are silicon oxide layers.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The fabrication steps for making the surface of the dummy gate flush with the surfaces of the interlayer dielectric layers on both sides include: A first interlayer dielectric layer and a second interlayer dielectric layer are sequentially formed on the contact hole etching stop layer; After planarizing the first interlayer dielectric layer, the second interlayer dielectric layer, the contact hole etching stop layer, and part of the hard mask layer, the hard mask layer and the first interlayer dielectric layer and the second interlayer dielectric layer on both sides are flush. The hard mask layer, a portion of the contact hole etching stop layer, and a portion of the sidewall structure are oxidized to form a surface oxide layer, which protrudes from the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer. A leveling layer is formed on the first interlayer dielectric layer, the second interlayer dielectric layer, and the surface oxide layer, wherein the leveling layer, the first interlayer dielectric layer, and the second interlayer dielectric layer are made of the same material; and The leveling layer, the surface oxide layer, part of the first interlayer dielectric layer, and part of the second interlayer dielectric layer are removed simultaneously, and the surface of the dummy gate is flush with the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The fabrication steps for making the surface of the dummy gate flush with the surfaces of the interlayer dielectric layers on both sides include: A first interlayer dielectric layer and a second interlayer dielectric layer are sequentially formed on the contact hole etching stop layer; The first interlayer dielectric layer, the second interlayer dielectric layer, the contact hole etch stop layer, and a portion of the hard mask layer are planarized, with the surfaces of the hard mask layer, a portion of the sidewall structure, and the contact hole etch stop layer being lower than the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides. Oxidizing the hard mask layer, a portion of the contact hole etch stop layer, and a portion of the sidewall structure to form a surface oxide layer, the surface of which is flush with the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer; and The surface oxide layer, part of the first interlayer dielectric layer, and part of the second interlayer dielectric layer are removed simultaneously, and the surface of the dummy gate is flush with the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer on both sides.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method for fabricating the surface oxide layer includes: The substrate, after planarizing the interlayer dielectric layer, is placed inside a plasma chamber; and The chamber is controlled to be circulated with oxygen-containing gas and auxiliary gas for oxidation at a preset temperature and preset power.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The preset temperature is 350℃~550℃, and the preset power is 3000W~14000W.

8. The method for fabricating a semiconductor device according to claim 6, characterized in that, The total flow rate of the oxygen-containing gas and the auxiliary gas is 300 sccm to 900 sccm, and the flow rate ratio of the oxygen-containing gas and the auxiliary gas is 1:1 to 2:1.

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