A method for manufacturing a shielded gate trench power device

Abstract

The application discloses a preparation method of a shield gate trench power device, a semiconductor structure for the shield gate trench power device, and the shield gate trench power device. The method comprises the following steps: providing a semiconductor substrate, forming a trench in the semiconductor substrate, and forming a first oxide layer on the surface of the substrate and the sidewall of the trench; filling polycrystalline silicon in the trench, and the surface of the polycrystalline silicon is lower than the upper surface of the first oxide layer on the surface of the substrate; forming a sidewall on the sidewall of the trench above the polycrystalline silicon; taking the sidewall as a hard mask, etching the polycrystalline silicon in the trench to a first depth; etching the first oxide layer of the sidewall of the trench to a second depth, and the second depth is smaller than the first depth; removing the sidewall, and performing thermal oxidation to form an oxide layer on the exposed part in the trench; and filling polycrystalline silicon in the first depth part and the second depth part of the trench. The scheme provided by the application can reduce the gate-source capacitance, thereby improving the opening speed of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a preparation method of a shielded gate trench power device, a semiconductor structure for a shielded gate trench power device and a shielded gate trench power device. BACKGROUND

[0002] SGT MOSFET (Shielded Gate Trench Metal-Oxide-Semiconductor Field-Effect Transistor) is a high-performance power semiconductor device, aiming to provide lower on-resistance and smaller switching loss than traditional normal trench MOSFET. SGT MOSFET technology mainly relies on a thermal oxidation growth process to form an inter-gate dielectric layer, which can generate high-quality silicon dioxide (SiO2) on the silicon surface, used as a gate insulating layer. In addition, by introducing a shielded gate structure, SGT MOSFET can reduce on-resistance and switching loss, and improve the overall performance of the device.

[0003] However, SGT MOSFET devices have various parasitic capacitances between the source, drain and gate, which will affect the opening speed of the device, therefore, how to improve the opening speed of the device has become a technical problem to be solved. SUMMARY

[0004] The present application provides a preparation method of a shielded gate trench power device, a semiconductor structure for a shielded gate trench power device and a shielded gate trench power device, which can reduce the integrated capacitance between the gate and the source, thereby improving the opening speed of the device. The specific scheme is as follows:

[0005] In a first aspect, the present application provides a preparation method of a shielded gate trench power device, the method comprising: providing a semiconductor substrate, the semiconductor substrate being formed with a trench, and a first oxide layer being formed on the surface of the substrate and the sidewall of the trench; filling polycrystalline silicon in the trench, and the surface of the polycrystalline silicon being lower than the upper surface of the first oxide layer on the surface of the substrate; forming a side wall on the sidewall of the trench above the polycrystalline silicon; etching the polycrystalline silicon in the trench to a first depth with the side wall as a hard mask; etching the first oxide layer of the sidewall of the trench to a second depth, and the second depth being smaller than the first depth; removing the side wall and performing thermal oxidation to form an oxide layer on the exposed part in the trench; and filling polycrystalline silicon in the first depth part and the second depth part of the trench.

[0006] ​Optionally, the filling the trench with polysilicon and the polysilicon surface being lower than the upper surface of the first oxide layer on the substrate surface comprises: depositing polysilicon on the substrate surface and in the trench until the trench is completely filled with polysilicon; grinding the deposited polysilicon and the first oxide layer on the substrate surface until the thickness of the first oxide layer on the substrate surface is 1000A-2000A; etching the polysilicon in the trench so that the polysilicon surface is lower than the upper surface of the first oxide layer on the substrate surface.

[0007] Optionally, the forming a side wall on the trench sidewall above the polysilicon comprises: depositing a barrier layer on the first oxide layer on the substrate surface, the upper surface of the polysilicon, and the trench sidewall above the polysilicon; removing the barrier layer on the substrate surface and the barrier layer on the upper surface of the polysilicon, and retaining the barrier layer on the trench sidewall above the polysilicon to form a side wall on the trench sidewall above the polysilicon.

[0008] Optionally, the etching the polysilicon in the trench to a first depth comprises: using dry anisotropic etching to etch the polysilicon in the trench to the first depth to retain the polysilicon under the side wall.

[0009] Optionally, the method for manufacturing the shielded gate trench power device further comprises: during or after the process of using dry anisotropic etching to etch the polysilicon in the trench, using isotropic etching with a set ratio to remove part of the polysilicon under the side wall to form a horn-shaped opening between the polysilicon under the side wall.

[0010] Optionally, the etching the first oxide layer of the trench sidewall to a second depth comprises: covering the area not needed to be etched by a photoetching process; performing wet etching to remove the first oxide layer exposed on the surface of the semiconductor substrate and etch the first oxide layer of the trench sidewall so that the depth of the area between the trench sidewall and the polysilicon sidewall formed under the side wall is the second depth; and removing the photoresist in the photoetching process.

[0011] Optionally, the removing the side wall and performing thermal oxidation to form an oxide layer on the exposed portions in the trench comprises: removing the side wall by etching, performing thermal oxidation to form an oxide layer on the polysilicon sidewall formed below the side wall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface and the trench sidewall above the first oxide layer in the trench, and partially oxidizing the polysilicon sidewall formed below the side wall in the trench; removing the oxide layer of the trench sidewall above the first oxide layer in the trench and the oxide layer of the substrate surface; performing thermal oxidation to form an oxide layer on the polysilicon sidewall formed below the side wall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface and the trench sidewall above the first oxide layer in the trench, and fully oxidizing the polysilicon sidewall formed below the side wall in the trench.

[0012] Optionally, the removing the side wall and performing thermal oxidation to form an oxide layer on the exposed portions in the trench comprises: cleaning the trench sidewall above the first oxide layer in the trench and the substrate surface to remove impurities on the trench sidewall above the first oxide layer in the trench and impurities on the substrate surface; performing thermal oxidation to form an oxide layer on the polysilicon sidewall formed below the side wall in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface and the trench sidewall above the first oxide layer in the trench, and fully oxidizing the polysilicon sidewall formed below the side wall in the trench.

[0013] Optionally, the filling the first depth portion and the second depth portion of the trench with polysilicon comprises: depositing polysilicon on the first depth portion, the second depth portion of the trench and the oxide layer of the substrate surface; and grinding and / or etching the deposited polysilicon to form three mutually separated sub-gates.

[0014] Optionally, after forming the three mutually separated sub-gates, the method further comprises: performing source and body implantation on the semiconductor substrate, depositing an interlayer dielectric layer and etching a contact hole to form a source electrode, a gate electrode and a drain electrode.

[0015] Optionally, the first oxide layer formed on the substrate surface and the trench sidewall has a thickness of 1000A-20000A.

[0016] Optionally, the polysilicon surface is lower than the upper surface of the first oxide layer of the substrate surface, and the height difference between the polysilicon surface and the upper surface of the first oxide layer of the substrate surface is 1500A-2000A.

[0017] Optionally, the barrier layer is one of SIN, SION and SIHN.

[0018] In a second aspect, the embodiments of the present application provide a semiconductor structure for a shielded-gate trench power device, comprising: a semiconductor substrate, wherein a trench is formed in the semiconductor substrate, and a gate oxide layer is formed on a sidewall of the trench; a shielded gate arranged on the trench bottom region of the gate oxide layer; and mutually separated sub-gates arranged on an upper region of the trench and above the shielded gate, wherein the mutually separated sub-gates are separated by an oxide layer, and at least one of the sub-gates is staggered from the shielded gate by a certain distance in a direction perpendicular to the depth direction.

[0019] Optionally, the mutually separated sub-gates are three, and a middle sub-gate is opposite to the shielded gate, and the other two sub-gates are arranged on both sides of the middle sub-gate.

[0020] Optionally, the mutually separated sub-gates are two, and the two sub-gates are placed side by side.

[0021] In a third aspect, the present application also provides a shielded-gate trench power device prepared by the method of the first aspect.

[0022] Compared with the prior art, the present application has the following advantages:

[0023] It can be seen that the method for preparing a shielded-gate trench power device provided by the embodiments of the present application fills the source electrode polysilicon on the upper surface of the first oxide layer with a lower surface than the substrate surface in the trench, so that a groove with a polysilicon bottom and a first oxide layer sidewall can be formed in the trench. Then, a side wall is formed on the sidewall of the groove, and the side wall is used as a hard mask to etch the polysilicon in the trench to form a first depth portion in the trench while protecting the polysilicon below the side wall from being etched, so that a polysilicon sidewall can be formed below the side wall. Then, based on the side wall and the polysilicon sidewall below the side wall, the first oxide layer on the sidewall of the trench can be etched, and the second depth of the etched first oxide layer on the sidewall of the trench is smaller than the first depth of the etched polysilicon in the trench, so that a second depth portion can be formed on both sides of the first depth portion in the trench, and the depth of the first depth portion is greater than the depth of the second depth portion. Then, the side wall is removed, and thermal oxidation is performed to oxidize the polysilicon sidewall in the trench to form an oxide layer. Finally, the first depth portion and the second depth portion are filled with polysilicon, so as to form a floating polysilicon in the first depth portion and two sub-gates in the second depth portion, thereby forming a three-gate structure with two sub-gates on both sides and a floating polysilicon in the middle above the shielded gate in the upper region of the trench. It can be seen that the facing area between the two sub-gates and the shielded gate is reduced, which can effectively reduce the integrated capacitance between the gate and the source, thereby improving the opening speed of the device.

[0024] In addition, the preparation method of the shielded gate trench type power device provided by the embodiment of the present application has the advantages that, since the gate polysilicon (two sub-gates on the left and right) and the shielded gate are staggered, there is no gate-source-drain electric problem, and the gate-source-drain electric is no longer affected by the interlayer oxide layer between the shielded gate and the control gate. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a flow chart of the preparation method of the shielded gate trench type power device provided by the present application.

[0026] Figure 2 is a schematic diagram of an example of the semiconductor substrate provided in the preparation method of the shielded gate trench type power device provided by the embodiment of the present application.

[0027] Figure 3 is a schematic diagram of an example of the formation of the first oxide layer on the substrate surface and the trench sidewall in the preparation method of the shielded gate trench type power device provided by the present application.

[0028] Figure 4 is a schematic diagram of an example of the filling of the polysilicon in the trench in the preparation method of the shielded gate trench type power device provided by the embodiment of the present application.

[0029] Figure 5 is a schematic diagram of an example of the filling of the polysilicon in the trench in the preparation method of the shielded gate trench type power device provided by the embodiment of the present application.

[0030] Figure 6 is a schematic diagram of an example of the etching of the polysilicon filled in the trench in the preparation method of the shielded gate trench type power device provided by the embodiment of the present application.

[0031] Figure 7 is a schematic diagram of an example of the deposition of the barrier layer in the preparation method of the shielded gate trench type power device provided by the embodiment of the present application.

[0032] Figure 8 is a schematic diagram of an example of the removal of the barrier layer outside the trench in the preparation method of the shielded gate trench type power device provided by the embodiment of the present application.

[0033] Figure 9 is a schematic diagram of an example of the etching of the polysilicon with the sidewall as a hard mask in the preparation method of the shielded gate trench type power device provided by the embodiment of the present application.

[0034] Figure 10 is a schematic diagram of an example of the etching of the first oxide layer of the trench sidewall in the preparation method of the shielded gate trench type power device provided by the embodiment of the present application.

[0035] Figure 11Fig. 1 is a schematic diagram of a shielding gate trench power device provided by an embodiment of the present application.

[0036] Figure 12 Fig. 2 is a schematic diagram of a method for manufacturing a shielding gate trench power device provided by an embodiment of the present application.

[0037] Figure 13 Fig. 3 is a schematic diagram of a first heat oxidation step for exposed portions in the trench provided by a method for manufacturing a shielding gate trench power device provided by an embodiment of the present application.

[0038] Figure 14 Fig. 4 is a schematic diagram of a step of removing the oxide layer on the surface of the polysilicon in the trench and the oxide layer on the surface of the substrate provided by a method for manufacturing a shielding gate trench power device provided by an embodiment of the present application.

[0039] Figure 15 Fig. 5 is a schematic diagram of a second heat oxidation step for exposed portions in the trench provided by a method for manufacturing a shielding gate trench power device provided by an embodiment of the present application.

[0040] Figure 16 Fig. 6 is a schematic diagram of a step of filling the trench with polysilicon at a first depth and a second depth provided by a method for manufacturing a shielding gate trench power device provided by an embodiment of the present application.

[0041] Figure 17 Fig. 7 is a schematic diagram of a step of processing the gate polysilicon provided by a method for manufacturing a shielding gate trench power device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0042] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without the specific details set forth in this description. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure aspects of the present application.

[0043] It should be noted that the terms "first", "second", "third", etc. in the claims, specification and drawings of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. The data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include", "have" and their variants are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0044] It should be understood that in the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the front and rear associated objects have an "or" relationship. "Including A, B and / or C" means including any one or any two or three of A, B and C.

[0045] It should be understood that in the embodiments of the present application, "B corresponding to A", "B corresponding to A", "A corresponding to B" or "B corresponding to A" means that B is associated with A, and B can be determined according to A. Determining B according to A does not mean that B is determined only according to A, but also can be determined according to A and / or other information.

[0046] The existing SGT MOSFET technology mainly relies on thermal oxidation growth process to form the gate dielectric layer. This method can generate high-quality silicon dioxide (SiO2) on the surface of silicon, In addition, by introducing the shield gate structure, the SGT MOSFET effectively reduces the on-resistance and switching loss, and improves the overall performance of the device. However, on the one hand, there are various parasitic capacitances between the source, drain and gate, which will increase the input capacitance and reduce the opening speed of the device; on the other hand, due to the change of the morphology and thickness of the gate dielectric layer formed by thermal oxidation, a large gate-source-drain current will be generated, which reduces the reliability of the device and limits its performance in high-performance application scenarios. Therefore, it is urgent to find a way to reduce the gate-source capacitance while ensuring that the gate-source-drain current is no longer affected by the interlayer oxide layer between the shield gate and the control gate.

[0047] For the above reasons, the first embodiment of the present application provides a preparation method of a shielded gate trench power device, which can reduce the integrated capacitance between the gate and the source while ensuring that the gate-source-drain current is no longer affected by the interlayer oxide layer between the shielded gate and the control gate.

[0048] The technical solutions of the present application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments.

[0049] In the following, the shielded gate trench power device provided by the embodiments of the present application will be described in detail. Figures 1-17 The preparation method of the shielded gate trench power device provided by the embodiments of the present application is introduced.

[0050] As shown in Figure 1 , it is a flow chart of the preparation method of the shielded gate trench power device provided by the present application, which includes the following steps S101-S107.

[0051] Step S101: providing a semiconductor substrate, the semiconductor substrate is formed with a trench, and a first oxide layer is formed on the surface of the substrate and the sidewall of the trench.

[0052] In semiconductor manufacturing, a semiconductor substrate refers to the basic material used to build a semiconductor device. The semiconductor substrate can include but is not limited to pure single crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc. The material of the semiconductor substrate can be selected according to actual needs in the preparation process.

[0053] As shown in Figure 2 , it is a schematic diagram of an example of a semiconductor substrate provided in the preparation method of the shielded gate trench power device provided by the embodiments of the present application. The semiconductor substrate can include an epitaxial layer 02 and a substrate layer 01, wherein the trench 03 is formed in the epitaxial layer 02.

[0054] The epitaxial layer refers to a process called epitaxial growth (Epitaxy or simply Epi), which grows a new material layer with a specific doping concentration and crystal structure on the original semiconductor substrate. This process can control the composition, thickness, and doping type and concentration of the new layer to achieve specific electrical properties. The epitaxial layer can be perfectly matched with the substrate at the atomic level, forming a continuous crystal structure. The epitaxial layer can be the same material as the substrate (homoepitaxy), or a different material (heteroepitaxy). Specifically, the epitaxial layer can be silicon-based or silicon carbide.

[0055] It's important to note that the epitaxial layer, used to support current transport in devices, typically has higher purity and fewer defects than the original substrate. Through epitaxial growth, the type and concentration of dopants in the epitaxial layer can be precisely controlled, thereby customizing the desired electrical characteristics. For example, in power MOSFETs, the breakdown voltage and on-resistance can be optimized by adjusting the doping of the epitaxial layer. Furthermore, during the epitaxial process, materials with different doping concentrations or types can be grown layer by layer as needed to form complex multilayer structures. This capability is crucial for manufacturing high-performance integrated circuits (ICs) and power devices.

[0056] like Figure 3 The diagram shown is a schematic diagram of an example of the formation of a first oxide layer on the substrate surface and the trench sidewall in the fabrication method of the shielded gate trench power device provided in this application. A first oxide layer 04 is formed on the surface of the epitaxial layer 02 and the sidewall of the trench 03.

[0057] The oxide layer refers to the layer of insulating material (usually silicon dioxide) grown or deposited on the sidewalls of the trenches (i.e., the inner surface of the trenches) and the surface of the epitaxial layer after trenches have been etched into the semiconductor substrate. ).

[0058] It should be noted that the oxide layer, as a dielectric, provides necessary electrical isolation, preventing current from flowing directly from the gate to the source or drain. This helps control and manage the current flowing through the channel, ensuring that current only flows under appropriate voltage conditions. Furthermore, forming an oxide layer inside the trench helps optimize the electric field distribution in the channel region. Especially in high-voltage applications, good electric field management can improve breakdown voltage and enhance device reliability and performance.

[0059] In a specific implementation, trenches and a first oxide layer can be formed in the semiconductor substrate to be processed where no trenches and a first oxide layer have been formed, through the following steps:

[0060] The epitaxial layer 02 of the semiconductor substrate to be processed is etched to form trench 03;

[0061] A first oxide layer 04 is formed on the sidewall of trench 03 and the surface of epitaxial layer 02.

[0062] In this implementation, the thickness of the first oxide layer 04 is 1000 Å to 20000 Å. This thickness range covers the different requirements of field oxide layers for MOSFET devices from low voltage to medium and high voltage, and can adapt to applications of various voltage platforms. Specifically, oxide layers can be formed on the trench sidewalls and the upper surface of the epitaxial layer through methods such as thermal oxidation or chemical vapor deposition (CVD). Among them, thermal oxidation is a method of growing silicon dioxide by exposing the substrate to oxygen or water vapor in a high-temperature environment. The process of thermal oxidation includes dry oxidation and wet oxidation. Dry oxidation refers to the use of pure oxygen as an oxidant to generate a high-quality, dense oxide layer. Wet oxidation refers to the use of water vapor to react with silicon to generate an oxide layer. The growth rate of wet oxidation is faster than that of dry oxidation, but the oxide layer density is lower than that of dry oxidation. Chemical vapor deposition is a technique that uses chemical reactions to deposit thin films on the surface of a substrate.

[0063] Step S102: Fill the trench with polysilicon, and the surface of the polysilicon is lower than the upper surface of the first oxide layer on the substrate surface.

[0064] This step is used to fill the trench with source polysilicon, and the upper surface of the filled source polysilicon is lower than the upper surface of the first oxide layer on the substrate surface, thereby forming a groove in the trench with oxide layer on the sidewalls and polysilicon on the bottom.

[0065] In the manufacturing process, step S102 can be specifically achieved through the following steps S201, S202 and S203.

[0066] Step S201: Deposit polysilicon on the substrate surface and in the trench until the trench is completely filled with polysilicon.

[0067] like Figure 4 The diagram shown is a schematic representation of an example of filling polysilicon into the trench in the fabrication method of the shielded gate trench power device provided in this application. After forming a first oxide layer 04 on the sidewall of the trench 03 and the surface of the epitaxial layer 02, source polysilicon is deposited on the trench 03 and the surface of the epitaxial layer 02 to completely fill the trench 03 with source polysilicon 05.

[0068] Step S202: Polish the polysilicon and the first oxide layer deposited on the substrate surface until the thickness of the first oxide layer on the substrate surface is 1000A~2000A.

[0069] like Figure 5 The diagram shown is a schematic representation of an example of filling polysilicon into the trench in the fabrication method of the shielded gate trench power device provided in this application. After depositing source polysilicon 05 on the surface of the trench 03 and the epitaxial layer 02, a chemical mechanical mask is applied to the source polysilicon 05 deposited on the surface of the epitaxial layer 02 and the first oxide layer 04, and the thickness of the first oxide layer 04 on the surface of the epitaxial layer 02 is 1000 Å to 2000 Å.

[0070] In the foregoing introduction, it is known that when the first oxide layer is formed on the substrate surface and the trench sidewall, the thickness of the first oxide layer is 1000A-20000A, and the thickness of the first oxide layer on the substrate surface is polished to 1000A-2000A in step S202. Specifically, if the thickness of the first oxide layer is 1000A-2000A, the polysilicon and the first oxide layer deposited on the substrate surface are polished in step S202, and the polishing can stop at the first oxide layer 04; if the thickness of the first oxide layer is greater than 2000A, the polysilicon and the first oxide layer deposited on the substrate surface are polished in step S202, and the first oxide layer on the substrate surface is substantially thinned. The polishing can be set based on the actual thickness of the first oxide layer formed on the substrate surface and the trench sidewall, which is not limited in the present application.

[0071] It should be noted that since the first oxide layer on the substrate surface needs to be removed in the subsequent process, if the thickness of the first oxide layer is greater than 2000A (for example, the first oxide layer is 5000A, or 10000A or 20000A), the removal cost of the first oxide layer on the substrate surface in the subsequent process will be higher, and a large step height difference will be formed between the termination region and the cell region of the device in the subsequent process. Therefore, when the polysilicon in the trench is removed in the subsequent process, the removal rate will be uneven due to the step difference, and polysilicon residues will easily appear in the low step region (such as the cell region), which will affect the reliability of the device; if the thickness of the first oxide layer is less than 1000A, it is difficult to effectively protect the underlying epitaxial layer silicon in the subsequent polysilicon etching process, which may cause the epitaxial layer to be over-etched or damaged, thereby affecting the reliability of the device. Therefore, by keeping the first oxide layer at 1000A-2000A in this step, the removal cost of the first oxide layer on the substrate surface in the subsequent process can be effectively reduced, and the reliability of the device can be improved.

[0072] Step S203: etching the polysilicon in the trench to make the surface of the polysilicon lower than the upper surface of the first oxide layer on the substrate surface.

[0073] As shown in Figure 6 Fig. 4 is a schematic diagram of an example of etching the polysilicon filled in the trench in the preparation method of the shield gate trench type power device provided by the present application. After the source polysilicon 05 and the first oxide layer deposited on the surface of the epitaxial layer 02 are polished, the source polysilicon 05 in the trench 03 is etched to make the surface of the source polysilicon in the trench 03 lower than the upper surface of the first oxide layer 04 on the surface of the epitaxial layer 02, so as to form a recess with the sidewall being the first oxide layer 04 and the bottom being the source polysilicon 05 in the trench 03.

[0074] In the present embodiment, after the source polysilicon 05 in the etching trench 03 is etched, the height difference between the surface of the source polysilicon 05 in the trench 03 and the upper surface of the first oxide layer 04 on the surface of the epitaxial layer 02 is 1500A-2000A. The height difference between the surface of the source polysilicon and the upper surface of the first oxide layer on the surface of the epitaxial layer is the longitudinal height of the side wall to be formed in the subsequent step. The height difference can provide sufficient longitudinal height for the side wall to be formed, so that the polysilicon directly below the side wall to be formed can be effectively protected as a hard mask when the side wall is used as a hard mask. Figure 6 The depth of the recess with the side wall being the first oxide layer 04 and the bottom being the source polysilicon 05 formed in the trench 03 is 1500A-2000A.

[0075] Etching generally includes dry etching and wet etching. Dry etching is carried out in a low-pressure environment, in which plasma is generated by a radio frequency power source to decompose reactive gases (such as , , etc.) into active ions and free radicals, and the polysilicon is removed by chemical reaction between the active substances and the polysilicon. Dry etching has high selectivity and anisotropy. Wet etching uses liquid chemicals such as a mixture of nitric acid , hydrofluoric acid (HF), and acetic acid to dissolve and remove the polysilicon, which is generally isotropic etching.

[0076] Step S103: Forming a side wall on the trench side wall above the polysilicon.

[0077] This step is used to form a barrier layer on the side wall of the recess formed in the trench 03, which is used to protect the polysilicon directly below it, so as to retain the polysilicon directly below the side wall when the polysilicon in the trench 03 is etched for the second time.

[0078] In a specific embodiment, step S103 can be implemented by the following steps S204 and S205.

[0079] Step S204: Depositing a barrier layer on the first oxide layer on the surface of the substrate, the upper surface of the polysilicon, and the trench side wall above the polysilicon.

[0080] As shown in Figure 7 , it is an example of depositing a barrier layer in the preparation method of the shielding gate trench power device provided by the present application. After the source polysilicon 05 in the trench 03 is etched, a barrier layer 06 can be deposited on the first oxide layer 04 on the surface of the epitaxial layer 02, the upper surface of the source polysilicon 05, and the trench side wall above the source polysilicon 05.

[0081] It should be noted that the barrier layer 06 is a film layer of a different material from the first oxide layer 04. For example, the barrier layer 06 can be a nitride film, specifically including but not limited to SiN (silicon nitride), SION (silicon oxynitride), or SIHN (silicon hydronitride) and other nitride film layers. In this embodiment, the thickness of the barrier layer 06 is less than twice the width of the source polysilicon 05. This prevents the grooves formed in the trench 03 from being blocked. Furthermore, the thickness of the barrier layer 06 is less than the thickness of the polysilicon that can be consumed in the subsequent S106 thermal oxidation step. This ensures that the polysilicon retained below the barrier layer 06 ( Figure 9 When the polysilicon sidewall 08 in the middle is subjected to the thermal oxidation step, the polysilicon retained below the barrier layer 06 can be completely oxidized.

[0082] Step S205: Remove the barrier layer on the substrate surface and the barrier layer on the upper surface of the polysilicon, while retaining the barrier layer on the trench sidewall above the polysilicon to form a sidewall on the trench sidewall above the polysilicon.

[0083] like Figure 8 The diagram shown illustrates an example of removing the barrier layer outside the trench in the fabrication method of the shielded gate trench power device provided in this application. After depositing the barrier layer 06 on the first oxide layer 04 on the surface of the epitaxial layer 02, the upper surface of the source polysilicon 05, and the trench sidewall above the source polysilicon 05, the barrier layer 06 can be etched to remove the barrier layer on the surface of the epitaxial layer 02 and the barrier layer on the upper surface of the source polysilicon 05 in the trench 03, while retaining the barrier layer 07 on the trench sidewall above the source polysilicon 05, thereby forming a sidewall on the trench sidewall above the source polysilicon 05.

[0084] Step S104: Using the sidewall as a hard mask, etch the polysilicon in the trench to a first depth.

[0085] This step is used to protect the polysilicon directly below the sidewalls from being etched while etching the polysilicon in the trenches.

[0086] like Figure 9 The diagram shown is a schematic representation of an example of etching polysilicon using a sidewall as a hard mask in the fabrication method of a shielded trench power device provided in this application. After forming a sidewall 07 on the trench sidewall above the source polysilicon 05, the source polysilicon 05 in the trench 03 is etched using the sidewall 07 as a hard mask, thereby protecting the source polysilicon directly below the sidewall 07 from being etched while etching the source polysilicon 05, thus forming a polysilicon sidewall 08.

[0087] In a specific implementation, dry anisotropic etching of the polysilicon in the trench can be used to a first depth. Anisotropy is a technique that mainly etches along the vertical direction. By using the sidewall as a hard mask, it is possible to retain the polysilicon below the sidewall while etching the source polysilicon in the trench, thereby forming a polysilicon sidewall below the sidewall.

[0088] It should be noted that during or after the dry anisotropic etching of the polysilicon in the trench, a portion of the polysilicon below the sidewalls can be removed using isotropic etching at a set ratio to form a funnel-shaped opening between the polysilicon particles below the sidewalls. The set ratio can be specifically set based on actual needs. Unlike anisotropic etching, isotropic etching proceeds at the same rate in all directions. In isotropic etching mode, not only downward etching but also lateral etching occurs, thereby adjusting the thickness of the remaining polysilicon on the sidewalls.

[0089] The isotropic etching ratio is smaller than the anisotropic etching ratio. This allows for fine-tuning of the thickness of the residual polysilicon on the sidewalls after the polysilicon sidewalls are formed below the sidewalls. The etching angle can also be adjusted between 85° and 95° to form a funnel-shaped opening, which facilitates the filling of the gate polysilicon in subsequent steps, ensuring good coverage and reducing voids.

[0090] Step S105: Etch the first oxide layer on the trench sidewall to a second depth, wherein the second depth is less than the first depth.

[0091] like Figure 10 The diagram shown is a schematic representation of an example of etching the first oxide layer on the trench sidewall in the fabrication method of the shielded gate trench power device provided in this application embodiment. After forming the polysilicon sidewall 08 on the trench sidewall, the first oxide layer 04 on the trench sidewall can be etched. The second depth to which the first oxide layer 04 on the trench 03 sidewall is etched is less than the first depth to which the source polysilicon 05 filled in the trench 03 is etched.

[0092] Furthermore, the etching of the first oxide layer to the second depth on the trench sidewall in step S105 can be achieved through the following steps:

[0093] Areas that do not require etching can be covered using photolithography.

[0094] Perform wet etching to remove the first oxide layer exposed on the surface of the semiconductor substrate, and etch the first oxide layer on the trench sidewall, such that the depth of the region between the trench sidewall and the polysilicon sidewall formed below the sidewall is the second depth;

[0095] Remove the photoresist from the photolithography process.

[0096] It should be noted that the semiconductor substrate also includes a region that does not need to be etched, which can be protected from etching by applying photoresist on its surface.

[0097] The accompanying drawings are incorporated into and constitute a part of this specification. Figure 9 The following will be described in conjunction with the accompanying drawings, Figure 9 The semiconductor substrate shown includes three trenches 05, the leftmost trench can be a region that does not need to be etched, which can be protected from etching during lithography by applying photoresist 06 thereon, thereby playing a role in adjusting the electric field and improving the withstand voltage.

[0098] By applying photoresist on the region that does not need to be etched, then performing wet etching, which is a process of removing a specific part of the surface of a material using a liquid chemical agent, in this way, the first oxide layer exposed on the surface of the semiconductor substrate can be removed, such as Figure 9 As shown, the first oxide layer 04 exposed on the surface of the semiconductor substrate that is not covered by the photoresist 06 is removed by wet etching, then the first oxide layer on the sidewall of the trench 03 can be etched to make the depth of the area between the sidewall of the trench 03 and the polysilicon sidewall 08 formed below the sidewall 07 be the second depth. Then, as shown in the accompanying drawings, Figure 10 The photoresist 06 is removed, and subsequent processes continue.

[0099] It should be noted that the accompanying drawings Figure 10 is a cross-sectional view of a shield gate trench type power device, the polysilicon sidewall 08 is not a structure that stands alone in the trench, as shown in Figure 11 is a three-dimensional view of an example of a polysilicon sidewall and a source polysilicon below it in a shield gate trench type power device provided by the present application, it can be seen that the polysilicon sidewall 08 forms a hollow ring structure with four sides connected together, which is stable and firm in structure and will not collapse, and the source polysilicon 05 below it is a solid structure.

[0100] Step S106: remove the sidewall and perform thermal oxidation to form an oxide layer on the exposed part in the trench.

[0101] The exposed part in the trench can be understood as the polysilicon sidewall 08 formed in the trench 03 in the accompanying drawings, Figure 12 This step is used to completely oxidize the exposed polysilicon sidewall in the trench to an oxide layer.

[0102] In one optional implementation, the polysilicon sidewalls 08 can be completely oxidized by performing a single thermal oxidation step. Specifically, thermal oxidation is performed to form an oxide layer on the polysilicon sidewalls formed below the sidewalls in the trench, the polysilicon surface below the first depth portion of the trench, the substrate surface, and the trench sidewalls above the first oxide layer in the trench, thereby oxidizing all the polysilicon sidewalls formed below the sidewalls in the trench.

[0103] In another alternative implementation, considering that an oxide layer naturally forms on the surface of a semiconductor substrate when it is exposed to air, but this oxide layer is usually not dense enough and may contain many defects and impurities, affecting the quality of subsequent processes and device performance, the oxide layer can be formed in the exposed portion of the trench through at least two of the following methods:

[0104] Implementation method one includes the following steps S206 to S209:

[0105] Step S206: Remove the sidewalls by etching;

[0106] like Figure 12 The diagram shown is an example of removing sidewalls in the fabrication method of the shielded gate trench power device provided in this application. After etching the first oxide layer of the trench sidewall to a second depth, the sidewall 07 can be removed by wet etching.

[0107] Step S207: Perform thermal oxidation to form an oxide layer on the polysilicon sidewalls formed below the sidewalls in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewalls above the first oxide layer in the trench, and to oxidize the polysilicon sidewalls formed below the sidewalls in the trench.

[0108] like Figure 13 The diagram shown is an example of a thermal oxidation step performed for the first exposed portion of the trench in the fabrication method of the shielded gate trench power device provided in this application embodiment. After removing the sidewalls 07 by etching, thermal oxidation is performed to form an oxide layer 13 on the polysilicon sidewalls 08 in the trench 03, the polysilicon surface 05 below the first depth portion in the trench 03, the surface of the epitaxial layer 02, and the trench sidewalls above the first oxide layer 04 in the trench 03.

[0109] Through the above step S207, the polycrystalline silicon sidewall 08 in the trench can be partially oxidized.

[0110] Step S208: Remove the oxide layer on the trench sidewall above the first oxide layer in the trench and the oxide layer on the substrate surface.

[0111] like Figure 14The diagram shown illustrates an example of removing the oxide layer on the polysilicon surface and the substrate surface in the fabrication method of the shielded gate trench power device provided in this application. After forming oxide layer 13 on the polysilicon sidewall 08 in the trench 03, the polysilicon surface 05 below the first depth portion of the trench 03, the surface of the epitaxial layer 02, and the trench sidewall above the first oxide layer 04 in the trench 03, the oxide layer on the trench sidewall above the first oxide layer 04 in the trench 03 and the oxide layer on the surface of the epitaxial layer 02 are completely removed, leaving only the oxide layer on the surface of the polysilicon sidewall 08 in the trench 03. In this way, impurities on the trench sidewall above the first oxide layer 04 in the trench 03 and impurities on the substrate surface can be removed.

[0112] Step S209: Perform thermal oxidation to form an oxide layer on the polysilicon sidewalls formed below the sidewalls in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewalls above the first oxide layer in the trench, and to oxidize all the polysilicon sidewalls formed below the sidewalls in the trench.

[0113] This step is used to completely oxidize the polysilicon sidewalls in the trench into an oxide layer.

[0114] like Figure 15 The diagram shown is an example of a second thermal oxidation step performed on the exposed portion of the trench in the fabrication method of the shielded gate trench power device provided in this application embodiment. After completely removing the oxide layer on the trench sidewall above the first oxide layer 04 in the trench 03 and the oxide layer on the surface of the epitaxial layer 02, a thermal oxidation step is performed on the polysilicon sidewall 08 in the trench 03, the polysilicon surface 05 below the first depth portion in the trench 03, the surface of the epitaxial layer 02, and the trench sidewall above the first oxide layer 04 in the trench 03, so as to completely oxidize the polysilicon sidewall 08 in the trench 03 into oxide layer 14, and form oxide layers on the polysilicon surface 05 below the first depth portion in the trench 03, the surface of the epitaxial layer 02, and the trench sidewall above the first oxide layer 04 in the trench 03.

[0115] Optionally, after step S208, the thermal oxidation step in step S209 can be further not performed, and the surface of the polysilicon sidewall formed under the spacer in the trench, the surface of the polysilicon under the first depth portion in the trench, the surface of the substrate, and the trench sidewall above the first oxide layer in the trench are formed with an oxide layer by performing a chemical vapor deposition step, and the polysilicon sidewall formed under the spacer in the trench is partially oxidized; or the surface of the polysilicon sidewall formed under the spacer in the trench, the surface of the polysilicon under the first depth portion in the trench, the surface of the substrate, and the trench sidewall above the first oxide layer in the trench are formed with an oxide layer by performing a thermal oxidation step and a chemical vapor deposition step, and the polysilicon sidewall formed under the spacer in the trench is fully oxidized.

[0116] It should be noted that if the thermal oxidation in the present application is selected as dry oxidation, the oxidation temperature is generally between 900°C and 1100°C, and the oxidation time depends on the thickness of the oxide layer to be generated, for example, it can take about 2 hours to grow a 100-nanometer-thick oxide layer by dry oxidation at 1000°C; if the thermal oxidation in the present application is selected as wet oxidation, the oxidation temperature is generally between 700°C and 1000°C, and the oxidation time also depends on the thickness of the oxide layer to be generated, but the speed of wet oxidation is greater than that of dry oxidation, for example, it can take about 10 to 15 minutes to grow a 100-nanometer-thick oxide layer by wet oxidation at 1000°C. It should be noted that the oxidation temperature and the oxidation time herein are only examples and do not limit the present application.

[0117] Embodiment two includes the following steps S210 and S211:

[0118] Step S210: cleaning the trench sidewall above the first oxide layer in the trench and the surface of the substrate to remove impurities on the trench sidewall above the first oxide layer in the trench and impurities on the surface of the substrate;

[0119] Step S211 (the same as step S209 in embodiment one): performing thermal oxidation to form an oxide layer on the surface of the polysilicon sidewall formed under the spacer in the trench, the surface of the polysilicon under the first depth portion in the trench, the surface of the substrate, and the trench sidewall above the first oxide layer in the trench, and fully oxidize the polysilicon sidewall formed under the spacer in the trench.

[0120] In order to form a denser, higher-quality oxide layer on the substrate surface and the trench sidewalls, the substrate surface and the trench sidewalls can typically be cleaned in step S210 to remove contaminants and naturally formed incomplete oxides. Specifically, the trench sidewalls above the first oxide layer in the trench and the substrate surface can be cleaned using one of the following: hydrofluoric acid (HF) solution, ammonia-hydrogen peroxide solution (SC-1 cleaning solution), hydrochloric acid-hydrogen peroxide solution (SC-2 cleaning solution), etc., thereby removing impurities on the trench sidewalls above the first oxide layer in the trench and impurities on the substrate surface.

[0121] Subsequently, thermal oxidation is performed to form an oxide layer on the polysilicon sidewalls formed below the sidewalls in the trench, the polysilicon surface below the first depth portion in the trench, the substrate surface, and the trench sidewalls above the first oxide layer in the trench, thereby oxidizing all the polysilicon sidewalls formed below the sidewalls in the trench. Step S211 can be referred to the description of step S209, and will not be repeated here.

[0122] In this application embodiment, the specific method of forming the gate oxide can be selected based on actual needs, and there are no specific restrictions here.

[0123] Step S107: Fill the first depth portion and the second depth portion of the trench with polycrystalline silicon.

[0124] This step is used to perform gate polysilicon deposition.

[0125] like Figure 16 The diagram shown is a schematic representation of an example of filling polysilicon in the first and second depth portions of the trench in the fabrication method of the shielded gate trench power device provided in this application embodiment. After completely oxidizing the polysilicon sidewalls 08 in the trench 03 to an oxide layer 14, and forming an oxide layer on the surface of the epitaxial layer and on the trench sidewalls above the first oxide layer 04 in the trench 03, gate polysilicon 09 is deposited in the first and second depth portions of the trench 03.

[0126] In a specific implementation, step S108 can be achieved through the following steps:

[0127] Polycrystalline silicon is deposited on the first depth portion, the second depth portion of the trench, and the oxide layer on the surface of the substrate;

[0128] The deposited polysilicon is ground and / or etched to form three mutually separated sub-gates.

[0129] After forming three mutually separated sub-gates, the fabrication method of the shielded gate trench type device provided in this application embodiment may further include the following steps:

[0130] The semiconductor substrate is subjected to source region and body region implantation, interlayer dielectric layer deposition and contact hole etching to form source electrodes, gate electrodes and drain electrodes.

[0131] As shown in Figure 17 , it is a schematic diagram of an example of processing the gate polysilicon in the preparation method of the shielded gate trench power device provided by the embodiments of the present application. After the gate polysilicon 09 is deposited, the gate polysilicon 09 is ground and / or etched to form three mutually separated sub-gates, namely, sub-gate 10, sub-gate 11 and sub-gate 12. Then, the semiconductor substrate is subjected to source region and body region implantation, impurities are implanted in specific regions by ion implantation to change the conductivity type (N-type or P-type) of these regions, thereby defining the functional regions of the transistor. Then, the interlayer dielectric layer is deposited. In this way, after the source region and body region implantation is completed, different conductive layers are isolated by depositing an insulating layer, and a foundation is provided for subsequent contact hole etching. Then, the contact hole is etched to form a contact hole at the position corresponding to the sub-gate 10 and the sub-gate 12, so that the subsequent metal interconnection layer can establish electrical connection with the electrodes through the contact hole.

[0132] It can be seen that, in the preparation method of the shielded gate trench power device provided by the embodiments of the present application, the source polysilicon with a surface lower than the upper surface of the first oxide layer is filled in the trench. In this way, a groove with a polysilicon bottom and a first oxide layer sidewall can be formed in the trench. Then, a sidewall is formed on the sidewall of the groove, and the sidewall is used as a hard mask to etch the polysilicon in the trench to a first depth while protecting the polysilicon below the sidewall from being etched. In this way, a polysilicon sidewall can be formed below the sidewall. Then, based on the sidewall and the polysilicon sidewall below the sidewall, the first oxide layer on the sidewall of the trench can be etched, and the first oxide layer on the sidewall of the trench is etched to a second depth smaller than the first depth to which the polysilicon in the trench is etched. In this way, a second depth portion can be formed on both sides of the first depth portion in the trench, and the depth of the first depth portion is greater than the depth of the second depth portion. Then, the sidewall is removed, and a thermal oxidation step is performed to oxidize the polysilicon sidewall in the trench to form an oxide layer. Finally, the first depth portion and the second depth portion are filled with polysilicon, thereby forming a floating polysilicon in the first depth portion and two sub-gates in the second depth portion. In this way, a three-gate structure is formed, in which the two sub-gates (i.e., the sub-gate 10 and the sub-gate 12 in Figure 17 , are located above the upper region of the trench and above the shielded gate, and the floating polysilicon (i.e., the floating polysilicon 11 in Figure 17 ) is located in the middle. It can be seen that, due to the two sub-gates (i.e., the sub-gate 10 and the sub-gate 12 in Figure 17 ) and the shielded gate (i.e., the shielded gate 08 in Figure 17 ), the three-gate structure is formed.The reduced area between the source polysilicon 05 and the floating polysilicon 11 effectively reduces the integrated capacitance between the gate and the source, thereby improving the device's turn-on speed.

[0133] Furthermore, the fabrication method of the shielded gate trench power device provided in this application embodiment has no gate-source leakage problem because the gate polysilicon (two sub-gates on the left and right) and the shielding gate are arranged in a staggered manner and there is no inter-gate oxide layer in the middle. This ensures that the gate-source leakage is no longer affected by the inter-layer oxide layer between the shielding gate and the control gate.

[0134] A second embodiment of this application provides a semiconductor structure for a shielded gate trench power device, comprising: a semiconductor substrate in which trenches are formed, and a gate oxide layer formed on the sidewalls of the trenches; a shielding gate disposed on the gate oxide layer in the bottom region of the trenches; and mutually discrete sub-gates disposed in the upper region of the trenches and above the shielding gate; the mutually discrete sub-gates are separated by an oxide layer; wherein at least one sub-gate is offset from the shielding gate by a predetermined distance in the direction perpendicular to the depth. In this embodiment, the gate oxide layer is the shielding gate. Figure 17 The first oxide layer 04 on the sidewall of the trench, in this embodiment, is the shielding gate disposed on the gate oxide layer in the bottom region of the trench. Figure 17 The source polysilicon 05 below the floating polysilicon 11 shown in the diagram, in this embodiment, is a separate sub-gate disposed in the upper region of the trench and located above the shielding gate. Figure 17 The sub-gates 10 and 12 shown in the figure, in this embodiment, the oxide layer between the mutually discrete sub-gates is the attached... Figure 17 Oxide layer 14 in the middle.

[0135] In one optional implementation, the mutually independent sub-gates are three in number, specifically including attached... Figure 17 The sub-gate 10, sub-gate 12, and floating polysilicon 11 shown in the diagram, with the middle sub-gate (i.e., the attached sub-gate) Figure 17 The floating polysilicon 11 shown) and the shielding gate (i.e., the attached) Figure 17 The source polysilicon 05 below the floating polysilicon 11 shown in the diagram is opposite to the other two sub-gates (i.e., attached). Figure 17 The sub-gates 10 and 12 shown are disposed on both sides of the sub-gate located in the middle.

[0136] The semiconductor structure for shielded gate trench power devices provided in this embodiment can be obtained by the fabrication method of shielded gate trench power devices provided in the first embodiment of this application. For details, please refer to the detailed description of the fabrication method of shielded gate trench power devices provided in the first embodiment of this application, which will not be repeated here.

[0137] In another alternative embodiment, the mutually separated sub-gates are two (i.e., the sub-gate 10 and the sub-gate 12 shown in FIG. 1B), which are placed side by side. In this embodiment, the semiconductor structure does not include the floating polysilicon 11 shown in FIG. 1A. Figure 17 In another alternative embodiment, the mutually separated sub-gates are two (i.e., the sub-gate 10 and the sub-gate 12 shown in FIG. 1B), which are placed side by side. In this embodiment, the semiconductor structure does not include the floating polysilicon 11 shown in FIG. 1A. Figure 17 In another alternative embodiment, the mutually separated sub-gates are two (i.e., the sub-gate 10 and the sub-gate 12 shown in FIG. 1B), which are placed side by side. In this embodiment, the semiconductor structure does not include the floating polysilicon 11 shown in FIG. 1A.

[0138] It can be seen that the semiconductor structure for the shielded gate trench power device provided in the second embodiment of the present application includes: a semiconductor substrate, a trench is formed in the semiconductor substrate, and a gate oxide layer is formed on the sidewall of the trench; a shield gate is arranged on the bottom region of the trench on the gate oxide layer; mutually separated sub-gates are arranged on the upper region of the trench and above the shield gate; the mutually separated sub-gates are separated by an oxide layer; and at least one sub-gate is staggered by a certain distance relative to the shield gate in the vertical direction. In this way, the facing area between the mutually separated sub-gates arranged on the upper region of the trench and above the shield gate and the shield gate arranged on the bottom region of the trench on the gate oxide layer is reduced, which can effectively reduce the integrated capacitance between the gate and the source, thereby improving the opening speed of the device.

[0139] The shielded gate trench power device provided in the third embodiment of the present application can be prepared by the preparation method of the shielded gate trench power device provided in the first embodiment of the present application. For details, refer to the detailed introduction of the preparation method of the shielded gate trench power device provided in the first embodiment of the present application, which will not be described here.

[0140] Although the above is disclosed with reference to the preferred embodiments, it is not intended to limit the present application, and any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims of the present application.

Claims

1. A method of manufacturing a shielded gate trench power device, characterized by, The method comprises: providing a semiconductor substrate formed with a trench, and a first oxide layer formed on the substrate surface and the trench sidewall; filling the trench with polysilicon, and the polysilicon surface is lower than the upper surface of the first oxide layer on the substrate surface; forming a side wall on the trench sidewall above the polysilicon; using the side wall as a hard mask, etching the polysilicon in the trench to a first depth; etching the first oxide layer of the trench sidewall to a second depth, and the second depth is smaller than the first depth; removing the side wall, and performing thermal oxidation to form an oxide layer on the exposed part in the trench; filling the trench with polysilicon at the first depth part and the second depth part of the trench.

2. The method of claim 1, wherein, The filling the trench with polysilicon, and the polysilicon surface is lower than the upper surface of the first oxide layer on the substrate surface, comprises: depositing polysilicon on the substrate surface and in the trench until the trench is completely filled with polysilicon; grinding the deposited polysilicon and the first oxide layer on the substrate surface until the thickness of the first oxide layer on the substrate surface is 1000A-2000A; etching the polysilicon in the trench so that the polysilicon surface is lower than the upper surface of the first oxide layer on the substrate surface.

3. The method of claim 1, wherein, The forming a side wall on the trench sidewall above the polysilicon, comprises: depositing a barrier layer on the first oxide layer on the substrate surface, the upper surface of the polysilicon, and the trench sidewall above the polysilicon; removing the barrier layer on the substrate surface and the barrier layer on the upper surface of the polysilicon, and retaining the barrier layer on the trench sidewall above the polysilicon to form a side wall on the trench sidewall above the polysilicon.

4. The method according to any one of claims 1 to 3, characterized in that, The etching the polysilicon in the trench to a first depth, comprises: using dry anisotropic etching to etch the polysilicon in the trench to a first depth to retain the polysilicon under the side wall.

5. The method of claim 4, wherein, Further comprising: during or after the using dry anisotropic etching to etch the polysilicon in the trench, using isotropic etching with a set ratio to remove part of the polysilicon under the side wall to form a horn-shaped opening between the polysilicon under the side wall.

6. The method of claim 1, wherein, The etching the first oxide layer of the trench sidewall to a second depth, comprises: covering the area not needed to be etched by a photoetching process; performing wet etching to remove the exposed first oxide layer on the semiconductor substrate surface and etch the first oxide layer of the trench sidewall so that the depth of the area between the trench sidewall and the polysilicon sidewall formed under the side wall is the second depth; removing the photoresist in the photoetching process.

7. The method according to claim 1 or 5 or 6, characterized in that, The removing the side wall, performing thermal oxidation, and forming an oxide layer on the exposed part in the trench, comprises: removing the side wall by etching; performing thermal oxidation to form an oxide layer on the polysilicon sidewall formed under the side wall in the trench, the polysilicon surface under the first depth part in the trench, the substrate surface, and the trench sidewall above the first oxide layer in the trench, and partially oxidize the polysilicon sidewall formed under the side wall in the trench; removing the oxide layer of the trench sidewall above the first oxide layer in the trench and the oxide layer on the substrate surface; performing thermal oxidation to form an oxide layer on the exposed portions in the trench, and to oxidize the polysilicon sidewall formed below the sidewall in the trench completely.

8. The method according to claim 1 or 5 or 6, characterized in that, The performing thermal oxidation to form an oxide layer on the exposed portions in the trench comprises: cleaning the trench sidewall above the first oxide layer in the trench and the substrate surface to remove impurities on the trench sidewall above the first oxide layer in the trench and impurities on the substrate surface; performing thermal oxidation to form an oxide layer on the exposed portions in the trench, and to oxidize the polysilicon sidewall formed below the sidewall in the trench completely.

9. The method of claim 1, wherein, The filling the first depth portion and the second depth portion of the trench with polysilicon comprises: depositing polysilicon on the oxide layer of the first depth portion, the second depth portion of the trench and the substrate surface; grinding and / or etching the deposited polysilicon to form three mutually separated sub-gates.

10. The method of claim 9, wherein, After forming the three mutually separated sub-gates, further comprising: performing source and body implantation, interlayer dielectric layer deposition and contact hole etching on the semiconductor substrate to form source electrode, gate electrode and drain electrode.

11. The method of claim 1, wherein, The first oxide layer formed on the substrate surface and the trench sidewall has a thickness of 1000A-20000A.

12. The method of claim 1, wherein, The polysilicon surface is lower than the upper surface of the first oxide layer on the substrate surface, and the height difference between the polysilicon surface and the upper surface of the first oxide layer on the substrate surface is 1500A-2000A.

13. The method of claim 3, wherein, The barrier layer is one of SIN, SION and SIHN.

14. A shielded gate trench power device, characterized by, Prepared by the method of any one of claims 1-13.

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