Manufacturing method of electronic device and electronic device manufactured by using same

Abstract

The invention provides a manufacturing method of an electronic device, which is characterized by comprising the following steps of: providing a substrate; forming a first conductive layer on the substrate; patterning the first conductive layer to form a first conductive pattern; forming a second conductive layer on the first conductive pattern; the second conductive layer is patterned to form a second conductive pattern, the second conductive pattern comprises a first sub-pattern and a second sub-pattern, and the first sub-pattern is arranged on the first conductive pattern; the distance between the first conductive pattern and the second sub-pattern is smaller than the distance between the first sub-pattern and the second sub-pattern.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing an electronic device, and in particular to a method for manufacturing an electronic device capable of reducing line width or increasing component density. Background Art

[0002] With the rapid advancement of technology over the past half century, electronic products have become indispensable to people's lives. As consumer habits change, electronic products are becoming increasingly thinner, lighter, shorter, and smaller. By miniaturizing components and increasing component density, these devices are becoming more and more applicable in miniaturized electronic devices.

[0003] However, due to process limitations such as yellow light processing and / or etching capabilities, pattern miniaturization is restricted, resulting in challenges in component miniaturization.

[0004] Therefore, there is an urgent need to provide a method for manufacturing an electronic device in order to improve the existing defects. Summary of the Invention

[0005] The present invention provides a method for manufacturing an electronic device, characterized in that it includes: providing a substrate; forming a first conductive layer on the substrate; patterning the first conductive layer to form a first conductive pattern; forming a second conductive layer on the first conductive pattern; and patterning the second conductive layer to form a second conductive pattern, the second conductive pattern including a first sub-pattern and a second sub-pattern, wherein the first sub-pattern is arranged on the first conductive pattern; wherein the distance between the first conductive pattern and the second sub-pattern is smaller than the distance between the first sub-pattern and the second sub-pattern.

[0006] The present invention further provides an electronic device, characterized in that it includes: a substrate; a first conductive pattern disposed on the substrate; and a second conductive pattern, the second conductive pattern including a first sub-pattern and a second sub-pattern, wherein the first sub-pattern is disposed on the first conductive pattern, and the second sub-pattern is disposed on the substrate; wherein the distance between the first conductive pattern and the second sub-pattern is smaller than the distance between the first sub-pattern and the second sub-pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A and Figure 1B FIG. 1 is a flow chart of a method for manufacturing a portion of an electronic device according to an embodiment of the present invention.

[0008] Figure 2A 、 Figure 2B-1 and Figure 2B-2 FIG. 1 is a flow chart of a method for manufacturing a portion of an electronic device according to an embodiment of the present invention.

[0009] Figures 3A to 3FFIG. 1 is a flow chart of a method for manufacturing a portion of an electronic device according to an embodiment of the present invention.

[0010] Figure 4 FIG. 1 is a schematic diagram of a portion of an electronic device according to an embodiment of the present invention.

[0011] Figure 5 FIG. 1 is a schematic diagram of a portion of an electronic device according to an embodiment of the present invention.

[0012] Description of Reference Numerals

[0013] 1: substrate;

[0014] 2: first conductive layer;

[0015] 21: first conductive pattern;

[0016] 3: second conductive layer;

[0017] 31: second conductive pattern;

[0018] 31A: first sub-pattern;

[0019] 31B, 31B': second sub-pattern;

[0020] 31C: third sub-pattern;

[0021] 4: the third conductive layer;

[0022] 5: first insulation layer;

[0023] 6: Etching barrier layer;

[0024] 61: mask;

[0025] 61A: first sub-mask;

[0026] 61B: second sub-mask;

[0027] 7: second insulating layer;

[0028] 8: fourth conductive layer;

[0029] e1, e2, e3, e3', e4, e5, e6, e7, e8, e9, e10: edge;

[0030] PR: photoresist layer;

[0031] PR1, PR2, PR3: patterned photoresist;

[0032] PR2A, PR3A: first sub-photoresist pattern;

[0033] PR2B, PR3B: second sub-photoresist pattern;

[0034] R1: Partial area;

[0035] V1: first opening;

[0036] V2: second opening;

[0037] D1, D2, D3: distance;

[0038] W1, W2, W3, W4: maximum width;

[0039] X1, X2, X3, X4, X5, X6, X7, X8: distance;

[0040] X, Y: direction;

[0041] Z: Looking down direction. DETAILED DESCRIPTION

[0042] The following describes the embodiments of the present invention through specific embodiments. Those skilled in the art will readily understand the other advantages and effects of the present invention from the disclosure herein. The present invention may also be implemented or applied through other different specific embodiments, and the details in this specification may be modified and altered to suit different viewpoints and applications without departing from the spirit of the present invention.

[0043] It should be noted that, in this document, unless otherwise specified, "having an element" is not limited to having a single element, but may include one or more elements. Furthermore, the use of ordinal numbers such as "first" and "second" in the specification and claims to modify claim elements does not in itself imply or represent any previous ordinal number of the claimed elements, nor does it represent the order of one claimed element to another claimed element, or the order in the manufacturing method. The use of such ordinal numbers is only used to clearly distinguish a claimed element with a certain name from another claimed element with the same name.

[0044] Throughout the present specification and claims, certain words will be used to refer to specific components. It will be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, words such as "comprising", "containing", and "having" are open-ended words and should be interpreted as meaning "including but not limited to..." Therefore, when the terms "comprising", "containing" and / or "having" are used in the description of the present invention, they specify the presence of corresponding features, areas, steps, operations and / or components, but do not exclude the presence of one or more corresponding features, areas, steps, operations and / or components.

[0045] In the present invention, the terms "about", "approximately", "substantially", and "roughly" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The numbers given here are approximate numbers, that is, in the absence of specific instructions for "about", "approximately", "substantially", or "roughly", the meanings of "about", "approximately", "substantially", and "roughly" may still be implied. In addition, the terms "range from a first value to a second value" and "range between a first value and a second value" mean that the range includes the first value, the second value, and other values ​​therebetween.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined herein.

[0047] In addition, relative terms, such as "below" or "bottom" and "above" or "top", may be used in the embodiments to describe the relative relationship of one element of the drawings to another element. It is understood that if the device in the drawings is turned upside down, the element described as being on the "below" side will become the element on the "above" side. When a corresponding component (such as a film layer or region) is referred to as being "on another component", it can be directly on the other component, or there can be other components between the two. On the other hand, when a component is referred to as being "directly on another component", there are no components between the two. In addition, when a component is referred to as being "on another component", the two have a top-down relationship in a top-down direction, and the component can be above or below the other component, and this top-down relationship depends on the orientation of the device.

[0048] In the present invention, distance, width, length, and thickness can be measured using an optical microscope or from cross-sectional images obtained using an electron microscope, but the present invention is not limited thereto. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If a first value is equal to a second value, this implies that there may be an error of approximately 10% between the first and second values. If a first direction is perpendicular to a second direction, the angle between the first and second directions may be between 80 and 100 degrees. If the first direction is parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0049] It should be noted that the technical solutions provided in the following different embodiments can be replaced, combined or mixed with each other to form another embodiment without violating the spirit of the present invention.

[0050] The electronic device of the present invention may include, for example, a display device, a sensing device, an antenna device, a touch device, a splicing device, or other suitable electronic devices, but is not limited thereto. The display device of the present invention may be a non-self-luminous display device or a self-luminous display device, such as a liquid crystal display (LCD), a cholesteric liquid crystal display (CLD), an electrophoretic display (EPD), an organic light emitting diode display (OLED), or a light emitting diode display (LED). The display device may include, but is not limited to, a light emitting diode, a light conversion layer, or other suitable materials, or a combination thereof. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot light emitting diode (QLED, QDLED), but is not limited thereto. The light conversion layer may include wavelength conversion materials and / or filter materials. For example, the light conversion layer may include fluorescence, phosphor, quantum dots (QDs), other suitable materials, or combinations thereof, but is not limited thereto. The sensing device may include, for example, a biometric sensor, a touch sensor, a fingerprint sensor, a light sensor, an infrared sensor, a temperature sensor, other suitable sensors, or combinations thereof. The antenna device may include, for example, a liquid crystal antenna or other antenna types, but is not limited thereto. The tiled device may include, for example, a tiled display device or a tiled antenna device, but is not limited thereto. The electronic device may include electronic components, which may include passive components, active components, or combinations thereof, such as, but is not limited to, capacitors, resistors, inductors, varactors, variable capacitors, filters, diodes, transistors, sensors, microelectromechanical systems (MEMS), chips, and the like. It should be noted that the electronic device of the present invention may be any combination of the above-mentioned devices, but is not limited thereto.

[0051] Figure 1A and Figure 1B FIG. 1 is a flow chart of a method for manufacturing a portion of an electronic device according to an embodiment of the present invention. Figure 1B The lower half is a top view of some electronic devices. Figure 1B The upper half is a schematic cross-sectional view of line segment L1-L1'.

[0052] In one embodiment of the present invention, Figure 1A As shown, the method for manufacturing an electronic device includes: providing a substrate 1; forming a first conductive layer 2 on the substrate 1. Next, patterning the first conductive layer 2 to form a first conductive pattern 21. More specifically, before patterning the first conductive layer 2, the method may include: forming a photoresist layer PR on the first conductive layer 2; and patterning the photoresist layer PR to form a patterned photoresist PR1. Using the patterned photoresist PR1 as a mask, the first conductive layer 2 may be patterned to form the first conductive pattern 21.

[0053] Afterwards, the patterned photoresist PR1 is removed; a second conductive layer 3 is formed on the first conductive pattern 21. Figure 1B As shown, the second conductive layer 3 is patterned to form a second conductive pattern 31, wherein the second conductive pattern 31 includes a first sub-pattern 31A and a second sub-pattern 31B, the first sub-pattern 31A is disposed on the first conductive pattern 21, and the second sub-pattern 31B is spaced a distance X1 from the first sub-pattern 31A. In more detail, the step of patterning the second conductive layer 3 may include: forming a photoresist layer on the second conductive layer 3; and patterning the photoresist layer to form a patterned photoresist PR2, as shown in FIG. Figure 1A As shown, after the step of patterning the second conductive layer 3, as shown Figure 1B As shown, in the top-view direction Z of the substrate 1 , the patterned photoresist PR2 overlaps the second conductive pattern 31 . By using the patterned photoresist PR2 as a mask, the second conductive layer 3 can be patterned to form the second conductive pattern 31 .

[0054] In one embodiment of the present invention, Figure 1A As shown, the patterned photoresist PR2 may include a first sub-photoresist pattern PR2A and a second sub-photoresist pattern PR2B. In the top view direction Z of the substrate 1, the first sub-photoresist pattern PR2A overlaps with the first conductive pattern 21. After the step of patterning the second conductive layer 3, as shown in FIG. Figure 1B As shown, the first sub-photoresist pattern PR2A overlaps the first sub-pattern 31A, and the second sub-photoresist pattern PR2B overlaps the second sub-pattern 31B. By using the first sub-photoresist pattern PR2A and the second sub-photoresist pattern PR2B as masks, the second conductive layer 3 can be patterned to form the first sub-pattern 31A and the second sub-pattern 31B. Figure 1BAs shown, edge e2 of the first sub-pattern 31A may be substantially aligned with edge e4 of the first sub-photoresist pattern PR2A, and edge e3 of the second sub-pattern 31B may be substantially aligned with edge e5 of the second sub-photoresist pattern PR2B. Therefore, the distance X1 between the first sub-pattern 31A and the second sub-pattern 31B may be substantially equal to the distance X3 between the first sub-photoresist pattern PR2A and the second sub-photoresist pattern PR2B. The "distance X1" refers, for example, to the shortest straight-line distance between edge e2 of the first sub-pattern 31A and edge e3 of the second sub-pattern 31B, as viewed in the top-down direction Z of the substrate 1. The "distance X3" refers, for example, to the shortest straight-line distance between edge e4 of the first sub-photoresist pattern PR2A and edge e5 of the second sub-photoresist pattern PR2B, as viewed in the top-down direction Z of the substrate 1. In one embodiment of the present invention, the distance D1 between the first sub-pattern 31A and the substrate 1 is greater than the distance D2 between the second sub-pattern 31B and the substrate 1. The “distance D1” refers to, for example, the distance between the upper surface of the first sub-pattern 31A and the upper surface of the substrate 1 in the top-view direction Z of the substrate 1. The “distance D2” refers to, for example, the distance between the upper surface of the second sub-pattern 31B and the upper surface of the substrate 1 in the top-view direction Z of the substrate 1.

[0055] In one embodiment of the present invention, the step of patterning the first conductive layer 2 may include etching the first conductive layer 2 with a first etching material. In one embodiment of the present invention, the step of patterning the second conductive layer 3 may include etching the second conductive layer 3 with a second etching material, wherein the first conductive layer 2 and the second conductive layer 3 have etching selectivity to the same etching material (e.g., the second etching material). Therefore, when etching the second conductive layer 3, the first conductive pattern 21 is not easily etched by the second etching material. Therefore, the distance X2 between the first conductive pattern 21 and the second sub-pattern 31B may be smaller than the distance X1 between the first sub-pattern 31A and the second sub-pattern 31B, and the distance X2 between the first conductive pattern 21 and the second sub-pattern 31B may be smaller than the distance X3 between the first sub-photoresist pattern PR2A and the second sub-photoresist pattern PR2B. By having the second etching material etch the first conductive layer 2 and the second conductive layer 3 at different rates, line width can be reduced or device density can be increased. More specifically, when, for example, the distance X3 between the first sub-photoresist pattern PR2A and the second sub-photoresist pattern PR2B is at the process limit, since the first conductive pattern 21 is not easily etched by the second etching material, the distance between components or conductive lines can be extended beyond the distance X3 between the first sub-photoresist pattern PR2A and the second sub-photoresist pattern PR2B. In other words, this can reduce line width or increase component density. The "distance X2" refers, for example, to the shortest straight-line distance between the edge e1 of the first conductive pattern 21 and the edge e3 of the second sub-pattern 31B, as viewed in the top-down direction Z of the substrate 1. The "distance X1" refers, for example, to the shortest straight-line distance between the edge e2 of the first sub-pattern 31A and the edge e3 of the second sub-pattern 31B, as viewed in the top-down direction Z of the substrate 1, based on the direction in which the distance X2 extends.

[0056] In the present invention, the methods for forming the first conductive layer 1, the second conductive layer 2, and the photoresist layer PR may each include chemical vapor deposition, physical vapor deposition, sputtering, electroplating, chemical plating, coating, or a combination thereof, but the present invention is not limited thereto. Suitable coating methods include dip coating, spin coating, roller coating, blade coating, spray coating, or a combination thereof, but the present invention is not limited thereto. Any suitable method may be used for patterning, for example, it may include a photolithography process and an etching process, wherein the etching process may include dry etching, wet etching, or a combination thereof, but the present invention is not limited thereto. The present invention can achieve the effect of reducing line width or increasing component density through multiple photolithography processes and etching processes, thereby reducing the size of the component and being applied to the process of microcomponents. In the present invention, a suitable method may be used to remove the photoresist, such as stripping it off with external force, but the present invention is not limited thereto.

[0057] In the present invention, substrate 1 may be a rigid substrate or a flexible substrate. Suitable materials include glass, quartz, sapphire, ceramic, plastic, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polymethylmethacrylate (PMMA), other suitable materials, or combinations thereof, but the present invention is not limited thereto. In the present invention, the material of first conductive layer 2 may include indium tin oxide (ITO), molybdenum, molybdenum nitride (MoN), tungsten-molybdenum alloy (MoW), tungsten, or combinations thereof, but the present invention is not limited thereto. In the present invention, the material of second conductive layer 3 may include titanium nitride (TiN), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum oxide (TiAlO), titanium silicon aluminum (TiSiAl), titanium tungsten alloy (TiW), titanium tungsten nitride (TiWN), aluminum nitride (AlNx), or combinations thereof, but the present invention is not limited thereto. In the present invention, the first etching material is different from the second etching material. For example, the first etching material may include oxalic acid (H2C2O4), nitric acid (HNO3), or a combination thereof, and the second etching material may include sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), boron trichloride (BCl3), chlorine (Cl2), or a combination thereof, but the present invention is not limited thereto.

[0058] Figure 2A 、 Figure 2B-1 and Figure 2B-2 FIG. 1 is a flow chart of a method for manufacturing a portion of an electronic device according to an embodiment of the present invention. Figure 2B-1 and Figure 2B-2 The rightmost picture is a top view of some electronic devices. Figure 2B-1 and Figure 2B-2 The middle figure is a schematic cross-sectional view of line segment L2-L2'.

[0059] In one embodiment of the present invention, a method for manufacturing an electronic device may include: providing a substrate 1; forming a second conductive layer 3 on the substrate 1; and forming a first conductive layer 2 on the second conductive layer 3. Next, patterning the first conductive layer 2 to form a first conductive pattern 21. More specifically, before patterning the first conductive layer 2, the method may include: forming a photoresist layer PR on the first conductive layer 2; and patterning the photoresist layer PR to form a patterned photoresist PR1. Using the patterned photoresist PR1 as a mask, the first conductive layer 2 may be patterned to form the first conductive pattern 21. Thereafter, the patterned photoresist PR1 is removed.

[0060] In the present invention, after completing Figure 2A After the steps shown, you can proceed as follows Figure 2B-1 or Figure 2B-2 In one embodiment of the present invention, as shown in FIG. Figure 2B-1 As shown, after patterning the first conductive layer 2, the second conductive layer 3 is then patterned to form a second conductive pattern 31, wherein the second conductive pattern 31 includes a first sub-pattern 31A and a second sub-pattern 31B, the first conductive pattern 21 is disposed on the first sub-pattern 31A, and the second sub-pattern 31B is spaced a distance X1 from the first sub-pattern 31A. In more detail, the step of patterning the second conductive layer 3 may include: forming a photoresist layer on the second conductive layer 3; and patterning the photoresist layer to form a patterned photoresist PR2, as shown in FIG. Figure 2B-1 As shown, the patterned photoresist PR2 is spaced a distance X4 from the first conductive pattern 21. After patterning the second conductive layer 3, in the top-down direction Z of the substrate 1, the first conductive pattern 21 overlaps with the first sub-pattern 31A, and the patterned photoresist PR2 overlaps with the second sub-pattern 31B. Using the first conductive pattern 21 and the patterned photoresist PR2 as masks, the second conductive layer 3 can be patterned to form the first sub-pattern 31A and the second sub-pattern 31B of the second conductive pattern 31. In one embodiment of the present invention, the distance X4 between the patterned photoresist PR2 and the first conductive pattern 21 is substantially equal to the distance X1 between the first sub-pattern 31A and the second sub-pattern 31B, but the present invention is not limited thereto. The "distance X1" refers, for example, to the shortest straight-line distance between the edge e2 of the first sub-pattern 31A and the edge e3 of the second sub-pattern 31B, as viewed in the top-down direction Z of the substrate 1. The “distance X4” refers to, for example, the shortest straight-line distance between the edge e6 of the patterned photoresist PR2 and the edge e1 of the first conductive pattern 21 when viewed in the top-view direction Z of the substrate 1 .

[0061] In one embodiment of the present invention, Figure 2B-2 As shown, after patterning the first conductive layer 2, the second conductive layer 3 is then patterned to form a second conductive pattern 31, wherein the second conductive pattern 31 includes a first sub-pattern 31A and a second sub-pattern 31B, the first conductive pattern 21 is disposed on the first sub-pattern 31A, and the second sub-pattern 31B is spaced a distance X1 from the first sub-pattern 31A. In more detail, the step of patterning the second conductive layer 3 may include: forming a photoresist layer on the first conductive pattern 21 and the second conductive layer 3; and patterning the photoresist layer to form a patterned photoresist PR2, as shown in FIG. Figure 2B-2As shown. The patterned photoresist PR2 may include a first sub-photoresist pattern PR2A and a second sub-photoresist pattern PR2B. In the top-view direction Z of the substrate 1, the first sub-photoresist pattern PR2A may partially overlap with the first conductive pattern 21. After patterning the second conductive layer 3, the first sub-photoresist pattern PR2A overlaps with a portion of the first sub-pattern 31A, and the second sub-photoresist pattern PR2B overlaps with the second sub-pattern 31B. The first sub-photoresist pattern PR2A and the first conductive pattern 21 are used as masks to pattern the second conductive layer 3 to form the first sub-pattern 31A of the second conductive pattern 31. The second sub-photoresist pattern PR2B is used as a mask to pattern the second conductive layer 3 to form the second sub-pattern 31B of the second conductive pattern 31. In one embodiment of the present invention, the distance X1 between the first sub-pattern 31A and the second sub-pattern 31B may be smaller than the distance X3 between the first sub-photoresist pattern PR2A and the second sub-photoresist pattern PR2B. The “distance X1” refers to, for example, the shortest straight-line distance between an edge e2 of the first sub-pattern 31A and an edge e3 of the second sub-pattern 31B, as viewed in the top-down direction Z of the substrate 1. The “distance X3” refers to, for example, the shortest straight-line distance between an edge e4 of the first sub-photoresist pattern PR2A and an edge e5 of the second sub-photoresist pattern PR2B, as viewed in the top-down direction Z of the substrate 1.

[0062] In one embodiment of the present invention, the step of patterning the first conductive layer 2 may include etching the first conductive layer 2 with a first etchant. In one embodiment of the present invention, the step of patterning the second conductive layer 3 may include etching the second conductive layer 3 with a second etchant. The first conductive layer 2 and the second conductive layer 3 have etching selectivity to the same etchant (e.g., the second etchant). Therefore, when etching the second conductive layer 3, the first conductive pattern 21 is not easily etched by the second etchant. Therefore, by using the first conductive pattern 21 as a mask, the present invention can achieve the effect of reducing line width or increasing device density. More specifically, when the distance X3 between the first sub-photoresist pattern PR2A and the second sub-photoresist pattern PR2B is the process limit, using the first conductive pattern 21 as a mask can eliminate the distance X1 between the first sub-pattern 31A and the second sub-pattern 31B from being limited to the distance X3 between the first sub-photoresist pattern PR2A and the second sub-photoresist pattern PR2B. In other words, the distance between devices or wires can be reduced.

[0063] In the present invention, the methods for forming the first conductive layer 2, the second conductive layer 3, and the photoresist layer PR can be as described above, and will not be repeated here. Any suitable method can be used for patterning and removing the photoresist, and suitable methods can also be as described above, and will not be repeated here. In addition, the materials of the substrate 1, the first conductive layer 2, and the second conductive layer 3 in the present invention can be as described above, and will not be repeated here. In the present invention, the first etching material is different from the second etching material, and the first etching material and the second etching material can be as described above, and will not be repeated here.

[0064] Figures 3A to 3F FIG. 1 is a flow chart of a method for manufacturing a portion of an electronic device according to an embodiment of the present invention. Figures 3A to 3F The upper half is a top view, and the lower half is a cross-sectional view of line segment L3-L3' and line segment L4-L4'. Figures 3A to 3F The production method and Figure 1A and Figure 1B Similar except for the following differences: In addition, for the convenience of illustration, some elements are omitted in the figure.

[0065] In one embodiment of the present invention, although not shown in the figure, the substrate 1 and the first conductive pattern 21 may include multiple insulating layers, semiconductor layers, conductive layers, other suitable layers or films, or a combination thereof, but the present invention is not limited thereto. Figure 3A As shown, a third conductive layer 4 and a first insulating layer 5 may be included between the substrate 1 and the first conductive pattern 21, so the manufacturing method may include: forming a third conductive layer 4 on the substrate 1; forming a first insulating layer 5 on the third conductive layer 4, wherein the first insulating layer 5 includes a first opening V1, and the first opening V1 exposes a portion of the third conductive layer 4. Then, a first conductive layer 2 is formed on the first insulating layer 5. Thereafter, the first conductive layer 2 is patterned to form a first conductive pattern 21. In one embodiment of the present invention, in the top-view direction Z of the substrate 1, the first conductive pattern 21 does not overlap with the first opening V1. In one embodiment of the present invention, in the top-view direction Z of the substrate 1, the shape of the first conductive pattern 21 is not particularly limited, for example, it may be circular, elliptical, rectangular, or rectangular with arc corners, but the present invention is not limited thereto.

[0066] Then, if Figure 3B As shown, a second conductive layer 3 is formed on the first conductive pattern 21 and in the first opening V1. Figure 3C and Figure 3DAs shown, an etch stop layer 6 is formed on the second conductive layer 3; and the etch stop layer 6 is patterned to form a mask 61, wherein the mask 61 overlaps with a portion R1 of the second conductive layer 3 in the top view direction Z of the substrate 1. In one embodiment of the present invention, a portion of the mask 61 overlaps with the first opening V1 in the top view direction Z of the substrate 1.

[0067] Then, if Figure 3E As shown, a photoresist layer is formed on the second conductive layer 3 and the mask 61; and the photoresist layer is patterned to form a patterned photoresist PR3. The patterned photoresist PR3 may include a first sub-photoresist pattern PR3A and a second sub-photoresist pattern PR3B. In the top view direction Z of the substrate 1, the first sub-photoresist pattern PR3A may partially overlap with the first conductive pattern 21, and the second sub-photoresist pattern PR3B may partially overlap with the first opening V1 and the mask 61.

[0068] Next, the second conductive layer 3 is patterned to form a second conductive pattern 31 by using the first sub-photoresist pattern PR3A, the second sub-photoresist pattern PR3B and the mask 61 as a mask. Thereafter, the patterned photoresist PR3 is removed. Figure 3F As shown, the second conductive pattern 31 includes a first sub-pattern 31A, a second sub-pattern 31B, and a third sub-pattern 31C. The first sub-pattern 31A is disposed on the first conductive pattern 21, the mask 61 is disposed on the second sub-pattern 31B, the third sub-pattern 31C is adjacent to the second sub-pattern 31B, and the second sub-pattern 31B corresponds to a partial region R1 of the second conductive layer 3. More specifically, in the top view direction Z of the substrate 1, the region of the second conductive pattern 31 that overlaps with the first conductive pattern 21 is the first sub-pattern 31A, the region of the second conductive pattern 31 that overlaps with the mask 61 is the second sub-pattern 31B, and the region of the second conductive pattern 31 that overlaps with the patterned photoresist PR3 (as shown in FIG. Figure 3E The area excluding the first sub-pattern 31A and the second sub-pattern 31B is the third sub-pattern 31C. In one embodiment of the present invention, part of the third sub-pattern 31C may be connected to the first sub-pattern 31A, for example Figure 3F In the example, two third sub-patterns 31C are connected to the first sub-pattern 31A respectively. In other words, the first sub-pattern 31A is arranged between the two third sub-patterns 31C. However, the present invention is not limited thereto. The number and arrangement positions of the third sub-patterns 31C can be adjusted as needed. For example, in one embodiment, the first sub-pattern 31A can be connected to one third sub-pattern 31C and arranged on one side of the third sub-pattern 31C. In one embodiment of the present invention, some third sub-patterns 31C can be connected to the second sub-pattern 31B, for example Figure 3FThe example uses two third sub-patterns 31C connected to the second sub-pattern 31B, respectively. In other words, the second sub-pattern 31B is disposed between the two third sub-patterns 31C. However, the present invention is not limited to this embodiment. The number and placement of the third sub-patterns 31C can be adjusted as needed. For example, in one embodiment, the second sub-pattern 31B can be connected to a third sub-pattern 31C and disposed on one side of the third sub-pattern 31C. Furthermore, in another embodiment (not shown), the second sub-pattern 31B and the first sub-pattern 31A can be disposed at either end of a third sub-pattern 31C. In one embodiment, the third sub-pattern 31C can extend in a direction (e.g., the Y direction). When viewed in the top direction Z of the substrate 1, the third sub-pattern 31C can be linear, curved, repeating S-shaped, Z-shaped, or a combination of these. In one embodiment, the plurality of third sub-patterns 31C can be parallel or non-parallel. In one embodiment of the present invention, when viewed in the top direction Z, the maximum width W1 of the first conductive pattern 21 along a direction (e.g., the X direction) may be greater than the maximum width W2 of the third sub-pattern 31C connected to the first sub-pattern 31A along the same direction (e.g., the X direction). In one embodiment of the present invention, when viewed in the top direction Z, the maximum width W3 of the mask 61 along a direction (e.g., the X direction) may be greater than the maximum width W4 of the third sub-pattern 31C connected to the second sub-pattern 31B along the same direction (e.g., the X direction).

[0069] In one embodiment of the present invention, the distance X2 between the first conductive pattern 21 and the second sub-pattern 31B is less than the distance X1 between the first sub-pattern 31A and the second sub-pattern 31B. In one embodiment of the present invention, the distance X5 between the third sub-pattern 31C and the second sub-pattern 31B is less than the distance X1 between the first sub-pattern 31A and the second sub-pattern 31B. The "distance X2" refers, for example, to the shortest straight-line distance between the edge e1 of the first conductive pattern 21 and the edge e3 of the second sub-pattern 31B, as viewed in the top-down direction Z of the substrate 1. The "distance X1" refers, for example, to the shortest straight-line distance between the edge e2 of the first sub-pattern 31A and the edge e3 of the second sub-pattern 31B, as viewed in the top-down direction Z of the substrate 1, based on the direction along which the distance X2 extends. The "distance X5" refers, for example, to the shortest straight-line distance between the edge e7 of the third sub-pattern 31C, which is adjacent to but not connected to a second sub-pattern 31B, and the edge e3 of the second sub-pattern 31B, as viewed in the top-down direction Z of the substrate 1. In one embodiment of the present invention, the distance X6 between two adjacent third sub-patterns 31C is greater than the distance X5 between the third sub-pattern 31C and the second sub-pattern 31B that are adjacent to but not connected to the second sub-pattern 31B. The "distance X6" refers to, for example, the shortest straight-line distance between the edge e7 and the edge e8 of two adjacent third sub-patterns 31C when viewed in the top direction Z of the substrate 1.

[0070] In one embodiment of the present invention, multiple insulating layers, semiconductor layers, conductor layers, other suitable layers or films, or combinations thereof may be selectively provided on the second conductive pattern 31 and the mask 61, but the present invention is not limited thereto. Figure 3F As shown, a second insulating layer 7 and a fourth conductive layer 8 may be further disposed on the second conductive pattern 31 and the mask 61. Therefore, the manufacturing method may further include: forming a second insulating layer 7 on the mask 61 and the second conductive pattern 31, wherein the second insulating layer 7 includes a second opening V2, and the second opening V2 exposes a portion of the first sub-pattern 31A. Then, forming a fourth conductive layer 8 on the second insulating layer 7 and in the second opening V2, and the fourth conductive layer 8 may be electrically connected to the first sub-pattern 31A through the second opening V2. In another embodiment of the present invention, although not shown in the figure, the second opening V2 may simultaneously expose the first sub-pattern 31A and a portion of the first conductive pattern 21, but the present invention is not limited to this.

[0071] In one embodiment of the present invention, the step of patterning the first conductive layer 2 may include etching the first conductive layer 2 with a first etching material. In one embodiment of the present invention, the step of patterning the second conductive layer 3 may include etching the second conductive layer 3 with a second etching material. The first conductive layer 2 and the second conductive layer 3 have etching selectivity for the same etching material (e.g., the second etching material). Therefore, when etching the second conductive layer 3, the first conductive pattern 21 is not easily etched by the second etching material. Therefore, the distance X2 between the first conductive pattern 21 and the second sub-pattern 31B may be smaller than the distance X1 between the first sub-pattern 31A and the second sub-pattern 31B. Furthermore, the second conductive layer 3 and the mask 61 have etching selectivity for the same etching material (e.g., the second etching material). Therefore, when etching the second conductive layer 3, the mask 61 can serve as a mask. This can reduce line width or increase device density.

[0072] In the present invention, the methods for forming the first conductive layer 2, the second conductive layer 3, and the photoresist layer can be as described above, and will not be repeated here. The methods for forming the third conductive layer 4, the fourth conductive layer 8, the first insulating layer 5, and the second insulating layer 7 can be similar to the methods for forming the first conductive layer 2, and will not be repeated here. Any suitable method can be used for patterning and removing the photoresist, and suitable methods can be as described above, and will not be repeated here. In the present invention, the first opening V1 and the second opening V2 can be formed by, for example, mechanical perforation, laser perforation, yellow light process, or a combination thereof, but the present invention is not limited thereto.

[0073] In the present invention, the materials for the substrate 1, first conductive layer 2, and second conductive layer 3 can each be as described above and will not be further described here. In the present invention, the materials for the third conductive layer 4 and fourth conductive layer 8 can each include a metal, a metal oxide, an alloy thereof, or a combination thereof, such as gold, silver, copper, palladium, platinum, ruthenium, aluminum, cobalt, nickel, titanium, molybdenum, manganese, indium zinc oxide (IZO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), aluminum zinc oxide (AZO), or a combination thereof, but the present invention is not limited thereto. In the present invention, the materials for the first insulating layer 5 and the second insulating layer 7 can each include silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or a combination thereof, but the present invention is not limited thereto. In the present invention, the material for the etch stop layer 6 can include indium tin oxide (ITO), molybdenum, molybdenum nitride (MoN), tungsten-molybdenum alloy (MoW), tungsten, or a combination thereof, but the present invention is not limited thereto. In the present invention, the first etching material is different from the second etching material, and the first etching material and the second etching material can be respectively as described above, which will not be repeated here.

[0074] Figure 4 Schematic diagram of a portion of an electronic device according to an embodiment of the present invention. Figure 4 The upper half is a top view, and the lower half is a cross-sectional view of line segment L3-L3' and line segment L4-L4'. Figure 4 Electronic devices and Figure 3F Similar to, and its preparation method is Figures 3A to 3F Similar, except for the following differences.

[0075] In one embodiment of the present invention, Figure 4 As shown, the electronic device may not be provided with the first conductive layer 2, therefore, Figure 4 The electronic device shown may not include the first conductive pattern 21 (eg Figure 3F As shown). In addition, the mask 61 may include a first sub-mask 61A and a second sub-mask 61B, and the first sub-mask 61A and the second sub-mask 61B are used together as masks to pattern the second conductive layer 3 to form a second conductive pattern 31. In which, in the top-view direction Z of the substrate 1, the area of ​​the second conductive pattern 31 that overlaps with the first sub-mask 61A and the second sub-mask 61B is the second sub-pattern 31B and 31B', and the area of ​​the second conductive pattern 31 excluding the second sub-pattern 31B and 31B' is the third sub-pattern 31C. In one embodiment of the present invention, in the top-view direction Z of the substrate 1, part of the first sub-mask 61A overlaps with the second opening V2, and part of the second sub-mask 61B overlaps with the first opening V1. In one embodiment of the present invention, as Figure 4 As shown, the second opening V2 may expose a portion of the first sub-mask 61A, but the present invention is not limited thereto.

[0076] In one embodiment of the present invention, the second conductive layer 3 is patterned using multiple sub-masks (e.g., a first sub-mask 61A and a second sub-mask 61B) to form multiple second sub-patterns 31B and 31B'. In the top-view direction Z of the substrate 1, one of the multiple second sub-patterns (e.g., the second sub-pattern 31B') overlaps with the first opening V1 of the first insulating layer 5, and another of the multiple second sub-patterns (e.g., the second sub-pattern 31B) overlaps with the second opening V2 of the second insulating layer 7. In one embodiment of the present invention, the distance X8 between adjacent second sub-patterns 31B and 31B' may be substantially equal to the distance X7 between the first sub-mask 61A and the second sub-mask 61B. In one embodiment of the present invention, the distance X5 between the third sub-pattern 31C and the second sub-pattern 31B' is less than the distance X8 between adjacent second sub-patterns 31B and 31B'. "Distance X8" refers, for example, to the shortest straight-line distance between the edge e3 of the adjacent second sub-pattern 31B and the edge e3' of the second sub-pattern 31B', as viewed in the top-view direction Z of the substrate 1. The "distance X5" refers, for example, to the shortest straight-line distance between an edge e7 of the third sub-pattern 31C, which is adjacent to and not connected to one of the plurality of second sub-patterns 31B and 31B' (e.g., the second sub-pattern 31B'), and an edge e3' of the second sub-pattern (e.g., the second sub-pattern 31B'), as viewed in the top-down direction Z of the substrate 1. The "distance X7" refers, for example, to the shortest straight-line distance between an edge e9 of the first sub-mask 61A and an edge e10 of the second sub-mask 61B, as viewed in the top-down direction Z of the substrate 1.

[0077] In the present invention, the detailed features, materials and manufacturing methods of each component in the electronic device are as described above and will not be repeated here.

[0078] Figure 5 Schematic diagram of a portion of an electronic device according to an embodiment of the present invention. Figure 5 The upper half is a top view, and the lower half is a cross-sectional view of line segment L3-L3' and line segment L4-L4'. Figure 5 Electronic devices and Figure 3F Similar to, and its preparation method is Figures 3A to 3F Similar, except for the following differences.

[0079] In one embodiment of the present invention, Figure 5 As shown, the first conductive pattern 21 can be disposed on the first sub-pattern 31A. Therefore, the method for manufacturing an electronic device may include: first forming a second conductive layer 3 (such as Figure 3B As shown) on the substrate 1, a first conductive pattern 21 and a mask 61 are formed on the second conductive layer 3 (as shown Figure 3BThen, the second conductive layer 3 (as shown) is formed by using the first conductive pattern 21, the mask 61 and the patterned photoresist (not shown) as a mask. Figure 3B As shown in FIG. 1 , the second conductive pattern 31 is patterned to form a second conductive pattern 31. In the top view direction Z of the substrate 1, the area of ​​the second conductive pattern 31 that overlaps with the first conductive pattern 21 is the first sub-pattern 31A, and the area that overlaps with the mask 61 is the second sub-pattern 31B. In one embodiment of the present invention, in the top view direction Z of the substrate 1, part of the mask 61 overlaps with the first opening V1, and part of the first conductive pattern 21 overlaps with the second opening V2. In one embodiment of the present invention, as shown in FIG. Figure 5 As shown, the second opening V2 may expose a portion of the first conductive pattern 21, but the present invention is not limited thereto. In another embodiment of the present invention, although not shown in the figure, the second opening V2 may simultaneously expose a portion of the first conductive pattern 21 and a portion of the first sub-pattern 31A, but the present invention is not limited thereto.

[0080] In one embodiment of the present invention, the distance X1 between the first sub-pattern 31A and the second sub-pattern 31B is substantially equal to the distance X2 between the first conductive pattern 21 and the second sub-pattern 31B. The "distance X2" refers, for example, to the shortest straight-line distance between the edge e1 of the first conductive pattern 21 and the edge e3 of the second sub-pattern 31B, as viewed in the top-down direction Z of the substrate 1. The "distance X1" refers, for example, to the shortest straight-line distance between the edge e2 of the first sub-pattern 31A and the edge e3 of the second sub-pattern 31B, as viewed in the top-down direction Z of the substrate 1, along the direction in which the distance X2 extends.

[0081] In the present invention, the detailed features, materials and manufacturing methods of each component in the electronic device are as described above and will not be repeated here.

[0082] In the present invention, since the second conductive layer 3 and the first conductive layer 2 (or the mask 61) have etching selectivity to the same etching material, the first conductive pattern 21 and / or the mask 61 can be selectively used together with the photoresist as a mask to pattern the second conductive layer 3, thereby achieving the effect of reducing the line width or increasing the component density.

[0083] The above specific embodiments are to be construed as merely illustrative, and not limitative of the remainder of the disclosure in any way whatsoever.

Claims

1. A method for manufacturing an electronic device, characterized in that: Include: providing a substrate; forming a first conductive layer on the substrate; patterning the first conductive layer to form a first conductive pattern; forming a second conductive layer on the first conductive pattern; as well as Patterning the second conductive layer to form a second conductive pattern, the second conductive pattern comprising a first sub-pattern and a second sub-pattern, wherein the first sub-pattern is disposed on the first conductive pattern; The distance between the first conductive pattern and the second sub-pattern is smaller than the distance between the first sub-pattern and the second sub-pattern.

2. The production method according to claim 1, characterized in that Before the step of patterning the second conductive layer, the method further comprises: forming an etch stop layer on the second conductive layer; and patterning the etch stop layer to form a mask; Wherein, in a top-view direction of the substrate, the mask overlaps with a portion of the second conductive layer.

3. The production method according to claim 2, characterized in that: After the step of patterning the second conductive layer, the second conductive pattern further includes a third sub-pattern adjacent to the second sub-pattern, wherein the second sub-pattern corresponds to the partial area of ​​the second conductive layer.

4. The production method according to claim 3, characterized in that: The distance between the third sub-pattern and the second sub-pattern is smaller than the distance between the first sub-pattern and the second sub-pattern.

5. The production method according to claim 1, characterized in that: The first conductive layer and the second conductive layer have etching selectivity to the same etching material.

6. The production method according to claim 1, characterized in that: The material of the first conductive layer includes indium tin oxide (ITO), molybdenum, molybdenum nitride (MoN), tungsten-molybdenum alloy (MoW), tungsten, or a combination thereof.

7. The production method according to claim 1, characterized in that: The material of the second conductive layer includes titanium nitride (TiN), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum oxide (TiAlO), titanium silicon aluminum (TiSiAl), titanium tungsten alloy (TiW), titanium tungsten nitride (TiWN), aluminum nitride (AlNx), or a combination thereof.

8. The production method according to claim 1, characterized in that: Before the step of patterning the second conductive layer, the method further comprises: forming a photoresist layer on the second conductive layer; and patterning the photoresist layer to form a patterned photoresist; After the step of patterning the second conductive layer, the patterned photoresist overlaps with the second conductive pattern in a top-view direction of the substrate.

9. The production method according to claim 8, characterized in that: The patterned photoresist includes a first sub-photoresist pattern and a second sub-photoresist pattern. In the top view direction of the substrate, the first sub-photoresist pattern overlaps with the first sub-pattern, and the second sub-photoresist pattern overlaps with the second sub-pattern.

10. The manufacturing method according to claim 9, characterized in that: A distance between the first conductive pattern and the second sub-pattern is smaller than a distance between the first sub-photoresist pattern and the second sub-photoresist pattern.

11. An electronic device, characterized in that: Include: a substrate; a first conductive pattern disposed on the substrate; and a second conductive pattern, the second conductive pattern comprising a first sub-pattern and a second sub-pattern, wherein the first sub-pattern is disposed on the first conductive pattern, and the second sub-pattern is disposed on the substrate; The distance between the first conductive pattern and the second sub-pattern is smaller than the distance between the first sub-pattern and the second sub-pattern.

12. The electronic device according to claim 11, wherein: The second conductive pattern further includes a third sub-pattern, wherein a distance between the third sub-pattern and the second sub-pattern is smaller than a distance between the first sub-pattern and the second sub-pattern.

13. The electronic device according to claim 12, wherein: The device also includes a mask disposed on the second sub-pattern.

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