Crystal grain, chip, layout design method and related equipment

Abstract

The invention relates to the technical field of semiconductors, in particular to a crystal grain, a chip, a layout design method and related equipment, and the crystal grain comprises a first logic gate unit and M first CNT groups; the first logic gate unit comprises N first FET groups, each FET group comprises a plurality of FETs with the same channel type, and the channel types of the FETs of different FET groups are different; each first CNT group comprises one or more CNTs; the FETs of the N first FET groups are prepared on the CNTs of the M first CNT groups; each first FET group corresponds to one or more first CNT groups, different FET groups correspond to different CNT groups, FETs in the same FET group are prepared on the CNT group corresponding to the FET group, and a plurality of FETs of at least one FET group in the N first FET groups are prepared on a plurality of CNT groups corresponding to the FET group. According to the invention, the influence of the MCNT on the logic gate unit can be reduced, and the circuit reliability is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for designing a grain, a chip, and a layout, and related equipment. Background Art

[0002] In recent decades, silicon-based transistor manufacturing technology has continued to develop and improve, resulting in ever-decreasing manufacturing costs and increasing computing energy efficiency. However, as the number of transistors packaged in integrated circuits continues to increase, the trend of improving energy efficiency appears to be coming to an end. Unlike traditional silicon-based field effect transistors (FETs), carbon nanotube field effect transistors (CNFETs) made from carbon nanotubes (CNTs) offer higher energy efficiency, faster manufacturing processes, and lower costs.

[0003] However, since currently produced carbon nanotubes (CNTs) are difficult to guarantee 100% semiconductor properties, CNTs may contain a small amount of metallic carbon nanotubes (MCNTs). Therefore, when using CNTs as the channel material to fabricate field-effect transistors (FETs), a small amount of MCNTs may be mixed in the channel, causing the resulting carbon nanotube field-effect transistor (CNFET) based on the metallic CNTs to be difficult to turn off. Logic gate units / circuits based on the CNFETs may also be adversely affected, such as a reduction in the static noise margin (SNM) of the logic gate units / circuits. The degree of impact of metallic CNTs on different logic gate units / circuits may vary. In severe cases, the SNM may be reduced to zero, causing the logic function of the logic gate units / circuits to fail and malfunction.

[0004] Therefore, how to provide a grain structure that can reduce the impact of metallic carbon nanotubes on logic gate units / circuits is an urgent problem to be solved. Summary of the Invention

[0005] The embodiments of the present application provide a method for designing a crystal grain, a chip, and a layout, and related equipment, which can reduce the degree to which the logical functions of logic gate units / circuits are affected by metallic carbon nanotubes and improve circuit reliability.

[0006] The present application is introduced below from different aspects. It should be understood that the implementation methods and beneficial effects of the following different aspects can be referenced to each other.

[0007] In the first aspect, the present application provides a grain, characterized in that the grain includes a first logic gate unit and M first carbon nanotube CNT groups; the first logic gate unit includes N first field effect transistor FET groups, each first FET group in the N first FET groups includes multiple first FETs with the same channel type, and the channel types of FETs in different FET groups in the N first FET groups are different, and N is an integer greater than or equal to 2; each first CNT group in the M first CNT groups includes one or more CNTs; M is an integer greater than or equal to 3; the FETs of the N first FET groups are prepared on the CNTs of the M first CNT groups; wherein each first FET group corresponds to one or more first CNT groups, and the one or more first CNT groups corresponding to different first FET groups are different, the multiple first FETs in each first FET group are prepared on the CNTs of the one or more first CNT groups corresponding to each first FET group, and the multiple first FETs in at least one first FET group among the N first FET groups are prepared on the CNTs of the corresponding multiple first CNT groups.

[0008] Unlike prior art solutions in which all FETs in any FET group of a logic gate unit are fabricated on CNTs in the same CNT group, when metallic carbon nanotubes (MCNTs) appear in a particular CNT group, all FETs in the FET group corresponding to that CNT group are affected by the MCNTs. In the embodiments of the present application, multiple FETs in the same FET group are fabricated on CNTs in different CNT groups. This reduces the number of FETs in the FET group that are simultaneously affected by a single MCNT, thereby reducing the degree to which the logic gate unit's logical function is affected by the MCNTs and improving circuit reliability.

[0009] In a possible implementation, the crystal grain includes a first CNT plane, and the M first CNT groups are all located in the first CNT plane.

[0010] In the embodiment of the present application, multiple CNT groups used to prepare FETs can be located on the same CNT plane, which can reduce the complexity of the manufacturing process and lower the cost.

[0011] In a possible implementation, the grain includes a second CNT plane and a third CNT plane, a first portion of the M first CNT groups is located in the second CNT plane, and a second portion of the M first CNT groups is located in the third CNT plane.

[0012] In the embodiment of the present application, multiple CNT groups used to prepare FETs can be located in different CNT planes, and FETs can be prepared on each CNT plane, which can improve the integration of the number of transistors.

[0013] In a possible implementation, any two of the M first CNT groups include different CNTs.

[0014] In an embodiment of the present application, among the multiple CNT groups used to prepare FETs, different CNT groups are completely isolated from each other, that is, the one or more CNTs included in different CNT groups are completely different. When MCNTs exist in a certain CNT group, the number of FETs affected by the MCNTs can be minimized, the degree to which the logic gate units are affected can be reduced, and the circuit stability can be further improved.

[0015] In one possible implementation, the grain further includes a second logic gate unit and K second CNT groups, each second CNT group includes one or more CNTs, and K is an integer greater than or equal to 1; the second logic gate unit includes multiple second FETs, and the multiple second FETs are prepared on the CNTs of the K second CNT groups; the M first CNT groups and the K second CNT groups are different; the first logic gate unit is used to drive the second logic gate unit, or the second logic gate unit is used to drive the first logic gate unit.

[0016] In an embodiment of the present application, a crystal grain may include a plurality of logic gate units, and these plurality of logic gate units may form a logic gate unit combination to perform more complex logic functions. The FETs of different logic gate units in the logic gate unit combination may be prepared on different CNT groups, thereby reducing the number of logic gate units in the logic gate unit combination that are simultaneously affected by one MCNT, thereby reducing the degree to which the logic gate unit combination is affected and improving circuit stability.

[0017] In one possible implementation, the grain includes at least one CNT plane; the M first CNT groups and the K second CNT groups are all in the same CNT plane, or the M first CNT groups and the K second CNT groups are in different CNT planes.

[0018] In the embodiment of the present application, each logic gate unit in the logic gate unit combination can be prepared on the same CNT plane to reduce process complexity and lower manufacturing cost; or it can be prepared on different CNT planes to increase the integration of the number of transistors.

[0019] In one possible implementation, the second logic gate unit includes multiple second FET groups, each second FET group includes multiple FETs with the same channel type among the multiple second FETs, and the channel types of FETs in different FET groups among the multiple second FET groups are different; the FETs in different FET groups among the multiple second FET groups are prepared on CNTs of different CNT groups among the K second CNT groups, and part or all of the FETs in at least one FET group among the multiple second FET groups are prepared on CNTs of different CNT groups among the K second CNT groups.

[0020] In an embodiment of the present application, for multiple logic gate units in a logic gate unit combination, multiple FETs belonging to the same FET group in each logic gate unit can be prepared separately on CNTs of different CNT groups, thereby reducing the number of FETs in the FET group that are simultaneously affected by one MCNT, thereby reducing the degree to which the logical functions of each logic gate unit are affected by the MCNT, thereby reducing the degree to which the logic gate unit combination is affected, and improving circuit reliability.

[0021] In a second aspect, the present application provides a grain, characterized in that the grain includes a third logic gate unit, a fourth logic gate unit and P CNT groups; the third logic gate unit is used to drive the fourth logic gate unit; the third logic gate unit includes one or more third FETs, and the fourth logic gate unit includes one or more fourth FETs; the one or more third FETs and the one or more fourth FETs are prepared on CNTs of different CNT groups among the P CNT groups.

[0022] In an embodiment of the present application, a crystal grain may include a plurality of logic gate units, and these plurality of logic gate units may form a logic gate unit combination to perform more complex logic functions. The FETs of different logic gate units in the logic gate unit combination may be prepared on different CNT groups, thereby reducing the number of logic gate units in the logic gate unit combination that are simultaneously affected by one MCNT, thereby reducing the degree to which the logic gate unit combination is affected and improving circuit stability.

[0023] In a third aspect, the present application provides a layout design method, characterized in that the method comprises:

[0024] A first logic gate unit and M first CNT groups are determined; the first logic gate unit includes N first FET groups, each of the N first FET groups includes multiple first FETs of the same channel type, and FETs in different FET groups in the N first FET groups have different channel types, where N is an integer greater than or equal to 2; each of the M first CNT groups includes one or more CNTs; and M is an integer greater than or equal to 3.

[0025] The first FETs of the N first FET groups in the first logic gate unit are mapped to the CNTs of the M first CNT groups; wherein, each first FET group corresponds to one or more first CNT groups, and the one or more first CNT groups corresponding to different first FET groups are different, the multiple first FETs in each first FET group are prepared on the CNTs of the one or more first CNT groups corresponding to each first FET group, and the multiple first FETs in at least one first FET group among the N first FET groups are prepared on the CNTs of the corresponding multiple first CNT groups.

[0026] In a possible implementation, the method further includes:

[0027] determining a first CNT plane;

[0028] The M first CNT groups are all mapped to the first CNT plane.

[0029] In a possible implementation, the method further includes:

[0030] determining a second CNT plane and a third CNT plane;

[0031] A first portion of the M first CNT groups is mapped to the second CNT plane, and a second portion of the M first CNT groups is mapped to the third CNT plane.

[0032] In a possible implementation, any two of the M first CNT groups include different CNTs.

[0033] In a possible implementation, the method further includes:

[0034] Determine a second logic gate unit and K second CNT groups; each of the K second CNT groups includes one or more CNTs, K is an integer greater than or equal to 1; the second logic gate unit includes a plurality of second FETs;

[0035] The multiple second FETs in the second logic gate unit are mapped to the CNTs of the K second CNT groups; the M first CNT groups and the K second CNT groups are different; the first logic gate unit is used to drive the second logic gate unit, or the second logic gate unit is used to drive the first logic gate unit.

[0036] In a possible implementation, the M first CNT groups and the K second CNT groups are all located in the same CNT plane, or the M first CNT groups and the K second CNT groups are located in different CNT planes.

[0037] In one possible implementation, the second logic gate unit includes a plurality of second FET groups, each second FET group includes a plurality of FETs having the same channel type among the plurality of second FETs, and the channel types of FETs in different FET groups among the plurality of second FET groups are different;

[0038] Mapping the plurality of second FETs in the second logic gate unit to the CNTs of the K second CNT groups includes:

[0039] Mapping FETs of different FET groups in the plurality of second FET groups to CNTs of different CNT groups in the K second CNT groups, and mapping part or all of the FETs in at least one FET group in the plurality of second FET groups to CNTs of different CNT groups in the K second CNT groups.

[0040] In a fourth aspect, the present application provides a layout design method, characterized in that the method includes:

[0041] Determine a third logic gate unit, a fourth logic gate unit, and P CNT groups; the third logic gate unit is used to drive the fourth logic gate unit; the third logic gate unit includes one or more third FETs, and the fourth logic gate unit includes one or more fourth FETs;

[0042] The one or more third FETs and the one or more fourth FETs are mapped to CNTs of different CNT groups among the P CNT groups.

[0043] In a fifth aspect, the present application provides a semiconductor chip, which includes the grain provided in any possible implementation of the first aspect or the second aspect.

[0044] In a sixth aspect, the present application provides a layout design device, which includes a module or unit for executing the method provided in any possible implementation of the third aspect or the fourth aspect.

[0045] In a seventh aspect, the present application provides a layout design device, which includes a processor, and the processor is used to implement the method provided by any possible implementation of the third aspect or the fourth aspect through a logic circuit or execution code instructions.

[0046] In an eighth aspect, the present application provides a computer-readable storage medium having program instructions stored thereon, which, when executed, enables the method described in any possible implementation of the third or fourth aspect to be executed.

[0047] In a ninth aspect, the present application provides a program product comprising program instructions, which, when executed, enables the method described in any possible implementation of the third or fourth aspect to be executed.

[0048] In the tenth aspect, the present application provides an electronic device, which includes a grain provided by any possible implementation of the first or second aspect above; the electronic device also includes a memory, which is used to store program instructions and data necessary for the electronic device to run; the electronic device may also include a communication interface for the electronic device to communicate with other devices or communication networks.

[0049] In an eleventh aspect, the present application provides an electronic device having the function of implementing any one of the layout design methods described in the third or fourth aspects. This function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions.

[0050] In a twelfth aspect, the present application provides a chip system, comprising a die provided in any possible implementation of the first or second aspects. Alternatively, in one possible design, the chip system includes a processor configured to implement the method described in any possible implementation of the third or fourth aspects. The chip system may consist of a chip alone, or may include a chip and other discrete components.

[0051] The technical effects achieved in the above-mentioned aspects can be referred to each other or to the beneficial effects in the method embodiments shown below, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0053] Figure 1 This is a schematic structural diagram of a carbon nanotube field-effect transistor provided in an embodiment of the present application;

[0054] Figure 2 is a schematic diagram of a grain structure provided in an embodiment of the present application;

[0055] Figure 3 is a cross-sectional schematic diagram of a grain structure provided in an embodiment of the present application;

[0056] Figure 4 is a schematic diagram of another grain structure provided in an embodiment of the present application;

[0057] Figure 5 This is a schematic diagram of a nand2 provided in an embodiment of the present application;

[0058] Figure 6 is a schematic diagram of a nand2 signal response characteristic provided in an embodiment of the present application;

[0059] Figure 7 This is a schematic diagram of a die structure including nand2 provided in an embodiment of the present application;

[0060] Figure 8 is a schematic diagram of another die structure including nand2 provided in an embodiment of the present application;

[0061] Figure 9 This is another schematic diagram of a die structure including nand2 provided in an embodiment of the present application;

[0062] Figure 10 Schematic diagram of a die structure including a combination of logic gate units provided in an embodiment of the present application;

[0063] Figure 11 is a schematic diagram of another die structure including a combination of logic gate units provided in an embodiment of the present application;

[0064] Figure 12a-12c Schematic diagram of several grain structures including nor2 provided in the embodiments of the present application;

[0065] Figure 13a-Figure 13c This is a schematic diagram of several nand3-containing grain structures provided in the embodiments of the present application;

[0066] Figure 14a-Figure 14c Schematic diagram of several nand4-containing grain structures provided in the embodiments of the present application;

[0067] Figure 15a-Figure 15c Schematic diagram of several grain structures including MUX2 provided in the embodiments of the present application;

[0068] Figure 16a-Figure 16c Schematic diagram of several grain structures including AOI22 provided in the embodiments of the present application;

[0069] Figure 17 This is a schematic diagram of a grain structure including a BUF provided in an embodiment of the present application;

[0070] Figure 18 This is a flow chart of a layout design method provided in an embodiment of the present application;

[0071] Figure 19 It is a flow chart of another layout design method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0072] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application.

[0073] In the description of this application, words such as "first" and "second" are only used to distinguish different objects and do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily mean different. For example, the first message and the second message are only used to distinguish different information and do not limit their order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0074] In the description of this application, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this article is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, "at least one (item)", "the following one (item) or more (items)" or similar expressions refer to any combination of these items, including any combination of single or plural items (items). For example, at least one item (item) of a, b, or c can mean: a, b, c; a and b; a and c; b and c; or a, b, and c. Among them, a, b, and c can be single or multiple.

[0075] In the description of this application, words such as "exemplary," "exemplarily," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary," "for example," or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0076] It can be understood that in the description of this application, "when", "if" and "if" all mean that the device will perform corresponding processing under certain objective circumstances, and do not limit the time. It does not require that the device must perform a judgment action when it is implemented, nor does it mean that there are other limitations.

[0077] The term "simultaneously" in this application may be understood as at the same time point, within a period of time, or within the same cycle, and may be understood in conjunction with the context.

[0078] Elements used in the singular herein are intended to mean "one or more" rather than "one and only one" unless specifically stated otherwise.

[0079] It is understood that in each embodiment of the present application, "A and B correspond" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B based solely on A, and B can also be determined based on A and / or other information.

[0080] In order to better understand the technical solutions of the embodiments of the present application, several terms or nouns related to the present application are briefly introduced below to facilitate understanding by those skilled in the art.

[0081] 1. Wafer and Die

[0082] A wafer is a silicon wafer used to make silicon semiconductor circuits. The starting material is silicon. High-purity polycrystalline silicon is dissolved, doped with silicon crystal seeds, and then slowly pulled out to form a cylindrical single crystal. This single crystal is then ground, polished, and sliced ​​to form a silicon wafer, or simply a wafer.

[0083] A die is a small piece cut from a wafer using a laser or a cutter. Each piece can have an independent function, and different functions can be achieved through different combinations of field-effect transistors. After these dies complete their functions and testing processes, they can be packaged to form the chip we are familiar with. The present application provides a die structure that can reduce the impact of metallic carbon nanotubes on the logical function of the logic gate unit and improve circuit reliability by optimizing the layout design of multiple carbon nanotube field-effect transistors (CNFETs) in the logic gate unit.

[0084] 2. Carbon Nanotube Field-Effect Transistor (CNTFET)

[0085] A carbon nanotube field effect transistor (CNTFET) is a type of field effect transistor (FET) that uses semiconducting carbon nanotubes (CNTs) as a channel material between two metal electrodes to form a contact between the source and drain. That is, a field effect transistor (FET) made from carbon nanotubes (CNTs) can be called a carbon nanotube field effect transistor (CNTFET). For example, see Figure 1 , Figure 1This is a schematic diagram of the structure of a carbon nanotube field-effect transistor provided in an embodiment of the present application. The surface of a silicon wafer or silicon grain includes many carbon nanotubes that are generally parallel to each other, such as S carbon nanotubes (for ease of understanding, they can be distinguished by serial numbers 1, 2, 3, ..., S-1, S), and tens of thousands of carbon nanotube field-effect transistors can be prepared on these carbon nanotubes. For example, the gate of the field-effect transistor can be made of polysilicon (Poly), the source and drain of the field-effect transistor can be made of metal materials, and these carbon nanotubes can be used as the channel material of the field-effect transistor to prepare a carbon nanotube field-effect transistor. There can be many carbon nanotube field-effect transistors on the surface of a wafer or grain. Different combinations of these carbon nanotube field-effect transistors can obtain different logic gate units, which can perform different logical functions.

[0086] 3. Logic Gate Unit, Logic Gate Circuit

[0087] Logic gates are the most basic arithmetic units in circuit design, used to perform Boolean logic operations and control signal processing. Logic gates can consist of multiple field-effect transistors, and different combinations of these transistors can implement different logical functions. Logic gates have specific inputs and outputs, generating output signals based on the logical state of the input signal. Common basic logic gates include AND gates, OR gates, NOT gates, and XOR gates. A logic gate circuit can include one or more logic gates.

[0088] First, the technical problem to be specifically solved by this application is analyzed and proposed. Currently, in order to solve the problem of reduced SNM of logic gate units / circuits caused by metallic carbon nanotubes (MCNTs) in carbon nanotubes, thermal ablation is generally used in the prior art to remove MCNTs. Specifically, a layer of organic film is first evaporated on the carbon nanotube substrate, and then the carbon nanotubes are heated using microwaves or by applying current to the source and drain ends. Due to the high heat generation of metallic carbon nanotubes (MCNTs), the organic film at the MCNTs will melt after heating, exposing the MCNTs. Finally, the exposed MCNTs are etched away, thereby reducing the impact of the MCNTs on the logic gate units / circuits.

[0089] The thermal ablation method for removing MCNTs has the following disadvantages:

[0090] Different metallic carbon nanotubes typically generate different heat outputs, making it difficult to remove metallic carbon nanotubes of varying diameters using a fixed microwave frequency. This makes MCNT removal costly. Furthermore, as the proportion of MCNTs in a substrate decreases (e.g., to 0.0001%), direct identification of their location becomes difficult using this method, requiring significant time and resources to achieve a reasonable level of effectiveness. Furthermore, once an MCNT is present, it can affect the FETs located at that location, thereby impacting the logic function of the corresponding logic gates / circuits.

[0091] To this end, the present application proposes a crystal grain, a chip and related equipment. By optimizing the design of multiple carbon nanotube field-effect transistors (CNFETs) in multiple CNFET groups in a logic gate unit on the layout, multiple CNFETs in the same CNFET group are prepared on different groups of carbon nanotubes, thereby reducing the number of CNFETs in the CNFET group that are simultaneously affected by a metallic carbon nanotube, thereby reducing the degree to which the logical function of the logic gate unit is affected by the metallic carbon nanotube and improving circuit reliability.

[0092] In addition, in the present application, by optimizing the layout design of multiple logic gate units in the logic gate unit combination, the multiple logic gate units in the logic gate unit combination can be prepared on different groups of carbon nanotubes, thereby reducing the number of logic gate units in these multiple logic gate units that are simultaneously affected by one metallic carbon nanotube, thereby reducing the degree to which the logical function of the logic gate unit combination is affected by the metallic carbon nanotube and improving circuit reliability.

[0093] For ease of understanding, the technical solution provided in this application will be described below with reference to more drawings.

[0094] In this application, unless otherwise specified, the same or similar parts between the various embodiments or implementation methods can refer to each other. In the various embodiments in this application, and the various implementation methods / implementation methods / implementation methods in each embodiment, if there is no special explanation and logical conflict, the terms and / or descriptions between different embodiments and the various implementation methods / implementation methods / implementation methods in each embodiment are consistent and can be referenced to each other. The technical features in different embodiments and the various implementation methods / implementation methods / implementation methods in each embodiment can be combined to form new embodiments, implementation methods, implementation methods, or implementation methods according to their inherent logical relationships. The implementation methods of this application described below do not constitute a limitation on the scope of protection of this application.

[0095] The following is a brief description of the grain structure provided in the embodiment of the present application. Figure 2 , Figure 2is a schematic diagram of a grain structure provided by an embodiment of the present application, wherein the grain may include a first logic gate unit and M first carbon nanotube (CNT) groups; wherein the first logic gate unit includes N first field effect transistor (FET) groups, each of the N first FET groups includes multiple first FETs of the same channel type, and the FETs of different FET groups in the N first FET groups have different channel types, where N is an integer greater than or equal to 2;

[0096] Each of the M first CNT groups includes one or more CNTs; at least one CNT in any two of the M first CNT groups does not belong to the two first CNT groups at the same time; M is an integer greater than or equal to 3;

[0097] The FETs of the N first FET groups are fabricated on the CNTs of the M first CNT groups; wherein, each first FET group corresponds to one or more first CNT groups, and the one or more first CNT groups corresponding to different first FET groups are different, the multiple first FETs in each first FET group are fabricated on the CNTs of the one or more first CNT groups corresponding to each first FET group, and the multiple first FETs in at least one first FET group among the N first FET groups are fabricated on the CNTs of the corresponding multiple first CNT groups. In other words, the FETs of different FET groups among the N first FET groups are fabricated on the CNTs of different CNT groups among the M first CNT groups, and some or all of the FETs in at least one FET group among the N first FET groups are fabricated on the CNTs of different CNT groups among the M first CNT groups.

[0098] For example, the first logic gate unit in the die may include two first FET groups (FET group 1 and FET group 2), that is, N is 2, FET group 1 includes multiple FETs of channel type (such as P-channel type) (corresponding to Figure 2 The field effect transistors a, b, ..., x in the FET group 2 include a plurality of FETs of a channel type (such as an N-channel type) (corresponding to Figure 2 The field effect transistors A, B, ..., X in the crystal grain are configured such that the channel type of the FETs in FET group 1 is different from the channel type of the FETs in FET group 2. The M first CNT groups in the crystal grain may include CNT group 1 (e.g., including CNT3 and CNT4), CNT group 2 (e.g., including CNT5 and CNT6), CNT group 3 (e.g., including CNT7 and CNT8), and CNT group 4 (e.g., including CNT9 and CNT10).

[0099] Wherein, the FETs in FET group 1 and FET group 2 are respectively prepared on CNTs of different CNT groups. For example, the FETs (such as a, b, ..., x) in FET group 1 are prepared on CNTs of CNT group 1, that is, FET group 1 corresponds to CNT group 1; and the FETs in FET group 2 can be prepared on CNTs of other CNT groups (such as CNT group 2, CNT group 3 and CNT group 4) other than CNT group 1, that is, FET group 2 corresponds to CNT group 2, CNT group 3 and CNT group 4; the FETs of different FET groups are prepared on CNTs of different CNT groups, that is, one or more first CNT groups corresponding to different first FET groups are different. In addition, multiple FETs of at least one FET group in FET group 1 and FET group 2 are prepared on CNTs of different CNT groups. Exemplarily, all FETs in FET group 1 (such as a, b, ..., x) are prepared on the CNT of CNT group 1, while some FETs in FET group 2 (such as A, B) are prepared on the CNT of CNT group 2, some FETs are prepared on the CNT of CNT group 3, and some FETs (such as X) are prepared on the CNT of CNT group 4. That is to say, multiple first FETs in at least one first FET group among the N first FET groups are prepared on the CNTs of corresponding multiple first CNT groups.

[0100] At this time, if CNT3 is a metallic carbon nanotube (MCNT), all FETs in FET group 1 (such as a, b, ..., x) are affected by MCNT, and if CNT9 is MCNT, only a part of FETs in FET group 2 (such as X) are affected by MCNT. Different from the solution in the prior art in which the FETs of any FET group of the logic gate unit are all prepared on the CNTs of the same CNT group (that is, all FET groups of the logic gate unit in the prior art are designed in accordance with the aforementioned method in which all FETs of FET group 1 are prepared on the CNTs of CNT group 1), the grain structure provided in the embodiment of the present application prepares multiple FETs in the same FET group on CNTs of different CNT groups, which can reduce the number of FETs in the FET group that are simultaneously affected by one MCNT, thereby reducing the degree to which the logical function of the logic gate unit is affected by the MCNT and improving circuit reliability.

[0101] Optionally, some or all of the FETs in each of the N first FET groups are fabricated on CNTs in different CNT groups in the M first CNT groups. That is, while the FETs in FET group 2 are fabricated on CNTs in different CNT groups, the FETs (e.g., a, b, ..., x) in FET group 1 can also be fabricated on CNTs in different CNT groups.

[0102] Optionally, the number of FETs included in different FET groups in the N first FET groups may be the same or different. For example, FET group 1 may include three P-channel FETs, and FET group 2 may include three N-channel FETs; or, FET group 1 may include four P-channel FETs, and FET group 2 may include five N-channel FETs. This is not specifically limited here.

[0103] In one possible implementation, the grain includes a first CNT plane, and the M first CNT groups are all located in the first CNT plane. In other words, CNT group 1, CNT group 2, CNT group 3, and CNT group 4 are located in the same CNT plane, and each FET in FET group 1 and FET group 2 can be fabricated on the same CNT plane.

[0104] In one possible implementation, the grain includes a second CNT plane and a third CNT plane, the first portion of the CNT groups in the M first CNT groups is in the second CNT plane, and the second portion of the CNT groups in the M first CNT groups is in the third CNT plane. In other words, the grain may include multiple CNT planes, and the CNT group 1, CNT group 2, CNT group 3, and CNT group 4 may be in different CNT planes. Then, the FETs in FET group 1 and FET group 2 may be prepared on different CNT planes, and then connected by metal wires or through-holes. For example, see Figure 3 , Figure 3 is a schematic cross-sectional view of a grain structure provided by an embodiment of the present application. The grain may include a second CNT plane and a third CNT plane. Each of the two CNT planes may include multiple CNTs. The FETs in FET group 1 (e.g., a, b, ..., x) may be fabricated on CNTs from different CNT groups in the second CNT plane, and the FETs in FET group 2 (e.g., A, B, ..., X) may be fabricated on CNTs from different CNT groups in the second CNT plane. Optionally, the number of CNTs included in the second CNT plane and the number of CNTs included in the third CNT plane may be the same or different, and are not specifically limited herein. It should be noted that when CNTs with the same sequence number exist in different CNT planes, these two CNTs may be considered different CNTs. For example, a CNT with sequence number 1 in the second CNT plane and a CNT with sequence number 1 in the third CNT plane are different CNTs, even if they have the same sequence number. Similarly, CNT groups with the same sequence number in different CNT planes are considered different CNT groups.

[0105] Optionally, at least one CNT in any two of the M first CNT groups does not belong to both of the two first CNT groups. For example, one of the two first CNT groups may include CNTs numbered 1, 2, and 3, while the other CNT group may include CNTs numbered 1, 2, 3, and 4, with the CNT numbered 4 not belonging to both of the two CNT groups. Assuming two FETs are fabricated on CNTs in each of these two CNT groups, if the CNTs numbered 1, 2, or 3 are MCNTs, both FETs are affected by the MCNTs, significantly impacting the logic function of the logic gate unit derived from these two FETs. If the CNT numbered 4 is an MCNT, only one of the two FETs is affected by the MCNTs, significantly impacting the logic function of the logic gate unit derived from these two FETs.

[0106] For another example, one of the two aforementioned first CNT groups may include CNTs numbered 1, 2, and 3, while the other CNT group may include CNTs numbered 2, 3, and 4. CNTs numbered 1 and 4 do not belong to both CNTs. Assume that two FETs are fabricated on CNTs in each of these two CNT groups. If CNT numbered 2 or 3 is an MCNT, both FETs are affected by the MCNT, significantly impacting the logic function of the logic gate unit based on these two FETs. If CNT numbered 1 or 4 is an MCNT, only one of the two FETs is affected by the MCNT, significantly impacting the logic function of the logic gate unit based on these two FETs.

[0107] Furthermore, any two of the M first CNT groups contain different CNTs. For example, one of the two first CNT groups may include CNTs numbered 1, 2, and 3, while the other may include CNTs numbered 4, 5, and 6. CNTs numbered 1, 2, 3, 4, 5, and 6 do not belong to both groups. The different CNT groups are completely isolated from each other. When a CNT group contains an MCNT, the number of FETs affected by the MCNT can be minimized, further minimizing the impact on the logic function of the logic gate unit.

[0108] In one possible implementation, the grain further includes a second logic gate unit and K second CNT groups, each second CNT group includes one or more CNTs, K is an integer greater than or equal to 1; the second logic gate unit includes a plurality of second FETs, and the plurality of second FETs are prepared on the CNTs of the K second CNT groups; the M first CNT groups and the K second CNT groups are different; the first logic gate unit is used to drive the second logic gate unit, or the second logic gate unit is used to drive the first logic gate unit. In other words, the above-mentioned grain may include a plurality of logic gate units, and a logic gate unit combination may be obtained based on these multiple logic gate units. Within one clock cycle, the multiple logic gate units that have the characteristics of the upper-level logic gate unit driving the lower-level logic gate unit and complete the combinational logic operation may be called a logic gate unit combination (or logic gate circuit). Figure 4 As shown, the M first CNT groups and the K second CNT groups are different from each other. In the embodiment of the present application, multiple logic gate units in the logic gate unit combination can be prepared on carbon nanotubes in different groups. For example, the FET of the first logic gate unit is prepared on the CNTs of the M first CNT group, and the FET of the second logic gate unit is prepared on the CNTs of the K second CNT group. This reduces the number of logic gate units in the multiple logic gate units that are simultaneously affected by one metallic carbon nanotube, thereby reducing the degree to which the logical function of the logic gate unit combination is affected by the metallic carbon nanotube and improving circuit reliability.

[0109] Optionally, the crystal grain includes at least one CNT plane; the M first CNT groups and the K second CNT groups are all in the same CNT plane, or the M first CNT groups and the K second CNT groups are in different CNT planes. In other words, the first logic gate unit and the second logic gate unit can be prepared on CNTs in the same CNT plane or on CNTs in different CNT planes, as shown in FIG. Figure 3 The relevant description of preparing different FET groups on CNTs in different CNT planes will not be repeated here.

[0110] Further optionally, the second logic gate unit may include a plurality of second FET groups, each second FET group includes a plurality of FETs of the same channel type among the plurality of second FETs, and the channel types of the FETs of different FET groups among the plurality of second FET groups are different; the FETs of different FET groups among the plurality of second FET groups are prepared on the CNTs of different CNT groups among the K second CNT groups, and part or all of the FETs in at least one FET group among the plurality of second FET groups are prepared on the CNTs of different CNT groups among the K second CNT groups. In simple terms, the preparation method of each FET group in the second logic gate unit on the CNTs of the K second CNT groups can refer to the preparation method of each FET group in the first logic gate unit on the CNTs of the M first CNT groups (such as Figure 2 ), which will not be expanded here.

[0111] For ease of understanding, the embodiment of the present application will take a logic gate unit as a NAND gate 2 (nand2) as an example to exemplarily illustrate the grain structure provided by the embodiment of the present application.

[0112] The following is a brief description of the NAND gate 2 in the embodiment of the present application. A NAND gate 2 (nand2) generally includes four field effect transistors (FETs), two of which are P-channel type and the other two are N-channel type. In one clock cycle, the combination of these four FETs has the logic function of nand2. Figure 5 As shown, Figure 5 The figure describes four logic gate units (such as units 1-4) and their corresponding equivalent circuit diagrams. Taking unit 1 in the upper left corner and unit 4 in the lower right corner as examples, two P-channel FETs are connected in parallel between VDD (power supply voltage) and VSS (circuit common ground voltage, i.e., ground point), and two N-channel FETs are connected in series between the parallel branch of the two P-channel FETs and VSS, so that the circuit parts of unit 1 and unit 4 have the following structure: Figure 6 The signal response characteristics shown are that, within one clock cycle, when the potential at either or both of the input terminals is not high level 1, the potential at the output terminal is high level 1.

[0113] like Figure 6As shown, for unit 1, when the potential of input terminal A1 is 0 and the potential of input terminal B1 is 0, the output of output terminal ZN1 is a high potential 1; for unit 4, when the potential of input terminal A4 is 1 and the potential of input terminal B4 is 0, the output of output terminal ZN4 is a high potential 1. It should be noted that the signal combinations of the input terminals and output terminals of unit 1 and unit 4 may include but are not limited to the above signal combinations. For example, the potentials of the two input terminals may be 0 and 1 respectively, while the potential of the output terminal is 1, or the potentials of the two input terminals may both be 1, while the potential of the output terminal is 0. As long as unit 1 and unit 4 have the ability to complete the nand2 logic function, the circuit part of unit 1 and unit 4 can be called nand2. Understandably, Figure 5 When the other units (unit 2 and unit 3) input the same signal as unit 1 and unit 4, they also have the same Figure 6 The signal response characteristics shown, that is, unit 2 and unit 3 also have the same nand2 logic function as unit 1 and unit 4, the circuit part of unit 2 and unit 3 can also be called nand2.

[0114] It should be noted that, in addition to the above-mentioned NAND gate 2 (nand2), the logic gate unit in this application can also be an AND gate, an OR gate, a NOT gate, a NOR gate, an AND-NOR gate, nor2, nand3 (NAND gate 3, which can be used as a non-volatile flash memory), nand4, MUX2 (which can be used as a multiplexer), AOI22 (which can be used as an inverter) and other types of logic gates. As long as the circuit part of the logic gate unit has the signal response characteristics corresponding to the above-mentioned types of logic gates, no specific limitation is made here.

[0115] In one possible implementation, the crystal grain provided in the embodiment of the present application may include a NAND gate 2 and multiple CNT groups, and the four field effect transistors (FETs) included in the NAND gate 2 (nand2) may be divided into two FET groups, one FET group (hereinafter referred to as FET group-P for ease of distinction) including two P-channel type FETs, and the other FET group including two N-channel type FETs (hereinafter referred to as FET group-N for ease of distinction). The FETs of the two FET groups in the NAND gate 2 are respectively prepared on CNTs of different CNT groups in the multiple CNT groups, that is, the FETs in FET group-P and the FETs in FET group-N are prepared on CNTs of different CNT groups; and, in the two FET groups of the NAND gate 2, multiple FETs in at least one FET group are prepared on CNTs of different CNT groups, that is, two FETs in FET group-P are prepared on CNTs of different CNT groups, and / or, two FETs in FET group-N are prepared on CNTs of different CNT groups.

[0116] For example, see Figure 7 , Figure 7This is a schematic diagram of a crystal structure including nand2 provided in an embodiment of the present application. Figure 7 The conventional nand2 cell layout design (method 1) and the optimized nand2 cell layout design (method 2) of the present application are shown in FIG. In the conventional design method, the two FETs in the FET group-P are prepared in the same CNT group (e.g. Figure 7 On the CNT of CNT group 1 in method 1, the two FETs in FET group-N are also prepared on the same CNT group (such as Figure 7 In the first method, the two FETs in the same FET group are connected along the length direction of the CNT. In the design method optimized by the present application, multiple FETs in at least one FET group in the nand2 unit are prepared on CNTs in different CNT groups, so that two FETs in one FET group that are originally connected along the length direction of the carbon tube (such as Figure 7 For example, one of the four FETs of the nand2 unit can be prepared on four CNT groups, that is, one FET is prepared on the CNT of one CNT group, thereby reducing the number of FETs affected along the length direction of the MCNT, thereby reducing the degree to which the nand2 logic function is affected. Exemplarily, the nand2 unit optimized in the embodiment of the present application can be divided into two parts on the same CNT plane, distributed between two VDD lines and one VSS line, and the two parts are connected by a metal connection line (M2). The optimized nand2 unit (such as Figure 7 Method 2) in the above method realizes the transformation from single height to double height.

[0117] In the above Figure 7 In the second approach, in the two FET groups of nand2, the two FETs in each FET group are respectively prepared on CNTs of different CNT groups, that is, one FET is prepared on a CNT of one CNT group, which can be called a "1-1-1-1" design. Figure 7 In addition to adopting the "1-1-1-1" design, the optimization of the second method can also adopt the "2-1-1" design, that is, in the two FET groups of nand2, the two FETs of one FET group are prepared on the CNTs of the same CNT group, and the two FETs of the other FET group are prepared on the CNTs of different CNT groups. As to whether the two FETs of FET group-P are prepared on the CNTs of the same CNT group or the two FETs of FET group-N are prepared on the CNTs of the same CNT group, there is no specific limitation here.

[0118] The optimization principle of the above scheme can be described as follows: the probability that a CNT is a MCNT is P(MCNT=1)=P0, the lower the P0, the better. Assuming Figure 7 A metallic carbon nanotube (ie Figure 7 The m-CNT in the CNT group affects the two P-channel FETs prepared along the length of the CNT. The impact on the nand2 logic function can be evaluated by the SNM value (such as SNM0). The higher the SNM0 value, the better. Since both P-channel FETs in the FET group-P are affected, the nand2 logic function is more affected and the SNM0 value is lower. Figure 7 In the optimization of the second method, two P-channel FETs in the FET group-P are prepared in different CNT groups (such as Figure 7 On the CNTs of CNT group 1 and CNT group 4 in method 2, two N-channel FETs in FET group-N are also prepared in different CNT groups (such as Figure 7 In Method 2, the area of ​​nand2 increases to nearly 1.5 times on the CNTs of CNT Group 2 and CNT Group 3, but one MCNT only affects one FET. Compared with the situation in Method 1 where one MCNT affects two FETs at the same time, the impact on the nand2 logic function is SNM0. Therefore, in Method 2, in order for the impact on the nand2 logic function to reach SNM0, at least two CNTs need to have MCNTs ( Figure 7 (not shown), the corresponding P(MCNT=2)=P0^2, which is much smaller than P0 (and the higher the purity of the CNT semiconductor (that is, the lower the value of P0), the higher the design benefit of the second method). In summary, this design prepares multiple CNFETs in the same CNFET group on different groups of carbon nanotubes, reducing the number of CNFETs in the CNFET group that are simultaneously affected by one metallic carbon nanotube, thereby reducing the degree to which the logical function of the logic gate unit is affected by the metallic carbon nanotube and improving circuit reliability.

[0119] In the above Figure 7 In the second method, the FETs of the two FET groups in nand2 can be prepared on CNTs of different CNT groups in the same CNT plane. In another possible implementation method, the FETs of the two FET groups in nand2 can be prepared on CNTs of different CNT groups in different CNT planes. Figure 8 , Figure 8 This is another schematic diagram of a die structure including nand2 provided in an embodiment of the present application. Figure 8 The figure shows the traditional nand2 unit layout design (method 1) and another nand2 unit layout design (method 2) optimized by the present application. Figure 8 The method shown is Figure 7 The method shown is the same as that shown in FIG1 and will not be described in detail here.

[0120] In another design optimized by the present application, multiple FETs in at least one FET group in the nand2 unit are prepared on CNTs of different CNT groups, and different CNT groups can be located on different CNT planes, such as Figure 8 The bottom tier (corresponding to the second CNT plane) and the top tier (corresponding to the third CNT plane) shown in FIG are used to realize the two FETs (such as Figure 7 or Figure 8 Method 1) in the above is used to disassociate. For example, Figure 8 In the second method, one FET in FET group-P can be prepared on the CNT of CNT group 1 in the bottom tier, and another FET can be prepared on the CNT of CNT group 1 in the top tier. One FET in FET group-N can be prepared on the CNT of CNT group 2 in the bottom tier, and another FET can be prepared on the CNT of CNT group 2 in the top tier, so that one of the four FETs of the nand2 unit can be prepared on four CNT groups, that is, one FET is prepared on the CNT of one CNT group, thereby reducing the number of FETs affected along the length direction of the MCNT, thereby reducing the degree to which the nand2 logic function is affected. For example, the optimized nand2 unit in the embodiment of the present application can be divided into two parts on the two CNT planes, distributed between two VDD lines and two VSS lines, and the two parts are connected by a metal connection line (M2). The optimized nand2 unit (such as Figure 8 Method 2) in the above method realizes the transformation from single-height to dual-stack.

[0121] For the optimization of FET layout design in nand2 by different CNT planes, in addition to the above Figure 8 In addition to the optimization scheme shown in the second method where the FETs of different FET groups are in the same CNT plane and the multiple FETs of the same FET group are in different CNT planes, the optimization scheme can also be performed by placing the FETs of different FET groups in different CNT planes and the multiple FETs of the same FET group in the same CNT plane. Figure 9 , Figure 9 This is another schematic diagram of a chip structure including nand2 provided in an embodiment of the present application. Figure 9In the second method, both FETs in FET group-P can be prepared on the CNT in the bottom tier, wherein one FET is prepared on the CNT of CNT group 1 and the other FET is prepared on the CNT of CNT group 2, and both FETs in FET group-N are prepared on the top CNT, so that one of the four FETs of the nand2 unit is prepared on each of the four CNT groups, that is, one FET is prepared on the CNT of one CNT group.

[0122] In the above, the crystal grain provided by the present application includes a single nand2 unit as an example for explanation. In addition to including the above-mentioned nand2 unit, the crystal grain provided by the embodiment of the present application can also include logic gate units (such as the aforementioned various logic gate units) that implement other logic functions. The multiple logic gate units included in the above-mentioned crystal grain can form a logic gate unit combination (which can be called a logic gate circuit) to complete more complex logic functions. The multiple logic gate units in the logic gate unit combination have the characteristic that within one clock cycle, the upper-level logic gate unit drives the lower-level logic gate unit to complete the combinational logic operation.

[0123] In one possible implementation, among the multiple logic gate units of the logic gate unit combination, the FETs of different logic gate units can be fabricated on CNTs of different CNT groups. For ease of understanding, the following is a brief description using two nand2 units included in the logic gate unit combination as an example. Figure 10 , Figure 10 is a schematic diagram of a die structure including a combination of logic gate units provided in an embodiment of the present application. Figure 10 The nand2 unit combination layout design before optimization and the nand2 unit combination layout design after optimization are shown in FIG. Regarding the nand2 unit combination before optimization, within one clock cycle, Figure 10 In the four nand2s shown, unit 1 is used as the nand2 of the previous stage, and unit 2 is used as the nand2 of the next stage. The output ZN1 of unit 1 drives the input A2 of unit 2. Finally, the nand2 unit combination outputs the electrical signal ZN2, and has the following characteristics: Figure 10 For example, for the nand2 unit combination (unit 1 and unit 2), within one clock cycle, when the potential of the input terminal A1 of unit 1 is 0 and the potential of the input terminal B1 is 0, the output of the output terminal ZN1 is a high potential 1, and the output of the output terminal ZN1 serves as the driving (driving) of the next level unit (unit 2), and the input terminal A2 of unit 2 serves as loading, and the output of the output terminal ZN1 of unit 1 is used as input, and when the potential of the input terminal B2 is 0, the output of ZN2 is a high potential 1. It can be understood that the signal combination of the input and output terminals of the nand2 unit combination may include but is not limited to the above signal combination, and reference may be made to the above Figure 6 The relevant description will not be expanded here.

[0124] like Figure 10 As shown, in the nand2 unit combination before optimization, the FETs in unit 1 and unit 2 are both prepared on the CNTs on CNT group 1 and CNT group 2. If there are metallic carbon nanotubes (MCNTs) in CNT group 1 or CNT group 2, for example, the third CNT in CNT group 1 is an MCNT, the two P-channel FETs in unit 1 and the two P-channel FETs in unit 2 are both affected by the MCNTs, then the logical functions of unit 1 and unit 2 will be affected, and the nand2 unit combination will be more affected.

[0125] For the optimized nand2 unit combination, within one clock cycle, Figure 10 In the four nand2s shown, unit 1 is used as the nand2 of the previous stage, unit 3 is used as the nand2 of the next stage, the output ZN1 of unit 1 drives the input A3 of unit 3, and finally the nand2 unit combination outputs the electrical signal ZN3, and has the following characteristics: Figure 10 For example, for a nand2 unit combination (unit 1 and unit 3), within a clock cycle, when the potential of input terminal A1 of unit 1 is 0 and the potential of input terminal B1 is 0, the output of output terminal ZN1 is a high potential 1. The output of output terminal ZN1 drives the next-level unit (unit 3). Input terminal A3 of unit 3 acts as a loading device, taking the output of output terminal ZN1 of unit 1 as input. When the potential of input terminal B3 is 0, the output of ZN3 is a high potential 1.

[0126] like Figure 10 As shown, in the optimized nand2 cell combination, the FETs in cell 1 (corresponding to the third logic gate cell) and cell 3 (corresponding to the fourth logic gate cell) are fabricated on CNTs from different CNT groups within the multiple CNT groups (corresponding to P CNT groups). For example, the FET in cell 1 is fabricated on CNTs from CNT groups 1 and 2 (corresponding to some of the P CNT groups), while the FET in cell 3 is fabricated on CNTs from CNT groups 3 and 4 (corresponding to some of the P CNT groups). If metallic carbon nanotubes (MCNTs) exist in CNT group 1 or CNT group 2—for example, if the third CNT in CNT group 1 is an MCNT—only the two P-channel FETs in cell 1 are affected, while the FETs in cell 3 are unaffected by the MCNT. Consequently, the impact on the nand2 cell combination is less than that of the pre-optimized design.

[0127] Optionally, the above Figure 10One or more logic gate units in the logic gate unit combination (such as nand2 unit combination) can also refer to Figure 7 In the layout design shown, the FETs of different FET groups in the logic gate unit are fabricated on CNTs of different CNT groups, and the multiple FETs of at least one FET group in the multiple FET groups are fabricated on CNTs of different CNT groups, thereby reducing the number of FETs affected by the MCNT, thereby reducing the degree of impact on the logic gate unit, and further reducing the impact on the logic gate unit combination. Figure 11 , Figure 11 This is another schematic diagram of a die structure including a logic gate unit combination provided by an embodiment of the present application. The logic gate unit combination includes unit 1 and unit 2 (taking the two units as nand2 as an example), and unit 1 is used to drive unit 2. For unit 1, the FETs in FET group-P and the FETs in FET group-N are prepared on CNTs in different CNT groups; and the two FETs in FET group-P are prepared in different CNT groups (such as Figure 11 On the CNTs of CNT group 1 and CNT group 4), and, two FETs in FET group-N were prepared on different CNT groups (such as Figure 11 The layout design of unit 2 is similar to that of unit 1. The two FETs in FET group-P are prepared on different CNT groups (such as Figure 11 On the CNTs of CNT group 5 and CNT group 8), and, two FETs in FET group-N were prepared on different CNT groups (such as Figure 11 On the CNTs of CNT group 6 and CNT group 7).

[0128] Optionally, the above Figure 10 One or more logic gate units in the logic gate unit combination (such as nand2 unit combination) can also be distributed on CNTs of different CNT groups in different CNT planes, as described above. Figure 8 or Figure 9 The relevant description will not be expanded here.

[0129] In summary, the optimized nand2 unit combination is to decouple the two nand2s distributed along the length direction of the carbon tube in the nand2 unit combination before optimization, and transform them from single height to double height or dual-stack, reducing the number of nand2 units in the nand2 unit combination affected by one MCNT at the same time, thereby reducing the degree of influence on the nand2 unit combination and improving circuit stability.

[0130] It should be noted that the above description is only based on the example of the nand2 unit as a logic gate unit, which is intended to facilitate understanding and should not constitute a limitation on the embodiments of the present application. In addition to the nand2 unit, the logic gate unit described in the embodiments of the present application can also be an AND gate, an OR gate, a NOT gate, an NOR gate, an AND-NOR gate, nor2, nand3, nand4, MUX2, AOI22, BUF and other types of logic gate units. In order to better illustrate the layout design optimization of the logic gate unit in the grain structure described in the embodiments of the present application, the following is a brief description using some or all of the above-mentioned logic gate units as examples.

[0131] For the layout design optimization of the nor2 unit, please refer to Figure 12a-12c , Figure 12a-12c This is a schematic diagram of several grain structures including nor2 provided in the embodiments of the present application.

[0132] Figure 12a The conventional NOR2 unit layout design (method 1) and the optimized NOR2 unit layout design (method 2) of the present application are shown in FIG. In method 1, the two FETs in the FET group-P are prepared in the same CNT group (such as Figure 12a On the CNT of CNT group 1 in method 1, the two FETs in FET group-N are also prepared on the same CNT group (such as Figure 12a In the first method, the two FETs in the same FET group are connected along the length direction of the CNT. In the design method optimized by the present application, multiple FETs in at least one FET group in the nor2 unit are prepared on CNTs in different CNT groups, so that two FETs in one FET group that are originally connected along the length direction of the carbon tube (such as Figure 12a Method 1) in the above is used to disassociate. For example, Figure 12aIn the second method, one of the four FETs of the nor2 unit can be prepared on each of the four CNT groups, that is, one FET is prepared on the CNT of one CNT group, and the number of FETs on each CNT group is "1-1-1-1", wherein the two P-channel type FETs in the FET group-P are prepared on the CNTs of the CNT group 2 and the CNT group 3, respectively, and the two N-channel type FETs in the FET group-N are prepared on the CNTs of the CNT group 1 and the CNT group 4, respectively; or, four FETs can be prepared on three CNT groups, and the number of FETs corresponding to each group is "2-1-1", which are not listed one by one here, thereby reducing the number of FETs affected along the length direction of the MCNT, thereby reducing the degree to which the nor2 logic function is affected. For example, the optimized nor2 unit in the embodiment of the present application can be divided into two parts on the same CNT plane, distributed between two VSS lines and one VDD line, and the two parts are connected by a metal connection line (M2). The optimized nor2 unit (such as Figure 12a Method 2) in the above method realizes the transformation from single height to double height.

[0133] Figure 12b The figure shows the traditional NOR2 unit layout design (method 1) and another NOR2 unit layout design (method 2) optimized by this application. Figure 12b The method shown is Figure 12a In another design optimized by the present application, multiple FETs in at least one FET group in the nor2 unit are prepared on CNTs of different CNT groups, and different CNT groups can be on different CNT planes, such as Figure 12b The bottom tier (corresponding to the second CNT plane) and the top tier (corresponding to the third CNT plane) shown in FIG are used to realize the two FETs (such as Figure 12a or Figure 12b Method 1) in the above is used to disassociate. For example, Figure 12b In method 2, one FET in FET group-N can be prepared on the CNT of CNT group 2 in the bottom tier, and another FET can be prepared on the CNT of CNT group 2 in the top tier; one FET in FET group-P can be prepared on the CNT of CNT group 1 in the bottom tier, and another FET can be prepared on the CNT of CNT group 1 in the top tier.

[0134] Figure 12cAnother approach to optimizing layout design on different CNT planes is shown in FIG. Figure 12c In the second method, both FETs in FET group-N can be prepared on the CNT in the top layer, wherein one FET is prepared on the CNT of CNT group 1 and the other FET is prepared on the CNT of CNT group 2, and both FETs in FET group-P can be prepared on the CNT in the bottom layer, wherein one FET is prepared on the CNT of CNT group 1 and the other FET is prepared on the CNT of CNT group 2.

[0135] For the layout design optimization of nand3 unit, please refer to Figure 13a-Figure 13c , Figure 13a-Figure 13c This is a schematic diagram of several grain structures including nand3 provided in the embodiments of the present application.

[0136] Figure 13a The figure shows the traditional nand3 cell layout design (method 1) and the nand3 cell layout design optimized by the present application (method 2). In method 1, the three FETs in the FET group-P are all prepared in the same CNT group (such as Figure 13a On the CNT of CNT group 1 in method 1, the three FETs in FET group-N are also prepared on the same CNT group (such as Figure 13a In the first method, the three FETs in the same FET group are connected along the length direction of the CNT. In the design method optimized by the present application, multiple FETs in at least one FET group in the nand3 unit are prepared on CNTs in different CNT groups, so that two FETs in one FET group that are originally connected along the length direction of the carbon tube (such as Figure 13a Method 1) in the above is used to disassociate. For example, Figure 13aIn the second method, 6 FETs of the nand3 unit can be prepared on 4 CNT groups respectively, and the number of FETs on each CNT group is "1-1-2-2", wherein 1 P-channel type FET in FET group-P is prepared on the CNT of CNT group 1, and the other 2 P-channel type FETs are prepared on the CNT of CNT group 4, and 1 N-channel type FET in FET group-N is prepared on the CNT of CNT group 2, and the other 2 N-channel type FETs are prepared on the CNT of CNT group 3; alternatively, 6 FETs can be prepared on 3 CNT groups, and the corresponding number of FETs in each group is "2-1-3", or 6 FETs can be prepared on 6 CNT groups, and the corresponding number of FETs in each group is "1-1-1-1-1-1", which are not listed one by one here, so that the number of FETs affected along the length direction of the MCNT is reduced, thereby reducing the degree of impact on the nand3 logic function. For example, the optimized nand3 unit in the embodiment of the present application can be divided into two parts on the same CNT plane, distributed between two VDD lines and one VSS line, and the two parts are connected by a metal connection line (M2). Figure 13a Method 2) in the above method realizes the transformation from single height to double height.

[0137] Figure 13b The figure shows the traditional nand3 unit layout design (method 1) and another nand3 unit layout design (method 2) optimized by this application. Figure 13b The method shown is Figure 13a In another design optimized by the present application, multiple FETs in at least one FET group in the nand3 unit are prepared on CNTs of different CNT groups, and different CNT groups can be on different CNT planes, such as Figure 13b The bottom tier (corresponding to the second CNT plane) and the top tier (corresponding to the third CNT plane) shown in FIG are used to realize the two FETs (such as Figure 13a or Figure 13b Method 1) in the above is used to disassociate. For example, Figure 13bIn method 2, two FETs in FET group-N can be prepared on the CNT of CNT group 2 in the bottom tier, and another FET can be prepared on the CNT of CNT group 2 in the top tier; two FETs in FET group-P can be prepared on the CNT of CNT group 1 in the bottom tier, and another FET can be prepared on the CNT of CNT group 1 in the top tier.

[0138] Figure 13c Another approach to optimizing layout design on different CNT planes is shown in FIG. Figure 13c In the second method, the three FETs in FET group-N can be prepared on the CNT in the top layer, wherein two FETs are prepared on the CNT of CNT group 1 and the other FET is prepared on the CNT of CNT group 2, and the three FETs in FET group-P can be prepared on the CNT in the bottom layer, wherein two FETs are prepared on the CNT of CNT group 1 and the other FET is prepared on the CNT of CNT group 2.

[0139] For the layout design optimization of nand4 unit, please refer to Figure 14a-Figure 14c , Figure 14a-Figure 14c This is a schematic diagram of several NAND4-containing grain structures provided in the embodiments of the present application.

[0140] Figure 14a The conventional nand4 cell layout design (method 1) and the nand4 cell layout design optimized by the present application (method 2) are shown in FIG. In method 1, the four FETs in the FET group-P are all prepared in the same CNT group (such as Figure 14a On the CNT of CNT group 1 in method 1, the four FETs in FET group-N are also prepared on the same CNT group (such as Figure 14a In the first method, the four FETs in the same FET group are connected along the length direction of the CNT. In the optimized design of this application, multiple FETs in at least one FET group in the nand4 unit are prepared on CNTs in different CNT groups, so that two FETs in one FET group that are originally connected along the length direction of the carbon tube (such as Figure 14a Method 1) in the above is used to disassociate. For example, Figure 14aIn the second method, 8 FETs of the nand4 unit can be prepared on 4 CNT groups respectively, and the number of FETs on each CNT group is "2-2-2-2", wherein, 2 P-channel type FETs in FET group-P are prepared on the CNT of CNT group 1, and the other 2 P-channel type FETs are prepared on the CNT of CNT group 4, and 2 N-channel type FETs in FET group-N are prepared on the CNT of CNT group 2, and the other 2 N-channel type FETs are prepared on the CNT of CNT group 3; alternatively, 8 FETs can be prepared on 6 CNT groups, and the corresponding number of FETs in each group is "2-1-1-2-1-1", or 8 FETs can be prepared on 8 CNT groups, and the corresponding number of FETs in each group is "1-1-1-1-1-1-1-1", which are not listed one by one here, so that the number of FETs affected along the length direction of the MCNT is reduced, thereby reducing the degree of impact on the nand4 logic function. For example, the optimized nand4 unit of the embodiment of the present application can be divided into two parts on the same CNT plane, distributed between two VDD lines and one VSS line, and the two parts are connected by a metal connection line (M2). Figure 14a Method 2) in the above method realizes the transformation from single height to double height.

[0141] Figure 14b The figure shows the traditional nand4 unit layout design (method 1) and another nand4 unit layout design (method 2) optimized by the present application. Figure 14b The method shown is Figure 14a In another design optimized by the present application, multiple FETs in at least one FET group in the nand4 unit are prepared on CNTs of different CNT groups, and different CNT groups can be on different CNT planes, such as Figure 14b The bottom tier (corresponding to the second CNT plane) and the top tier (corresponding to the third CNT plane) shown in FIG are used to realize the two FETs (such as Figure 14a or Figure 14b Method 1) in the above is used to disassociate. For example, Figure 14bIn method 2, two FETs in FET group-N can be prepared on the CNT of CNT group 2 in the bottom tier, and the other two FETs can be prepared on the CNT of CNT group 2 in the top tier; two FETs in FET group-P can be prepared on the CNT of CNT group 1 in the bottom tier, and the other two FETs can be prepared on the CNT of CNT group 1 in the top tier.

[0142] Figure 14c Another approach to optimizing layout design on different CNT planes is shown in FIG. Figure 14c In the second method, the four FETs in FET group-N can be prepared on the CNT in the top layer, wherein two FETs are prepared on the CNT of CNT group 1 and the other two FETs are prepared on the CNT of CNT group 2, and the four FETs in FET group-P can be prepared on the CNT in the bottom layer, wherein two FETs are prepared on the CNT of CNT group 1 and the other two FETs are prepared on the CNT of CNT group 2.

[0143] For the layout design optimization of MUX2 unit, please refer to Figure 15a-Figure 15c , Figure 15a-Figure 15c This is a schematic diagram of several grain structures including MUX2 provided in the embodiments of the present application.

[0144] Figure 15a The conventional MUX2 unit layout design (method 1) and the optimized MUX2 unit layout design (method 2) of the present application are shown in FIG. In method 1, the 7 FETs in FET group-P are all prepared in the same CNT group (such as Figure 15a On the CNT of CNT group 1 in method 1, the 7 FETs in FET group-N are also prepared on the same CNT group (such as Figure 15a In the first method, the seven FETs in the same FET group are connected along the length direction of the CNT. In the optimized design of the present application, the multiple FETs in at least one FET group in the MUX2 unit are prepared on the CNTs of different CNT groups, so that the two FETs in one FET group that are originally connected along the length direction of the carbon tube (such as Figure 15a Method 1) in the above is used to disassociate. For example, Figure 15aIn the second method, 14 FETs of the MUX2 unit can be prepared on 4 CNT groups respectively, and the number of FETs on each CNT group is "3-4-3-4", wherein 4 P-channel FETs in FET group-P are prepared on the CNT of CNT group 2, and another 3 P-channel FETs are prepared on the CNT of CNT group 3, and 3 N-channel FETs in FET group-N are prepared on the CNT of CNT group 1, and another 4 N-channel FETs are prepared on the CNT of CNT group 4; alternatively, 14 FETs can be prepared on 3 CNT groups, and the number of FETs corresponding to each group is "3-4-7", or 14 FETs can be prepared on 6 CNT groups, and the number of FETs corresponding to each group is "3-3-1-3-3-1", which are not listed one by one here, so that the number of FETs affected along the length direction of the MCNT is reduced, thereby reducing the degree to which the MUX2 logic function is affected. For example, the optimized MUX2 unit of the embodiment of the present application can be divided into two parts on the same CNT plane, distributed between two VSS lines and one VDD line. Figure 15a Method 2) in the above method realizes the transformation from single height to double height.

[0145] Figure 15b The figure shows the traditional MUX2 unit layout design (method 1) and another MUX2 unit layout design (method 2) optimized by the present application. Figure 15b The method shown is Figure 15a In another design optimized by the present application, multiple FETs in at least one FET group in the MUX2 unit are prepared on CNTs of different CNT groups, and different CNT groups can be on different CNT planes, such as Figure 15b The bottom tier (corresponding to the second CNT plane) and the top tier (corresponding to the third CNT plane) shown in FIG are used to realize the two FETs (such as Figure 15a or Figure 15b Method 1) in the above is used to disassociate. For example, Figure 15b In method 2, the four FETs in FET group-N can be prepared on the CNTs of CNT group 2 in the bottom tier, and the other three FETs can be prepared on the CNTs of CNT group 2 in the top tier; the three FETs in FET group-P can be prepared on the CNTs of CNT group 1 in the bottom tier, and the other four FETs can be prepared on the CNTs of CNT group 1 in the top tier.

[0146] Figure 15c Another approach to optimizing layout design on different CNT planes is shown in FIG. Figure 15c In the second method, all 7 FETs in FET group-N can be prepared on the CNT in the top layer, wherein 4 FETs are prepared on the CNT of CNT group 1 and the other 3 FETs are prepared on the CNT of CNT group 2, and all 7 FETs in FET group-P can be prepared on the CNT in the bottom layer, wherein 3 FETs are prepared on the CNT of CNT group 1 and the other 4 FETs are prepared on the CNT of CNT group 2.

[0147] For layout design optimization of AOI22 unit, please refer to Figure 16a-Figure 16c , Figure 16a-Figure 16c This is a schematic diagram of several grain structures including AOI22 provided in the embodiments of the present application.

[0148] Figure 16a The conventional AOI22 unit layout design (method 1) and an AOI22 unit layout design optimized by the present application (method 2) are shown in FIG. In method 1, the four FETs in the FET group-P are all prepared in the same CNT group (e.g. Figure 16a On the CNT of CNT group 1 in method 1, the four FETs in FET group-N are also prepared on the same CNT group (such as Figure 16a In the first method, the four FETs in the same FET group are connected along the length direction of the CNT. In the optimized design of the present application, multiple FETs in at least one FET group in the AOI22 unit are prepared on CNTs in different CNT groups, so that two FETs in one FET group that are originally connected along the length direction of the carbon tube (such as Figure 16a Method 1) in the above is used to disassociate. For example, Figure 16aIn the second method, 8 FETs of the AOI22 unit can be prepared on 4 CNT groups respectively, and the number of FETs on each CNT group is "2-2-2-2", wherein, 2 P-channel type FETs in FET group-P are prepared on the CNT of CNT group 2, and another 2 P-channel type FETs are prepared on the CNT of CNT group 3, and 2 N-channel type FETs in FET group-N are prepared on the CNT of CNT group 1, and another 2 N-channel type FETs are prepared on the CNT of CNT group 4; alternatively, 8 FETs can be prepared on 6 CNT groups, and the corresponding number of FETs in each group is "2-1-1-2-1-1", or 8 FETs can be prepared on 8 CNT groups, and the corresponding number of FETs in each group is "1-1-1-1-1-1-1-1", which are not listed one by one here, so that the number of FETs affected along the length direction of the MCNT is reduced, thereby reducing the degree of impact on the logical function of AOI22. For example, the optimized AOI22 unit of the embodiment of the present application can be divided into two parts on the same CNT plane, distributed between two VSS lines and one VDD line. Figure 16a Method 2) in the above method realizes the transformation from single height to double height.

[0149] Figure 16b The figure shows the traditional AOI22 unit layout design (method 1) and another AOI22 unit layout design (method 2) optimized by the present application. Figure 16b The method shown is Figure 16a In another design optimized by the present application, multiple FETs in at least one FET group in the AOI22 unit are prepared on CNTs of different CNT groups, and different CNT groups can be on different CNT planes, such as Figure 16b The bottom tier (corresponding to the second CNT plane) and the top tier (corresponding to the third CNT plane) shown in FIG are used to realize the two FETs (such as Figure 16a or Figure 16b Method 1) in the above is used to disassociate. For example, Figure 16bIn method 2, two FETs in FET group-N can be prepared on the CNT of CNT group 2 in the bottom tier, and the other two FETs can be prepared on the CNT of CNT group 2 in the top tier; two FETs in FET group-P can be prepared on the CNT of CNT group 1 in the bottom tier, and the other two FETs can be prepared on the CNT of CNT group 1 in the top tier.

[0150] Figure 16c Another approach to optimizing layout design on different CNT planes is shown in FIG. Figure 16c In the second method, the four FETs in FET group-N can be prepared on the CNT in the top layer, wherein two FETs are prepared on the CNT of CNT group 1 and the other two FETs are prepared on the CNT of CNT group 2, and the four FETs in FET group-P can be prepared on the CNT in the bottom layer, wherein two FETs are prepared on the CNT of CNT group 1 and the other two FETs are prepared on the CNT of CNT group 2.

[0151] For the layout design optimization of BUF unit, please refer to Figure 17 , Figure 17 This is a schematic diagram of a grain structure including a BUF provided in an embodiment of the present application. Figure 17 The conventional BUF unit layout design (method 1) and the optimized BUF unit layout design (method 2) of the present application are shown in FIG. In method 1, the two FETs in the FET group-P are prepared in the same CNT group (such as Figure 17 On the CNT of CNT group 1 in method 1, the two FETs in FET group-N are also prepared on the same CNT group (such as Figure 17 In the first method, the two FETs in the same FET group are connected along the length direction of the CNT. In the optimized design of the present application, multiple FETs in at least one FET group in the BUF unit are prepared on CNTs in different CNT groups, so that two FETs in one FET group that are originally connected along the length direction of the carbon tube (such as Figure 17 Method 1) in the above is used to disassociate. For example, Figure 17In the second method, 4 FETs of the BUF unit can be prepared on 4 CNT groups respectively, and the number of FETs on each CNT group is "1-1-1-1", wherein the 2 P-channel type FETs in FET group-P are prepared on the CNTs of CNT group 2 and CNT group 3 respectively, and the 2 N-channel type FETs in FET group-N are prepared on the CNTs of CNT group 1 and CNT group 4 respectively; or, 4 FETs can be prepared on 3 CNT groups, and the number of FETs corresponding to each group is "2-1-1", which are not listed one by one here, thereby reducing the number of FETs affected along the length direction of the MCNT, thereby reducing the degree to which the BUF logic function is affected. For example, the optimized BUF unit in the embodiment of the present application can be divided into two parts on the same CNT plane, distributed between two VSS lines and one VDD line, and the optimized BUF unit (such as Figure 17 Method 2) in the BUF unit achieves the transition from a single-height structure to a double-height structure. Regarding the implementation of fabricating multiple FETs within at least one FET group within the BUF unit on CNTs from different CNT groups, with the different CNT groups being located on different CNT planes, reference can be made to the relevant descriptions of the various logic gate units described above and will not be elaborated upon here.

[0152] The above is an exemplary description of the grain structure provided in the embodiment of the present application. For ease of understanding, the layout design method provided in the embodiment of the present application will be described below in conjunction with some or all of the above-mentioned drawings. The layout design method provided in the embodiment of the present application can be applied to the simulation stage in the chip design and production process. For example, various computer-aided design software can be used to create chip circuit diagrams with various logical functions, and the layout design method provided in the embodiment of the present application can be used to design the chip circuit diagram. After a series of simulations, tests and verifications are performed on the chip circuit diagram and the requirements are met, the final tape-out is carried out.

[0153] See Figure 18 , Figure 18 This is a flow chart of a layout design method provided in an embodiment of the present application, including but not limited to the following steps:

[0154] S180: Determine a first logic gate unit and M first CNT groups.

[0155] The first logic gate unit includes N first FET groups, each of the N first FET groups includes multiple first FETs of the same channel type, and FETs of different FET groups in the N first FET groups have different channel types, and N is an integer greater than or equal to 2; each of the M first CNT groups includes one or more CNTs; and M is an integer greater than or equal to 3;

[0156] S181: Map the first FETs of the N first FET groups in the first logic gate unit to the CNTs of the M first CNT groups.

[0157] Each first FET group corresponds to one or more first CNT groups, and the one or more first CNT groups corresponding to different first FET groups are different. The multiple first FETs in each first FET group are prepared on the CNTs of the one or more first CNT groups corresponding to each first FET group, and the multiple first FETs in at least one first FET group among the N first FET groups are prepared on the CNTs of the corresponding multiple first CNT groups. In other words, the FETs of different FET groups among the N first FET groups are prepared on the CNTs of different CNT groups among the M first CNT groups, and some or all of the FETs in at least one FET group among the N first FET groups are prepared on the CNTs of different CNT groups among the M first CNT groups.

[0158] Based on the above steps S180-S181, a layout design similar to Figure 2 If the first logic gate unit is a nand2 unit, for example, the layout design based on the above steps S180-S181 can include the following: Figure 7 The grain structure of the nand2 layout is shown in the second embodiment. It is understandable that the first logic gate unit can also be other types of logic gates, which are not listed here one by one.

[0159] In a possible implementation, the method further includes the following steps:

[0160] S182: Determine a first CNT plane;

[0161] S183: Mapping the M first CNT groups to the first CNT plane.

[0162] That is to say, the M first CNT groups are all located in the first CNT plane.

[0163] In a possible implementation, the method further includes the following steps:

[0164] S184: Determine a second CNT plane and a third CNT plane;

[0165] S185: Mapping a first portion of the M first CNT groups to the second CNT plane, and mapping a second portion of the M first CNT groups to the third CNT plane.

[0166] That is, the first part of the M first CNT groups is located in the second CNT plane, and the second part of the M first CNT groups is located in the third CNT plane. Based on the above steps S184, S185, S180 and S181, a similar layout can be obtained. Figure 3 If the first logic gate unit is a nand2 unit, for example, the layout design based on the above steps S180-S181 can include the following: Figure 8 or Figure 9 The grain structure of the nand2 layout is shown in the second method.

[0167] In one possible implementation, any two of the M first CNT groups contain different CNTs. Different CNT groups are completely isolated from each other. When MCNTs are present in a CNT group, the number of FETs affected by the MCNTs can be minimized, further minimizing the impact on the logic function of the logic gate unit.

[0168] In a possible implementation, the method further includes the following steps:

[0169] S186: Determine a second logic gate unit and K second CNT groups.

[0170] Each of the K second CNT groups includes one or more CNTs, and K is an integer greater than or equal to 1; and the second logic gate unit includes a plurality of second FETs.

[0171] S187: Map the plurality of second FETs in the second logic gate unit to the CNTs of the K second CNT groups.

[0172] The M first CNT groups and the K second CNT groups are different; the first logic gate unit is used to drive the second logic gate unit, or the second logic gate unit is used to drive the first logic gate unit.

[0173] Based on the above steps S186, S187, S180 and S181, a layout design similar to Figure 4 The grain structure shown.

[0174] In a possible implementation, the M first CNT groups and the K second CNT groups are all located in the same CNT plane, or the M first CNT groups and the K second CNT groups are located in different CNT planes.

[0175] In one possible implementation, the second logic gate unit includes a plurality of second FET groups, each second FET group includes a plurality of FETs having the same channel type among the plurality of second FETs, and the channel types of FETs in different FET groups among the plurality of second FET groups are different;

[0176] Mapping the plurality of second FETs in the second logic gate unit to the CNTs of the K second CNT groups includes:

[0177] Mapping the FETs of different FET groups in the plurality of second FET groups to the CNTs of different CNT groups in the K second CNT groups, and mapping part or all of the FETs in at least one FET group in the plurality of second FET groups to the CNTs of different CNT groups in the K second CNT groups. Based on the above layout design, the following can be obtained: Figure 11 The grain structure of the nand2 unit combination layout is shown.

[0178] above Figure 18 The layout design method is to optimize the design based on the FET group in the logic gate unit. In addition, the layout design method provided in the embodiment of the present application can also optimize the design based on the logic gate unit in the logic gate unit combination. Figure 19 , Figure 19 This is a flow chart of another layout design method provided in an embodiment of the present application, including but not limited to the following steps:

[0179] S190: Determine a third logic gate unit, a fourth logic gate unit, and P CNT groups.

[0180] Wherein, the third logic gate unit is used to drive the fourth logic gate unit; the third logic gate unit includes one or more third FETs, and the fourth logic gate unit includes one or more fourth FETs;

[0181] S191: Mapping one or more third FETs in the third logic gate unit and one or more fourth FETs in the fourth logic gate unit to CNTs in different CNT groups among the P CNT groups.

[0182] Based on the above steps S190-S191, the layout design can be performed to obtain the following Figure 10Optionally, for one or more logic gate units in a logic gate unit combination (such as a nand2 unit combination), reference may also be made to the following examples: Figure 7 In the layout design shown in FIG, the FETs of different FET groups in the logic gate unit are prepared on CNTs of different CNT groups, and the multiple FETs of at least one FET group in the multiple FET groups are respectively prepared on CNTs of different CNT groups, which can include Figure 11 The grain structure of the optimized nand2 unit combination layout.

[0183] Optionally, the P CNT groups may be located in the same CNT plane or in different CNT planes.

[0184] Optionally, at least one CNT in any two of the P CNT groups does not belong to the two CNT groups at the same time. Further, optionally, the CNTs in any two of the P CNT groups are different.

[0185] Understandably, the above Figure 18 and Figure 19 The layout designs of various grain structures and various logic gate units obtained by optimizing the layout design in the corresponding embodiments can refer to the above Figure 2-Figure 17 The description of any embodiment in will not be described in detail here.

[0186] It should be noted that the layout design optimization methods of the above-mentioned embodiments are all based on the preparation of CNFETs based on CNTs as an example to explain, and should not constitute a limitation on the embodiments of the present application. In addition, gate-all-around FETs (GAAFETs) prepared based on CNTs are also applicable to the layout design optimization methods of the above-mentioned embodiments. At the same time, other FETs prepared based on one-dimensional channel materials are also applicable to the layout design optimization methods of the above-mentioned embodiments. One-dimensional channel materials refer to materials with special structures and properties in one-dimensional space, such as a ratio of length to diameter (aspect ratio) greater than or equal to a certain threshold value. One-dimensional channel materials include the above-mentioned carbon nanotubes (CNTs), boron nitride (BN) nanotubes, and germanium (Ge) nanowires.

[0187] The present application also provides a semiconductor chip, which includes the die provided by any one of the above embodiments of the present application. It is understood that the structure of the die and the layout design of the logic gate unit included in the die can refer to the above Figures 2 to 17 The specific implementation methods in the corresponding embodiments will not be repeated here.

[0188] The present application also provides an electronic device, which includes the die provided by any one of the above embodiments of the present application. It is understood that the structure of the die and the layout design of the logic gate unit included in the die can refer to the above Figures 2 to 17 The specific implementation methods in the corresponding embodiments are not described in detail here. Optionally, the electronic device may further include a communication interface for the electronic device to communicate with other devices or a communication network.

[0189] The present application also provides an electronic device having the function of implementing any of the above-mentioned layout design methods. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions.

[0190] The present application provides a computer storage medium, which stores a computer program. When the computer program is executed, the functions involved in any of the above-mentioned layout design method processes can be implemented.

[0191] The present application provides a computer program, which includes instructions. When the computer program is executed, the functions involved in executing any of the above-mentioned layout design method processes are realized.

[0192] The present application provides a chip system, which includes the die provided by any one of the above-mentioned embodiments. Alternatively, in one possible design, the chip system may include a processor, and the memory is used to implement the functions involved in any of the above-mentioned layout design method flows. Optionally, the chip system may be composed of a chip, or may include a chip and other discrete devices.

[0193] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0194] It should be noted that, for the sake of simplicity, the aforementioned method embodiments are described as a series of action combinations. However, those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0195] In several embodiments provided in this application, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices or units, or may be an electrical, mechanical or other form of connection.

[0196] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A crystal grain, characterized in that: The crystal grain includes a first logic gate unit and M first carbon nanotube (CNT) groups; the first logic gate unit includes N first field effect transistor (FET) groups, each of the N first FET groups includes a plurality of first FETs of the same channel type, and FETs of different FET groups in the N first FET groups have different channel types, where N is an integer greater than or equal to 2; Each of the M first CNT groups includes one or more CNTs; M is an integer greater than or equal to 3; The FETs of the N first FET groups are prepared on the CNTs of the M first CNT groups; wherein, each first FET group corresponds to one or more first CNT groups, and the one or more first CNT groups corresponding to different first FET groups are different, the multiple first FETs in each first FET group are prepared on the CNTs of the one or more first CNT groups corresponding to each first FET group, and the multiple first FETs in at least one first FET group among the N first FET groups are prepared on the CNTs of the corresponding multiple first CNT groups.

2. The crystal grain according to claim 1, wherein The crystal grain includes a first CNT plane, and the M first CNT groups are all located in the first CNT plane.

3. The crystal grain according to claim 1, wherein The crystal grain includes a second CNT plane and a third CNT plane. A first portion of the M first CNT groups is located in the second CNT plane, and a second portion of the M first CNT groups is located in the third CNT plane.

4. The crystal grain according to any one of claims 1 to 3, characterized in that The CNTs included in any two of the M first CNT groups are different.

5. The grain according to any one of claims 1 to 4, characterized in that The grain also includes a second logic gate unit and K second CNT groups, each second CNT group includes one or more CNTs, and K is an integer greater than or equal to 1; the second logic gate unit includes multiple second FETs, and the multiple second FETs are prepared on the CNTs of the K second CNT groups; the M first CNT groups and the K second CNT groups are different; the first logic gate unit is used to drive the second logic gate unit, or the second logic gate unit is used to drive the first logic gate unit.

6. The crystal grain according to claim 5, wherein: The crystal grain includes at least one CNT plane; the M first CNT groups and the K second CNT groups are all located in the same CNT plane, or the M first CNT groups and the K second CNT groups are located in different CNT planes.

7. The crystal grain according to any one of claims 5 to 6, characterized in that The second logic gate unit includes multiple second FET groups, each second FET group includes multiple FETs with the same channel type among the multiple second FETs, and the channel types of FETs in different FET groups among the multiple second FET groups are different; the FETs of different FET groups among the multiple second FET groups are prepared on CNTs of different CNT groups among the K second CNT groups, and part or all of the FETs in at least one FET group among the multiple second FET groups are prepared on CNTs of different CNT groups among the K second CNT groups.

8. A crystal grain, characterized in that: The grain includes a third logic gate unit, a fourth logic gate unit and P CNT groups; the third logic gate unit is used to drive the fourth logic gate unit; the third logic gate unit includes one or more third FETs, and the fourth logic gate unit includes one or more fourth FETs; the one or more third FETs and the one or more fourth FETs are prepared on CNTs of different CNT groups among the P CNT groups.

9. A layout design method, characterized in that: The method comprises: A first logic gate unit and M first CNT groups are determined; the first logic gate unit includes N first FET groups, each of the N first FET groups includes multiple first FETs of the same channel type, and FETs in different FET groups in the N first FET groups have different channel types, where N is an integer greater than or equal to 2; each of the M first CNT groups includes one or more CNTs; and M is an integer greater than or equal to 3. The first FETs of the N first FET groups in the first logic gate unit are mapped to the CNTs of the M first CNT groups; wherein, each first FET group corresponds to one or more first CNT groups, and the one or more first CNT groups corresponding to different first FET groups are different, the multiple first FETs in each first FET group are prepared on the CNTs of the one or more first CNT groups corresponding to each first FET group, and the multiple first FETs in at least one first FET group among the N first FET groups are prepared on the CNTs of the corresponding multiple first CNT groups.

10. The method according to claim 9, wherein The method further comprises: determining a first CNT plane; The M first CNT groups are all mapped to the first CNT plane.

11. The method according to claim 9, wherein The method further comprises: determining a second CNT plane and a third CNT plane; A first portion of the M first CNT groups is mapped to the second CNT plane, and a second portion of the M first CNT groups is mapped to the third CNT plane.

12. The method according to any one of claims 9 to 11, wherein The CNTs included in any two of the M first CNT groups are different.

13. The method according to any one of claims 9 to 12, wherein: The method further comprises: Determine a second logic gate unit and K second CNT groups; each of the K second CNT groups includes one or more CNTs, K is an integer greater than or equal to 1; the second logic gate unit includes a plurality of second FETs; The multiple second FETs in the second logic gate unit are mapped to the CNTs of the K second CNT groups; the M first CNT groups and the K second CNT groups are different; the first logic gate unit is used to drive the second logic gate unit, or the second logic gate unit is used to drive the first logic gate unit.

14. The method according to claim 13, wherein The M first CNT groups and the K second CNT groups are all located in the same CNT plane, or the M first CNT groups and the K second CNT groups are located in different CNT planes.

15. The method according to any one of claims 12 to 13, wherein: The second logic gate unit includes a plurality of second FET groups, each second FET group includes a plurality of FETs having the same channel type among the plurality of second FETs, and the channel types of FETs in different FET groups among the plurality of second FET groups are different; Mapping the plurality of second FETs in the second logic gate unit to the CNTs of the K second CNT groups includes: Mapping FETs of different FET groups in the plurality of second FET groups to CNTs of different CNT groups in the K second CNT groups, and mapping part or all of the FETs in at least one FET group in the plurality of second FET groups to CNTs of different CNT groups in the K second CNT groups.

16. A layout design method, characterized in that: The method comprises: Determine a third logic gate unit, a fourth logic gate unit, and P CNT groups; the third logic gate unit is used to drive the fourth logic gate unit; the third logic gate unit includes one or more third FETs, and the fourth logic gate unit includes one or more fourth FETs; The one or more third FETs and the one or more fourth FETs are mapped to CNTs of different CNT groups among the P CNT groups.

17. A semiconductor chip, characterized in that: The invention comprises the grain according to any one of claims 1 to 8.

18. A layout design device, characterized in that: The method comprises a module or a unit for executing the method according to any one of claims 9 to 16.

19. A layout design device, characterized in that: The method comprises a processor, wherein the processor is configured to implement the method according to any one of claims 9 to 16 through a logic circuit or executing code instructions.

20. A computer-readable storage medium, characterized in that The storage medium stores a computer program or instruction, and when the computer program or instruction is executed, the method according to any one of claims 9 to 16 is implemented.

21. A computer program, characterized in that The computer program comprises instructions, and when the computer program is executed, the method according to any one of claims 9 to 16 is implemented.

22. An electronic device, characterized in that: A device comprising the die according to any one of claims 1 to 8, and for implementing the method according to any one of claims 9 to 16.

23. A chip system, characterized in that: The chip system includes a processor or a die according to any one of claims 1 to 8, and the processor is used to support the device to implement the functions involved in the method according to any one of claims 9 to 16.

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