Semiconductor structure, method of manufacturing a semiconductor structure, and image sensor

Abstract

The embodiment of the present application provides a semiconductor structure, a manufacturing method of the semiconductor structure and an image sensor, the semiconductor structure comprising: a substrate; a transfer gate formed on a surface of the substrate; a floating diffusion region and a transition doped region formed in the substrate; wherein the transition doped region is located between a projection of the transfer gate on the substrate and the floating diffusion region; a doping concentration of the transition doped region is less than a doping concentration of the floating diffusion region; the transition doped region comprises a first doped region and a second doped region formed based on an ion implantation process; a doping type of the first doped region is different from a doping type of the floating diffusion region; a doping type of the second doped region is the same as the doping type of the floating diffusion region; and along a normal direction of the substrate, an ion implantation depth of the second doped region is greater than an ion implantation depth of the first doped region. Through the embodiment of the present application, occurrence of gate-induced drain leakage is reduced, and imaging quality of the CMOS image sensor is improved.

Description

TECHNICAL FIELD

[0001] Embodiments in the present application relate to the technical field of semiconductor technology, and in particular to a semiconductor structure, a manufacturing method of the semiconductor structure, and an image sensor. BACKGROUND

[0002] A CMOS image sensor (CIS) is an image sensing device that integrates a photosensitive element, an amplifier, an analog-to-digital converter, a memory, a digital signal processor, and a computer interface circuit on the same silicon substrate. Due to its low power consumption, high performance, and ease of integration, the CMOS image sensor has been widely used in consumer electronics, security monitoring, assisted driving, and medical devices.

[0003] A pixel array is a key component of a CMOS image sensor, and the performance of each pixel in the pixel array has an important influence on the imaging quality and resolution of the CMOS image sensor as a whole. Among various pixel structures that make up the pixel array, the four-transistor active pixel structure (4T-APS) has been widely used in the design and manufacture of CMOS image sensors due to its high integration, fast response speed, low power consumption, and low cost.

[0004] However, in a pixel array composed of existing four-transistor active pixel structures, white pixels can be caused when the transistors are in an off or standby state, which reduces the imaging quality of the CMOS image sensor. SUMMARY

[0005] In view of this, embodiments of the present application provide a semiconductor structure, a manufacturing method of the semiconductor structure, and an image sensor to improve the imaging quality of the CMOS image sensor.

[0006] In one aspect, one embodiment of the present application provides a semiconductor structure, comprising: a substrate; a transfer gate formed on a surface of the substrate; a floating diffusion region and a transition doped region formed in the substrate; wherein the transition doped region is located between a projection of the transfer gate on the substrate and the floating diffusion region; a doping concentration of the transition doped region is less than a doping concentration of the floating diffusion region; the transition doped region comprises a first doped region and a second doped region formed based on an ion implantation process; a doping type of the first doped region is different from a doping type of the floating diffusion region; a doping type of the second doped region is the same as the doping type of the floating diffusion region; along a normal direction of the substrate, an ion implantation depth of the second doped region is greater than an ion implantation depth of the first doped region.

[0007] Optionally, the semiconductor structure further comprises: a first gate side wall formed on a side of the transfer gate and a surface of the substrate; wherein a material of the first gate side wall is different from a material of the substrate; a second gate side wall formed on a side of the first gate side wall away from the transfer gate and away from the substrate; the first doped region is present between a projection of the second gate side wall on the substrate and the floating diffusion region.

[0008] Optionally, the transfer gate comprises a first gate doped region and a second gate doped region; wherein, taking a direction perpendicular to the normal direction of the substrate as a width direction of the transfer gate, along the width direction of the transfer gate, the first gate doped region is located between the second gate doped region and the first gate side wall; a doping type of the first gate doped region is different from a doping type of the second gate doped region.

[0009] Optionally, the transfer gate comprises a third gate doped region; in the third gate doped region, a region closer to the first gate side wall has a lower doping concentration.

[0010] In another aspect, one embodiment of the present application provides a manufacturing method of a semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate; forming a transfer gate on a surface of the substrate; performing ion implantation on the substrate to form a floating diffusion region and a transition doped region in the substrate, to obtain the semiconductor structure; wherein the transition doped region is located between a projection of the transfer gate on the substrate and the floating diffusion region; a doping concentration of the floating diffusion region is greater than a doping concentration of the transition doped region; the transition doped region comprises a first doped region and a second doped region formed based on an ion implantation process; a doping type of the first doped region is different from a doping type of the floating diffusion region; a doping type of the second doped region is the same as the doping type of the floating diffusion region; along a normal direction of the substrate, an ion implantation depth of the second doped region is greater than an ion implantation depth of the first doped region.

[0011] Optionally, the semiconductor structure further comprises a first gate sidewall and a second gate sidewall; the step of performing ion implantation on the substrate to form a floating diffusion region and a transition doping region in the substrate to obtain the semiconductor structure comprises: performing a first ion implantation on the substrate; forming the first gate sidewall on the surface of the transfer gate and the surface of the substrate; wherein the material of the first gate sidewall is different from that of the substrate; performing at least two second ion implantations on the substrate; wherein the ion type of the second ion implantation is different from that of the first ion implantation; the implantation depth of the second ion implantation is greater than that of the first ion implantation; the implantation depths of the at least two second ion implantations are different; performing annealing on the substrate; forming the second gate sidewall on the side of the first gate sidewall away from the transfer gate and away from the substrate; performing a third ion implantation on the substrate to form the floating diffusion region on the side of the projection of the second gate sidewall on the substrate away from the projection of the transfer gate on the substrate, and to form a first doping region and a second doping region between the floating diffusion region and the projection of the transfer gate on the substrate to obtain the semiconductor structure; wherein the ion type of the third ion implantation is the same as that of the second ion implantation; the implantation dose of the third ion implantation is greater than that of the second ion implantation.

[0012] Optionally, the method further comprises: after the floating diffusion region is formed, performing a fourth ion implantation on the substrate so that the second doping region exists between the projection of the second gate sidewall on the substrate and the floating diffusion region; wherein the ion type of the fourth ion implantation is the same as that of the third ion implantation; the implantation energy of the fourth ion implantation is less than that of the second ion implantation and greater than that of the first ion implantation.

[0013] Optionally, the step of forming the transfer gate on the surface of the substrate comprises: forming a first transition gate on the surface of the substrate; performing a first gate ion implantation on the first transition gate to form a first gate doping region; wherein the first gate ion implantation on the first transition gate is completed in the same process step as the first ion implantation on the substrate; performing a second gate ion implantation on the first transition gate to form a second gate doping region to obtain the transfer gate; wherein the ion type of the second gate ion implantation is different from that of the first gate ion implantation; the width direction of the transfer gate is the direction perpendicular to the normal direction of the substrate; along the width direction of the transfer gate, the first gate doping region is located between the second gate doping region and the first gate sidewall.

[0014] Optionally, the step of forming the transfer gate on the substrate surface comprises: forming a gate material layer on the substrate surface; performing a third gate ion implantation on the gate material layer based on a gate ion implantation mask; etching and removing part of the gate material layer based on a gate etching mask to form a second transition gate; wherein the etching blocking size of the gate etching mask is greater than the implantation opening size of the gate ion implantation mask; performing annealing on the second transition gate to form the transfer gate; wherein the transfer gate comprises a third gate doped region; in the third gate doped region, the lower the doping concentration of the area closer to the first gate sidewall.

[0015] In yet another aspect, one embodiment of the present application provides an image sensor, comprising a semiconductor structure as described in the above embodiments or manufactured according to the manufacturing method of the semiconductor structure as described in the above embodiments.

[0016] In the embodiments provided in the present application, a transition doped region is formed between the projection of the transfer gate on the substrate surface and the floating diffusion region of the substrate, wherein the doping concentration of the transition doped region is less than the doping concentration of the floating diffusion region, the transition doped region comprises a first doped region and a second doped region formed based on an ion implantation process, the doping type of the first doped region is different from the doping type of the floating diffusion region, the doping type of the second doped region is the same as the doping type of the floating diffusion region, and the ion implantation depth of the second doped region is greater than the ion implantation depth of the first doped region along the normal direction of the substrate. The unexpected effects achieved include: since in the transition doped region, the ion implantation depth of the first doped region with a doping type different from that of the floating diffusion region is less than the ion implantation depth of the second doped region with a doping type the same as that of the floating diffusion region, the first doped region can be used to push the depletion region from the substrate surface to the inside of the substrate, optimize the electric field distribution of the substrate surface, and thus reduce the occurrence of gate-induced drain leakage, and improve the imaging quality of the CMOS image sensor. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0018] Figure 1 A circuit connection schematic diagram of a four-tube active pixel structure provided by the related art.

[0019] Figure 2 A structure schematic diagram of a transfer part in an existing four-tube active pixel structure provided by the related art.

[0020] Figure 3 A schematic diagram of a structure of a transfer part in a four-tube active pixel structure is provided for the related art.

[0021] Figure 4 A schematic diagram of forming an N-type ion implantation region is provided for the related art.

[0022] Figure 5 A schematic diagram of forming a lightly doped region is provided for the related art.

[0023] Figure 6 A schematic diagram of a partial electric field distribution in a region within a dashed line circle. Figure 2

[0024] A schematic diagram of a manufacturing method of a semiconductor structure is provided for an embodiment of the present application. Figure 7

[0025] A schematic diagram of a structure of a substrate is provided for an embodiment of the present application. Figure 8

[0026] A schematic diagram of a process of forming a transfer gate on a surface of a substrate is provided for an embodiment of the present application. Figure 9

[0027] A schematic diagram of forming a first transfer gate on a surface of a substrate is provided for an embodiment of the present application. Figure 10

[0028] A schematic diagram of performing a first ion implantation on a substrate is provided for an embodiment of the present application. Figure 11

[0029] A schematic diagram of forming a second gate doping region and a first ion implantation region is provided for an embodiment of the present application. Figure 12

[0030] A schematic diagram of a process of forming a transfer gate on a surface of a substrate is provided for another embodiment of the present application. Figure 13

[0031] A schematic diagram of forming a gate material layer on a surface of a substrate is provided for another embodiment of the present application. Figure 14

[0032] A schematic diagram of forming a gate implantation region in the gate material layer is provided for another embodiment of the present application. Figure 15

[0033] A schematic diagram of forming a second transfer gate is provided for another embodiment of the present application. Figure 16

[0034] A schematic diagram of forming a second transfer gate is provided for another embodiment of the present application. Figure 17 ​

[0035] Figure 18 A flow diagram of forming a floating diffusion region and a transition doped region in a substrate by ion implantation is provided for one embodiment of the application.

[0036] Figure 19 A diagram of performing a first ion implantation into a substrate is provided for another embodiment of the application.

[0037] Figure 20 A diagram of forming a first gate sidewall based on a first transfer gate is provided for one embodiment of the application.

[0038] Figure 21 A diagram of forming a first gate sidewall based on a second transfer gate is provided for another embodiment of the application.

[0039] Figure 22 A diagram of forming a second ion implantation region is provided for one embodiment of the application.

[0040] Figure 23 A diagram of forming a second ion implantation region is provided for another embodiment of the application.

[0041] Figure 24 A diagram of annealing a substrate having a second ion implantation region formed therein is provided for one embodiment of the application.

[0042] Figure 25 A diagram of annealing a substrate having a second ion implantation region formed therein is provided for another embodiment of the application.

[0043] Figure 26 A diagram of forming a second gate sidewall based on a first transfer gate is provided for one embodiment of the application.

[0044] Figure 27 A diagram of forming a second gate sidewall based on a second transfer gate is provided for another embodiment of the application.

[0045] Figure 28 A diagram of forming a floating diffusion region is provided for one embodiment of the application.

[0046] Figure 29 A diagram of forming a floating diffusion region is provided for another embodiment of the application.

[0047] Figure 30 A diagram of forming a first doped region and a second doped region is provided for one embodiment of the application.

[0048] Figure 31 A diagram of forming a first doped region and a second doped region is provided for another embodiment of the application.

[0049] Figure 32 A schematic diagram of a first semiconductor structure is provided for one embodiment of the present application.

[0050] Figure 33 A schematic diagram of a second semiconductor structure is provided for another embodiment of the present application.

[0051] Figure 34 A schematic diagram of forming a second ion implantation region is provided for one embodiment of the present application.

[0052] Figure 35 A schematic diagram of forming a transition doping region is provided for one embodiment of the present application.

[0053] Figure 36 A Figure 32 An enlarged schematic diagram of the local electric field distribution in the area enclosed by the dashed line.

[0054] Structure label explanation

[0055] 1, clamped photodiode; 2, floating diffusion region; 3, reset transistor; 4, transfer transistor; 5, source follower transistor; 6, select transistor; 7, P-type heavily doped region; 100, transfer part of existing four-tube active pixel structure; 100a, transfer part of improved four-tube active pixel structure; 101, P-type doped silicon substrate; 102, P-type well region; 103, floating diffusion doping region; 104, photodiode doping region; 105, shallow trench isolation structure; 106, pinning layer; 107, lightly doped region; 107a, N-type ion implantation region; 111, first side wall; 112, second side wall; 113, gate; 114, oxide layer; 200, first semiconductor structure; 201, substrate; 202, doped well region; 203, photodiode; 204, isolation structure; 205, heavily doped region; 2061, first ion implantation region; 2062, second ion implantation region; 207, floating diffusion region; 208, transition doping region; 2081, first doping region; 2082, second doping region; 211, gate oxide layer; 212, first transition gate; 213, first transfer gate; 2131, first gate doping region; 2132, second gate doping region; 2133, gate implantation region; 214, gate material layer; 215, third gate doping region; 216, first gate side wall; 217, second gate side wall; 221, gate etching mask; 222, gate ion implantation mask; 223, second ion implantation mask; 224, third ion implantation mask; 224', fourth ion implantation mask; 300, second semiconductor structure. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0057] The drawings provided in the embodiments of the present application only schematically illustrate the basic concept of the present application, and only show the components related to the present application in the drawings, but are not drawn according to the number, shape and size of the components in actual implementation. The shape, number and ratio of each component can be changed in actual implementation, and the component layout form can also be more complex.

[0058] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application, and do not indicate or imply that the indicated device or component must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first" and "second" can explicitly or implicitly include one or more of the features.

[0059] Please refer to Figure 1 In the related art, a four-tube active pixel structure can generally include two ion-doped regions for realizing photoelectric signal conversion and four transistors. Specifically, the two ion-doped regions can include a pinned photodiode (PPD) 1 for generating a photoelectric signal and a floating diffusion (FD) 2 for temporarily storing the charge generated by the photodiode and converting the charge signal into a voltage signal. The four transistors can include a reset transistor 3 for resetting the photodiode and the floating diffusion, a transfer transistor 4 for controlling the switch of the photo-generated charge transmission channel, i.e., a transfer gate (TG), a source follower transistor 5 for buffering and reading out the voltage signal of the floating diffusion, and a select transistor 6 for realizing row selection output. A P-type heavily doped region 7 for stabilizing the working state of the pinned photodiode 1 is formed on the side of the pinned photodiode 1 close to the transfer transistor 4.

[0060] The working process of the four-transistor active pixel structure can be divided into four stages: a reset stage, an integration stage, a transfer stage, and a read stage. In the reset stage, the reset transistor 3 is turned on, and the floating diffusion region 2 is reset to a voltage near the power supply voltage Vdd. In the integration stage, the reset transistor 3 is turned off, and the clamping photodiode 1 starts to accumulate photo-generated charges. In the transfer stage, the transfer transistor 4 is turned on, and the charges accumulated in the clamping photodiode 1 are transferred to the floating diffusion region 2. In the read stage, the select transistor 6 is turned on, and the source follower transistor 5 amplifies the voltage change of the floating diffusion region 2 and outputs it to the column line. The voltage change on the column line is collected by the readout circuit as the output voltage Vout and ultimately converted into an image signal.

[0061] However, as the application scenarios of CMOS image sensors employing the four-transistor active pixel structure continue to expand, researchers have found that abnormal bright spots that do not correspond to the actual lighting conditions often exist in the images output by the CMOS image sensors, leading to a decrease in the clarity and accuracy of the images. Analysis of the causes of the above problems shows that in the CMOS image sensor, some pixels may be converted into "white pixels" due to defects such as leakage, and "white pixels" usually exhibit abnormally high brightness, thereby appearing as abnormal bright spots in the output images.

[0062] Researchers have further explored the causes of "white pixels".

[0063] Please refer to Figure 2 In the transfer part 100 of the existing four-transistor active pixel structure, a P-type well region 102 for dividing the active area range and a shallow trench isolation (STI) structure for isolating different pixel regions are formed in a P-type doped silicon substrate 101, an oxide layer 114 is formed on the surface of the P-type doped silicon substrate 101, and a gate 113 of the transfer transistor is formed on the side of the oxide layer 114 away from the P-type doped silicon substrate 101. Specifically, in the active area divided by the P-type well region 102, a photodiode doped region 104, a floating diffusion doped region 103, a pinning layer 106 for achieving pinning between the photodiode doped region 104 and the oxide layer 114, and a lightly doped region 107 for reducing short channel effects are formed. Among them, the doping types of the photodiode doped region 104, the floating diffusion doped region 103, and the lightly doped region 107 can all be N-type, and the doping concentration of the lightly doped region 107 is less than that of the floating diffusion doped region 103. The doping type of the pinning layer 106 can be P-type. A first side wall 111 and a second side wall 112 are sequentially formed on the side of the gate 113 of the transfer transistor, and the materials of the first side wall 111 and the second side wall 112 are different.

[0064] The researchers found during the experiment that, in the case that the transfer transistor is in the off or standby state, there is a high voltage difference between the gate 113 of the transfer transistor and the floating diffusion doped region 103, i.e., the gate-drain voltage V GD is high, so that the electric field intensity near the overlapping area between the gate 113 of the transfer transistor and the floating diffusion doped region 103 is strong, which causes the electrons in the silicon between the projection of the gate 113 of the transfer transistor on the P-type doped silicon substrate 101 and the floating diffusion doped region 103 to undergo band-to-band tunneling (BTBT) between the valence band and the conduction band, forming a current from the floating diffusion doped region 103 to the bulk, which induces the gate-induced drain leakage (GIDL) phenomenon. The gate-induced drain leakage can increase the static power consumption of the transfer transistor, reduce the energy efficiency ratio of the transfer transistor, and also can cause the reliability of the transfer transistor to decrease, thereby causing the appearance of "white pixels".

[0065] To improve the gate-induced drain leakage problem of the transfer transistor, the researchers improved the structure of the transfer part 100 of the existing four-tube active pixel structure.

[0066] Please refer to Figure 3 . In the direction perpendicular to the normal direction of the P-type doped silicon substrate 101 as the width direction, the researchers increased the width of the second side wall 112 along the width direction, realized the increase of the distance between the projection of the gate 113 of the transfer transistor on the P-type doped silicon substrate 101 and the floating diffusion doped region 103, i.e., the increase of the width of the lightly doped region 107 along the width direction, thereby reducing the voltage difference between the gate 113 of the transfer transistor and the floating diffusion doped region 103. It can be seen from Figure 2 and Figure 3 that the width D2 of the lightly doped region 107 along the width direction in the improved four-tube active pixel structure transfer part 100a is greater than the width D1 of the lightly doped region 107 along the width direction in the existing four-tube active pixel structure transfer part 100.

[0067] However, in order to adapt to the trend of device thinning and miniaturization, the size requirement of CMOS image sensors is constantly shrinking. Forming a pixel array based on the improved four-tube active pixel will result in an increase in the area occupied by the CMOS image sensor, which is difficult to meet the current size requirements of CMOS image sensors.

[0068] To improve the gate-induced drain leakage of the transfer transistor without increasing the size of the CMOS image sensor, the researchers analyzed the lightly doped region 107 in the existing four-tube active pixel structure transfer part 100 as follows.

[0069] Please refer to Figure 4 and Figure 5 In the transfer part 100 of the existing four-tube active pixel structure, the lightly doped region 107 is formed by the following process: first, using the first side wall 111 as a mask, ion implantation is performed on the P-type doped silicon substrate 101 to form an N-type ion implantation region 107a, and then annealing is performed to diffuse the N-type ion implantation region 107a to form a lightly doped region 107 in the shape of an approximately elliptical shape. Since the doping type of the lightly doped region 107 is N-type, which is different from the doping type of the P-type well region 102, a PN junction with a spherical interface shape will be formed at the junction of the lightly doped region 107 and the P-type well region 102. At this time, the interface curvature of the PN junction is large, and the charge distribution is uneven. Correspondingly, the electric field may be concentrated in the area with large curvature, resulting in a stronger local electric field in the area with large curvature.

[0070] Please refer to Figure 6 In addition, in the case where the transfer transistor is in an off or standby state, an electric field will be formed near the lightly doped region 107 between the photodiode doped region and the floating diffusion doped region. The electrons and holes in the lightly doped region 107 move in different directions under the driving of the electric field force, forming a depletion region with a width of W1, and the boundary of the depletion region covers the intersection plane P1 of the P-type doped silicon substrate 101 and the oxide layer 114. However, due to the limitation of the process quality of the oxide layer 114, there may be vacancies, dislocations and other lattice defects at the P1 plane, which introduce defect energy levels in the forbidden band and form interface states. By analyzing the electric field distribution near the lightly doped region 107, it can be found that the electric field strength near the P1 plane is greater than that near the internal P2 plane of the P-type doped silicon substrate 101. Therefore, under the action of the stronger electric field, band-to-band tunneling effect may occur, and the electrons and holes may be captured and recombined at the defect energy levels at the internal P1 plane, resulting in leakage.

[0071] In summary, in the transfer part of the existing four-tube active pixel structure, the shape of the lightly doped region and the electric field distribution near the lightly doped region can exacerbate the gate-induced drain leakage problem.

[0072] Therefore, it is necessary to provide a semiconductor structure which can improve the gate-induced drain leakage of the transfer transistor without increasing the size of the CMOS image sensor.

[0073] Please refer to Figure 7 An embodiment of the present application provides a manufacturing method of a semiconductor structure. The manufacturing method of the semiconductor structure can include steps S110, S120 and S130.

[0074] S110: providing a substrate.

[0075] Please refer to Figure 8In this embodiment, the substrate can include a substrate 201, a doped well region 202 formed in the substrate 201, a photodiode 203, an isolation structure 204, and a heavily doped region 205. The specific description of each part of the substrate is as follows.

[0076] In this embodiment, the substrate 201 can be used as the basis for forming the semiconductor structure. Specifically, the substrate 201 can be made of semiconductor material, insulating material, conductor material, or any combination thereof. For example, the substrate 201 can be made of silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), etc. The substrate 201 can be a single-layer structure or a multi-layer structure. In this embodiment, taking into account factors such as dielectric loss requirements, manufacturing process, and manufacturing cost, a silicon wafer doped with P-type ions is used as the substrate 201 to reduce the resistance of the substrate 201.

[0077] In this embodiment, the doped well region 202 and the isolation structure 204 can be used to determine the range of the active region and achieve isolation between different pixels. Specifically, the positions of the plurality of isolation structures 204 can be defined in the substrate 201 first, and the substrate material at these positions can be etched away, and the isolation material can be filled into the grooves where the substrate material has been removed to form a plurality of mutually spaced isolation structures 204. Subsequently, ion implantation can be performed in the spacing region between adjacent isolation structures 204 to form the doped well region 202. The doped well region 202 can be P-type, and the isolation material can be oxide.

[0078] In this embodiment, the photodiode 203 can be used to achieve photoelectric conversion, and the heavily doped region 205 can be used to fix the potential on the surface of the photodiode 203 and achieve isolation between the photodiode 203 and the structure on the surface of the substrate. Specifically, the doping type of the photodiode 203 and the doping type of the heavily doped region 205 can be different, and the doping concentration of the heavily doped region 205 can be greater than the doping concentration of the photodiode 203. For example, the doping type of the photodiode 203 can be N-type, and the doping type of the heavily doped region 205 can be P-type.

[0079] S120: Form a transfer gate on the surface of the substrate.

[0080] In this embodiment, the transfer gate can be used to control the charge transfer between the photodiode and the floating diffusion region. Specifically, under the condition that the transfer gate is applied with a certain voltage, an electron transfer channel between the photodiode and the floating diffusion region will be formed, and under the condition that the transfer gate is not applied with voltage, the transfer gate can achieve isolation between the photodiode and the floating diffusion region to reduce the charge leakage or interference therebetween.

[0081] The researchers found in the experiment and test process that, in addition to the distance between the projection of the transfer gate on the substrate and the floating diffusion region, the coupling electric field strength between the transfer gate and the floating diffusion region is also affected by the resistance value of the edge of the transfer gate. Therefore, in order to weaken the coupling electric field strength between the transfer gate and the floating diffusion region, in the process of preparing the transfer gate, the doping distribution in the transfer gate can be changed by adding a reverse-type doping region or a gradually changing doping in the transfer gate, increasing the resistance value of the edge of the transfer gate, and improving the gate-induced drain leakage problem.

[0082] Please refer to Figure 9 In this embodiment, the step of forming the transfer gate on the substrate surface can include sub-steps S1211, S1221 and S1231.

[0083] S1211: Form a first transition gate on the substrate surface.

[0084] Please refer to Figure 10 To achieve electrical insulation between the transfer gate and the substrate, a gate oxide layer 211 can be formed on the substrate surface before preparing the transfer gate, and then a gate material layer is formed on the side of the gate oxide layer 211 away from the substrate. A part of the gate material layer is removed based on the gate etching mask 221 by using a photolithography process and an etching process to form the first transition gate 212. Specifically, the material of the gate oxide layer 211 can be silicon oxide (SiO2). In the direction perpendicular to the normal direction of the substrate as the width direction, along the width direction, the etching blocking size of the gate etching mask 221 can be equal to the critical dimension (CD) of the preset transfer gate, so that the width of the first transition gate 212 formed along the width direction can be equal to the critical dimension of the transfer gate, and the projection of the first transition gate 212 on the substrate can partially overlap with the heavily doped region 205. To fully play the blocking role of the gate etching mask 221, in this embodiment, the gate etching mask 221 on the side of the first transition gate 212 away from the substrate can be reserved after the first transition gate 212 is formed.

[0085] S1221: Perform first gate ion implantation on the first transition gate to form a first gate doping region.

[0086] Please refer to Figure 11 and Figure 12. To reduce the process cost and shorten the processing time, the first gate ion implantation can be performed on the first transition gate 212 based on the reserved gate etching mask 221, and by controlling the direction of ion implantation, the first ion implantation on the substrate is realized in the same process step, thereby forming the first gate doped region 2131 at the side edge portion of the first transition gate 212 and forming the first ion implantation region 2061 in the substrate. Specifically, the implantation ion type of the first gate ion implantation and the first ion implantation can be P type. For example, the implantation ion of the first gate ion implantation and the first ion implantation can be boron fluoride (BF2) ion, the ion implantation energy can be 10 KeV, the ion implantation dose can be 1.0×10 13 ions / cm², the rotation angle of ion implantation can be 30°, the inclination angle can be 0°, and the implantation times can be 4 times.

[0087] S1231: performing second gate ion implantation on the first transition gate to form a second gate doped region, and obtaining a transmission gate.

[0088] Please continue to refer to Figure 12 . To enhance the conductivity of the transmission gate and reduce the overall resistance of the transmission gate, after the first gate doped region 2131 is formed, the second gate ion implantation can be performed on the whole first transition gate 212, thereby forming the second gate doped region 2132 in the part of the first transition gate 212 except the side edge portion, and obtaining the first transmission gate 213. Specifically, the ion implantation dose of the second gate ion implantation can be greater than the ion implantation dose of the first gate ion implantation, and the implantation ion type of the second gate ion implantation is different from the implantation ion type of the first gate ion implantation, therefore, the doping type of the second gate doped region 2132 is different from the doping type of the first gate doped region 2131. For example, in the case that the implantation ion type of the first gate ion implantation is P type, the implantation ion type of the second gate ion implantation can be N type. The other process parameters used in the second gate ion implantation are the transmission gate ion implantation process parameters commonly used in the related art, which are not described here.

[0089] Because the implantation ion types of the two times of gate ion implantation are different, and the ion implantation dose of the second gate ion implantation is greater than the ion implantation dose of the first gate ion implantation, during the second gate ion implantation, part of the ions implanted into the side edge portion of the first transition gate 212 combine with part of the ions in the previously formed first gate doped region 2131, so that the doping concentration of the formed second gate doped region 2132 is greater than the doping concentration of the first gate doped region 2131, that is, along the width direction, the doping concentration of the first transmission gate 213 gradually decreases from the center to the edge.

[0090] Please refer to Figure 13In some embodiments, the step of forming the transfer gate on the substrate surface can include sub-steps S1212, S1222, S1232 and S1242.

[0091] S1212: Forming a gate material layer on the substrate surface.

[0092] S1222: Performing a third gate ion implantation to the gate material layer based on the gate ion implantation mask.

[0093] Please refer to Figure 14 and Figure 15 In the present embodiment, the process of forming the gate oxide layer 211 and the gate material layer 214 is substantially the same as that in the above-mentioned embodiments, and thus will not be described herein. A third gate ion implantation can be performed to the gate material layer based on the gate ion implantation mask 222, so as to form a gate implantation region 2133 in the gate material layer 214. Specifically, taking the direction perpendicular to the normal direction of the substrate as the width direction, along the width direction, the implantation opening size of the gate ion implantation mask 222 can be smaller than the critical dimension of the transfer gate, so that the width of the gate implantation region 2133 formed along the width direction is smaller than the critical dimension of the transfer gate, thereby providing a basis for the subsequent formation of the second transfer gate gradual doping. 14 For example, the implantation ions of the third gate ion implantation can be phosphorus (P) ions, the ion implantation energy can be 10 KeV, the ion implantation dose can be 1.0×10

[0094] S1232: Etching and removing part of the gate material layer based on the gate etching mask to form a second transfer gate.

[0095] Please refer to Figure 16 After the formation of the gate implantation region 2133, part of the gate material layer 214 and the gate oxide layer 211 can be etched and removed based on the gate etching mask 221 to form a second transfer gate. Specifically, along the width direction, since the implantation opening size of the gate ion implantation mask 222 is smaller than the critical dimension of the transfer gate, the etching blocking size of the gate etching mask 221 can be larger than the implantation opening size of the gate ion implantation mask 222, so as to form a doping distribution in the second transfer gate, in which the doping concentration in the central part is relatively high, and the doping concentration in the side edge part is close to zero. The process parameters for etching and removing part of the gate material layer 214 are the process parameters commonly used in the related art for etching the transfer gate, and thus will not be described herein.

[0096] S1242: Annealing the second transfer gate to form a transfer gate.

[0097] Referring to Figure 17 To enhance the conductivity of the transfer gate, while keeping the side edge of the transfer gate having a higher resistance, the second transfer gate can be annealed to diffuse the dopant ions in the gate implant region to the side edge of the second transfer gate which is not doped, and then the gate etching mask on the surface of the second transfer gate is removed to obtain the second transfer gate. Specifically, the second transfer gate can include a third gate doping region 215, i.e., an ion doping region in the second transfer gate. In the third gate doping region 215, the doping concentration gradually decreases from the center to the edge along the width direction.

[0098] S130: performing ion implantation on the substrate to form a floating diffusion region and a transition doping region in the substrate to obtain a semiconductor structure.

[0099] In the embodiment, the floating diffusion region can be used to receive and temporarily store the charges transferred from the photodiode, and convert the received charges into a voltage signal.

[0100] In the embodiment, the transition doping region can be used to reduce the electric field intensity near the floating diffusion region, and suppress the short channel effect. Specifically, the transition doping region can be located between the projection of the transfer gate on the substrate and the floating diffusion region. The transition doping region can include a first doping region and a second doping region formed based on an ion implantation process.

[0101] In the embodiment, the first doping region can be used to optimize the electric field distribution in the substrate when the transfer transistor is in an off or standby state. Specifically, the doping type of the first doping region can be different from the doping type of the floating diffusion region. For example, when the doping type of the floating diffusion region is N-type, the doping type of the first doping region can be P-type.

[0102] In the embodiment, the second doping region can be used to reduce the curvature of the PN junction interface near the floating diffusion region, and improve the local electric field concentration of the PN junction interface. Specifically, the interface between the second doping region and the doping well region can be approximately planar. The doping type of the second doping region can be the same as the doping type of the floating diffusion region, and accordingly, the doping type of the second doping region is different from the doping type of the first doping region. Moreover, the ion implantation depth of the second doping region is greater than the ion implantation depth of the first doping region along the normal direction of the substrate, so that the first doping region can be used to isolate the second doping region and the gate oxide layer on the surface of the substrate to a certain extent, and the depletion region near the floating diffusion region is pushed away from the interface plane between the substrate and the gate oxide layer on the surface of the substrate, thereby reducing the occurrence of band-to-band tunneling effect.

[0103] Referring to Figure 18In the present embodiment, the step of performing ion implantation on the substrate to form the floating diffusion region and the transition doped region in the substrate can include sub-steps S131, S132, S133, S134, S135 and S136.

[0104] S131: performing first ion implantation on the substrate.

[0105] After performing the first ion implantation on the substrate, a first ion implantation region for forming the first doped region can be formed on the substrate at a side of the projection of the transfer gate away from the heavily doped region. Wherein, the projection of the transfer gate on the substrate can partially overlap with the first ion implantation region.

[0106] For further reference, please refer to Figure 12 In the present embodiment, in the process of preparing the floating diffusion region and the transition doped region based on the substrate on which the first transfer gate has been formed, the first ion implantation and the first gate ion implantation can be implemented in the same process step, thus the process parameters of the first ion implantation are the same as the process parameters of the first gate ion implantation, which will not be described herein.

[0107] For further reference, please refer to Figure 19 In some embodiments, in the process of preparing the floating diffusion region and the transition doped region based on the substrate on which the second transfer gate has been formed, the implantation ion type of the first ion implantation can be P type. For example, in the case of performing the first ion implantation on the substrate on which the second transfer gate has been formed, the process parameters of the first ion implantation can include: the implantation ion is boron fluoride (BF2) ion, the ion implantation energy is 10 KeV, the ion implantation dose is 1.0 x 1013ions / cm2, the rotation angle of the ion implantation is 30°, the inclination angle is 0°, and the implantation times is 4. 13

[0108] S132: forming a first gate sidewall on the surface of the transfer gate and the surface of the substrate.

[0109] In order to reduce the damage of the high-concentration ion implantation process step for forming the floating diffusion region and the transition doped region to the first ion implantation region, a first gate sidewall covering the surface of the transfer gate and the surface of the substrate can be formed.

[0110] For further reference, please refer to Figure 20 and Figure 21 ​In the embodiment, the first gate sidewall 216 can be formed based on a thin film growth process such as vapor deposition, molecular beam epitaxy, etc. The first gate sidewall 216 is different from the material of the substrate 201. Specifically, the process of forming the first gate sidewall 216 based on the first transfer gate 213 and the process of forming the first gate sidewall 216 based on the second transfer gate are basically the same. The material of the first gate sidewall 216 can include silicon oxide and silicon nitride (Si3N4). Since the materials are the same, the gate oxide layer 211 can be part of the first gate sidewall 216. A silicon oxide layer can be formed on the surface of the substrate first, and then a silicon nitride layer can be formed on the side of the silicon oxide layer away from the substrate. In the growth direction of the first gate sidewall 216 as the thickness direction of the first gate sidewall 216, the thickness of the silicon oxide layer can be less than the thickness of the silicon nitride layer. The thickness of the silicon oxide layer can fall within the range of 25Å~35Å, and the thickness of the silicon nitride layer can fall within the range of 75Å~85Å. For example, the thickness of the silicon oxide layer can be 25Å, 30Å, 35Å, and the thickness of the silicon nitride layer can be 75Å, 80Å, 85Å.

[0111] S133: Perform at least two second ion implantations on the substrate.

[0112] To optimize the electric field distribution in the substrate and improve the local electric field concentration at the PN junction interface near the floating diffusion region, at least two second ion implantations can be performed on the substrate under the blocking effect of the first gate sidewall after the first gate sidewall is formed, thereby forming at least two second ion implantation regions distributed along the normal direction of the substrate on the side of the projection of the transfer gate on the substrate away from the heavily doped region.

[0113] Please refer to Figure 22 and Figure 23 In the embodiment, the implantation ion type of the second ion implantation is different from the implantation ion type of the first ion implantation, the implantation depth of the second ion implantation can be greater than the implantation depth of the first ion implantation, and the implantation depths of the at least two second ion implantations are different. Specifically, the process and process parameters of performing the second ion implantation on the substrate formed with the first transfer gate 213 and performing the second ion implantation on the substrate formed with the second transfer gate are basically the same. In the case that the implantation ion type of the first ion implantation is P type, the implantation ion type of the second ion implantation can be N type. The process parameters such as implantation ion type, ion implantation dose, and ion implantation angle of the at least two second ion implantations can remain unchanged, and the ion implantation depths of different second ion implantations can be made different by changing the ion implantation energy. Taking the case of performing two second ion implantations as an example, the implantation ions of the two second ion implantations can both be phosphorus (P) ions, the ion implantation dose can both be 1.0×1016 ions / cm2, and the ion implantation angle can both be 7°. The ion implantation energy of the first second ion implantation can be 60 keV, and the ion implantation energy of the second second ion implantation can be 80 keV. 13The ion implantation rate is ions / cm², and the rotation angle and tilt angle can both be 0°. The number of implantation cycles can both be 4. The ion implantation energy for the first and second ion implantations can be 40 keV, and the ion implantation energy for the second and second ion implantations can be 20 keV.

[0114] S134: Anneal the substrate.

[0115] To improve the doping distribution in the first and second ion implantation regions and reduce lattice defects inside the substrate, the substrate can be annealed after the first and second ion implantation regions are formed in the substrate.

[0116] Please refer to the following: Figure 24 and Figure 25 In this embodiment, the annealing process and process parameters for the substrate with the first transmission gate 213 and the substrate with the second transmission gate are basically the same. Specifically, a rapid thermal processing (RTP) process can be used to anneal the substrate at a temperature of 1050°C to activate the dopant and repair the lattice while reducing excessive diffusion. The annealing time can be 20 seconds to reduce the negative effects of prolonged heating while achieving a certain activation and repair effect.

[0117] S135: A second gate sidewall is formed on the side of the first gate sidewall that is away from the transmission gate and away from the substrate.

[0118] To protect the transport gate during subsequent high-energy ion implantation processes and to provide an alignment reference for subsequent ion implantation processes, a second gate sidewall can be formed on the side of the first gate sidewall that is away from the transport gate and away from the substrate.

[0119] Please refer to the following: Figure 26 and Figure 27In the embodiment, the second gate sidewall 217 can be formed by a deposition process and an etching process. Specifically, the process procedure and process parameters for forming the second gate sidewall 217 based on the first transfer gate 213 are substantially the same as those for forming the second gate sidewall 217 based on the second transfer gate. For example, a layer of second gate sidewall material can be formed on the side of the first gate sidewall 216 away from the transfer gate and away from the substrate by a chemical vapor deposition (CVD) process, and then a part of the layer of second gate sidewall material can be removed by an anisotropic etching process to form the second gate sidewall 217. The second gate sidewall 217 can include a silicon oxide layer and a silicon nitride layer. The thickness of the silicon oxide layer can be less than the thickness of the silicon nitride layer. The thickness of the silicon oxide layer can fall within a range from 75 Å to 85 Å, and the thickness of the silicon nitride layer can fall within a range from 440 Å to 460 Å. For example, the thickness of the silicon oxide layer can be 75 Å, 80 Å or 85 Å, and the thickness of the silicon nitride layer can be 440 Å, 450 Å or 460 Å.

[0120] S136: performing a third ion implantation on the substrate to form a floating diffusion region on the side of the projection of the second gate sidewall on the substrate away from the projection of the transfer gate on the substrate, and to form a first doped region and a second doped region between the floating diffusion region and the projection of the transfer gate on the substrate, to obtain a semiconductor structure.

[0121] To increase the distance between the floating diffusion region and the transfer gate, enhance the withstand voltage of the floating diffusion region, and reduce gate-induced drain leakage, a third ion implantation can be performed on the substrate to form the floating diffusion region after the second gate sidewall is formed, and the doping range of the floating diffusion region is controlled by means of the third ion implantation mask.

[0122] For reference, please also refer to Figure 28 and Figure 29 In the embodiment, the implantation ion type of the third ion implantation is the same as the implantation ion type of the second ion implantation, and the implantation dose of the third ion implantation is greater than the implantation dose of the second ion implantation. Specifically, the process procedure and process parameters for performing the third ion implantation on the substrate with the first transfer gate 213 and for performing the third ion implantation on the substrate with the second transfer gate are substantially the same. To reduce the size of the floating diffusion region 207 along the width direction, the distance between the projection edge of the third ion implantation mask 224 on the substrate and the heavily doped region 205 can be greater than the distance between the projection edge of the second gate sidewall 217 on the substrate and the heavily doped region 205. In the case where the implantation ion type of the second ion implantation is N type, the implantation ion type of the third ion implantation can also be N type. For example, the process parameters of the third ion implantation can include: the implantation ion is arsenic (As) ion, the ion implantation energy is 20 KeV, and the ion implantation dose is 1.0×1016 ions / cm2. 15ions / cm², the rotation angle of ion implantation is 0°, the tilt angle of ion implantation is 0°, and the number of implantation is 4 times.

[0123] Please refer to Figure 30 and Figure 31 In order to reduce the number of process steps, shorten the process time, and save the process cost, in the embodiment, after the floating diffusion region 207 is formed by the third ion implantation, the third ion implantation mask 224 can be trimmed to obtain a fourth ion implantation mask 224', wherein the distance between the projection edge of the substrate and the heavily doped region 205 of the fourth ion implantation mask 224' can be equal to the distance between the projection edge of the substrate and the heavily doped region 205 of the second gate side wall 217. Subsequently, the fourth ion implantation can be performed on the substrate based on the fourth ion implantation mask 224', so that the second doped region 2082 exists between the projection of the second gate side wall 217 on the substrate and the floating diffusion region 207, to reduce the possible PN junction at the interface between the substrate and the first gate side wall 216. Specifically, the process procedure and process parameters of the fourth ion implantation performed on the substrate with the first transfer gate 213 and the fourth ion implantation performed on the substrate with the second transfer gate are basically the same. The implantation ion type of the fourth ion implantation can be the same as the implantation ion type of the third ion implantation, and in the case that the implantation ion type of the third ion implantation is N type, the implantation ion type of the third ion implantation can be N type. The implantation energy of the fourth ion implantation can be less than the implantation energy of the second ion implantation and greater than the implantation energy of the first ion implantation. For example, the process parameters of the fourth ion implantation can include: the implantation ion is arsenic (As) ion, the ion implantation energy is 15 KeV, the ion implantation dose is 1.0×1013 ions / cm², the rotation angle of ion implantation is 0°, the tilt angle of ion implantation is 0°, and the number of implantation is 4 times. 13 ions / cm², the rotation angle of ion implantation is 0°, the tilt angle of ion implantation is 0°, and the number of implantation is 4 times.

[0124] After the fourth ion implantation is completed, the second doped region 2082 with the same doping type as the floating diffusion region 207 can be formed between the projection edge of the second gate side wall 217 on the substrate and the floating diffusion region 207, and the first doped region 2081 with a different doping type from the floating diffusion region 207 can be formed on the side of the second doped region 2082 away from the floating diffusion region 207, and the transition doped region 208 is composed of the second doped region 2082 and the first doped region 2081.

[0125] Please refer to Figures 32 to 33 After the transition doped region 208 is formed, the fourth ion implantation mask can be removed to obtain the first semiconductor structure 200 including the first transfer gate 213, or the second semiconductor structure 300 including the second transfer gate.

[0126] Please refer to Figure 34 andFigure 35 In the semiconductor structure provided by the embodiment of the present application, the transition doped region is formed by the following process: first, a first ion implantation region 2061 is formed by performing ion implantation into the doped well region 202 of the substrate with the transfer gate as a mask. Then, at least two second ion implantation regions 2062 are formed by performing ion implantation into the doped well region 202 of the substrate with the first gate sidewall 216 as a mask, and the at least two second ion implantation regions 2062 are distributed along the normal direction of the substrate. Subsequently, annealing is performed to diffuse the at least two second ion implantation regions 2062 to form a first doped region 2081 and a second doped region 2082 which is approximately in the shape of the intersection of at least two ellipses. By optimizing the process parameters such as ion implantation energy, ion implantation dose and annealing temperature, the morphology of the second doped region 2082 can be controlled, so that a PN junction with an interface approximately in the shape of a plane is formed at the junction of the second doped region 2082 and the doped well region 202. At this time, the curvature of the interface of the PN junction is small, the charge distribution is uniform, and accordingly, the local electric field is weak. In addition, since the first doped region 2081 and the second doped region 2082 are of different doping types, on the basis that the junction of the second ion implantation region 2062 and the doped well region 202 is approximately in the shape of a plane, the depletion region boundary in the transition doped region 208 can be pushed away from the substrate surface and moved towards the interior of the substrate by the first doped region 2081.

[0127] For further details, please refer to Figure 36 . Taking the first semiconductor structure 200 as an example, in the case that the transfer transistor is in the off state or standby state, an electric field is formed near the transition doped region 208 between the photodiode and the floating diffusion region, and the electrons and holes in the transition doped region 208 move in different directions under the driving of the electric field force, forming a depletion region with a width of W2. Although the boundary of the depletion region covers the junction plane P3 of the substrate and the first gate sidewall 216, the peak of the electric field strength of the electric field near the transition doped region 208 appears at the internal plane P4 of the substrate due to the influence of the first doped region 2081, thereby reducing the electrons and holes that recombine at the P3 plane, lowering the probability of band-to-band tunneling effect, and improving the gate-induced drain leakage phenomenon.

[0128] For further details, please refer to Figure 32 and Figure 33 The semiconductor structure provided by another embodiment of the present application can include a substrate, a transfer gate formed on the surface of the substrate, a floating diffusion region 207 and a transition doped region 208 formed in the substrate.

[0129] In the embodiment, the transition doped region 208 can be located between the projection of the transfer gate on the substrate and the floating diffusion region 207. Specifically, the doping concentration of the transition doped region 208 can be less than the doping concentration of the floating diffusion region 207. The transition doped region 208 can include a first doped region 2081 and a second doped region 2082 formed based on an ion implantation process. The first doped region 2081 has a different doping type from the doping type of the floating diffusion region 207, and the second doped region 2082 has the same doping type as the doping type of the floating diffusion region 207. In the normal direction of the substrate, the ion implantation depth of the second doped region 2082 is greater than the ion implantation depth of the first doped region 2081.

[0130] To reduce the damage to the doped regions in the substrate caused by the high-concentration ion implantation process for forming the floating diffusion region 207 and the transition doped region 208, in the embodiment, the semiconductor structure can further include a first gate side wall 216 formed on the side surface of the transfer gate and the surface of the substrate, and a second gate side wall 217 formed on the side of the first gate side wall 216 away from the transfer gate and away from the substrate. Specifically, the first gate side wall 216 has a material different from the substrate. The first doped region 2081 can be present between the projection of the second gate side wall 217 on the substrate and the floating diffusion region 207.

[0131] To increase the edge resistance of the transfer gate, reduce the potential at the edge of the transfer gate, weaken the coupling electric field intensity between the transfer gate and the floating diffusion region 207, and improve the gate-induced drain leakage phenomenon, in the embodiment, the transfer gate can include a first gate doped region 2131 and a second gate doped region 2132. Specifically, taking the direction perpendicular to the normal direction of the substrate as the width direction of the transfer gate, along the width direction of the transfer gate, the first gate doped region 2131 is located between the second gate doped region 2132 and the first gate side wall 216. The doping type of the first gate doped region 2131 is different from the doping type of the second gate doped region 2132. For example, the doping type of the first gate doped region 2131 can be P-type, and correspondingly, the doping type of the second gate doped region 2132 can be N-type.

[0132] Alternatively, in some embodiments, the transfer gate can include a third gate doped region 215. Specifically, in the third gate doped region 215, the doping concentration of the region closer to the first gate side wall 216 is lower.

[0133] The semiconductor structure described in the above embodiments has other technical effects, which can be explained by referring to other embodiments of the present application, and will not be described here in detail.

[0134] In the semiconductor structure provided by the embodiment of the present application, a transition doped region is formed between the projection of the transfer gate on the surface of the substrate and the floating diffusion region, wherein the doping concentration of the transition doped region is less than the doping concentration of the floating diffusion region, the transition doped region includes a first doped region and a second doped region formed based on an ion implantation process, the doping type of the first doped region is different from the doping type of the floating diffusion region, the doping type of the second doped region is the same as the doping type of the floating diffusion region, and in the normal direction of the substrate, the ion implantation depth of the second doped region is greater than the ion implantation depth of the first doped region. The unexpected effects achieved include that the interface shape of the PN junction at the interface between the second doped region and the doped well region can be improved, the charge distribution can be optimized, the depletion region can be pushed from the surface of the substrate to the inside of the substrate by the first doped region, the electric field distribution near the transition doped region can be optimized, the occurrence of gate-induced drain leakage can be reduced, and the imaging quality of the CMOS image sensor can be improved.

[0135] It can be understood that the specific examples in the present application are only to help those skilled in the art better understand the embodiments of the present application, and not to limit the scope of the present application.

[0136] It can be understood that in various embodiments in the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0137] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0138] Unless otherwise specified, all technical and scientific terms used in the embodiments of the present application have the same meanings as those commonly understood by those skilled in the art of the present application. The terms used in the present application are only for the purpose of describing the specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0139] In several embodiments provided by the present application, it should be understood that the disclosed semiconductor structure and image sensor can be implemented in other ways. For example, the above-described embodiments of the semiconductor structure and the image sensor are only illustrative.

[0140] The above merely provides the specific examples of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A transmission gate formed on the surface of the substrate; A floating diffusion region and a transition doped region are formed within the substrate; wherein the transition doped region is located between the projection of the transfer gate onto the substrate and the floating diffusion region; the doping concentration of the transition doped region is less than the doping concentration of the floating diffusion region; the transition doped region includes a first doped region and a second doped region formed by an ion implantation process; the doping type of the first doped region is different from the doping type of the floating diffusion region; the doping type of the second doped region is the same as the doping type of the floating diffusion region; along the normal direction of the substrate, the ion implantation depth of the second doped region is greater than the ion implantation depth of the first doped region.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: A first gate sidewall is formed on the side of the transmission gate and the surface of the substrate; wherein the first gate sidewall is made of a different material than the substrate; A second gate sidewall is formed on the side of the first gate sidewall that is away from the transport gate and away from the substrate; the first doped region exists between the projection of the second gate sidewall onto the substrate and the floating diffusion region.

3. The semiconductor structure according to claim 2, characterized in that, The transmission gate includes a first gate doped region and a second gate doped region; wherein, the direction perpendicular to the normal direction of the substrate is taken as the width direction of the transmission gate, and along the width direction of the transmission gate, the first gate doped region is located between the second gate doped region and the first gate sidewall; the doping type of the first gate doped region is different from the doping type of the second gate doped region.

4. The semiconductor structure according to claim 2, characterized in that, The transport gate includes a third gate doped region; in the third gate doped region, the doping concentration is lower in the region closer to the first gate sidewall.

5. A method for manufacturing a semiconductor structure, characterized in that, The method includes: Provide a base; A transmission gate is formed on the surface of the substrate; The substrate is ion implanted to form a floating diffusion region and a transition doped region within the substrate, thereby obtaining the semiconductor structure. The transition doped region is located between the projection of the transfer gate onto the substrate and the floating diffusion region. The doping concentration of the floating diffusion region is greater than that of the transition doped region. The transition doped region includes a first doped region and a second doped region formed by the ion implantation process. The doping type of the first doped region is different from that of the floating diffusion region. The doping type of the second doped region is the same as that of the floating diffusion region. Along the normal direction of the substrate, the ion implantation depth of the second doped region is greater than that of the first doped region.

6. The method according to claim 5, characterized in that, The semiconductor structure further includes a first gate sidewall and a second gate sidewall; the step of performing ion implantation on the substrate to form a floating diffusion region and a transition doped region within the substrate to obtain the semiconductor structure includes: A first ion implantation is performed on the substrate; A first gate sidewall is formed on the surface of the transmission gate and the surface of the substrate; wherein the first gate sidewall is made of a different material than the substrate; At least two second ion implantations are performed on the substrate; wherein the type of implanted ions in the second ion implantation is different from the type of implanted ions in the first ion implantation; the implantation depth of the second ion implantation is greater than the implantation depth of the first ion implantation; and the implantation depths of the at least two second ion implantations are different. The substrate is annealed; A second gate sidewall is formed on the side of the first gate sidewall that is away from the transmission gate and away from the substrate; A third ion implantation is performed on the substrate, and a floating diffusion region is formed on the side of the second gate sidewall on the substrate away from the projection of the transport gate on the substrate. A first doped region and a second doped region are formed between the floating diffusion region and the projection of the transport gate on the substrate to obtain the semiconductor structure. The implanted ion type of the third ion implantation is the same as that of the second ion implantation, and the implantation dose of the third ion implantation is greater than that of the second ion implantation.

7. The method according to claim 6, characterized in that, The method further includes: After the floating diffusion region is formed, a fourth ion implantation is performed on the substrate, such that a second doped region exists between the projection of the second gate sidewall onto the substrate and the floating diffusion region; wherein the implanted ion type of the fourth ion implantation is the same as that of the third ion implantation; the implantation energy of the fourth ion implantation is less than that of the second ion implantation and greater than that of the first ion implantation.

8. The method according to claim 6, characterized in that, The step of forming a transmission gate on the surface of the substrate includes: A first transition gate is formed on the surface of the substrate; A first gate ion implantation is performed on the first transition gate to form a first gate doped region; wherein, the first gate ion implantation on the first transition gate and the first ion implantation on the substrate are performed in the same process step; A second gate ion implantation is performed on the first transition gate to form a second gate doped region, thereby obtaining the transport gate; wherein the implanted ion type of the second gate ion implantation is different from that of the first gate ion implantation; the width direction of the transport gate is defined as the direction perpendicular to the normal direction of the substrate, and the first gate doped region is located between the second gate doped region and the first gate sidewall along the width direction of the transport gate.

9. The method according to claim 6, characterized in that, The step of forming a transmission gate on the surface of the substrate includes: A gate material layer is formed on the surface of the substrate; A third gate ion implantation is performed on the gate material layer based on the gate ion implantation mask; A second transition gate is formed by etching away part of the gate material layer using a gate etching mask; wherein the etching barrier size of the gate etching mask is larger than the implantation opening size of the gate ion implantation mask. The second transition gate is annealed to form the transport gate; wherein the transport gate includes a third gate doped region; in the third gate doped region, the doping concentration is lower in the region closer to the first gate sidewall.

10. An image sensor, characterized in that, The image sensor includes a semiconductor structure as described in any one of claims 1 to 4 or a semiconductor structure manufactured according to a method for manufacturing a semiconductor structure as described in any one of claims 5 to 9.

Images