A POI substrate based on Si-SiC-graphene substrate and a preparation method thereof

Abstract

The application discloses a POI substrate based on a Si-SiC-graphene substrate and a preparation method thereof, and belongs to the technical field of POI substrate preparation. The method comprises the following steps: (1) performing step-by-step C ion implantation on a Si substrate to obtain a wafer implantation sheet sequentially comprising a film layer, an implantation layer and a residual layer; (2) performing annealing repair on a support substrate, and then performing high-temperature heating treatment to form a Si-SiC-graphene mixed layer; (3) bonding the support substrate and the wafer implantation sheet to obtain a bonded body; and (4) heating the bonded body to separate the film layer and the residual layer, thereby obtaining a POI substrate. The POI substrate prepared by the method comprises the film layer, the Si-SiC-graphene mixed layer and a Si layer, has the advantages of reducing the cracking risk of the POI substrate, reducing warping, improving the bonding strength and reducing the production cost, and promotes the industrialization process of high-performance filters.

Description

TECHNICAL FIELD

[0001] The application relates to a POI substrate based on a Si-SiC-graphene substrate and a preparation method thereof, and belongs to the technical field of POI substrate preparation. BACKGROUND

[0002] The third-generation semiconductor industry is facing major challenges: the growth rate of SiC crystals is slow, the wafer yield is less than 30%, and large-size wafer preparation is difficult, which leads to high production costs. At the same time, the high hardness of SiC makes it difficult to process devices, resulting in a substantial increase in production costs.

[0003] In the patent CN119252733A, the Si substrate is processed into a composite substrate including a Si layer, a SiO2 layer and a SiC layer which are sequentially stacked by O ion implantation and C ion implantation on the Si substrate. However, the composite substrate mainly uses the formed SiC layer to bond with the SiC substrate, changes the hetero-bonding of the Si substrate and the SiC substrate into homo-bonding, to avoid the problems of large lattice mismatch and thermal expansion mismatch caused by hetero-bonding. When the composite substrate is bonded with a piezoelectric wafer made of lithium tantalate / lithium niobate, the problem of hetero-bonding still exists, and it is difficult to achieve good bonding with the piezoelectric wafer, resulting in an increase in the defect density of the POI substrate and a decrease in the performance stability.

[0004] In addition, the Si layer and the SiC layer of the composite substrate are separated by a SiO2 layer. Since the thermal conductivity of SiO2 is extremely low (about 1.4 W / m·K), which is much lower than the thermal conductivity of SiC (about 490 W / m·K) and the thermal conductivity of Si (about 150 W / m·K), the presence of the SiO2 layer will cause heat to accumulate in the SiO2 layer, resulting in local temperature rise and thermal failure. At the same time, the thermal expansion coefficient of SiO2 (about 0.5x10 -6 / K) is significantly different from the thermal expansion coefficient of Si (about 2.6x10 -6 / K) and the thermal expansion coefficient of SiC (about 4.0x10 -6 / K), which is easy to produce mechanical stress at the interface and may cause the SiO2 layer to crack or the interface to peel off, so that the yield of the POI substrate is greatly reduced. SUMMARY

[0005] In order to solve the above problems, a POI substrate based on a Si-SiC-graphene substrate and a preparation method thereof are provided. The POI substrate prepared by the method includes a thin film layer, a Si-SiC-graphene mixed layer and a Si layer, which has the advantages of reducing the risk of cracking of the POI substrate, reducing warping, improving bonding strength and reducing production cost, and promoting the industrialization process of high-performance filters.

[0006] According to one aspect of the present application, a method for preparing a POI substrate based on a Si-SiC-graphene substrate is provided, comprising the following steps:

[0007] (1) performing step-by-step C ion implantation on the surface of a Si substrate to obtain a support substrate comprising a first Si layer, a C implantation layer, and a second Si layer, wherein the concentration of C ions in the C implantation layer gradually decreases from the second Si layer to the first Si layer, and performing ion implantation on a piezoelectric wafer to obtain a wafer implantation sheet comprising a thin film layer, an implantation layer, and a residual layer in sequence;

[0008] (2) annealing and repairing the support substrate, forming a Si-SiC mixed layer in the C implantation layer, removing the second Si layer of the support substrate to expose the Si-SiC mixed layer, and then performing high-temperature heating treatment on the support substrate to convert the Si-SiC mixed layer into a Si-SiC-graphene mixed layer;

[0009] (3) cleaning the support substrate and the wafer implantation sheet obtained in step (2), and then activating and bonding the Si-SiC-graphene mixed layer of the support substrate and the thin film layer of the wafer implantation sheet to obtain a bonded body;

[0010] (4) heating the bonded body to separate the thin film layer and the residual layer, thereby obtaining a POI substrate.

[0011] In the present application, C ion implantation is performed on a Si substrate to form a Si-SiC mixed layer, wherein the concentration of SiC in the layer gradually increases from the first Si layer to the second Si layer, so that the thermal expansion coefficient of the support substrate gradually increases from 2.6×10 -6 / K of the first Si layer to 4.5×10 -6 / K, thereby reducing the warping of the substrate caused by thermal mismatch; and the SiC in the Si-SiC mixed layer is uniformly transitional, and there is no obvious interface with the first Si layer, thereby avoiding stress concentration caused by sudden change of Young's modulus at the interface and reducing the risk of film cracking.

[0012] In addition, in step (2) of the present application, high-temperature heating treatment is performed on the support substrate to convert the Si-SiC mixed layer into a Si-SiC-graphene mixed layer. The high-temperature heating treatment causes the exposed SiC on the surface of the Si-SiC mixed layer to grow into graphene, forming a uniform graphene layer which can better bond with the wafer implantation sheet and improve the bonding strength, and can release stress through in-plane deformation (such as wrinkling and bending) rather than breaking, thereby avoiding debonding and fragmentation caused by stress concentration and reducing the stress at the bonding interface.

[0013] Optionally, in step (1), the depth of the C implantation layer is 1.2-9.2 μm.

[0014] The depth determines the thickness of the Si-SiC mixed layer. Within the above range, a bonding layer with a uniform thermal expansion coefficient gradient can be formed, which can improve the bonding strength and the performance stability of the POI substrate. If the thickness decreases, the thermal expansion coefficient (CTE) gradient will be insufficient, which will cause interface delamination and crack formation during the heating process, and the crack will propagate to the Si substrate through the mixed layer. In addition, a decrease in thickness will also make the Si-SiC mixed layer more sensitive to annealing temperature fluctuations, causing surface SiC agglomeration or interface amorphization, thereby affecting the quality of the graphene layer, causing stress concentration, leading to debonding and fragmentation, and significantly reducing the bonding strength, thereby reducing the yield of the composite film. At the same time, the decrease in the thickness of the Si-SiC mixed layer will increase the thermal resistance, causing the temperature of the device to rise sharply under high power, affecting the heat dissipation performance of the device. If the thickness increases, it will affect the thickness of the first Si layer, causing the performance of the POI substrate to also decrease.

[0015] Optionally, in step (1), the specific operation of the stepwise C ion implantation is as follows:

[0016] The initial implantation energy is 1000-5000 keV, and the implantation dose is 8×10 15 -2.5×10 16 atoms / cm 2 After each implantation, the implantation energy is reduced by 5%-10% of the initial implantation energy, and the implantation dose is increased by 1×10 14 -5×10 15 atoms / cm 2 , until the implantation energy is 50-500 keV.

[0017] The above operation is to meet the gradual decrease of the C ion in the C implantation layer from the second Si layer to the first Si layer. This setting is to facilitate operation and improve the uniformity of batch substrates. Second, it can promote the uniform implantation of C ions into the Si substrate and combine with Si components to improve the uniformity of SiC components, thereby improving the overall performance uniformity of the substrate.

[0018] Optionally, the energy for ion implantation on the piezoelectric wafer in step (1) is 50-500 KeV, and the dose is 3×10 15 -5×10 18 .

[0019] Optionally, the ion species used in the ion implantation are hydrogen ions, helium ions, or mixed ions of hydrogen and helium.

[0020] Optionally, the specific operation of step (2) for high-temperature heating treatment of the support substrate to convert the Si-SiC mixed layer into a Si-SiC-graphene mixed layer is as follows:

[0021] The supporting substrate is heated to 1600-2000℃ under the protection of protective gas for 5 min, and then cooled to 600-800℃ for 5 min, and the cycle is repeated for 3-5 times.

[0022] The above operation is to form a uniform graphene layer on the exposed SiC surface in the Si-SiC mixed layer, and the cycle of high temperature-cooling treatment can improve the uniformity of the graphene layer, thereby improving the performance uniformity of the whole substrate.

[0023] If the heating temperature is lower than 1600℃, the sublimation rate of Si atoms in the SiC surface layer decreases, resulting in insufficient supply of carbon atoms, low nucleation density of graphene, uneven coverage, and difficulty in forming a continuous graphene layer; if the heating temperature is higher than 2000℃, the SiC surface decomposes too quickly, forming roughness or holes, destroying the flatness, and at the same time, the supply of carbon atoms is excessive, forming super-thick graphene or amorphous carbon deposition, and the high temperature leads to too fast reaction kinetics, making it difficult to accurately control the thickness and uniformity of graphene, and in addition, the thermal stress of the supporting substrate increases, and the interface between the first Si layer and the Si-SiC mixed layer is highlighted; if the cooling temperature is lower than 600℃, the carbon atoms are difficult to fully diffuse and recombine at low temperature, and the stress in the graphene layer cannot be effectively released, resulting in increased lattice distortion or wrinkles and disordered interlayer stacking, and if the cooling temperature is higher than 800℃, the evaporated silicon atoms are re-deposited on the SiC surface and react with the enriched carbon to form secondary SiC, destroying the continuity of graphene.

[0024] Optionally, the cooling rate from 1600-2000℃ to 600-800℃ is 5-10℃ / min.

[0025] This cooling rate can promote the uniform generation of graphene and improve the thickness uniformity of the graphene layer; at the same time, it can also avoid introducing thermal stress, reduce the cracking and warping of the supporting substrate, and improve the surface flatness of the supporting substrate, which can avoid silicon vapor supersaturation and reduce the probability of re-adsorption.

[0026] If the cooling rate is lower than 5℃ / min, the carbon atoms have more time to migrate and aggregate, resulting in an increase in the proportion of multi-layer graphene and the formation of local carbon islands, which destroys the uniformity; a long cooling time increases the probability of re-deposition of evaporated silicon atoms, resulting in the reaction with surface carbon to form amorphous SiC, which contaminates the graphene layer; a too low cooling rate leads to high time cost, which is not suitable for industrial production; if the cooling rate is higher than 10℃ / min, thermal stress causes graphene to crack or peel off from the substrate; silicon droplets form on the surface under high temperature, which are converted into silicon particles after cooling, destroying the continuity of graphene.

[0027] Under the above settings, the thickness of the graphene layer in the Si-SiC-graphene mixed layer is 0.3-0.7nm.

[0028] Optionally, the annealing in step (2) is performed under a protective atmosphere, the annealing temperature is 1000-1600℃, and the annealing time is 60-800min.

[0029] The annealing in step (2) can make the implanted C ions form SiC with Si, and the formation of SiC by C ion implantation is prone to cause lattice damage, thus increasing the defects of the substrate and reducing the reliability of the substrate.

[0030] In the present application, the C ions are uniformly transitional, and thus the SiC formed at the annealing temperature is also uniformly transitional and has no obvious stratification. In combination with the setting of the C ion concentration, the lattice damage caused by the C ions can be repaired at the annealing temperature, so as to reduce the number of defects in the support substrate and improve the overall reliability of the POI substrate.

[0031] Optionally, the heating temperature in step (4) is 100-300℃, and the heating time is 0.5-60h.

[0032] The temperature can make the implanted layer form a gas, achieve good separation of the thin film layer and the residual layer, and further eliminate the internal stress of the POI substrate and improve the performance of the POI substrate.

[0033] Optionally, the piezoelectric wafer and the support substrate have a diameter of 4-12 inches and an initial thickness of 100-1000μm.

[0034] The piezoelectric wafer is made of at least one of lithium niobate, lithium tantalate, quartz, lithium tetraborate, and lanthanum gallium silicate.

[0035] According to another aspect of the present application, a POI substrate of a Si-SiC-graphene substrate prepared by the preparation method described in any one of the above is provided, and the POI substrate comprises a thin film layer, a Si-SiC-graphene mixed layer, and a first Si layer.

[0036] The beneficial effects of the present application include but are not limited to:

[0037] 1. According to the preparation method of the POI substrate based on the Si-SiC-graphene substrate of the present application, the C ion concentration in the C implantation layer gradually decreases from the second Si layer to the first Si layer, and thus the content of Si in the Si-SiC mixed layer gradually increases from the first Si layer to the thin film layer. Firstly, the stress concentration caused by the sudden change of Young's modulus at the interface can be avoided, and the risk of substrate cracking can be reduced. Secondly, the smooth transition of the thermal expansion coefficient can be achieved, so as to reduce the warping caused by thermal mismatch.

[0038] 2. The method for preparing the POI substrate based on the Si-SiC-graphene substrate according to the present application, wherein the supporting substrate bonded with the wafer injection sheet is composed of a first Si layer and a Si-SiC-graphene mixed layer, and the Si-SiC-graphene mixed layer is formed on the Si substrate, which can greatly reduce the difficulty of slicing and thinning of the high-hardness SiC material and the production cost, and further promote the industrialization process of the high-performance filter.

[0039] 3. The method for preparing the POI substrate based on the Si-SiC-graphene substrate according to the present application, wherein the supporting substrate is subjected to at least 3 cycles of heating-cooling treatment, which can convert the Si-SiC mixed layer into the Si-SiC-graphene mixed layer, and the graphene layer formed has extremely high in-plane flexibility and bendability, allows nanoscale slip at high temperature, and can release stress through in-plane deformation (such as folding and bending) instead of breaking, thereby avoiding debonding and fragmentation caused by stress concentration, improving the bonding effect of the supporting substrate and the wafer injection sheet, reducing the bonding interface stress, improving the bonding strength, and further improving the use stability of the POI substrate.

[0040] 4. The method for preparing the POI substrate based on the Si-SiC-graphene substrate according to the present application, wherein the at least 3 cycles of heating-cooling treatment of the supporting substrate can further promote the combination of the Si component in the Si-SiC-graphene mixed layer and the free C ions to form dense SiC, and the SiC has good cross-compatibility with the original Si component without obvious interface separation, so as to improve the performance uniformity of the supporting substrate; meanwhile, the operation can further promote the uniform transition of the thermal expansion coefficient and the Young's modulus, and further reduce the cracking and warping of the substrate.

[0041] 5. The method for preparing the POI substrate based on the Si-SiC-graphene substrate according to the present application, which can effectively improve the yield of the SIC-based POI substrate, reduce the difficulty of slicing and thinning and greatly reduce the production cost, and further promote the industrialization of the high-performance filter. BRIEF DESCRIPTION OF DRAWINGS

[0042] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and serve to explain the present application, and do not constitute improper limitations on the present application. In the drawings:

[0043] Figure 1 The preparation flow chart of the POI substrate involved in the embodiments 1-3 of the present application.

[0044] Figure 2 The large-scale morphology and atomically resolved morphology of the graphene of the supporting substrate involved in the embodiment 3 of the present application.

[0045] Figure 3 Large-scale topography of graphene on the support substrate involved in Example 6 of the present application and atomically resolved topography.

[0046] Figure 4 Surface profile of the POI substrate involved in Example 3 of the present application.

[0047] Figure 5 Surface profile of the POI substrate involved in Example 6 of the present application.

[0048] Figure 6 Surface profile of the POI substrate involved in Comparative Example 1 of the present application.

[0049] Parts and list of reference numerals:

[0050] 100, Si substrate; 110, first Si layer; 120, C implantation layer; 121, Si-SiC mixed layer; 122, Si-SiC-graphene mixed layer; 130, second Si layer; 200, piezoelectric wafer; 210, thin film layer; 220, implantation layer; 230, excess mass layer. DETAILED DESCRIPTION

[0051] The present application will be described in detail below with reference to examples, but the present application is not limited to these examples.

[0052] The raw materials in the examples and comparative examples of the present application are all purchased through commercial channels unless otherwise specified.

[0053] The methods used in the examples and comparative examples of the present application are conventional methods in the prior art unless otherwise specified.

[0054] Example 1

[0055] Reference Figure 1 The present example relates to a method for preparing a POI substrate based on a Si-SiC-graphene substrate, comprising the following steps:

[0056] (1) Stepwise C ion implantation is performed on the surface of a Si substrate 100 with a thickness of 1000 μm to obtain a support substrate comprising a first Si layer 110, a C implantation layer 120, and a second Si layer 130, wherein the C ion concentration in the C implantation layer 120 gradually decreases from the second Si layer 130 to the first Si layer 110; hydrogen ion implantation is performed on a lithium niobate piezoelectric wafer 200 with a thickness of 1000 μm, the implantation energy is 500 KeV, and the implantation dose is 5×1016ions / cm2; 18 to obtain a wafer implantation sheet comprising a thin film layer 210, an implantation layer 220, and an excess mass layer 230 in sequence;

[0057] The specific operation of stepwise C ion implantation is as follows:

[0058] The initial implantation energy is 1000 keV, and the implantation dose is 8×10 15 atoms / cm 2 The implantation energy is reduced by 100 keV and the implantation dose is increased by 1×10 14 atoms / cm 2 for each implantation, until the implantation energy is 100 keV and the depth of the C implantation layer 120 is 1.2 μm;

[0059] (2) The support substrate is annealed for 800 min at 1000°C in a protective atmosphere, the C implantation layer 120 forms a Si-SiC mixed layer 121, the second Si layer 130 of the support substrate is removed to expose the Si-SiC mixed layer 121, and the support substrate is heated to 2000°C for 5 min under the protection of a protective gas, then cooled to 600°C at a cooling rate of 10°C / min for 5 min, and the cycle is repeated 3 times, so that the Si-SiC mixed layer 121 is converted into a Si-SiC-graphene mixed layer 122;

[0060] (3) The support substrate and wafer injection sheet obtained in step (2) are cleaned, and then the Si-SiC-graphene mixed layer 122 of the support substrate and the thin film layer 210 of the wafer injection sheet are bonded after plasma activation to obtain a bonded body;

[0061] (4) The bonded body is heated to 100°C and treated for 60 h, so that the thin film layer 210 and the residual layer 230 are separated, and a POI substrate is obtained.

[0062] Embodiment 2

[0063] With reference to Figure 1 , this embodiment relates to a preparation method of a POI substrate based on a Si-SiC-graphene substrate, comprising the following steps:

[0064] (1) Stepwise C ion implantation is performed on the surface of a Si substrate 100 with a thickness of 100 μm to obtain a support substrate comprising a first Si layer 110, a C implantation layer 120, and a second Si layer 130, the concentration of C ions in the C implantation layer 120 gradually decreases from the second Si layer 130 to the first Si layer 110, and hydrogen ion implantation is performed on a lithium niobate piezoelectric wafer 200 with a thickness of 100 μm, the implantation energy is 50 KeV, and the implantation dose is 3×10 15 to obtain a wafer injection sheet comprising a thin film layer 210, an implantation layer 220, and a residual layer 230 in sequence;

[0065] The specific operation of stepwise C ion implantation is as follows:

[0066] The initial implantation energy is 5000 keV, and the implantation dose is 2.5×10 16 atoms / cm 2 The implantation energy is reduced by 250 keV and the implantation dose is increased by 5×10 15 atoms / cm 2 with each implantation until the implantation energy is 250 keV and the depth of the C implantation layer 120 is 9.2 μm.

[0067] (2) The support substrate is annealed at 1600℃ for 60 min in a protective atmosphere, the C implantation layer 120 forms a Si-SiC mixed layer 121, the second Si layer 130 of the support substrate is removed to expose the Si-SiC mixed layer 121, and the support substrate is heated to 1600℃ for 5 min under the protection of a protective gas, then cooled to 800℃ at a cooling rate of 5℃ / min for 5 min, and the cycle is repeated 5 times, so that the Si-SiC mixed layer 121 is converted into a Si-SiC-graphene mixed layer 122;

[0068] (3) The support substrate and wafer implantation sheet obtained in step (2) are cleaned, and then the Si-SiC-graphene mixed layer 122 of the support substrate and the thin film layer 210 of the wafer implantation sheet are bonded after surface activation to obtain a bonded body;

[0069] (4) The bonded body is heated to 300℃ for 0.5 h, so that the thin film layer 210 and the residual layer 230 are separated, and a POI substrate is obtained.

[0070] Example 3

[0071] With reference to Figure 1 , this embodiment relates to a preparation method of a POI substrate based on a Si-SiC-graphene substrate, comprising the following steps:

[0072] (1) Stepwise C ion implantation is performed on the surface of a Si substrate 100 with a thickness of 500 μm to obtain a support substrate comprising a first Si layer 110, a C implantation layer 120, and a second Si layer 130, the concentration of C ions in the C implantation layer 120 gradually decreases from the second Si layer 130 to the first Si layer 110, and hydrogen ion implantation is performed on a lithium niobate piezoelectric wafer 200 with a thickness of 500 μm, the implantation energy is 300 KeV, and the implantation dose is 5×10 17 to obtain a wafer implantation sheet comprising a thin film layer 210, an implantation layer 220, and a residual layer 230 in sequence;

[0073] The specific operation of stepwise C ion implantation is as follows:

[0074] The initial implantation energy is 2500 keV, and the implantation dose is 1.0×1016 atoms / cm 2 , the implantation energy is decreased by 150 keV and the implantation dose is increased by 1 x 10 15 atoms / cm 2 , until the implantation energy is 100 keV and the depth of the C implantation layer 120 is 4.5 μm;

[0075] (2) annealing the support substrate under a protective atmosphere at 1400 °C for 200 min to repair the C implantation layer 120 to form a Si-SiC mixed layer 121, removing the second Si layer 130 of the support substrate to expose the Si-SiC mixed layer 121, and heating the support substrate to 1800 °C under a protective gas for 5 min, then cooling to 700 °C at a rate of 5 °C / min and maintaining for 5 min, and repeating the cycle 4 times to convert the Si-SiC mixed layer 121 to a Si-SiC-graphene mixed layer 122;

[0076] (3) cleaning the support substrate and wafer injection sheet obtained in step (2), and then using plasma activation to bond the Si-SiC-graphene mixed layer 122 of the support substrate and the thin film layer 210 of the wafer injection sheet to obtain a bonded body;

[0077] (4) heating the bonded body to 200 °C and treating for 15 h to separate the thin film layer 210 and the remaining layer 230, thereby obtaining a POI substrate.

[0078] Example 4

[0079] The difference between this example and Example 3 is that in step (1), the specific operation of stepwise C ion implantation on the surface of the Si substrate is as follows:

[0080] High-energy implantation: the implantation energy is 2500 keV and the implantation dose is 1.0 x 10 16 atoms / cm 2 ;

[0081] Medium-energy implantation: the implantation energy is 1500 keV and the implantation dose is 3.0 x 10 16 atoms / cm 2 ;

[0082] Low-energy implantation: the implantation energy is 100 keV and the implantation dose is 6.0 x 10 16 atoms / cm 2 .

[0083] The content of SiC in the Si-SiC mixed layer formed in this embodiment is not gradually changed, but is divided into three layers, and the content of SiC in the three layers gradually decreases from the second Si layer to the first Si layer, but the content of SiC in each layer is the same.

[0084] Embodiment 5

[0085] The difference between this embodiment and embodiment 3 is that the specific operation of step (1) is that the surface of the Si substrate is subjected to stepwise C ion implantation.

[0086] The initial implantation energy is 2500 keV, and the implantation dose is 5.0×10 16 atoms / cm 2 , and each time the implantation energy is reduced by 150 keV and the implantation dose is increased by 8.0×10 15 atoms / cm 2 , until the implantation energy is 100 keV and the depth of the C implantation layer 120 is 4.5 μm.

[0087] Embodiment 6

[0088] The difference between this embodiment and embodiment 3 is that the temperature of the annealing repair in step (2) is 1800°C.

[0089] Embodiment 7

[0090] The difference between this embodiment and embodiment 3 is that the cooling rate of the supporting substrate from 1800°C to 700°C in step (2) is 15°C / min.

[0091] Embodiment 8

[0092] The difference between this embodiment and embodiment 3 is that in step (2), the supporting substrate is heated to 1500°C for 5 min, and then cooled to 700°C at a cooling rate of 5°C / min for 5 min, and the cycle is repeated 4 times, so that the Si-SiC mixed layer is converted into a Si-SiC-graphene mixed layer.

[0093] Embodiment 9

[0094] The difference between this embodiment and embodiment 3 is that in step (2), the supporting substrate is heated to 2200°C for 5 min, and then cooled to 700°C at a cooling rate of 5°C / min for 5 min, and the cycle is repeated 4 times, so that the Si-SiC mixed layer is converted into a Si-SiC-graphene mixed layer.

[0095] Embodiment 10

[0096] The difference between this embodiment and embodiment 3 is that in step (2), the support substrate is heated to 1800℃ for 5 min, and then cooled to 1000℃ at a cooling rate of 5℃ / min for 5 min, and the cycle is repeated 4 times, so that the Si-SiC mixed layer is converted into a Si-SiC-graphene mixed layer.

[0097] Example 11

[0098] The difference between this embodiment and embodiment 3 is that in step (2), the support substrate is heated to 1800℃ for 5 min, and then cooled to 500℃ at a cooling rate of 5℃ / min for 5 min, and the cycle is repeated 4 times, so that the Si-SiC mixed layer is converted into a Si-SiC-graphene mixed layer.

[0099] Comparative Example 1

[0100] The difference between this comparative example and embodiment 3 is that in step (1), the surface of the Si substrate is subjected to one-step C ion implantation, the implantation energy is 1500 keV, and the implantation dose is 6.0×10 16 atoms / cm 2 In this comparative example, the content of SiC in the Si-SiC mixed layer is consistent.

[0101] Comparative Example 2

[0102] The difference between this comparative example and embodiment 3 is that after the second Si layer of the support substrate is removed to expose the Si-SiC mixed layer in step (2), step (3) is performed, and the step of converting the Si-SiC mixed layer into a Si-SiC-graphene mixed layer by high-temperature heating treatment is no longer performed.

[0103] Comparative Example 3

[0104] The composite substrate obtained by the operations of steps (1)-(3) in Example 1 of CN119252733A is used to replace the support substrate of the Si-SiC-graphene mixed layer in embodiment 3, and the composite substrate and the wafer implantation sheet in embodiment 3 are bonded and subjected to heating treatment in the same manner as in embodiment 3 to obtain a POI substrate.

[0105] Test Example

[0106] The POI substrates in the above embodiments and comparative examples are subjected to uniformity testing of the graphene layer film, bonding force testing of the bonded body, Warp and Bow surface warping testing of the POI substrate, and the pass rate of the POI substrate is counted, and the test results are shown in Table 1.

[0107] The calculation method of the thickness uniformity of the graphene is as follows: the surface topography and height data are obtained by scanning the surface topography of the graphene, the area of the region with a thickness of 0.3-0.7 nm of the graphene layer is counted, and the proportion of the area in the total area is the thickness uniformity.

[0108] The statistics of the qualification rate of the POI substrate refers to that 100 POI substrates are prepared by using the method, and the percentage of the number of qualified POI substrates in the total number of 100 is taken as the qualification rate. For example, 96 qualified POI substrates are obtained in Example 1, and the qualification rate is 96%. The POI substrate without breakage or crack is qualified, and the POI substrate with breakage or crack is unqualified.

[0109] Table 1

[0110]

[0111] According to the test results, the Si-SiC-graphene mixed layer formed by stepwise C ion implantation and high-temperature addition treatment on the Si substrate can improve the bonding strength with the piezoelectric wafer and the qualification rate of the POI substrate.

[0112] According to the comparison between Example 4 and Example 3, when the stepwise C ion implantation is performed by gradient variation, the bonding strength and the qualification rate are obviously increased, and the surface quality of the substrate is better.

[0113] According to the comparison between Example 5 and Example 3, when the same stepwise C ion implantation is performed, if the C ion concentration gradient of the C implantation layer changes too much, the surface quality is deteriorated, the thickness uniformity of the graphene is reduced, and then the bonding strength and the qualification rate are reduced.

[0114] According to the comparison between Example 6 and Example 3, when the stepwise C ion implantation is the same, Figure 4 and Figure 5 According to the comparison between Example 6 and Example 3, when the stepwise C ion implantation is the same, Figure 2 Fig. 1 (a) is a large-scale topography of the graphene of the support substrate of Example 3, Figure 2 Fig. 1 (b) is an atomic resolution topography of the graphene of the support substrate of Example 3, Figure 3 Fig. 2 (a) is a large-scale topography of the graphene of the support substrate of Example 6, Figure 3 Fig. 2 (b) is an atomic resolution topography of the graphene of the support substrate of Example 6. From Figure 2 and Figure 3 According to the comparison between Example 6 and Example 3, when the stepwise C ion implantation is the same,

[0115] According to the comparison of Example 7-Example 11 and Example 3, it can be known that the high-temperature heat treatment forms a graphene layer on the surface of the Si-SiC mixed layer, when the high-temperature heat treatment temperature and the cooling rate change, the uniformity of the thickness of the graphene is affected, and then the bonding strength is affected, and because it is high-temperature treatment, the internal stress of the POI substrate is affected, the surface quality of the POI substrate is reduced, if the internal stress is too large or cannot be released in time, the POI substrate will also crack or break, affecting the yield of the POI substrate.

[0116] According to the comparison of Comparative Example 1 and Example 3, combined with Figure 4 and Figure 6 It can be known that when only a SiC layer is generated on the Si substrate, the yield of the POI substrate is significantly reduced, because there is a clear Si layer-SiC layer interface, resulting in stress concentration in the support substrate, resulting in poor surface quality of the POI substrate, and the thin film is more prone to cracking.

[0117] According to the comparison of Comparative Example 2 and Example 3, it can be known that when there is no graphene layer for transition, the surface quality of the POI substrate is greatly reduced, and the bonding strength and the yield are also significantly reduced.

[0118] According to the comparison of Comparative Example 3 and Example 3, it can be known that when a SiO2 layer is further provided between the Si layer and the SiC layer, and the SiC concentration of the SiC layer is the same, the support substrate still has the problem of poor surface quality, and the bonding strength with the piezoelectric substrate is also low, the support substrate is also easy to break or crack during the bonding process, so that the yield of the POI substrate is reduced.

[0119] The above is only an embodiment of the present application, and the protection scope of the present application is not limited by these specific embodiments, but is determined by the claims of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the technical idea and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method for the production of a POI substrate based on a Si-SiC-graphene substrate, characterized in that, The method comprises the following steps: (1) performing step-by-step C ion implantation on the surface of a Si substrate to obtain a support substrate comprising a first Si layer, a C implantation layer, and a second Si layer, wherein the C ion concentration in the C implantation layer gradually decreases from the second Si layer to the first Si layer, and performing ion implantation on a piezoelectric wafer to obtain a wafer implantation sheet comprising a thin film layer, an implantation layer, and a residual layer in sequence; (2) performing annealing repair on the support substrate, forming a Si-SiC mixed layer in the C implantation layer, removing the second Si layer of the support substrate to expose the Si-SiC mixed layer, and then performing high-temperature heating treatment on the support substrate to convert the Si-SiC mixed layer into a Si-SiC-graphene mixed layer; (3) cleaning the support substrate and the wafer implantation sheet obtained in step (2), and then activating and bonding the Si-SiC-graphene mixed layer of the support substrate and the thin film layer of the wafer implantation sheet to obtain a bonded body; (4) heating the bonded body to separate the thin film layer and the residual layer, thereby obtaining a POI substrate.

2. The production method according to claim 1, characterized by, In step (1), the depth of the C implantation layer is 1.2-9.2 μm.

3. The preparation method according to claim 1, characterized in that, In step (1), the specific operation of step-by-step C ion implantation is as follows: The initial implantation energy is 1000-5000 keV and the implantation dose is 8x1014 atoms / cm2. 15 - 2.5x1014 atoms / cm2. 16 - 2.5x1014 atoms / cm2. 2 For each implantation, the implantation energy is decreased by 5-10% of the initial implantation energy and the implantation dose is increased by 1x1014 atoms / cm2 14 - 5x1014 atoms / cm2. 15 - 5x1014 atoms / cm2. 2 until the implantation energy is 50-500 keV.

4. The method of claim 1, wherein, The energy of ion implantation in step (1) is 50 - 500 KeV, and the dose is 3 x 10 15 -5 x 10 18 .

5. The preparation method according to claim 1, characterized in that, The ion implantation uses hydrogen ions, helium ions, or mixed ions of hydrogen and helium.

6. The method of claim 1, wherein, In step (2), the specific operation of performing high-temperature heating treatment on the support substrate to convert the Si-SiC mixed layer into a Si-SiC-graphene mixed layer is as follows: The support substrate is heated to 1600-2000 ℃ under the protection of a protective gas for 5 min, and then cooled to 600-800 ℃ for 5 min, and the cycle is repeated for 3-5 times.

7. The preparation method according to claim 6, characterized in that, The cooling rate from 1600-2000 ℃ to 600-800 ℃ is 5-10 ℃ / min.

8. The method of claim 1, wherein, The annealing repair in step (2) is performed under a protective atmosphere, the annealing temperature is 1000-1600 ℃, and the time is 60-800 min.

9. The method of claim 1, wherein, The heating temperature in step (4) is 100-300 ℃, and the time is 0.5-60 h.

10. The POI substrate of the Si-SiC-graphene substrate produced by the production method according to any one of claims 1 to 9, characterized by The POI substrate comprises a thin film layer, a Si-SiC-graphene mixed layer, and a first Si layer.

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