Selective thin film resistor and manufacturing method thereof

Abstract

The present disclosure includes methods for manufacturing selective thin film resistors and thin film resistors including a dielectric core material having a thin film resistor material located between copper conductors, but where no thin film resistor material is located below the copper conductors. Embodiments of the present disclosure provide a method of manufacturing a selective thin film resistor ("STFR") having a thin film resistor material ("TFRM") disposed only on selective regions on a core material rather than having the TFRM present on the entire core material and under a copper conductor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 434,836, filed on December 22, 2022, the contents of which are incorporated herein by reference in their entirety. Background Art

[0003] Resistors are standard components in many semiconductor integrated circuits. For example, resistors are often used to control the corresponding resistance of other electronic components of the integrated circuit, which can be any of radio frequency (RF) circuits (e.g., oscillators, phase shift networks, filters, converters, etc.), memory circuits (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), etc.), and various analog / mixed-signal circuits. Many integrated circuit devices incorporate thin film resistors (TFRs), which offer various advantages over other types of resistors. For example, TFRs can be highly accurate and can be fine-tuned to provide very precise resistance values. As another example, TFRs typically have smaller parasitic parameters, which provides favorable high-frequency behavior. In addition, TFRs typically have a low temperature coefficient of resistance (TCR). For example, after a suitable annealing process, the TCR can be "tuned" to a customer-specified near-zero value, which can provide stable operation over a wide operating temperature range. However, there remains a need for more efficient and accurate thin film resistors. Summary of the Invention

[0004] Embodiments of the present disclosure include methods for making selective thin film resistors and thin film resistors that include a dielectric core having thin film resistor material between copper conductors, but wherein no thin film resistor material is located beneath the copper conductors. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A diagram of the related art of thin film resistors (TFRs) is provided. Typically there is a copper layer, then a thin film resistor layer on a core material (ie, dielectric material), followed by another thin film resistor layer, and finally another copper layer.

[0006] Figure 2A and Figure 2B A comparison of non-selective thin film resistor circuitization and selective thin film resistor circuitization is shown. Figure 2A shows a conventional circuitization using TFRs, referred to as "non-selective" because the film resistor material is located below the copper material, as opposed to a "selective" circuitization showing the thin film resistor material (TFRM) not being located below the copper material (e.g. Figure 2B ), but rather on selected desired areas on the core material. Figure 2BA selective TFR of the present disclosure is shown having thin film resistor material (3) located only on desired areas of the core material (2) and not beneath the copper film (4).

[0007] Figure 3A The initial construction steps are shown. The thin film resistor material (TFRM) (3) layer and copper foil (4a) can be supplied by a supplier and then bonded to the core material (HF dielectric material) (2). Alternatively, the complete construction can be supplied by a laminate supplier. Alternatively, the thin film resistor material (TFRM) (3) layer can be applied to the core material (HF dielectric material) (2). Thereafter, a first copper foil layer (4a) is applied over the TFRM (3) using known methods.

[0008] Figure 3B The copper etching step is shown. A first copper foil layer (4a) located above the thin film resistor layer can be etched to produce a first thin copper layer (4b) because a thinner copper layer improves feature resolution. Alternatively, a thinner starting copper foil layer can be used instead of etching the starting copper foil layer to achieve similar results.

[0009] Figure 3C The lamination of a photoimageable resist material (4c) is shown.

[0010] Figure 3D The next step is shown. Photoresist material is exposed over the desired thin film resistor areas (5). The exposed areas are polymerized and therefore will not be developed away.

[0011] Figure 4 The unexposed photoresist material is shown having been developed away. This leaves the exposed resist material (5b) in the desired location above the first thin copper layer (4b), which is above the thin film resistor material (3). The exposed resist material (5b) covers the thin film resistor at the desired area, and this is the beginning of the process for defining a selective thin film resistor.

[0012] Figure 5 The resulting structure is shown after the etchant has removed the first thin copper layer (4b) and the areas of the thin film resistor material TFRM (3) not protected by the exposed resist material (5b), leaving only the "sandwich" (15) located above the core material (2), which "sandwich" includes the TFRM (3) layer, the first thin copper layer (4b) and the exposed resist material (5b).

[0013] Figure 6The resulting TFR structure is shown after the exposed resist material (5b) has been stripped from the interlayer. The figure shows that the TFRM has been removed from all areas except those located beneath the copper layer, leaving an interlayer (16) comprising the TFRM (3) layer and the first thin copper layer (4b). Removing the thin film resistive layers applied to the core (except for the TFRM in the interlayer (16)) overcomes the adhesion challenges of the subsequent metal application (the "metallization step").

[0014] Figure 7 The application of a thin seed copper layer (6) is shown in preparation for semi-additive plating (SAP).The thin seed copper layer (6) is applied to the core and interlayer (16) using methods and materials known in the art.

[0015] Figure 8 The application of a second layer of imageable resist material (7) is shown as a preparatory step for semi-additive plating (SAP).

[0016] Figure 9 The second imageable resist material (9) is shown being exposed to mask the seed copper layer (6) and the interlayer (16) (metallization bus layer) prior to development in order to open the resistor features (16) and associated connectors. The exposure is based on a UV light source and can be a direct imaging technique or a photolithographic technique.

[0017] Figure 10 The exposed second imageable resist material layer (9) is shown being developed in preparation for semi-additive plating (SAP). Only the unexposed second imageable resist material layer will be developed away.

[0018] Figure 11 Circuit construction using SAP pattern plating is shown. The circuit is constructed using electrolytic copper. With the exposed second imageable resist material layer (9) still present, a layer of electrolytic copper (8) is added (using known deposition and photolithography methods) at the desired locations.

[0019] Figure 12 The removal of the exposed second imageable resist material layer is shown in preparation for circuit definition. Prior to differential etching, the exposed second imageable resist material layer (9) is stripped using NaOH or other chemicals.

[0020] Figure 13 Differential etching for feature definition is shown. The seed copper (6) has been removed to define the circuit.

[0021] Figure 14 It is shown that a third layer of photoimageable resist material (11) has been applied.

[0022] Figure 15 It is shown that exposing the third photoimageable resist material layer (11) facilitates high resolution resistor definition.

[0023] Figure 16 The resist material development step and the selective copper etching step to form the resistor are shown. The third photoimageable resist material layer (11) is developed to expose the copper (17) below the third photoimageable resist material layer (11). The copper (17) below is then etched away to expose the selective thin film resistor (20). The remaining third photoimageable resist layer (11) is stripped using NaOH or other chemicals.

[0024] Figure 17 A selective thin film resistor is shown. DETAILED DESCRIPTION

[0025] Embodiments of the present disclosure provide a method for manufacturing a selective thin film resistor ("STFR") that has thin film resistor material ("TFRM") placed only on selective areas of a core material, rather than having the TFRM present on the entire core material and underneath the copper conductor. In other words, the TFRM is not present underneath the copper film.

[0026] Figure 1 The overall overview of building a thin film resistor (TFR) is shown. As shown in the figure, the overall construction includes a top copper layer with a certain thickness, which can be, for example, 18μm, 35μm, or other thickness. Below the top copper layer is a TFRM that acts as a predetermined resistor. Below the TFRM is a high frequency (HF) dielectric material, which can be provided in different thicknesses. Below this layer is another TFRM layer, and then a bottom copper layer ... Figure 1 As shown, these layers may be pre-laminated or may be laminated by applying a bonding material between at least the TFRM and the dielectric layer.To complete the circuitization, an imageable resist material for selective plating or etching is applied to the copper layer. Figure 2A A typical thin film resistor structure is shown having a TFRM (3) located on a core material (2) and also located below an adjacent copper film (4). Figure 2B Shown is an STFR (1) in which the TFRM (3) is located on the core material (2) but not underneath the adjacent area of ​​the copper film (4). By having the TFRM only in the desired location on the core material and not underneath the copper film, the STFR exhibits less "skin effect" and therefore has lower signal loss than traditional thin film resistors (TFRs).

[0027] Typically, TFRs have core materials that are high frequency dielectrics (often referred to herein as HF dielectric cores) and are typically polytetrafluoroethylene (PTFE) or a mixture containing PTFE. TFRMs are typically alloys of NiCr (nickel-chromium) "nickel chromium" or tantalum nitride (TAN).

[0028] Figure 3A The initial build in a process for making a selective thin film resistor (STFR) is shown. A first copper foil layer (4a) is applied over the thin film resistor material (3) which has been applied to the HF dielectric core material (2).

[0029] Figure 3B The copper etching step is shown. Here, the previously applied first copper foil layer (4a) is etched to thin the layer, thereby producing a first thin copper layer (4b). For example, an acid etch is used to etch the layer from about 18 μm to between 2-4 μm. Typical acid etching materials can be used for this etching step. Alternatively, a thinner starting copper foil layer can be used instead of etching the starting copper foil layer to achieve similar results. The thinner copper layer improves the feature resolution after etching.

[0030] Figure 3C The lamination step is shown. A photoimageable resist material (4c) is applied on top of the first thin copper layer (4b).

[0031] Figure 3D The next step is shown in which a photoimageable resist material (4c) is exposed on the desired thin film resistor area (5). This exposed desired thin film resistor area (5) is polymerized and will therefore not be developed away. The exposure is based on a UV light source and can be a direct imaging technique or photolithography can be used.

[0032] Figure 4 The unexposed photoimageable resist material is shown being developed away. Known developing solutions can be used. This leaves the exposed resist material (5b) in the desired position above the first thin copper layer (4b), which is above the thin film resistor material (3). The exposed resist material (5b) covers the area that will become the desired thin film resistor, and this is the beginning of the process for defining a selective thin film resistor.

[0033] The resist material is any known and useful material that "protects" the copper film from the acid etchant that is used to remove the desired areas of the copper film and thin film resistor material (TFRM) (3) that are not protected by the resist material. Known materials can be used to remove the copper layer that is not protected by the resist material. Typically, a slightly alkaline etchant is applied to remove the copper film that is not protected by the resist material. Thereafter, the TFRM (3) that is not protected by the resist material is removed using materials and processes suitable for removing the TFRM. Figure 5 The resulting product is shown. It shows the "sandwich" (15) remaining on the core material (2) after the etching step discussed above, the sandwich comprising the TFRM (3) layer, the first thin copper layer (4b) and the exposed resist material (5b).

[0034] The next step is to remove the exposed resist material (5b). NaOH or other chemicals can be used to strip the exposed resist material (5b). The resulting structure is Figure 6 Shown in. Figure 6 The resulting product is shown after the exposed resist material (5b) has been removed, leaving behind an interlayer (16) comprising a TFRM (3) layer and a first thin copper layer (4b). Removing the thin film resistor material deposited on the core material (2) (except in desired areas, such as the TFRM in the interlayer (16)) overcomes adhesion challenges for subsequent metal application ("metallization step"). For example, high frequency dielectrics present adhesion challenges for subsequent metallization steps. Removing the thin film resistor layer overcomes this.

[0035] The next step in the process of making a selective thin film resistor ("STFR") involves applying a thin seed copper layer (6) over the interlayer (16) and core material (2) using known copper deposition methods, such as Figure 7 The use of a low-deposition electroless copper metallization step allows for high-precision and high-density circuitry.

[0036] A second layer of imageable resist material (7) is then applied at the desired location. Figure 8 As shown, a second imageable resist layer (7) is placed over the interlayer (16) and the seed copper layer (6). A sheet laminator may be used to apply the second imageable resist material layer (7).

[0037] The second imageable resist material layer (7) is exposed to produce an exposed second imageable resist layer (9), which is used to protect the interlayer (16) and the seed copper (6) in areas that do not need to be thickened by acid copper plating as etching protection. That is, the second imageable resist material layer is selectively exposed in certain areas to produce an exposed second imageable resist layer (9), thereby protecting the resistor area and the seed copper. The exposure is based on a UV light source and can be a direct imaging technique or a photolithography method.

[0038] Figure 10 The exposed second imageable resist material layer (9) is shown being developed in preparation for semi-additive plating (SAP). Known imageable resist layer materials (liquid or dry) can be used with known development processes. Only unexposed resist will be developed away.

[0039] Figure 11 Circuit construction using SAP pattern plating is shown. The circuit is constructed using electrolytic copper. With the exposed second imageable resist material layer (9) still present, a layer of electrolytic copper (8) is added (using known deposition and photolithography methods) at the desired locations.

[0040] Figure 12 The removal of the exposed second imageable resist material layer is shown in preparation for circuit definition. Prior to differential etching, the exposed second imageable resist layer material (9) is stripped using NaOH or other chemicals.

[0041] Figure 13 The differential etching steps for feature definition are shown. The seed copper (6) is removed to define the circuitry.

[0042] Next, a third layer of photoimageable resist material (11) is applied, such as Figure 14 As shown. Figure 15 As shown, the third photoimageable resist material layer (11) is exposed to facilitate high resolution resistor definition. The exposure is based on a UV light source and can be a direct imaging technique or a photolithographic technique. The desired section is masked to provide an unexposed area of ​​the third photoimageable resist material layer (12), as shown. Figure 15 shown.

[0043] Figure 16 The resist material development step and the selective copper etching step are shown to form the resistor. The third photoimageable resist material layer (11) is developed to expose the copper (17) below the third photoimageable resist material layer (11). The copper (17) below is then etched away to expose the selective thin film resistor (20). Figure 17As shown, the remaining third photoimageable resist layer (11) is stripped using NaOH or other chemicals, and the resulting selective thin film resistor (20) between the copper conductors is shown. It is noteworthy that no thin film resistor material is located under the copper conductors.

Claims

1. A method for manufacturing a selective thin film resistor, the method comprising: a) providing a substrate, the substrate comprising a high-frequency dielectric material core, the high-frequency dielectric material core having a thin film resistor material TFRM layer and a first copper foil layer on the thin film resistor material; b) etching the first copper foil layer located above the thin film resistor layer to produce a first thin copper layer; c) laminating the first thin copper layer with a first photoimageable resist material; d) exposing the first photoimageable resist material at desired locations, the exposed areas corresponding to areas where the selective thin film resistor is to be located; e) developing the unexposed areas of the first photoimageable resist material; f) removing the first thin copper layer and the areas of thin film resistor material not underlying the exposed first photoimageable resist material with an etchant; g) stripping the exposed areas of the first photoimageable resist material layer to leave a "sandwich layer" on the high frequency dielectric material core, wherein the "sandwich layer" includes the thin film resistor layer and the first thin copper layer; h) applying a thin seed copper layer on the interlayer and the core material; i) applying a second layer of imageable resist material over the thin seed copper layer; j) exposing desired areas of the second layer of imageable resist material; k) developing the second layer of imageable resist material to remove unexposed portions of the second layer of imageable resist material; 1) adding a layer of electrolytic copper at a desired location while the exposed second layer of imageable resist material is still present; m) removing the exposed second imageable resist material layer; n) removing a desired peripheral area of ​​the thin seed copper layer located on the high-frequency dielectric material core; o) applying a third layer of imageable resist material; p) exposing portions of the third layer of imageable resist material; q) developing unexposed portions of the third layer of imageable resist material; r) etching the copper layer beneath the developed unexposed portions of the third imageable resist material layer to expose the thin film resistor material; s) removing the exposed portions of the third layer of imageable resist material to form a selective thin film resistor positioned between the copper conductors.

2. A thin film resistor prepared by the method according to claim 1.

3. A thin film resistor, wherein: The thin film resistor material is located between the copper conductors, wherein no thin film resistor material is located beneath the copper conductors.

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