Charged particle optical element, charged particle optical module, evaluation device, chip assembly, and manufacturing method

Abstract

A charged particle optical element is disclosed. The element is for a charged particle optical module configured to direct charged particles along at least one beam path to a sample. In one arrangement, the element comprises a chip comprising an integrated circuit (64) formed in a semiconductor substrate (61). The substrate defines at least one aperture (63) for passage of at least one beam path through the at least one aperture (63). The size of the substrate exceeds the maximum die size of a lithographic imaging system used during fabrication of the integrated circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to EP application 23156956.7 filed on February 16, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003]

[0014] Embodiments provided herein generally relate to apparatus for directing charged particles, such as electrons, to a sample, and related apparatus and methods. Background Art

[0004] When manufacturing semiconductor integrated circuit (IC) chips, during the manufacturing process, undesirable pattern defects may appear on the substrate (e.g., wafer) or mask, thereby reducing the yield. Defects may be caused by, for example, optical effects and incident particles or other process steps (such as etching, deposition, or chemical mechanical polishing). Therefore, monitoring the extent of undesirable pattern defects is an important process in the manufacture of IC chips. More generally, inspection and / or measurement of the surface of a substrate or other object / material is an important process during and / or after the manufacture of the IC chip.

[0005] Pattern evaluation systems, such as pattern inspection tools with charged particle beams, have been used to evaluate objects, such as detecting pattern defects. These tools typically use electron microscopy techniques, such as scanning electron microscopes (SEMs). In an SEM, a primary electron beam of relatively high-energy electrons lands on a target with a relatively low landing energy, with a final deceleration step as the target. The electron beam is focused into a detection spot on the target. The interaction between the material structure at the detection spot and the landing electrons from the electron beam causes electrons such as secondary electrons, backscattered electrons, or Auger electrons to be emitted from the surface. These electrons are collectively referred to as signal electrons, or more generally, signal particles. The generated secondary electrons can be emitted from the material structure of the target.

[0006] By scanning the primary electron beam as a detection spot on the target surface, secondary electrons can be emitted on the surface of the target. By collecting these secondary electrons emitted from the target surface, the pattern inspection tool (or device) can obtain an image-like signal that represents the characteristics of the material structure of the target surface. In such an inspection, the collected secondary electrons are detected by a detector within the device. The detector generates a signal in response to the incident charged particles. When an area of ​​the sample is inspected, these signals include data that are processed to generate an inspection image corresponding to the inspected area of ​​the sample.

[0007] Charged particle optical elements (e.g., electron optical elements) can be used to manipulate beams of charged particles and / or detect signal particles. Such elements may require relatively high power and / or be located in a spatially limited location. Charged particles may also impact such elements or structures in thermal contact with such elements, thereby generating heat. Controlling the temperature of charged particle elements may be difficult, and / or the need to control the temperature may impose functional limitations on the elements, such as limiting the performance of the elements. Integrated circuits can be used to perform complex functions in charged particle optical elements. Integrated circuits generate heat and generally need to be operated without exceeding the maximum recommended operating temperature. Summary of the Invention

[0008] It is an object of the present disclosure to at least partially address one or more of the challenges discussed above, including, for example, improving thermal management in charged particle optical elements.

[0009] According to one aspect of the present invention, a charged particle optical element for a charged particle optical module is provided, which is configured to guide charged particles toward a sample along at least one beam path, and the charged particle optical element includes: a chip, which includes an integrated circuit formed in a semiconductor substrate, the substrate defining at least one aperture, which is used for a passage of at least one beam path through the at least one aperture, wherein: the size of the substrate exceeds the tube core size of the lithography imaging system used during the manufacture of the integrated circuit.

[0010] Configuring the substrate to have dimensions that exceed the die size can facilitate temperature control by providing additional space for cooling arrangements and / or allowing heat sources to be positioned away from the beam region. The increased size can additionally or alternatively provide design freedom to improve the mechanical support of the substrate. Improved mechanical support can contribute to effective temperature control, for example, by providing a low thermal resistance path for efficient heat conduction away from the substrate.

[0011] In one embodiment, the substrate includes an inner region and a peripheral region; integrated circuits are formed within the inner region; the peripheral region is free of any functional integrated circuits; and the peripheral region is located laterally outward from the inner region when viewed perpendicular to a major surface of the substrate. In one embodiment, a cooling element is mounted to the peripheral region and configured to extract heat from the substrate. The increased space provided by sizing the substrate to exceed the die size facilitates configuring the cooling element to have high performance. The peripheral region provides a relatively large contact area for the cooling element, which can facilitate improved cooling performance. The increased space can allow the cooling element to be larger and / or facilitate the provision of efficient internal channels for a heat exchange fluid.

[0012] In one embodiment, the contact area between the cooling element and the substrate is larger than 10% of the die size of a lithographic imaging system used during fabrication of the integrated circuit.Providing a larger contact area may improve cooling performance.

[0013] In one embodiment, the mechanical support element is configured to mechanically support the substrate, wherein the mechanical support element is configured to support the substrate via a peripheral region of the substrate. The increased space provided by sizing the substrate to exceed the die size facilitates configuring the mechanical support element to have high performance. The mechanical support element can, for example, contact the substrate over a larger area, thereby distributing forces applied to the substrate and reducing potentially damaging pressures and / or torques. Additionally, the larger contact area can allow the mechanical support element to facilitate improved cooling of the substrate by providing a highly thermally conductive path for heat to flow away from the substrate.

[0014] According to one aspect of the present invention, a chip assembly is provided, comprising: a chip including an integrated circuit formed in a semiconductor substrate, wherein the substrate has a size that exceeds the tube die size of a photolithography imaging system used during the manufacture of the integrated circuit; and a cooling element mounted to a peripheral area, which is formed laterally outside an internal area in the integrated circuit, wherein the cooling element includes a heat sink body defining one or more internal channels for directing the flow of a heat exchange fluid through the body.

[0015] According to one aspect of the present invention, a method for manufacturing a charged particle optical element is provided, the method comprising: manufacturing an integrated circuit within a die of a semiconductor wafer, the die size of the die being defined by a photolithography imaging system used during the manufacture of the integrated circuit; cutting a chip from the wafer, wherein the chip comprises an integrated circuit formed in a substrate originating from the wafer; forming at least one aperture in the substrate for passage through the substrate of at least one beam path of a charged particle beam, wherein: the size of the substrate exceeds the die size of the photolithography imaging system.

[0016] Advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings which illustrate and illustrate certain embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects of the present disclosure will become more apparent from the following description of exemplary embodiments with reference to the accompanying drawings.

[0018] Figure 1 is a schematic diagram illustrating an exemplary evaluation apparatus.

[0019] Figure 2 is shown as Figure 1Schematic diagram of an exemplary multi-beam charged-particle optical device with portions of an exemplary evaluation apparatus.

[0020] Figure 3 As Figure 1 Schematic diagram of an exemplary charged particle optics device including a collimator element array and a scanning deflector array of portions of an exemplary evaluation apparatus.

[0021] Figure 4 is included Figure 3 Schematic diagram of an exemplary charged particle optical device array of a charged particle optical device.

[0022] Figure 5 As Figure 1 Schematic diagram of an alternative exemplary charged-particle optical device of portions of an exemplary evaluation apparatus.

[0023] Figure 6 Yes, it can be Figure 3 、 Figure 4 as well as Figure 5 Schematic diagram of an exemplary charged particle optics module of a portion of a charged particle optics device.

[0024] Figure 7 is a schematic diagram of an exemplary charged particle optical element.

[0025] Figure 8 is a schematic diagram of an exemplary charged particle optical element.

[0026] Figure 9 yes Figure 8 Schematic plan view of a charged particle optical element of the type depicted.

[0027] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which, unless otherwise indicated, like reference numerals in different figures represent like or similar elements. The implementations set forth in the following description of the exemplary embodiments are not intended to represent all implementations consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with aspects related to the present invention as recited in the appended claims. DETAILED DESCRIPTION

[0028] By significantly increasing the packaging density of circuit components (such as transistors, capacitors, diodes, etc.) on IC chips, a reduction in the physical size of the device and an increase in the computing power of electronic devices can be achieved. This has been achieved through increased resolution that enables smaller structures to be manufactured. Semiconductor IC manufacturing is a complex and time-consuming process with hundreds of individual steps. An error in any step of the process of manufacturing an IC chip is likely to have an adverse effect on the functionality of the final product. Just one defect can cause a device failure. It is desirable to improve the overall yield of the process. For example, in order to obtain a 75% yield for a 50-step process (where a step may indicate the number of layers formed on a wafer), each individual step must have a yield higher than 99.4%. If a single step has a 95% yield, the yield of the entire process will be as low as 7-8%.

[0029] Maintaining a high substrate (i.e., wafer) throughput (defined as the number of substrates processed per hour) is also desirable. High process yield and high substrate throughput can be impacted by the presence of defects. This is particularly true if operator intervention is required to view the defect. High-throughput detection and identification of micro- and nano-scale defects by an evaluation system, such as a scanning electron microscope ("SEM"), is desirable for maintaining high yield and low cost for IC chips.

[0030] A scanning electron microscope (SEM) comprises a scanning device and a detector assembly. The scanning device includes an irradiation device comprising an electron source for generating primary electrons and a projection device for scanning a target (such as a substrate) using one or more focused beams of primary electrons. The primary electrons interact with the target and generate interaction products, such as signal particles, for example, secondary electrons and / or backscattered electrons. Secondary electrons can be considered to have energies up to 50 eV. Although backscattered electrons have an energy spectrum ranging from essentially zero to the maximum energy of a charged particle device, backscattered electrons are typically defined as electrons (or signal electrons) with energies exceeding 50 eV. The detection assembly captures the signal particles (such as secondary electrons and / or backscattered electrons) from the target as it is scanned, allowing the SEM to create an image of the scanned area of ​​the target. Charged particle optical device designs that embody these SEM characteristics can have a single beam. To achieve higher throughput (such as for evaluation), some device designs use multiple focused beams of primary electrons, known as multibeams. The component beams of a multibeam can be referred to as sub-beams or beamlets. Multiple beams can simultaneously scan different parts of a target. Thus, a multi-beam evaluation device can evaluate the target much faster than a single-beam evaluation device, for example by moving the target at a higher speed.

[0031] The implementation of a known multi-beam evaluation device is described below.

[0032] The accompanying drawings are schematic diagrams. Therefore, the relative sizes of the components in the drawings are exaggerated for clarity. In the following description of the figures, the same or similar reference numerals refer to the same or similar components or entities, and only the differences with respect to individual embodiments are described. Although the description and drawings are directed to electron-optical devices, it should be understood that these embodiments are not intended to limit the present disclosure to specific charged particles. Therefore, references to electrons and matters related to references to electrons in this document can be considered more generally as references to charged particles and matters related to references to charged particles, where the charged particles are not necessarily electrons.

[0033] Now refer to Figure 1 , Figure 1 is a schematic diagram illustrating an exemplary evaluation device 100 or inspection device. Figure 1 The evaluation apparatus 100 includes a vacuum chamber 10, a load lock chamber 20, a charged particle optical device, an equipment front end module (EFEM) 30, and a controller 50. The charged particle optical device 40 may be located within the vacuum chamber 10. The electron optical device may include the charged particle optical device 40 (also referred to as an electron optical device, an electron beam device, or an electron beam device) and a motorized or actuated stage.

[0034] The EFEM 30 includes a first load port 30a and a second load port 30b. The EFEM 30 may also include additional load port(s). The first load port 30a and the second load port 30b can, for example, receive front-opening pods (FOUPs) containing substrates (e.g., semiconductor substrates or substrates made of other material(s)) or targets to be evaluated (substrates, wafers, and samples are collectively referred to as "targets" hereinafter). One or more robotic arms (not shown) in the EFEM 30 transport the targets to the load lock chamber 20.

[0035] The load lock chamber 20 is used to remove gas from around the target. The load lock chamber 20 can be connected to a load lock vacuum pump system (not shown), which removes gas particles from the load lock chamber 20. Operation of the load lock vacuum pump system can cause the load lock chamber to reach a first pressure lower than atmospheric pressure. The main chamber 10 is connected to a main chamber vacuum pump system (not shown). The main chamber vacuum pump system removes gas molecules within the main chamber 10, causing the pressure around the target to reach a second pressure lower than the first pressure. After reaching the second pressure, the target is transferred to a charged particle optical device 40, through which the target can be evaluated. The charged particle optical device 40 can include a single beam or multi-beam charged particle optical device.

[0036] The controller 50 is electrically connected to the charged particle optical device 40. The controller 50 may be a processor (such as a computer) configured to control the charged particle beam evaluation apparatus 100. The controller 50 may also include processing circuitry configured to perform various signal and image processing functions. Figure 1 Controller 50 is shown as being located outside of the structure including main chamber 10, load lock chamber 20, and EFEM 30, but it should be understood that controller 50 can be part of the structure. Controller 50 can be located in one of the components of the charged particle beam evaluation device, or it can be distributed across at least two components. Although the present disclosure provides an example of a main chamber 10 housing an electron beam evaluation device, it should be noted that the aspects of the present disclosure, in its broadest sense, are not limited to chambers housing charged particle optical equipment. Rather, it should be understood that the foregoing principles can also be applied to other devices and other arrangements of devices operating at a second pressure.

[0037] Now refer to Figure 2 , Figure 2 is a schematic diagram of an exemplary multi-beam charged particle optical device 40 of an evaluation apparatus, e.g. Figure 1 Evaluation device 100. In an alternative embodiment, evaluation device 100 is a single-beam evaluation device. Charged particle optical device 40 may include electron source 201, beam former array 372 (also known as a gun aperture plate, Coulomb aperture array, or pre-beamlet forming aperture array), converging lens 310, source converter (or micro-optical array) 320, objective lens 331, and target 308. In one embodiment, converging lens 310 is magnetic. Target 308 may be supported by a support on a stage. The stage may be motorized. The stage moves so that target 308 is scanned by incident electrons. Electron source 201, beam former array 372, and converging lens 310 may be components of an irradiation device included in charged particle optical device 40. Source converter 320 (also known as a source conversion unit) (described in more detail below) and objective lens 331 may be components of a projection device included in charged particle optical device 40.

[0038] The electron source 201, the beam former array 372, the converging lens 310, the source converter 320, and the objective lens 331 are aligned with the main electron optical axis 304 of the charged particle optical device 40. The electron source 201 can generate a primary beam 302 that is substantially along the electron optical axis 304 and has a source intersection (virtual or real) 301S. During operation, the electron source 201 is configured to emit electrons. The electrons are extracted or accelerated by the extractor and / or the anode to form the primary beam 302.

[0039] The beam former array 372 cuts off the peripheral electrons of the primary electron beam 302 to reduce the resulting Coulomb effect. The primary electron beam 302 can be trimmed into a specified number of beamlets, such as three beamlets 311, 312, and 313, by the beam former array 372. It should be understood that the present description is intended to be applicable to charged particle optical devices 40 having any number of beamlets, such as one, two, or more than three. The beam former array 372 is configured to block peripheral electrons in operation to reduce the Coulomb effect.

[0040] Source converter 320 is configured to convert the beam (including beamlets, if any) transmitted by beamformer array 372 into beamlets that are projected onto target 308. In one embodiment, source converter is a single unit. Alternatively, the term source converter may be used simply as a collective term for a group of components that form a beam from beamlets.

[0041] like Figure 2 As shown, in one embodiment, the charged particle optical device 40 includes a beam-limiting aperture array 321 having an aperture pattern (i.e., apertures arranged in a certain pattern) configured to define the outer dimensions of the beam (or beamlets) projected toward the target 308. In one embodiment, the beam-limiting aperture array 321 is part of the source converter 320. In an alternative embodiment, the beam-limiting aperture array 321 is part of the system upbeam of the master device. In one embodiment, the beam-limiting aperture array 321 splits one or more of the beamlets 311, 312, and 313 into beamlets such that the number of beamlets projected toward the target 308 is greater than the number of beamlets transmitted through the beam former array 372. In an alternative embodiment, the beam-limiting aperture array 321 maintains the number of beamlets incident on the beam-limiting aperture array 321, in which case the number of beamlets can be equal to the number of beamlets projected toward the target 308.

[0042] like Figure 2 As shown, in one embodiment, the charged particle optical device 40 includes a pre-bend deflector array 323 having pre-bend deflectors 323_1, 323_2, and 323_3 to respectively bend beamlets 311, 312, and 313. The pre-bend deflectors 323_1, 323_2, and 323_3 can bend the paths of the beamlets 311, 312, and 313 onto the beam-limiting aperture array 321.

[0043] The charged particle optical device 40 may further include an imaging element array 322 having imaging deflectors 322_1, 322_2, and 322_3. Corresponding imaging deflectors 322_1, 322_2, and 322_3 are associated with the path of each beam wave. Deflectors 322_1, 322_2, and 322_3 are configured to deflect the path of the beam wave to the electron optical axis 304. The deflected beam wave forms a virtual image (not shown) of the source intersection 301S. In the current embodiment, these virtual images are projected onto the target 308 through the objective lens 331, and detection spots 391, 392, and 393 are formed on the target 308. The charged particle optical device 40 may further include an aberration compensator array 324, which is configured to compensate for the aberrations that may exist in each beamlet. In one embodiment, the aberration compensator array 324 includes a lens that is configured to operate on the corresponding beam wave. The lens may take the form of a lens array. The lenses in the array can operate on different beams in the multiple beams. The aberration compensator array 324 can, for example, include a field curvature compensator array (not shown), which can include, for example, microlenses. The field curvature compensators and microlenses can, for example, be configured to compensate for field curvature aberrations that occur in the detection spots 391, 392, and 393 of the individual beamlets. The aberration compensator array 324 can include an astigmatism compensator array (not shown) having micro-astigmatism correctors. For example, the micro-astigmatism correctors can be controlled to operate on the beamlets to compensate for astigmatism aberrations that would otherwise exist in the detection spots 391, 392, and 393.

[0044] The imaging element array 322, the aberration compensator array 324, and the pre-bent deflector array 323 may include multiple layers of beamlet steering devices, some of which may take the form of arrays, such as microdeflectors, microlenses, or microastigmatism correctors. The beam path may be rotationally steered. Rotational correction may be applied via magnetic lenses. Additionally or alternatively, rotational correction may be implemented via existing magnetic lenses, such as a converging lens arrangement.

[0045] Objective lens 331 focuses the beam onto the surface of target 308, i.e., objective lens 331 projects three virtual images onto the target surface. The three images formed on the target surface by the three beamlets 311 to 313 form three detection spots 391, 392, and 393 thereon. In one embodiment, the deflection angles of beamlets 311 to 313 are adjusted to pass through or approach the front focus of objective lens 331 to reduce or limit off-axis aberrations of the three detection spots 391 to 393. In one arrangement, objective lens 331 is magnetic. Although three beams are mentioned, this is merely an example. Any number of beams may be present.

[0046] In one embodiment, a beam splitter (not shown) is provided. The beam splitter can be a downbeam of the source converter 320. For example, the beam splitter can be a Wien filter comprising an electrostatic dipole field and a magnetic dipole field. The beam splitter can be an upbeam of the objective lens 331. In operation, the beam splitter can be configured to exert an electrostatic force on the individual electrons of the beamlet via the electrostatic dipole field. In one embodiment, the electrostatic force is equal in magnitude to, but opposite in direction to, the magnetic force exerted by the magnetic dipole field of the beam splitter on the individual primary electrons of the beamlet. Thus, the beamlet can pass through the beam splitter at least substantially in a straight line, with a deflection angle that is at least substantially zero. The direction of the magnetic force depends on the direction of motion of the electrons, whereas the direction of the electrostatic force does not depend on the direction of motion of the electrons. Therefore, since the primary electrons and backscattered electrons (or signal electrons) generally move in opposite directions compared to the primary electrons, the magnetic force exerted on the secondary electrons and backscattered electrons (or signal particles) will no longer cancel the electrostatic force. As a result, the secondary electrons and backscattered electrons moving through the beam splitter will be deflected away from the electron optical axis 304.

[0047] In one embodiment, a secondary device (not shown) is provided, which includes detection elements for detecting the corresponding secondary charged particle beam. When the secondary beam is incident on the detection elements, these elements can generate corresponding intensity signal outputs. These outputs can be directed to an image processing system (e.g., a controller 50). Each detection element can include an array, which can be in the form of a grid. The array can have one or more pixels; each pixel can correspond to an element of the array. The intensity signal output of the detection element can be the sum of the signals generated by all pixels within the detection element.

[0048] In one embodiment, a secondary projection device and its associated electronic detection equipment (not shown) are provided. The secondary projection device and its associated electronic detection equipment can be aligned with the secondary electron optical axis of the secondary device. In one embodiment, the beam splitter is arranged to deflect the path of the secondary electron beam toward the secondary projection device. The secondary projection device then focuses the path of the secondary electron beam onto multiple detection areas of the electronic detection equipment. The secondary projection device and its associated electronic detection equipment can use secondary electrons or backscattered electrons (or signal particles) to record and generate an image of the target 308.

[0049] Such a Wien filter, secondary device and / or secondary projection device can be provided in a single beam evaluation device. In addition and / or alternatively, the detection device can be present in the downstream beam of the objective lens, for example facing the sample during operation. In an alternative arrangement, the detector device is positioned along the path of the charged particle beam toward the sample. Such an arrangement does not have a Wien filter, secondary device and secondary projection device. The detection device can be positioned at one or more positions along the path of the charged particle beam toward the sample, such as facing the sample during operation, for example surrounding the path of the charged particle beam. Such a detector device can have an aperture and can be annular. Different detector devices can be positioned along the path of the charged particles to detect signal particles with different characteristics. Electron optical elements along the path of the charged particle beam (which may include one or more electrostatic plates with apertures for the path of the charged particle beam) can be arranged and controlled to focus signal particles with different corresponding characteristics onto corresponding detector devices at different positions along the path of the charged particle beam. Such electrostatic plates can be arranged in series with two or more adjacent plates along the path of the charged particle beam.

[0050] Any element or collection of elements within the charged particle optical device may be replaceable or field replaceable. One or more electron optical components in the charged particle optical device, particularly those that manipulate or generate beamlets, such as aperture arrays and manipulator arrays, may include one or more microelectromechanical systems (MEMS). The pre-bend deflector array 323 may be a MEMS. MEMS are micromechanical and electromechanical components manufactured using micromachining techniques. In one embodiment, the charged particle optical device 40 includes an aperture, lenses, and deflectors formed as MEMS. In one embodiment, the manipulators, such as lenses and deflectors 322_1, 322_2, and 322_3, may be passively controlled, actively controlled, controlled as an entire array, individually controlled, or controlled in groups within the array to control the beam wave of charged particles projected onto the target 308.

[0051] In one embodiment, the charged particle optical device 40 may include alternative and / or additional components in the charged particle path, such as lenses and other components, some of which have been previously described with reference to FIG. Figure 1 and Figure 2 An example of such an arrangement is Figure 3 and Figure 4 As shown, Figure 3 and Figure 4This will be described in more detail later. A detector is provided to detect charged particles emitted by the sample. The detector can be integrated into the objective lens. The detector can be located on the bottom surface of the objective lens so as to face the sample when in use. The detector can include an array, such as an array of detector elements, which can correspond to an array of beam waves arranged in a multi-beam arrangement. The detectors (or detector elements) in the detector array can generate detection signals that can be associated with pixels of the generated image. The converging lens, objective lens and / or detector can be formed as MEMS or CMOS devices.

[0052] Figure 3 2 is a schematic diagram of another design of an exemplary charged particle optical device 40. The charged particle optical device 40 may include a source 201 and one or more electron optical components. Alternatively, an electron optical arrangement including the charged particle optical device 40 may include the source 201. The charged particle optical device 40 may include a beam limiter 252, a collimator element array 271, a control lens array 250, a scanning deflector array 260, an objective lens array 241, a beam shaping limiter 242, and a detector array. The source 201 provides a beam of charged particles (e.g., electrons).

[0053] The upper beam limiter 252 defines an array of beam limiting apertures. The upper beam limiter 252 can be referred to as an upper beam limiting aperture array or an uplink beam limiting aperture array. The upper beam limiter 252 can include a plate (which can be a plate-shaped body) having multiple apertures. The upper beam limiter 252 forms the beam of charged particles emitted by the source 201 into a beamlet. Portions of the beam other than those that contribute to the formation of the beamlet can be blocked (e.g., absorbed) by the upper beam limiter 252 so as not to interfere with the downlink beam of the beamlet. The upper beam limiter 252 can be referred to as a beamlet limiting aperture array.

[0054] The collimator element array 271 is provided with the downlink beam of the upper beam limiter 252. Each collimator element collimates a corresponding sub-beam. The collimator element array 271 can be formed using MEMS manufacturing technology to be compact in space. In some embodiments, as shown in FIG. Figure 3 As illustrated in FIG, collimator element array 271 is the first deflecting or focusing electron optical array element in the downlink beam path of source 201. In another arrangement, the collimator can take the form of a macro-collimator in whole or in part. Such a macro-collimator can be the uplink beam of upper beam limiter 252, so that it operates on the beam from the source before generating multiple beams. A magnetic lens can be used as a macro-collimator.

[0055] The downstream beam of the collimator element array is the control lens array 250. The control lens array 250 includes a plurality of control lenses. Each control lens includes at least two electrodes (e.g., two or three electrodes) connected to corresponding potential sources. The control lens array 250 may include two or more (e.g., three) plate electrode arrays connected to corresponding potential sources. The control lens array 250 is associated with the objective lens array 241 (e.g., the two arrays are positioned close to each other and / or mechanically connected to each other and / or controlled together as a unit).

[0056] As described above, the control lens array 250 is associated with the objective lens array 241. As described above, the control lens array 250 can be considered to provide electrodes in addition to the electrodes 242 and 243 of the objective lens array 241, for example as part of the objective lens array assembly. The additional electrodes of the control lens array 250 allow further degrees of freedom for controlling the electron optical parameters of the beamlets.

[0057] For ease of illustration, the lens array is schematically represented herein by an array of ellipses. Each ellipse represents a lens in the lens array. Elliptical shapes are often used to represent lenses, similar to the biconvex form often used in optical lenses. However, in the context of charged particle arrangements such as the charged particle arrangements discussed herein, it should be understood that the lens array will typically operate electrostatically and therefore may not require any physical elements that utilize biconvex shapes. As mentioned above, the lens array can also instead include multiple plates with apertures.

[0058] A scanning deflector array 260 comprising a plurality of scanning deflectors may be provided. The scanning deflector array 260 may be formed using MEMS manufacturing techniques. Each scanning deflector scans a corresponding beamlet over the sample 208. In one embodiment, the scanning deflectors described in EP2425444, which is incorporated herein by reference in its entirety (particularly with respect to scanning deflectors), may be used to implement the scanning deflector array 260.

[0059] An objective lens array 241 comprising a plurality of objective lenses is provided to direct the beamlets onto the sample 208. Each objective lens comprises at least two electrodes (eg, two or three electrodes) connected to respective potential sources.

[0060] The objective lens array may form part of an objective lens array assembly together with any or all of the scanning deflector array 260, the control lens array 250 and the collimator element array 271. The objective lens array assembly may also include a beam shaping limiter 242. The beam shaping limiter 242 defines an array of beam limiting apertures.

[0061] In one arrangement, the beam shaping limiter 242 is structurally integrated with the electrodes 302 of the objective lens array 241. Ideally, the beam shaping limiter 242 is positioned in an area of ​​low electrostatic field strength. Each beam-limiting aperture is aligned with a corresponding objective lens in the objective lens array 241.

[0062] In one embodiment, the charged particle optical device 40 is configured to control the objective lens array assembly (e.g., by controlling the potential applied to electrodes of the control lens array 250) so that the focal length of the control lens is larger than the spacing between the control lens array 250 and the objective lens array 241.

[0063] Power may be provided to apply corresponding potentials to electrodes of the control lenses of the control lens array 250 and the objective lenses of the objective lens array 241 .

[0064] A detector array (not shown) is provided to detect charged particles emitted from the sample 208. The detected charged particles may include any charged particles (e.g., signal particles) detected by the scanning electron microscope, including secondary (e.g., emitted) electrons and / or backscattered electrons from the sample 208. The detector may be an array that provides a surface of the charged particle optical device facing the sample 208, such as the bottom surface of the charged particle optical device. Alternatively, the detector array may be an uplink beam of the bottom surface, such as an uplink beam of an objective lens array or a control lens array. The elements of the detector array may correspond to beam waves of a multi-beam arrangement. The signals generated by the detection of electrons by the elements of the array are sent to a processor for generating an image. The signals may correspond to pixels of the image.

[0065] In other embodiments, both a macro-scanning deflector and a scanning deflector array 260 are provided. In such an arrangement, scanning of the beamlets over the sample surface can be achieved by controlling the macro-scanning deflector and the scanning deflector array 260 together, preferably in a synchronized manner.

[0066] In one embodiment, Figure 4 As illustrated in FIG, an array of charged particle optical devices 500 is provided. The array 500 may include a plurality of charged particle optical devices of any charged particle optical device described herein. Each charged particle optical device simultaneously focuses a corresponding plurality of beams onto a different area of ​​the same sample.

[0067] Any number of charged particle optical devices may be used in array 500. When reference is made to a single charged particle optical device, each charged particle optical device in array 500 may be configured in any of the ways described herein, such as described above, particularly with respect to reference to Figure 3The details of such an arrangement are described in EPA 20184161.6 filed on July 6, 2020, which is incorporated herein by reference with respect to how the objectives can be combined and adapted for use in a multi-device arrangement.

[0068] exist Figure 4 In the example of the array 500, the array 500 includes the above reference Figure 3 A multiple charged particle optical device of the type described.

[0069] Alternative designs for multi-beam charged particle optics may have similarities to those described with respect to Figure 3 The same features as above, except as described below and Figure 5 In addition to the features shown in , an alternative design of a multi-beam charged particle optical device may include a converging lens array 231 for the upgoing beams of an objective lens array arrangement 241, as disclosed in EP application 20158804.3 filed on February 21, 2020, which is incorporated herein by reference for the description of a multi-beam device with a collimator and components thereof.

[0070] exist Figure 5 As shown in and referenced Figure 5 In one embodiment of the described arrangement, the detector may be located in a similar position in the charged particle optical device 40 as described with reference to FIG. Figure 3 The charged particle optical device described in Figure 3 The detector 240 can be integrated into the objective lens array 241 and the control lens array 250 (when present, Figure 5 (not depicted in FIG. 1 ). The detector may have more than one detector at different positions along the path of the beamlets of the multibeam.

[0071] like Figure 4 As shown in , the charged particle optical device array can have a Figure 3 The multi-beam device of this design describes multiple multi-beam devices. Multiple multi-beam devices can be arranged into an array of multi-beam devices. Such an arrangement is shown and described in EP application 20158732.6 filed on February 21, 2020, which is incorporated herein by reference regarding a multi-device arrangement of a multi-beam device, which is characterized by disclosing a design of a multi-beam device with a collimator at an intermediate focus. Another alternative design of the multi-beam device includes multiple single-beam devices.

[0072] The charged particle optical device 40 can be a component of an evaluation apparatus (e.g., for inspection, metrology, metrological inspection, or any other type of evaluation), or part of an electron beam lithography apparatus or other type of charged particle induced sample patterning apparatus. Multi-beam charged particle apparatuses can be used for a variety of different applications, including general electron microscopy (not just scanning electron microscopy) and lithography.

[0073] The charged particle optical device 40 may include, for example Figure 6 , for manipulating electron beam waves. For example, the charged particle optical module 55 may include one or more of the following (but not limited to the listed ones): the objective lens array 241 and / or the converging lens array 231 and / or the collimator element array 271 and / or the individual beam corrector and / or the deflector and / or the Wien filter array. Specifically, the objective lens 331 and / or the converging lens 310 and / or the control lens 250 may include the charged particle optical module 55. The charged particle optical module 55 is configured to provide a potential difference between two or more plates (or substrates).

[0074] Figure 6 The charged particle optical module 55 is schematically depicted. The charged particle optical module 55 is configured to guide electrons along at least one beam path to a sample location. Figure 6 In the orientation shown in , the at least one beam path passes vertically from top to bottom through the middle of the charged particle optical module 55. There may be one beam path corresponding to one electron beam. Alternatively, there may be multiple beam paths corresponding to multiple charged particle beamlets in a multi-beam.

[0075] like Figure 6 As shown in FIG, in one embodiment, the charged particle optical module 55 includes a plurality of planar elements arranged across the beam path. In one embodiment, one or more planar elements are charged particle optical elements 60. The charged particle optical element 60 is configured to operate on one or more charged particle beams. Figure 6As shown in , in one embodiment, all planar elements are charged particle optical elements 60. Alternatively, one or more planar elements may be planar elements other than charged particle optical elements. For example, one or more planar elements may be elements that do not require a voltage to perform their function, or the planar elements require a voltage to be applied so that there is a substantially zero potential difference between the element and adjacent elements along the beam path. One example is a planar element that is a beam-limiting aperture array that includes apertures sized to shape the charged particle beam. For example, these apertures can allow charged particle beams of a particular shape to pass through while blocking charged particles outside of these beams. As another alternative, the planar elements configured to shape the charged particle beam may also have a potential difference relative to the uplink beam planar element and / or the downlink beam planar element, so that the electromagnetic field affects the charged particle beam in addition to its beam-shaping function.

[0076] like Figure 6 As shown in FIG, in one embodiment, the charged particle optical module 55 includes one or more spacers 70. The spacers 70 are configured to mechanically support the planar element. Figure 6 As shown in , in one embodiment, spacers 70 are configured to mechanically isolate planar elements (such as charged particle optical elements 60) from each other. In one embodiment, spacers 70 are configured to electrically isolate planar elements (such as charged particle optical elements 60) from each other. However, it is not necessary for spacers 70 to provide electrical isolation. For example, two adjacent charged particle optical elements 60 can be arranged to operate at the same voltage (i.e., there is no potential difference between them), in which case electrical isolation may not be required. In one embodiment, one or more pairs of adjacent planar elements are adjacent to each other, i.e., without intermediate spacers 70. Spacers 70 are an optional feature.

[0077] The charged particle beam is configured to pass through the beam region 62 of the charged particle optical module 55. Figure 6 As shown in , beam region 62 can be located in a central portion of charged particle optical module 55. When viewed in a direction parallel to at least one beam path, beam region 62 is located substantially in the center. When viewed in a direction perpendicular to the plane of the planar element, beam region 62 is located in the center.

[0078] In one embodiment, the charged particle optical module 55 is included in the charged particle optical device 40 (e.g., Figure 2 、 Figure 3 and / or Figure 5 As shown and referenced 2, Figure 3 and / or Figure 5In one embodiment, the charged particle optics module 55 is field replaceable. The charged particle optics module 55 can be removed from the charged particle optics device 40 and / or inserted into the charged particle optics device 40 without requiring any substantial disassembly of the other components of the charged particle optics device 40. In other words, the charged particle optics module 55 can be removed from the charged particle optics device 40 and / or inserted into the charged particle optics device 40.

[0079] In one embodiment, the charged particle optical module 55 includes an objective lens assembly including an objective lens array 241. The charged particle optical module 55 may also include a control lens array 250, a detector 240, and / or a deflector array. In an alternative embodiment, the charged particle optical module 55 may be a converging lens assembly. The charged particle optical module 55 may include a converging lens array 231. The charged particle optical module 55 may also include one or more of a deflector array and / or a beam-limiting aperture array.

[0080] Figure 7 and Figure 8 is a schematic side cross-sectional view of an exemplary charged particle optical element 60 . Figure 9 yes Figure 8 Schematic plan view of an element 60 of the type depicted in FIG. For clarity, Figures 7 to 9 The relative sizes and / or aspect ratios in FIG. 6 are exaggerated. Element 60 may be configured to be suitable for incorporation into a charged particle optical module 55, such as Figure 6 The charged particle optical module 55 is shown in FIG. The charged particle optical module 55 is configured to guide charged particles to the sample 208 along at least one beam path.

[0081] In one embodiment, the charged particle optical element 60 comprises a chip. The chip includes an integrated circuit 64. The integrated circuit 64 is formed in a semiconductor substrate 61. The substrate 61 comprises or consists of a semiconductor material such as silicon. The chip is formed by cutting the substrate 61 from a larger substrate (such as a silicon wafer) after the integrated circuit has been formed using a photolithographic manufacturing process. The photolithographic manufacturing process uses a photolithographic imaging system to define the pattern to be formed in one or more layers of the integrated circuit. The substrate 61 can be substantially planar.

[0082] In one embodiment, integrated circuit 64 includes multiple layers. These layers may define one or more layers of circuitry. For example, these layers may define complementary metal oxide semiconductor (CMOS) circuitry. Thus, integrated circuit 64 may include CMOS components. In one embodiment, the CMOS circuitry includes one or more metal layers. In one embodiment, the integrated circuit is configured to detect signal particles emitted from a sample. For example, the metal layer may include one or more electrodes that may provide a surface of the CMOS circuitry on substrate 61 that may face sample 208 during operation. The metal layer may include detector elements configured to detect signal particles. These detector elements may be referred to as capture electrodes. Capture electrodes are examples of sensor cells used to detect signal particles. Power and control signals for the CMOS circuitry may be connected to the CMOS circuitry via electrical connections extending from an external region of integrated circuit 64 to integrated circuit 64. The CMOS circuitry may include a logic layer. This logic layer may be in a different layer from the one or more electrodes. The logic layer may include amplifiers such as transimpedance amplifiers (TIAs), filters, analog-to-digital converters (ADCs), and / or readout logic. In other embodiments, the integrated circuit may be formed using SiGe or GaAs technology. Thus, the integrated circuit may alternatively or additionally include SiGe circuitry or GaAs circuitry.

[0083] In one embodiment, Figure 7 and Figure 8 As illustrated in FIG, the substrate 61 includes (e.g., defines) at least one aperture 63. The aperture or each aperture 63 passes through the chip 61. The aperture or each aperture 63 is configured to allow at least one beam path to pass through the aperture or each aperture 63. Thus, each aperture 63 provides a route for at least one beam of charged particles to pass through the substrate 61. Figure 7 and Figure 8 In the example of FIG. 5 , the substrate 61 includes a plurality of apertures 63 . Each aperture 63 may allow one charged particle beam or a group of charged particle beams to pass through the aperture 63 . Figure 7 and Figure 8 Four apertures 63 are schematically shown. The number of apertures 63 can be much greater than four. Figure 7 and Figure 8As indicated in , an aperture 63 is provided in the beam region 62 of the charged particle optical element 60. In alternative embodiments, there may be only one aperture 63. For example, the charged particle optical device 40 including the charged particle optical element 60 may be configured to direct a single charged particle beam to the sample 208. Alternatively, a single aperture 63 may be used for the passage of multiple beamlets of a multibeam (or beam grid) through the single aperture 63. In this case, the charged particle optical element 60 having a single aperture 63 may be a macro element that is configured to operate on all beamlets of the multibeam.

[0084] like Figure 7 and Figure 8 As shown in FIG, in one embodiment, an integrated circuit 64 is located adjacent to one or more apertures 63. In one embodiment, the integrated circuit 64 surrounds each of the one or more apertures 63. In one embodiment, the integrated circuit 64 defines one or more electrodes at each aperture 63. In one embodiment, the integrated circuit 64 may include one or more electrodes defining the one or more apertures 63. These electrodes may operate on the charged particle beam passing through the aperture 63.

[0085] In one embodiment, the integrated circuit includes and / or controls one or more deflectors. Each deflector can be configured to operate a charged particle beam (or a group of charged particle beams) passing through a corresponding aperture 63. The deflector can be configured to control the direction of the charged particle beam downlink of the charged particle optical element 60. For example, the deflector can be configured to control the position at which the charged particle beam is incident on the downlink beam charged particle optical element 60 or the sample 208. The deflector can be configured to control whether one or more charged particle beams pass through the aperture of the downlink beam plane element or whether one or more charged particle beams are blocked by the downlink beam plane element.

[0086] In one embodiment, the integrated circuit 64 includes and / or controls a multipole. The multipole may include a plurality of electrodes for corresponding apertures 63. The multipole may be configured to correct one or more parameters of the charged particle beam passing through the aperture 63. For example, in one embodiment, the multipole may be an astigmatism corrector configured to adjust the shape of the charged particle beam passing through the aperture 63.

[0087] In one embodiment, the integrated circuit 64 includes and / or controls one or more aberration compensators or correctors. The aberration compensators can be formed as an aberration compensator array. In one embodiment, the aberration compensators can be configured to operate on individual apertures 63. For example, the aberration compensators can be configured to control the field curvature and / or astigmatism of the charged particle beam.

[0088] As described in the introduction to the specification, the charged particle optical element 60 may be subjected to significant heating during use. Heating may particularly occur within and / or near the beam region 62. Heating sources include charged particle beams and active electronic devices (such as integrated circuits 64). Embodiments of the present disclosure facilitate temperature control by configuring the substrate 61 to have a size (e.g., defined by the area of ​​the main surface of the substrate 61) that exceeds the die size (e.g., processable area) of the lithography imaging system used during the manufacture of the integrated circuit 64. Therefore, the substrate 61 is significantly larger in the transverse direction than is typically the case for a substrate 61 containing an integrated circuit 64. The substrate 61 can be described as extending laterally. Extending the substrate 61 laterally provides additional space in the peripheral region. The additional space can be utilized to improve the temperature control of the substrate 61. The additional space can be used to provide a more efficient cooling arrangement and / or position other heat sources further away from the beam region 62. Alternatively or additionally, the increase in size can provide design freedom for improving the mechanical support of the substrate 61. The improved mechanical support may be configured to facilitate temperature control of the substrate 61 , for example by providing a low thermal resistance path for heat to be efficiently conducted away from the substrate 61 .

[0089] In one embodiment, the size of substrate 61 is larger than the maximum die size of the lithographic imaging system. The maximum die size is the maximum die area that the lithographic imaging system can process. The die size of the lithographic imaging system can be referred to as the field size of the lithographic imaging system. In one embodiment, substrate 61 is at least 1.5 times larger, at least 2 times larger, at least 3 times larger, at least 4 times larger, or at least 5 times larger than the maximum die size of the lithographic imaging system. As a result of being larger than the die size, substrate 61 may include one or more scribe lane structures 67, such as scribe lane alignment marks. One or more scribe lane structures 67 may be formed in a scribe lane that is located outside of integrated circuit 64 when viewed perpendicular to the major surface of substrate 61. In one embodiment, one or more scribe lane structures 67 are located between integrated circuit 64 and at least a portion of peripheral region 83 when viewed perpendicular to the major surface of substrate 61. Such scribe lane structures 67 are typically not present in a chip after the chip has been cut from a larger semiconductor substrate (e.g., a silicon wafer) after integrated circuit 64 has been formed by a photolithographic manufacturing process. Thus, the presence of scribe street structures 67 indicates that the size of substrate 61 is larger than the die size of the photolithographic imaging system used during the fabrication of integrated circuit 64 .

[0090] Thus, a method for manufacturing a charged particle optical element 60 can be provided. The method includes manufacturing an integrated circuit 64 within a die of a semiconductor wafer. The die size of the die is defined by a photolithography imaging system, for example, by the field size of the photolithography imaging system. Any of various known types of photolithography imaging systems can be used. The integrated circuit 64 can take any of the forms described above. The method also includes cutting a chip from the wafer. The chip includes the integrated circuit 64 in a substrate 61 derived from the wafer. The method includes forming at least one aperture 63 in the substrate 61. The at least one aperture 63 can be formed, for example, by etching. The at least one aperture 63 can take any of the forms described above. The at least one aperture 63 is configured to allow at least one beam path of a charged particle beam to pass through the substrate 61. The method is configured such that the size of the substrate 61 exceeds the die size of the photolithography imaging system.

[0091] In one embodiment, substrate 61 includes an inner region 82 and a peripheral region 83. Integrated circuit 64 is formed within inner region 82. Peripheral region 83 does not have any functional integrated circuits. Thus, no portion of a functional integrated circuit is formed in peripheral region 83. Peripheral region 83 is located laterally outside inner region 82 when viewed perpendicular to a major surface of substrate 61 (e.g., perpendicular to the largest surface of substrate 61, such as the top surface or the bottom surface). Peripheral region 83 may extend to the outer boundary or edge of substrate 61. Peripheral region 83 may surround inner region 82 when viewed perpendicular to the major surface of substrate 61. Peripheral region 83 is integrally connected to inner region 82. Thus, the material of substrate 61 extends continuously from inner region 82 to peripheral region 83 without any interface or structural mismatch separating inner region 82 from peripheral region 83. For example, inner region 82 and peripheral region 83 may originate from the same silicon wafer and represent a single continuous portion of the silicon wafer. In one embodiment, inner boundary 81 of peripheral region 83 defines an area (when viewed perpendicular to the plane of substrate 61) that is equal in size (e.g., surface area) to the die size of a lithographic imaging system used during fabrication of the integrated circuit. Inner boundary 81 is Figures 7 to 9 Depicted by a dotted line.

[0092] In one embodiment, component 60 is configured to provide multiple conductive paths from peripheral region 83 to integrated circuit 64. These conductive paths may include one or more of the following: one or more redistribution layers; and one or more through-substrate vias (TSVs). These conductive paths allow components positioned laterally outside of inner region 82 to be electrically connected to integrated circuit 64.

[0093] In one embodiment, Figures 7 to 9As depicted in FIG, at least a subset of the conductive paths connects the integrated circuit 64 to the electronic unit 68. The electronic unit 68 may include a printed circuit board (PCB). In one embodiment, the electronic unit 68 is located on a side of the substrate 61 opposite the integrated circuit 64. Figure 7 and Figure 8 As shown, in some embodiments, the electronic unit 68 is provided on the up-beam side of the substrate 61 (located above the substrate 61 in the orientation shown), and the integrated circuit 64 is provided on the down-beam side of the substrate 61 (located below the substrate 61 in the orientation shown). In an alternative embodiment, the electronic unit 68 is provided at the down-beam side of the substrate 61.

[0094] In one embodiment, an electronic unit 68 (e.g., a PCB) is secured to the substrate 61. The electronic unit 68 may be bonded to the substrate 61. The electronic unit 68 may be secured to a major surface of the substrate 61. The electronic unit 68 may overlap a portion of the major surface of the substrate 61. Figure 7 and Figure 8 As shown in , in one embodiment, the electronic unit 68 extends laterally beyond the peripheral outer edge of the substrate 61. In one embodiment, the electronic unit 68 is configured to transmit power to the integrated circuit 64. For example, the electronic unit 68 can be electrically connected to a power supply configured to supply power to the integrated circuit 64. Additionally or alternatively, the electronic unit 68 can be configured to transmit a signal to the integrated circuit 64. For example, in one embodiment, the electronic unit 68 is configured to supply a control signal to the integrated circuit 64. The control signal can be, for example, a control signal for controlling the gain and / or offset of an analog-to-digital converter (ADC) included in the integrated circuit 64. In one embodiment, the electronic unit 68 is configured to transmit a signal from the integrated circuit 64. For example, in one embodiment, the electronic unit 68 is configured to transmit a signal indicative of a current of signal particles emitted from the sample 208 and detected at the substrate 61.

[0095] In one embodiment, Figure 7 and Figure 8 As depicted, the conductive path may include one or more TSVs 65. Each TSV passes through substrate 61 from the upper beam side of substrate 61 to the lower beam side of substrate 61. The TSVs allow electrical connection to be made between one side of substrate 61 and the other side of substrate 61.

[0096] In one embodiment, the charged particle optical element 60 may be the charged particle optical element for the lowest downstream beam in the charged particle optical device 40. There may be only a small gap between the charged particle optical element 60 and the sample 208. Alternatively, there may be only a small gap between the charged particle optical element 60 and the next component of the charged particle optical device 40. Thus, the upstream beam side of the substrate 61 may be more accessible than the downstream beam side of the substrate 61. The TSVs 65 direct electrical contact from the downstream beam side to the more accessible upstream beam side of the substrate 61.

[0097] In one embodiment, Figure 7 and Figure 8 As depicted in , the conductive path may include one or more conductive tracks in layer 69, which extends parallel to the plane of substrate 61. Layer 69 may include a coating on substrate 61 or a coating formed on a layer (e.g., an insulating layer) on substrate 61. The conductive path in layer 69 can be defined by applying a patterning process to the metal layer to selectively remove portions of the metal layer. Multiple patterned metal sublayers separated from each other by insulating sublayers can be formed to provide more complex wiring arrangements. The conductive tracks in different sublayers can be selectively interconnected by appropriately positioned metal vias. Thus, layer 69 may include one or more sublayers containing conductive tracks that are configured to distribute electrical signals or power laterally. Layer 69 may be referred to as a redistribution layer.

[0098] exist Figure 7 In the example shown, a layer 69 containing conductive tracks is provided on the same side of the substrate 61 as the integrated circuit 64 (i.e., below the substrate 61 in the orientation shown). The layer 69 extends from an area at least laterally overlapping the integrated circuit 64 to an area laterally outside the integrated circuit 64, optionally laterally overlapping a peripheral area 83 of the substrate 61. Figure 7 In the example shown, layer 69 laterally overlaps the location of an electronic unit 68 (e.g., a PCB). One or more TSVs 65 provide electrical connections between layer 69 and electronic unit 68. In other embodiments, an additional layer 69 may be provided on the side of substrate 61 where electronic unit 68 is located to allow electrical signals or power to be directed laterally to appropriate electrical connection points of electronic unit 68.

[0099] exist Figure 8 In the example of FIG, a layer 69 containing conductive tracks is provided on a side of the substrate 61 opposite the integrated circuit 64 (i.e., above the substrate 61 in the orientation shown). The layer 69 extends from an area that at least laterally overlaps one or more TSVs 65 that are configured to provide direct or indirect electrical connection to the integrated circuit 64 through the substrate 61. Figure 8, TSVs 65 are shown that provide connections directly from integrated circuit 64 to layer 69 above substrate 61. In other embodiments, layer 69 may redistribute signals or power laterally away from integrated circuit 64 before connecting to one or more TSVs 65 to provide electrical connections through substrate 61 to layer 69 above substrate 61.

[0100] In one embodiment, layer 69 is configured to transmit power and / or communication signals (eg, control signals) between electronic unit 68 and integrated circuit 64. Conductive tracks in layer 69 may be soldered or wire-bonded to electronic unit 68, for example.

[0101] Figure 9 The view in FIG is from the uplink beam side of the substrate 61. The beam region 62 is circular in the example shown, but may include any other shape, including, for example, a square, rectangle, hexagon, or any other regular or irregular polygon. In one embodiment, the charged particle optical element 60 includes one or more connector regions 75. The connector region 75 is the region where a plurality of TSVs 65 are located. These TSVs may be arranged relatively close to each other within the connector region 75. Figure 9 In the example of FIG, the element 60 comprises three connector areas 75. In one embodiment, the number of connector areas 75 is one, two, four or more than four. Each connector area 75 is connected to the electronic unit 68 via a conductive track in the corresponding layer 69.

[0102] In one embodiment, Figures 7 to 9As schematically shown in FIG, a cooling element 86 may be provided for cooling substrate 61. In one embodiment, cooling element 86 is mounted to a peripheral region 83 of substrate 61. In the example shown, cooling element 86 is mounted to the uplink side of substrate 61. Cooling element 86 is mounted to provide a high thermal conductivity connection to substrate 61. Having a high thermal conductivity connection improves the efficiency with which heat can be conducted away from substrate 61, thereby improving cooling performance. In one embodiment, cooling element 86 is connected to substrate 61 via a relatively large contact area. Providing a relatively large contact area promotes high thermal conductivity. As described above, sizing substrate 64 to exceed the die size of the photolithography imaging system used during the fabrication of integrated circuit 64 facilitates providing a large contact area. For example, in one embodiment, the contact area is greater than 10% of the die size, optionally greater than 20% of the die size, optionally greater than 30% of the die size, optionally greater than 40% of the die size, or optionally greater than 50% of the die size. In one embodiment, the cooling element 86 includes a heat sink body (e.g., a block of material having a relatively high heat capacity and thermal conductivity). The heat sink body defines one or more internal channels 88 for directing the flow of a heat exchange fluid through the body. The increased space provided by arranging the size of the substrate 64 to exceed the size of the tube core facilitates configuring the cooling element 86 to have high performance. This can be achieved, for example, by increasing the size of the cooling element 86 to improve its function as a heat sink. Alternatively or additionally, the increased space can allow more efficient internal channels 88 to be formed in the heat sink body, for example, by configuring the cooling channels to provide a greater flow rate and / or increasing the surface area of ​​contact between the heat exchange fluid and the walls of the internal channels 88. In one embodiment, a liquid management system can be provided for driving the flow of the heat exchange fluid through the one or more internal channels 88.

[0103] In one embodiment, Figure 9 As shown in , mechanical support elements 84 may be provided for mechanically supporting the substrate 61. Figure 9In the example shown, two of the mechanical support elements 85 are provided. Each mechanical support element 84 is configured to mechanically support the substrate 61 via a peripheral region 83 of the substrate 61. Thus, each mechanical support element 84 can be mechanically connected to the substrate 61 partially or entirely in the peripheral region 83. Each mechanical support element 84 can be rigidly connected directly or indirectly to the substrate 61. Each mechanical support element 84 can rigidly connect the substrate 61 to another element of the module 55 or to one or more elements external to the module 55. The increased space provided by sizing the substrate 61 larger than the die size facilitates configuring each mechanical support element 84 to have high performance. Each mechanical support element 84 can, for example, contact the substrate 61 over a larger area, thereby distributing forces exerted on the substrate 61 and reducing potentially damaging pressure and / or torque. Additionally, the larger contact area can allow the mechanical support elements 84 to facilitate improved cooling of the substrate 61 by providing a highly thermally conductive path for heat to flow away from the substrate 61.

[0104] The arrangement of the present disclosure may be embodied in an evaluation device for evaluating a sample 208 using charged particles. The evaluation device may take the form of the device described above with reference to Figure 1 The evaluation device may include a charged particle optical device 40. The charged particle optical device may take the form of a charged particle optical device as described above. Figures 2 to 5 In one embodiment, the evaluation apparatus comprises a sample holder configured to support the sample 208. In one embodiment, the evaluation apparatus comprises a charged particle optical module 55 configured to direct the charged particles along at least one beam path to the sample 208. The charged particle module 55 may take the form described above, for example, with reference to Figures 6 to 9 Any of the forms described.

[0105] In one embodiment, a chip assembly is provided. The chip assembly includes a chip including an integrated circuit 64 formed in a semiconductor substrate 61. The substrate 61 may include an aperture 63 for a beam path. Thus, the chip may take the form described above with reference to FIG. Figures 7 to 9 Alternatively, the substrate 61 of the chip assembly may be provided without any aperture 63 for the beam path. Thus, the chip of the chip assembly may be used in contexts other than as part of a charged particle optical element. In this case, the chip may take the form described above with reference to Figures 7 to 9any of the forms described, but without aperture 63. In one embodiment, the dimensions of substrate 61 exceed the die dimensions of a lithographic imaging system used during fabrication of integrated circuit 64. As described above, configuring substrate 61 to have a die dimension that exceeds the die dimensions of a lithographic imaging system used during fabrication of integrated circuit 64 can facilitate temperature control of the chip by providing more space in the peripheral region 83 of substrate 61. In one embodiment, a cooling element is mounted to the peripheral region 83. The peripheral region 83 is located laterally outside of the interior region 82 in which the integrated circuit 64 is formed. The cooling element 86 may include a heat sink and / or define one or more internal channels 88 for directing the flow of a heat exchange fluid. The cooling element 86 and / or the internal channels 88 may take the form described above with reference to Figure 7 and Figure 8 In one embodiment, a fluid management system is provided for driving the flow of a heat exchange fluid through one or more internal channels 88. In one embodiment, the chip includes one or more scribe structures between the integrated circuit 64 and the peripheral region 83.

[0106] In one embodiment, charged particle optical element 60 and / or charged particle optical module 55 can be formed using micro-electromechanical components (MEMS) manufacturing technology and / or be referred to as MEMS elements. One or more such elements can be controlled to be set with a high potential difference relative to a reference potential (e.g., ground) during use. Such elements can be electrically connected to one or more voltage sources for supplying voltage to the element. In one embodiment, a controller is configured to control the voltage applied to the element.

[0107] Examples are provided according to the following numbered clauses:

[0108] Clause 1: A charged particle optical element for use in a charged particle optical module configured to guide charged particles along at least one beam path toward a sample, the charged particle optical element comprising:

[0109] A chip comprising an integrated circuit formed in a semiconductor substrate, the substrate defining at least one aperture for passage of the at least one beam path therethrough, wherein:

[0110] The dimensions of the substrate exceed the die dimensions of a photolithographic imaging system used during fabrication of the integrated circuit.

[0111] Clause 2. The element of clause 1, wherein the integrated circuit is configured to detect signal particles emitted from the sample.

[0112] Clause 3. The element of clause 1 or 2, wherein the integrated circuit comprises: complementary metal oxide semiconductor (CMOS) circuitry; SiGe circuitry; and / or GaAs circuitry.

[0113] Clause 4. An element according to any preceding clause, wherein:

[0114] The substrate includes an inner region and a peripheral region;

[0115] The integrated circuit is formed within the inner region;

[0116] The peripheral area does not have any functional integrated circuits; and

[0117] The peripheral region is laterally outside the inner region when viewed perpendicularly to the major surface of the substrate.

[0118] Clause 5. The element of Clause 4, wherein the inner boundary of the peripheral region defines an area equal in size to the die size of the photolithographic imaging system used during fabrication of the integrated circuit when viewed perpendicular to the major surface of the substrate.

[0119] Item 6. The component of Item 4 or 5, configured to provide a plurality of conductive paths from the peripheral region to the integrated circuit.

[0120] Clause 7. The component of clause 6, wherein one or more of the conductive paths comprises:

[0121] one or more redistribution layers; and

[0122] One or more through substrate vias (TSVs).

[0123] Item 8. An element according to any one of Items 4 to 7, wherein the substrate includes one or more scribe lane structures, the one or more scribe lane structures being formed in scribe lanes that are located outside the integrated circuit when viewed perpendicular to the main surface of the substrate.

[0124] Item 9. The component of Item 8, wherein the one or more scribe lane structures are located between the integrated circuit and at least a portion of the peripheral region when viewed perpendicular to the main surface of the substrate.

[0125] Clause 10. The element of Clause 8 or 9, wherein the one or more scribe lane structures include one or more alignment marks.

[0126] Item 11. A charged particle optical module comprising an element according to any preceding claim, wherein the substrate comprises an inner region and a peripheral region, the integrated circuit being formed within the inner region, the peripheral region being free of any functional integrated circuits, and the peripheral region being laterally outside the inner region when viewed perpendicularly to a major surface of the substrate.

[0127] Clause 12. The module of Clause 11, further comprising a cooling element mounted to the peripheral region and configured to extract heat from the substrate.

[0128] Clause 13. The module of Clause 12, wherein the cooling element comprises a heat sink body defining one or more internal channels for directing the flow of a heat exchange fluid through the body.

[0129] Clause 14. The module of Clause 12 or 13, wherein the contact area between the cooling element and the substrate is greater than 10% of the die size of a photolithographic imaging system used during fabrication of the integrated circuit.

[0130] Clause 15. The module of any one of clauses 11 to 14, further comprising a mechanical support element configured to mechanically support the substrate, wherein the mechanical support element is configured to support the substrate via the peripheral region of the substrate.

[0131] Clause 16. An evaluation device for evaluating a sample using charged particles, the device comprising:

[0132] a sample holder configured to support a sample; and

[0133] A module according to any of clauses 11 to 15, configured to direct charged particles along at least one beam path towards the sample.

[0134] Clause 17. A chip assembly comprising:

[0135] a chip comprising an integrated circuit formed in a semiconductor substrate, wherein a size of the substrate exceeds a die size of a photolithographic imaging system used during fabrication of the integrated circuit; and

[0136] a cooling element mounted to a peripheral region laterally outward from an interior region in which the integrated circuit is formed, wherein the cooling element includes a heat sink body defining one or more internal channels for directing a flow of a heat exchange fluid through the body.

[0137] Clause 18. The chip assembly of Clause 17, wherein the chip comprises one or more scribe lane structures formed in scribe lanes that are located outside of the integrated circuit when viewed perpendicular to the main surface of the substrate.

[0138] Clause 19. A method of manufacturing a charged particle optical element, comprising:

[0139] fabricating integrated circuits within dies of a semiconductor wafer, said dies having die dimensions defined by a photolithographic imaging system used during said fabrication of said integrated circuits;

[0140] cutting chips from the wafer, wherein the chips include the integrated circuits formed in a substrate derived from the wafer;

[0141] At least one aperture is formed in the substrate for passage of at least one beam path of a charged particle beam through the substrate, wherein:

[0142] The size of the substrate exceeds the die size of the lithographic imaging system.

[0143] Although the present invention has been described in conjunction with various embodiments, other embodiments of the present invention will be apparent to those skilled in the art by considering the description and practice of the invention disclosed herein. For example, as described above in the embodiments, the substrate has portions of different thicknesses, wherein the electrical connector extends through the thinner portion. However, the thickness of the substrate may alternatively be uniform. The electrical connection for the electronic components may be closer to the periphery of the substrate than the electronic components, and the conductive layer may be electrically connected to the electrical connection. The description and examples are intended to be considered as merely exemplary, and the true scope and spirit of the present invention are indicated by the appended claims.

[0144] The above description is intended to be illustrative and not restrictive. Therefore, it will be appreciated by those skilled in the art that modifications may be made as described without departing from the scope of the claims and clauses as set forth.

[0145] Although the present invention has been described in conjunction with various embodiments, other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the invention being indicated by the claims.

Claims

1. A charged particle optical element for use in a charged particle optical module, the charged particle optical module being configured to guide charged particles along at least one beam path toward a sample, the charged particle optical element comprising: A chip comprising an integrated circuit formed in a semiconductor substrate, the substrate defining at least one aperture for passage of the at least one beam path therethrough, wherein: The dimensions of the substrate exceed the maximum die size of a photolithographic imaging system used during fabrication of the integrated circuit. 2 . The element according to claim 1 , wherein the integrated circuit is configured to detect signal particles emitted from the sample.

3. The component according to claim 1 or 2, wherein the integrated circuit comprises: Complementary Metal Oxide Semiconductor (CMOS) circuit system; SiGe circuit system; and / or GaAs circuitry.

4. The element according to claim 1, wherein: The substrate includes an inner region and a peripheral region; The integrated circuit is formed within the inner region; The peripheral area does not have any functional integrated circuits; and The peripheral region is laterally outside the inner region when viewed perpendicularly to the major surface of the substrate.

5. The element of claim 4, wherein the inner boundary of the peripheral region defines an area that is equal in size to the die size of the photolithographic imaging system used during fabrication of the integrated circuit when viewed perpendicular to the major surface of the substrate. 6 . The component of claim 4 , configured to provide a plurality of conductive paths from the peripheral region to the integrated circuit.

7. The component of claim 6, wherein one or more of the conductive paths comprises: one or more redistribution layers; as well as One or more through substrate vias (TSVs).

8. The element according to claim 4, wherein the substrate includes one or more scribe lane structures formed in scribe lanes that are located outside the integrated circuit when viewed perpendicularly to the main surface of the substrate. 9 . The component according to claim 8 , wherein the one or more scribe lane structures are located between the integrated circuit and at least a portion of the peripheral region when viewed perpendicularly to the main surface of the substrate.

10. A charged particle optical module comprising an element according to any preceding claim, wherein the substrate comprises an inner region and a peripheral region, the integrated circuit being formed within the inner region, the peripheral region being free of any functional integrated circuits and being laterally outside the inner region when viewed perpendicularly to a major surface of the substrate.

11. The module of claim 10, further comprising a cooling element mounted to the peripheral region and configured to extract heat from the substrate.

12. The module of claim 11, wherein the contact area between the cooling element and the substrate is greater than 10% of the die size of a photolithographic imaging system used during fabrication of the integrated circuit. 13 . The module of claim 10 , further comprising a mechanical support element configured to mechanically support the substrate, wherein the mechanical support element is configured to support the substrate via the peripheral region of the substrate.

14. An evaluation device for evaluating a sample using charged particles, the device comprising: a sample holder configured to support a sample; as well as A module according to any one of claims 10 to 13, configured to direct charged particles along at least one beam path towards the sample.

15. A chip assembly comprising: a chip comprising an integrated circuit formed in a semiconductor substrate, wherein a size of the substrate exceeds a maximum die size of a lithographic imaging system used during fabrication of the integrated circuit; and a cooling element mounted to a peripheral region laterally outward from an interior region in which the integrated circuit is formed, wherein the cooling element includes a heat sink body defining one or more internal channels for directing a flow of a heat exchange fluid through the body.

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