Method of etching features in stack

Abstract

A method of etching features in a stack is presented, the stack including a silicon oxide layer under a mask. A substrate support is cooled to a temperature below 0 DEG C, the substrate support for supporting the stack in the etch chamber. An etching gas is provided, the etching gas including a halogen-containing component and a phosphorus-containing component. A plasma is generated from the etching gas. A bias is provided to accelerate ions from the plasma to the stack. Features are selectively etched in the stack relative to the mask.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. application No. 63 / 448,049, filed on February 24, 2023, which is incorporated herein by reference. Technical Field

[0002] The present disclosure relates to methods for forming semiconductor devices on semiconductor wafers. More particularly, the present disclosure relates to etching stacks during the formation of memory or other semiconductor devices. Background Art

[0003] During the formation of semiconductor devices, an etch layer can be etched to form memory holes or lines. Some semiconductor devices can be formed by etching a stack of silicon oxide and silicon nitride (ONON) layers. Such stacks can be used in memory applications, such as forming dynamic random access memory (DRAM) and three-dimensional negative-AND gates (3D NAND).

[0004] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. The information described in this background section and aspects of the specification that were not determined to be prior art at the time of filing the application are neither explicitly nor implicitly admitted to be prior art against the present disclosure. Summary of the Invention

[0005] To achieve the foregoing and in accordance with the objectives of the present disclosure, a method for etching features in a stack comprising a silicon oxide layer beneath a mask is provided. A substrate support is cooled to a temperature below 0°C, the substrate support being used to support the stack in an etching chamber. An etching gas is provided, the etching gas comprising a halogen-containing component and a phosphorus-containing component. A plasma is generated from the etching gas. A bias is provided to accelerate ions from the plasma toward the stack. A plurality of features are selectively etched in the stack relative to the mask.

[0006] In another embodiment, an apparatus for processing a stack above a substrate, the stack having at least one silicon oxide layer, is provided. An etching chamber includes a substrate support for supporting the substrate within the etching chamber. A temperature controller controls the temperature of the substrate support. A gas source provides an etching gas to the etching chamber. The gas source includes a halogen-containing component source and a phosphorus-containing component source. An electrode provides power to the etching gas. A power supply provides power to the electrode.

[0007] In another aspect, a method of etching features in a stack comprising a silicon oxide layer beneath a mask is provided. A substrate support is cooled to a temperature below 0° C., the substrate support supporting the stack in an etching chamber. An etching gas is provided, the etching gas comprising a halogen-containing component and a phosphorus-containing component. Multi-state power is provided, the multi-state power having at least three states, wherein the multi-state power generates a plasma from the etching gas and provides a bias to accelerate ions from the plasma into the stack. A plurality of features are selectively etched in the stack relative to the mask.

[0008] These and other features of the present disclosure will be described in more detail below in the detailed description and in conjunction with the following figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings and in which like references indicate similar elements and in which:

[0010] Figure 1 is a high-level flow chart that may be used in some embodiments.

[0011] Figure 2A -B is a schematic cross-sectional view of a stack processed according to one embodiment.

[0012] Figure 3 is a schematic diagram of an etch chamber that may be used in some embodiments.

[0013] Figure 4 is a schematic diagram of a computer system that can be used to implement one embodiment.

[0014] Figure 5 is a high-level flow chart that may be used in some embodiments.

[0015] Figure 6A is the clock signal used in some implementations.

[0016] Figure 6B A digital pulse signal is depicted for use in some embodiments.

[0017] Figure 6C Depicted are RF signals used in some embodiments.

[0018] Figure 7 is a schematic diagram of another etch chamber that may be used in some embodiments. DETAILED DESCRIPTION

[0019] The present invention will now be described in detail with reference to several preferred embodiments shown in the accompanying drawings. In the following description, many specific details are set forth in order to provide a thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without some or all of these specific details. In other cases, well-known process steps and / or structures are not described in detail in order to avoid unnecessarily obscuring the present invention.

[0020] In very high aspect ratio contact dielectric etching, especially during low temperature etching of 3D NAND columnar structures, there is a significant challenge in controlling the profile: large bow CD with small bottom CD. This may be due to increased accumulation of byproducts near the etch front, which slows down the SiO2 reactive ion etching (RIE). The most common way to increase the etch rate (ER) of high aspect ratios is to increase the ion energy and ion flux. This leads to poor bow CD control (larger bow). Another common practice to increase bottom CD and ER is to change the plasma chemistry. This approach can cause other problems such as increased bow, capping, or excessive contact distortion.

[0021] In some embodiments, the etch front surface is modified to enhance etching of silicon oxide (SiO2, also known as SiO) and silicon nitride (Si3N4, also known as SiN). Some embodiments add a phosphorus (P)-containing precursor to the plasma. It is believed that the P-containing precursor causes P doping of the SiO2 and Si3N4 materials. The doped SiO2 material will lower the activation energy of the RIE. Therefore, even low-energy ions from the plasma can provide etching. Phosphine (PH3) and phosphorus trifluoride (PF3) are two main compounds that can be used as P-containing precursors in some embodiments. Some embodiments can use other compounds, such as phosphorus trichloride (PCl3), phosphorus tribromide (PBr3), phosphorus oxyfluoride (POF3), or phosphorus triiodide (PI3), which are liquid or solid at room temperature and are therefore more difficult to produce. Some embodiments can use phosphorus pentafluoride (PF5).

[0022] For RIE, phosphorus doping to reduce the etching activation energy of SiO2 and Si3N4 will help maintain a high ONON pillar ER, even at high aspect ratios. This will enable more efficient utilization of the reactive ions delivered to the etch front. Some embodiments make silicon oxide etching more chemical in nature and more similar to silicon nitride etching, thereby providing a more uniform ONON etch. In some embodiments, boron can be used to provide boron doping for RIE.

[0023] For ease of understanding, Figure 11 is a high-level flow chart that can be used in some embodiments. In some embodiments, the stack is placed on a substrate support in an etching chamber (step 104). In some embodiments, the stack is placed under a patterned carbon-containing mask. In some embodiments, the carbon-containing mask is an amorphous carbon mask. Figure 2A is a schematic cross-sectional view of a stack 200 used in embodiments. In some embodiments, the stack includes a substrate 208 below a plurality of bilayers 212, with the plurality of bilayers 212 located below a patterned carbon-containing mask 216. One or more layers may be located between the substrate 208 and the plurality of bilayers 212, or between the plurality of bilayers 212 and the patterned carbon-containing mask 216. However, some embodiments do not include a silicon-containing mask above the plurality of bilayers 212 or above the patterned carbon-containing mask 216. The patterned carbon-containing mask 216 may be amorphous carbon. In some embodiments, the patterned mask pattern provides mask features 220 for high aspect ratio contacts. In some embodiments, the mask features are formed before the substrate is placed in the etch chamber. In other embodiments, the mask features 220 are formed while the substrate is in the etch chamber. In some embodiments, the plurality of bilayers 212 are bilayers of a silicon oxide 224 layer and a silicon nitride 228 layer.

[0024] After the stack 200 has been placed in the etching chamber, the stack is cooled by providing a cooler temperature below 0° (step 108). The cooler cools the coolant, which cools the stack 200. In some embodiments, the cooler is cooled to a temperature below -40°.

[0025] An etching gas comprising a halogen-containing component and a phosphorus-containing component is provided (step 112). In some embodiments, the etching gas is flowed into the etching chamber. In some embodiments, the etching gas comprises a halogen-containing component, a phosphorus-containing component, a hydrogen-containing component, a hydrocarbon-containing component, and a fluorocarbon-containing component. In some embodiments, the halogen-containing component comprises a bromofluorocarbon C x Br y F z , chlorofluorocarbons C x Cl y F z , chlorinated hydrocarbons C x H y Cl z , brominated hydrocarbons C x H y Br z , fluorinated hydrocarbons C x H y F z , fluorocarbon C x F yThe etching gas may further include at least one of: silicon tetrachloride (SiCl4), boron trichloride (BCl3), nitrogen trifluoride (NF3), C4F8, octafluoropropane (C3F8), hexafluoro-1,3-butadiene (C4F6), sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), chlorine (Cl2), hydrogen bromide (HBr), trifluoroiodomethane (CF3I), fluoromethane (CH3F), difluoromethane (CH2F2), hydrogen chloride (HCl), and trifluoromethane (CHF3). In some embodiments, the halogen-containing component is a metal halide. In some embodiments, the etching gas further includes at least one of methane (CH4), hydrogen fluoride (HF), and hydrogen (H2). In some embodiments, the etching gas further includes an inert gas such as argon (Ar), helium (He), krypton (Kr), neon (Ne), xenon (Xe), or nitrogen (N2). In some embodiments, the inert gas provides ions for ion bombardment to promote etching and can therefore be an inert bombardment gas. In some embodiments, the etching gas is oxygen-free and does not contain octafluorocyclobutane (C4F8) and hexafluorocyclobutene (C4F6). In some embodiments, the etching gas further includes at least one of methane (CH4) and hydrogen (H2). In some embodiments, the phosphorus-containing component is at least one of PF5, PH3, PF3, PCl3, PBr3, POF3, and PI3. In some embodiments, examples of etching gases include 5-120 sccm NF3, 50-400 sccm H2, 0-100 sccm CH3F, 1-100 sccm PH3, 0-100 sccm Cl2, 0-100 sccm HBr, and 20-200 sccm CH2F2. In this example, a pressure of 5 to 60 mTorr is provided. In some embodiments, the halogen-containing component can include a fluorine-, chlorine-, or bromine-containing component.

[0026] The etching gas is formed into an etching plasma (step 116). This can be achieved by providing an excitation RF with a frequency of 60 megahertz (MHz) and 200 to 15,000 watts. In some embodiments, the RF power is in the range of 0 to 25,000 watts at a frequency of 60 MHz. The stack 200 is exposed to the plasma (step 120). A bias is provided in the range of 200 volts to 15,000 volts (step 124). In some embodiments, the bias power is at least 200 volts. In some embodiments, the RF power can be used to use both an excitation RF power of a higher frequency and a bias RF power of a lower frequency, and the RF power is a continuous RF power or a pulsed RF power with a peak power in the range of 3 kW to 150 kW. The bias causes ions to be accelerated to the stack 200, thereby causing selective etching of high aspect ratio etch features (relative to the patterned carbon-containing mask) into the stack 200 (step 128). In some embodiments, the bias is provided by a pulsed bias with at least two states, wherein the bias source is a pulsed bias source. The bias source may include a primary pulsed bias source and an auxiliary pulsed bias source. In some embodiments, the bias is provided by an RF power source. The plasma is maintained for 180 to 3600 seconds. The etch is capable of etching both silicon oxide and silicon nitride layers. After the etch is complete, the substrate is then removed from the etch chamber (step 132).

[0027] Figure 2B FIG2 is a cross-sectional view of stack 200 after contact 232 has been etched. The contact is a high aspect ratio contact. Preferably, the contact has an aspect ratio of etch depth to feature CD width greater than 30:1. Preferably, the high aspect ratio contact has a height to CD width ratio greater than 40:1. More preferably, the high aspect ratio contact has a height to CD width ratio greater than 100:1.

[0028] The etching process is capable of selectively etching silicon oxide and silicon nitride layers relative to amorphous carbon with a selectivity greater than 3:1 while etching high aspect ratio features. The resulting features also have reduced bowing, striations, distortion, capping, and tapering. In addition, the present embodiment allows the use of a patterned carbon-containing mask (e.g., amorphous carbon) without the need for a silicon-containing mask (e.g., polysilicon), resulting in reduced cost and defects.

[0029] Previous processes using etching (where the stack is processed at temperatures above 0°C) rely on fluorocarbon chemistries to etch and provide sidewall protection. Such processes result in etch selectivities of less than 3:1 mask ratio to silicon oxide and silicon nitride. Sidewall protection is provided by polymer deposition, which is controlled by carbon concentration (where higher concentrations of carbon increase sidewall deposition) and by oxygen (where higher concentrations of oxygen consume the deposited polymer). Higher concentrations of oxygen also increase mask consumption. Some previous processes use silicon-containing masks.

[0030] Compared to traditional methods, some embodiments increase the etching rate and improve the contact shape / stripes. Without being limited by theory, it is believed that adding a phosphorus-containing component to the etching gas causes phosphorus dopants to be deposited in the silicon-containing oxide and silicon nitride layers. The phosphorus dopant reduces the activation energy required to etch the silicon-containing oxide layer, thereby making the silicon oxide easier to etch and making the lower energy ions more effective. Providing lower energy ions for etching results in a reduction in bending and a reduction in other etching problems caused by high energy ions. The phosphorus dopant can also reduce the activation energy required to etch the silicon nitride. However, compared to phosphorus reducing the activation energy of silicon nitride, the phosphorus dopant reduces the activation energy of silicon oxide more. In the prior art, silicon oxide etches slower than silicon nitride, resulting in uneven etching of the ONON stack. Providing phosphorus dopant allows the ONON to etch more uniformly.

[0031] In some embodiments, the electrostatic chuck is cooled to a temperature below 0°C. In some embodiments, the chuck is cooled to a temperature below -10°C. In some embodiments, the chuck is cooled to a temperature below -20°C. In some embodiments, the chuck is cooled to a temperature between -80°C and 0°C to provide improved handling. In some embodiments, the stack is cooled to a temperature between -60°C and -20°C.

[0032] In some embodiments, the stack comprises one or more layers of at least one of silicon oxide and silicon nitride. In some embodiments, the stack is a single layer of silicon oxide or silicon nitride. In some embodiments, the silicon oxide and / or silicon nitride layer is doped. In some embodiments, the silicon oxide and / or silicon nitride layer is undoped. In some embodiments, the stack comprises alternating layers of silicon oxide and polysilicon (OPOP).

[0033] In some embodiments, when manufacturing a 3D NAND memory device, an ONON stack may be etched to form contact holes, channel holes, or trenches. Other embodiments may etch an OPOP (alternating layers of SiO2 and polysilicon) stack to form contact holes, channel holes, or trenches when manufacturing a 3D NAND memory device. Other embodiments may be used for DRAM capacitor etching. Capacitor etching may have a depth of 1.5 microns and have a dense CD, thereby providing high aspect ratio features in silicon oxide. Some embodiments provide etching features with an aspect ratio greater than 10:1. Some embodiments provide a CD less than 50nm and an etching depth greater than 20 microns, thereby providing features with a depth-to-width aspect ratio of at least 4000:1. In some embodiments, the etching depth is greater than 3 microns. Some embodiments allow etching of at least 192 or 256 silicon oxide and silicon nitride bilayers in a single etching step using a single amorphous carbon mask less than 1 micron thick.

[0034] In some embodiments, the etching gas may include at least one of Cl 2 and HBr as halogen-containing components, and PF 5 as a phosphorus-containing component.

[0035] In some embodiments, providing the etching gas and ion etching can be provided as sequential steps in a cyclic process. Providing the etching gas and ion etching simultaneously can provide a faster process than a sequential cyclic process.

[0036] Figure 33 is a schematic diagram of an etching reactor that can be used in embodiments. In one or more embodiments, the etching reactor 300 includes a gas distribution plate 306 (which provides a gas inlet) and an electrostatic chuck (ESC) 308 within an etching chamber 349 surrounded by a chamber wall 352. Within the etching chamber 349, the stack 200 is placed above the ESC 308, wherein the ESC 308 acts as a substrate support. The ESC 308 can be biased by an ESC power supply 348. An etching gas source 310 is connected to the etching chamber 349 via the gas distribution plate 306. In some embodiments, the etching gas source 310 includes a phosphorus-containing component source 312, a halogen-containing component source 316, and other gas sources 318, such as a hydrogen-containing component source and a fluorocarbon-containing component source. The ESC temperature controller 350 is connected to a cooler 314. The cooler 314 is capable of cooling the ESC 308 to a temperature of less than 0°C. In this embodiment, a cooler 314 provides coolant to channels 313 in or adjacent to the ESC 308. A radio frequency (RF) power source 330 provides RF power to the lower electrode and / or upper electrode, which in this embodiment is the ESC 308 and the gas distribution plate 306. In an exemplary embodiment, 400 kilohertz (kHz), 60 megahertz (MHz), and optionally 2 MHz and 27 MHz power sources constitute at least the primary and auxiliary power sources for the RF power source 330 and the ESC power supply. In this embodiment, the upper electrode is grounded. In this embodiment, one generator is provided for each frequency. In other embodiments, the generators may be in separate RF sources, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have inner and outer electrodes connected to different RF sources. In other embodiments, other configurations of RF sources and electrodes may be used. The RF power may be continuous or pulsed. Non-sinusoidal waveforms may be used to deliver some or all of the RF power. The controller 335 is controllably connected to the RF power supply 330, the ESC power supply 348, the exhaust pump 320, and the etching gas source 310. An example of such an etching chamber is the Exelan etch chamber manufactured by Lam Research Corporation (Fremont, CA). Dielectric etch systems, or Dielectric Etching System: The etching chamber may be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor, wherein the electrodes may be coils.

[0037] Figure 4Shown is a high-level block diagram of a computer system 400 suitable for implementing the controller 335 used in the embodiments. The computer system can have a variety of physical forms, ranging from integrated circuits, printed circuit boards, and small handheld devices to giant supercomputers. The computer system 400 includes one or more processors 402, and can further include an electronic display device 404 (for displaying graphics, text, and other data), a main memory 406 (e.g., random access memory (RAM)), a storage device 408 (e.g., a hard drive), a removable storage device 410 (e.g., an optical drive), a user interface device 412 (e.g., a keyboard, touch screen, keypad, mouse, or other positioning device, etc.), and a communication interface 414 (e.g., a wireless network interface). The communication interface 414 enables software and data to be transmitted between the computer system 400 and external devices via a link. The system can also include a communication infrastructure 416 (e.g., a communication bus, a cross-over bar, or a network) connected to the aforementioned devices / modules.

[0038] The information transmitted via the communication interface 414 can be in the form of a signal that can be received by the communication interface 414 through a communication link, such as an electronic, electromagnetic, optical, or other signal, which carries the signal and can be a communication link implemented using wire or cable, optical fiber, telephone line, cellular telephone link, radio frequency link, and / or other communication channels. Using such a communication interface, it is contemplated that one or more processors 402 can receive information from a network or can output information to a network in the course of implementing the above-described method steps. In addition, the method embodiments can be executed solely on the processor or can be executed in conjunction with a remote processor over a network such as the Internet, which shares a portion of the processing.

[0039] The term "non-transitory computer-readable medium" is generally used to refer to media such as main memory, secondary memory, removable storage, and storage devices (e.g., hard disks, flash memory, hard drive memory, CD-ROMs, and other forms of permanent memory), and should not be interpreted as encompassing transitory subject matter such as carrier waves or signals. Examples of computer-readable code include machine code, such as that produced by a compiler, and files including higher-level code that is executed by a computer using an interpreter. A computer-readable medium may also be computer code transmitted by a computer data signal embodied in a carrier wave and represented as a sequence of instructions that can be executed by a processor.

[0040] In some embodiments, liquid nitrogen is used as the coolant that flows through the ESC 308 to provide cooling. In other embodiments, liquid Vertel Sinera manufactured by DuPont Corporation (Wilmington, DE) TM Can be used as a coolant.

[0041] In some embodiments, RF power is provided using a multi-state pulse having at least three states, wherein the multi-state pulse generates a plasma from an etching gas and provides a bias. In some embodiments, the multi-state pulse has at least a primary RF signal in a first frequency range and an auxiliary RF signal in a second frequency range, wherein both the primary RF signal and the auxiliary RF signal are pulsed between at least a first state, a second state, and a third state. In some embodiments, one or more of these RF signals has a non-sinusoidal waveform.

[0042] In some embodiments, in a first state, the primary RF signal is at a first primary power level and the auxiliary RF signal is at a first auxiliary power level; in a second state, the primary RF signal is at a second primary power level and the auxiliary RF signal is at a second auxiliary power level; in a third state, the primary RF signal is at a third primary power level and the auxiliary RF signal is at a third auxiliary power level. In some embodiments, in the first state, the primary RF signal is at a first primary power level and the auxiliary RF signal is at a first auxiliary power level; in the second state, the primary RF signal is at a second primary power level and the auxiliary RF signal is at a second auxiliary power level; in the third state, no RF power is provided. In some embodiments, the first primary power level is greater than the first auxiliary power level, the second primary power level is less than the second auxiliary power level, and the absolute value of the difference between the third primary power level and the third auxiliary power level is less than the absolute value of the difference between the first primary power level and the first auxiliary power level and the absolute value of the difference between the second primary power level and the second auxiliary power level.

[0043] Figure 5 A flow chart of a process using multi-state pulses in some embodiments may be used. The stack is placed in a chamber (step 504). In some embodiments, the stack may be Figure 2A After the stack 200 has been placed in the etching chamber, the stack is cooled to a temperature below 0° (step 508). In some embodiments, the stack is cooled to a temperature below -40°.

[0044] An etching gas comprising a halogen-containing component and a phosphorus-containing component is flowed into the etching chamber (step 512). In some embodiments, the etching gas comprises a halogen-containing component, a phosphorus-containing component, a hydrogen-containing component, a hydrocarbon-containing component, and a fluorocarbon-containing component. In some embodiments, the halogen-containing component comprises a bromofluorocarbon C x Br y F z , chlorofluorocarbons C x Cl y F z , chlorinated hydrocarbons C x H y Cl z , brominated hydrocarbons C x H y Br z , fluorinated hydrocarbons C x H y F z , fluorocarbon C x F yAt least one of: chlorine (Cl), silicon tetrachloride (SiCl), boron trichloride (BCl), nitrogen trifluoride, C4F8, octafluoropropane (C3F8), hexafluoro-1,3-butadiene (C4F6), sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), chlorine (Cl2), hydrogen bromide (HBr), trifluoroiodomethane (CF3I), fluoromethane (CH3F), difluoromethane (CH2F2), hydrogen chloride (HCl), and trifluoromethane (CHF3). In some embodiments, the halogen-containing component is a metal halide. In some embodiments, the etching gas further comprises an inert gas such as argon (Ar), helium (He), krypton (Kr), neon (Ne), xenon (Xe), or nitrogen (N2). In some embodiments, the inert gas provides ions for ion bombardment to promote etching and can therefore be an inert bombardment gas. In some embodiments, the etching gas is oxygen-free and does not contain octafluorocyclobutane (C4F8) and hexafluorocyclobutene (C4F6). In some embodiments, the etching gas is oxygen-free and carbon-free. In some embodiments, the etching gas further comprises at least one of methane (CH4), hydrogen fluoride (HF), and hydrogen (H2). In some embodiments, the phosphorus-containing component is at least one of PF5, PH3, PF3, PCl3, PBr3, POF3, and PI3. In some embodiments, examples of etching gases are 0–120 sccm NF3, 0–400 sccm H2, 1–100 sccm PF5, 0–100 sccm Cl2, 0–100 sccm HBr, 0–250 sccm HF, and 0-200 sccm CH2F2. In this example, a pressure of 5 to 60 mTorr is provided. In some embodiments, the halogen-containing component may include a fluorine-, chlorine-, or bromine-containing component. In some embodiments, boron trifluoride (BF3) or boron trichloride (BCl3) may be used.

[0045] A multi-state pulse is provided (step 516). In some embodiments, the multi-state pulse for any state can have a duty cycle in the range of 1% to 99%. Figure 6A 6 is a graph 602 of a clock signal 604 that may be used to provide a multi-state pulse in some embodiments. Graph 602 plots logic levels on the y-axis and time t on the x-axis. The y-axis of graph 602 includes a logic level 0 and a logic level 1. The x-axis of graph 602 includes a plurality of times t0, t1, t2, t3, t4, and t5.

[0046] The time intervals between any two consecutive times on the x-axis of graph 602 are the same. For example, the time interval between times t0 and t1 is equal to the time interval between times t1 and t2, and the time interval between times t1 and t2 is equal to the time interval between times t2 and t3. The time interval between times t3 and t4 is equal to the time interval between times t2 and t3, and the time interval between times t4 and t5 is equal to the time interval between times t3 and t4. Time t1 immediately follows time t0. Similarly, time t2 immediately follows time t1, time t3 immediately follows time t2, time t4 immediately follows time t3, and time t5 immediately follows time t4.

[0047] Clock signal 604 periodically transitions between logic levels 0 and 1. For example, during the first half of cycle 1 of clock signal 604, clock signal 604 is at logic level 1. At time t1, clock signal 604 transitions from logic level 1 to logic level 0. During the second half of cycle 1 of clock signal 604, clock signal 604 has logic level 0. At time t2, clock signal 604 transitions from logic level 0 to logic level 1. During the first half of cycle 2 of clock signal 604, clock signal 604 is at logic level 1. At time t3, clock signal 604 transitions from logic level 1 to logic level 0. During the second half of cycle 2 of clock signal 604, clock signal 604 is at logic level 0. At time t4, clock signal 604 transitions from logic level 0 to logic level 1.

[0048] Period 2 of clock signal 604 occurs immediately after period 1 of clock signal 604. For example, there are no other clock periods between periods 1 and 2 of clock signal 604. Period 1 occurs between time t0 and time t2, and period 2 occurs between time t2 and time t4.

[0049] Figure 6B 6 is a diagram of an embodiment of a graph 606 that depicts an embodiment using a digital pulse signal 608 in some embodiments. Graph 606 plots the logic level of digital pulse signal 608 on the y-axis and time t on the x-axis. The y-axis of graph 606 includes logic levels 0, 1, and 2. The x-axis of graph 606 includes time t0, time t0a, time t0b, time t1, time t2, time t2a, time t2b, and times t3 and t4. Time t0a occurs between time t0 and t0b, and time t0b occurs between time t0a and t1. Additionally, time t2a occurs between time t2 and t2b, and time t2b occurs between time t2a and t3.

[0050] The digital pulse signal 608 periodically transitions between a first state (S1), a second state (S2), and a third state (S0). For example, from time t0 to time t0a, the digital pulse signal 608 has state S1, which is defined by a logic level 0. For illustration, during state S1 of the digital pulse signal 608, the digital pulse signal 608 is at a logic level 0. At time t0a, the digital pulse signal 608 transitions from logic level 0 to logic level 1. State S2 of the digital pulse signal 608 is defined by a logic level 1. For illustration, during state S2 of the digital pulse signal 608, the digital pulse signal 608 is at a logic level 1.

[0051] From time t0a to time t0b, digital pulse signal 608 has state S2. At time t0b, digital pulse signal 608 transitions from state S2 to state S0, which is defined by a logic level 2. For illustration, during state S0 of digital pulse signal 608, digital pulse signal 608 is at a logic level 2. From time t0b to time t2, digital pulse signal 608 has state S0. At time t2, digital pulse signal 608 transitions from state S0 back to state S1.

[0052] From time t2 to time t2a, digital pulse signal 608 is in state S1. At time t2a, digital pulse signal 608 transitions from state S1 to state S2. From time t2a to time t2b, digital pulse signal 608 is in state S2. At time t2b, digital pulse signal 608 transitions from state S2 to state S0. From time t2b to time t4, digital pulse signal 608 is in state S0. At time t4, digital pulse signal 608 transitions from state S0 back to state S1.

[0053] It should be noted that multiple instances of each of the states S1, S2, and S0 of the digital pulse signal 608 occur. For example, a first instance of the state S1 of the digital pulse signal 608 occurs between times t0 and t0a, and a second instance of the state S1 of the digital pulse signal 608 occurs between times t2 and t2a. As another example, a first instance of the state S2 of the digital pulse signal 608 occurs between times t0a and t0b, and a second instance of the state S2 of the digital pulse signal 608 occurs between times t2a and t2b. As yet another example, a first instance of the state S0 of the digital pulse signal 608 occurs between times t0b and t2, and a second instance of the state S0 of the digital pulse signal 608 occurs between times t2a and t4. As another example, the first instance of the state S2 of the digital pulse signal 608 immediately follows the first instance of the state S1 of the digital pulse signal 608, and the first instance of the state S0 of the digital pulse signal 608 immediately follows the first instance of the state S2 of the digital pulse signal 608. The second instance of state S1 of the digital pulse signal 608 immediately follows the first instance of state S0 of the digital pulse signal 608. Furthermore, the second instance of state S2 of the digital pulse signal 608 immediately follows the second instance of state S1 of the digital pulse signal 608, and the second instance of state S0 of the digital pulse signal 608 immediately follows the second instance of state S2 of the digital pulse signal 608.

[0054] Figure 6C 6 is an embodiment of a graph 610 of a primary RF signal 612 and an auxiliary RF signal 614 used in some embodiments. The primary RF signal 612 and the auxiliary RF signal 614 are synchronized with the digital pulse signal 608. For example, at time t0a when the digital pulse signal 608 transitions from state S1 to state S2, each of the primary RF signal 612 and the auxiliary RF signal 614 begins to transition from state S1 to state S2. As another example, at time t0b when the digital pulse signal 608 transitions from state S2 to state S0, each of the primary RF signal 612 and the auxiliary RF signal 614 begins to transition from state S2 to state S0. As yet another example, at time t2 when the digital pulse signal 608 transitions from state S0 to state S1, each of the primary RF signal 612 and the auxiliary RF signal 614 begins to transition from state S0 to state S1.

[0055] Graph 610 plots the power levels of a primary RF signal 612 and an auxiliary RF signal 614. For example, the y-axis of graph 610 includes power levels P0, P1, P2, P3, and P4. Power level P1 is greater than power level P0. Furthermore, power level P2 is greater than power level P1, and power level P3 is greater than power level P2. Power level P4 is greater than power level P3. In addition, graph 610 plots time t on the x-axis. For example, the x-axis of graph 610 includes times t0, t0a, t0b, t1, t2, t2a, t2b, t3, and t4.

[0056] As used herein, a power level is the envelope of an RF signal, such as the peak-to-peak amplitude. For example, the power level includes one or more peak-to-peak power values ​​within a predetermined range of power levels, such as peak-to-peak power values ​​greater than or less than the value of the power level. As another example, the power level is a statistical value, such as the mean or median, of all peak-to-peak power values ​​of the power level. As another example, the power level is the highest of all peak-to-peak power values ​​of the power level. As yet another example, the power level is the lowest of all peak-to-peak power values ​​of the power level.

[0057] In an example used in some embodiments, a first state (S1) is from t0 to t0a, wherein the primary RF signal 612 is provided at a first primary power level P4 and the auxiliary RF signal 614 is provided at a first auxiliary power level P1, where P4 is greater than P1, as shown. A second state (S2) is from t0a to t0b, wherein the primary RF signal 612 is provided at a second primary power level P2 and the auxiliary RF signal 614 is provided at a second auxiliary power level P3, where P3 is greater than P2, as shown. A third state (S0) is from t0b to t2, wherein the primary RF signal 612 is provided at a third primary power level of 0 and the auxiliary RF signal 614 is provided at a third auxiliary power level of 0, as shown. In this example, during S0, the power level of the primary RF signal 612 is equal to the power level of the auxiliary RF signal 614, which is 0. More generally, in some embodiments, the third primary power level is approximately equal to the third auxiliary power level. More generally, in some embodiments, the absolute value of the difference between the third primary power level and the third auxiliary power level is smaller than the absolute value of the difference between the first primary power and the first auxiliary power and the absolute value of the difference between the second primary power and the second auxiliary power.

[0058] It should be noted that, in some embodiments, the RF signals described herein do not transition instantaneously from one state to its adjacent state. For example, the transition of the primary RF signal 612 from state S1 to state S2 is not instantaneous. For illustration, the transition of the primary RF signal 612 from state S1 to state S2 occurs within a time window. As another example, as used herein, a time window for transitioning from a time is a time period occurring during the states after that time. For illustration, the time window starting at time t0a is a time period occurring after time t0a during state S2 of the digital pulse signal 608. This time period after time t0a occurs during state S2 of the digital pulse signal 608 from time t0a to a time between times t0a and t0b.

[0059] The state S1 of the primary RF signal 612 between times t0 and t0a is a first instance of the state S1 of the primary RF signal 612, and the state S1 of the primary RF signal 612 between times t2 and t2a is a second instance of the state S1 of the primary RF signal 612. Similarly, the state S2 of the primary RF signal 612 between times t0a and t0b is a first instance of the state S2 of the primary RF signal 612, and the state S2 of the primary RF signal 612 between times t2a and t2b is a second instance of the state S2 of the primary RF signal 612. Furthermore, the state S0 of the primary RF signal 612 between times t0b and t2 is a first instance of the state S0 of the primary RF signal 612, and the state S0 of the primary RF signal 612 between times t2b and t4 is a second instance of the state S0 of the primary RF signal 612.

[0060] Similarly, the state S1 of the primary RF signal 612 between times t0 and t0a is a first instance of the state S1 of the primary RF signal 612, and the state S1 of the primary RF signal 612 between times t2 and t2a is a second instance of the state S1 of the primary RF signal 612. Similarly, the state S2 of the primary RF signal 612 between times t0a and t0b is a first instance of the state S2 of the primary RF signal 612, and the state S2 of the primary RF signal 612 between times t2a and t2b is a second instance of the state S2 of the primary RF signal 612. Furthermore, the state S0 of the primary RF signal 612 between times t0b and t2 is a first instance of the state S0 of the primary RF signal 612, and the state S0 of the primary RF signal 612 between times t2b and t4 is a second instance of the state S0 of the primary RF signal 612.

[0061] In some embodiments, providing higher power to the main RF signal 612 during state S1 allows for increased bias, thereby providing higher aspect ratio etching. However, higher bias power can cause negative effects such as increased bowing, reduced selectivity, clogging or necking, and faceting. To reduce or remove some of the negative effects of increasing bias power, state S2 is provided, in which the bias power provided by the main RF signal 612 is reduced and the plasma source power provided by the auxiliary RF signal 614 is increased. In some embodiments, the power level of the auxiliary RF signal 614 is increased to a level greater than the power level of the main RF signal 612. To remove some of the negative effects not removed by state S2, a third state S0 is provided. Thus, using multi-state RF power having at least three states to provide etching of a stack having a silicon oxide layer beneath a mask (where the etching gas has a halogen-containing component and a phosphorus-containing component) provides improved etching that is more selective and reduces negative effects. In some embodiments, the etching gas does not contain a metal-containing component.

[0062] In some embodiments, in state S1, where the main power level is higher than the auxiliary power level, a higher bias power is provided to provide faster high aspect ratio etching. In some embodiments, the higher bias etching removes some mask and may cause some sputtering, which may redeposit on the sides of the feature, causing some necking, which may cause some blockage. In some embodiments, state S2, which has a higher auxiliary power level and a lower main power level, allows for an increase in plasma density with a lower bias, thereby allowing for the removal of any necking and blockage that is formed. In some embodiments, four or more states are used, where two states S1 and S2 are at significantly higher main and auxiliary powers than state S3 and include a state S0 with zero power. In some embodiments, during state S0, the power level of the main RF signal 612 is approximately equal to the power level of the auxiliary RF signal 614. In some embodiments, during state S0, the power level of the main RF signal 612 and the power level of the auxiliary RF signal 614 are each less than 300 watts. In some embodiments, during state S0, the power level of the main RF signal 612 and the power level of the auxiliary RF signal 614 are zero watts. In some embodiments, the lower power levels of the main RF signal 612 and the auxiliary RF signal 614 cause neutral deposits to be deposited on the mask, thereby allowing etching selectivity to be increased by adding these neutral deposits to the mask. In some embodiments, the duty cycle of the third state S0 is greater than the duty cycle of the first state S1 and the duty cycle of the second state S2, so as to provide a longer time for deposition on the mask, thereby increasing selectivity. In some embodiments, the duty cycle of the third state S0 is in the range of 25% to 94%. In some embodiments, state S0 may precede state S1. In some embodiments, state S0 may be between state S1 and state S2. In some embodiments, state S2 may precede state S1.

[0063] In some embodiments, a fourth state (S3) is used in a multi-state pulse. State S3 may precede or follow state S1, state S2, or state S0. Some embodiments have more than four states. In some embodiments, one or more states have zero RF power.

[0064] In some embodiments, the first state (S1) has a high RF power, the second state (S2) has a medium RF power, and the third state (S0) has a low RF power that is lower than the medium RF power. In some embodiments, the high RF power of the first state (S1) has a first main power and a first auxiliary power, the RF power in the second state (S2) has a second main power and a second auxiliary power, and the low RF power of the third state (S0) has a third main power and a third auxiliary power. In some embodiments, the first main power is greater than the second main power, the second main power is greater than the third main power, the first auxiliary power is greater than the second auxiliary power, and the second auxiliary power is greater than the third auxiliary power. In some embodiments, the low RF power is 0 watts, so that the third main power and the third auxiliary power are 0 watts.

[0065] In some embodiments, during the etching process, as the etched features are etched deeper, such that the aspect ratio of height to width increases, the parameters of states S1, S2, and S0 may be changed. For example, in some embodiments, the bias during S1 may be increased over time. In some embodiments, the duty cycle of state S0 may be increased over time. In some embodiments, the duty cycle of S2 may be increased over time.

[0066] Figure 77 is a schematic diagram of an etching reactor that can be used in some embodiments. In some embodiments, the etching reactor 700 includes a gas distribution plate 706 (which provides a gas inlet) and an electrostatic chuck (ESC) 708 within an etching chamber 749 surrounded by a chamber wall 752. Within the etching chamber 749, the stack 200 is placed above the ESC 708, wherein the ESC 708 acts as a substrate support. An etching gas source 710 is connected to the etching chamber 749 via the gas distribution plate 706. In some embodiments, the etching gas source 710 includes a phosphorus-containing component source 712, a halogen-containing component source 716, and other gas sources 718, such as a hydrogen-containing component source and a fluorocarbon-containing component source. The ESC temperature controller 750 is connected to a cooler 714. The cooler 714 is capable of cooling the ESC 708 to a temperature of less than 0°C. In this embodiment, the cooler 714 provides coolant to a channel 713 in or adjacent to the ESC 708. A main radio frequency (RF) power supply 780 provides a main RF signal to the lower electrode, which in this embodiment is the ESC 708. An auxiliary RF power supply 784 provides an auxiliary RF signal to the ESC 708. The gas distribution plate 706 forms a grounded upper electrode. In some embodiments, at least one of a 400 kilohertz (kHz) power supply and a 2 MHz power supply may constitute the main RF power supply 780. In some embodiments, at least one of a 60 MHz power supply and a 27 MHz power supply constitutes the auxiliary RF power supply 784. In other embodiments, other configurations of RF sources and electrodes may be used. The controller 735 is controllably connected to the main RF power supply 780 that provides the main signal, the auxiliary RF power supply 784 that provides the auxiliary signal, the ESC power supply 748, the exhaust pump 720, and the etch gas source 710. An example of such an etch chamber is the Exelan etch chamber manufactured by Lam Research Corporation (Fremont, CA). Dielectric Etch Systems and Dielectric Etching System: The etching chamber may be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor, wherein the electrodes may be coils.

[0067] In some embodiments, the controller 735 is configured to cool the substrate support to a temperature not exceeding 0° C., provide an etching gas comprising a halogen-containing component from a halogen-containing component source and a phosphorus-containing component from a phosphorus-containing component source, generate a plasma from the etching gas, and provide a bias to accelerate ions from the plasma to the stack.

[0068] Although the present disclosure has been described in terms of several preferred embodiments, there are changes, modifications, permutations, and various alternative equivalents that fall within the scope of the present invention. It should also be noted that there are many alternative ways to implement the method and apparatus of the present invention. Therefore, the following claims are intended to be interpreted as including all such changes, modifications, permutations, and various alternative equivalents that fall within the true spirit and scope of the present invention. As used herein, the phrase "A, B, or C" should be interpreted as meaning a logic using a non-exclusive logical "OR" ("A or B or C"), and should not be interpreted as meaning "only" one of A or B or C. The various steps in the process may be selective and non-essential steps. Different embodiments may have one or more steps removed or the steps may be in different orders. In addition, various embodiments may provide different steps simultaneously rather than sequentially.

Claims

1. A method for etching a feature in a stack, the stack comprising a silicon oxide layer beneath a mask, the method comprising: cooling a substrate support for supporting the stack in an etching chamber to a temperature below 0° C.; providing an etching gas, wherein the etching gas comprises a halogen-containing component and a phosphorus-containing component; generating a plasma from the etching gas; providing a bias to accelerate ions from the plasma to the stack; as well as Features are selectively etched in the stack relative to the mask. The method of claim 1 , wherein the etching gas further comprises a hydrogen-containing component. The method of claim 1 , wherein the mask is a carbon-containing mask. The method of claim 3 , wherein the carbon-containing mask is amorphous carbon. The method according to claim 1 , wherein the etching gas is free of oxygen and free of C 4 F 8 and C 4 F 6 .

6. The method of claim 1 , wherein the halogen-containing component comprises at least one of chlorinated chlorinated hydrocarbons, bromofluorocarbons, chlorofluorocarbons, SiCl 4 , BCl 3 , NF 3 , C 4 F 8 , C 3 F 8 , C 4 F 6 , SF 6 , CF 4 , Cl 2 , HBr , CF 3 I , CH 3 F , CH 2 F 2 , CHF 3 and HCl. 7 . The method according to claim 1 , wherein the etching gas further comprises at least one of HF, H 2 , O 2 and CH 4 .

8. The method of claim 1 , wherein cooling a substrate support for supporting the stack in an etching chamber to a temperature below 0° C. further comprises: The substrate support is cooled to a temperature below -10°C.

9. The method of claim 1, wherein the mask is a carbon-containing mask and the stack comprises a plurality of alternating silicon oxide layers or silicon nitride layers.

10. The method according to claim 1, further comprising: RF power is provided, the RF power having a peak power in the range of 3 kW to 150 kW.

11. The method of claim 1, wherein the phosphorus-containing component comprises at least one of PF5, PH3, PF3, PCl3, PBr3, POF3, and PI3.

12. The method of claim 1, wherein the phosphorus-containing component comprises at least one of PH3 and PF3.

13. The method according to claim 1, wherein the etching gas further comprises an inert gas, the inert gas comprising at least one of He, Ne, Ar, Kr, Xe, and N2.

14. The method of claim 1, wherein the mask is a carbon-containing mask, and wherein the stack comprises a plurality of alternating silicon oxide layers and polysilicon layers.

15. The method of claim 1 wherein the features have an aspect ratio greater than 10:

1.

16. The method of claim 1, wherein the phosphorus-containing component comprises PF5.

17. The method of claim 1, wherein the phosphorus-containing component comprises at least one of PF3 and PF5, the method further comprising providing RF power, wherein the RF power is continuous.

18. The method of claim 1, wherein said providing said bias provides a bias greater than 200 volts.

19. The method of claim 1, wherein the biasing is provided by a pulsed bias of at least two states.

20. The method of claim 1, wherein the bias is provided by an RF power source.

21. An apparatus for processing a stack on a substrate, the stack having at least one silicon oxide layer, the apparatus comprising: Etching room; a substrate support for supporting a substrate in the etching chamber; a temperature controller for controlling the temperature of the substrate support; a gas source that provides an etching gas, The gas source comprises: Sources of halogen-containing ingredients; and Sources of phosphorus-containing components; an electrode for providing power to the etching gas; and A power supply is used to provide power to the electrodes.

22. The apparatus according to claim 21, further comprising: a controller controllably connected to the gas source, the power source, and the temperature controller, the controller configured to: cooling the substrate support to a temperature not exceeding 0° C.; providing the etching gas, the etching gas comprising a halogen-containing component from the halogen-containing component source and a phosphorus-containing component from the phosphorus-containing component source; generating a plasma from the etching gas; and A bias is provided to accelerate ions from the plasma to the stack.

23. The apparatus of claim 22, wherein the gas source further comprises a source of a hydrogen-containing component.

24. The apparatus of claim 23, wherein the controller is further configured to provide the hydrogen-containing component from the hydrogen-containing component source.

25. The apparatus of claim 22, wherein the power source comprises: a primary power supply providing a primary signal in a first frequency range; as well as an auxiliary power supply providing an auxiliary signal in a second frequency range, wherein the controller is further configured to: providing the primary signal in pulsed form in at least three states including a first state, a second state, and a third state; and The auxiliary signal in the first state, the second state, and the third state is provided in a pulsed manner.

26. The device according to claim 25, wherein during the first state, the primary signal has a first primary power level and the secondary signal has a first secondary power level; wherein during the second state, the primary signal has a second primary power level and the secondary signal has a second secondary power level; and During the third state, the main signal has a third main power level and the auxiliary signal has a third auxiliary power level, wherein the first main power level is greater than the second main power level, the second main power level is greater than the third main power level, the first auxiliary power level is greater than the second auxiliary power level, and the second auxiliary power level is greater than the third auxiliary power level.

27. The apparatus of claim 25, wherein the primary signal is a primary RF signal and the auxiliary signal is an auxiliary RF signal.

28. The apparatus of claim 25, wherein the primary signal is a primary pulsed bias signal and the auxiliary signal is an auxiliary pulsed bias signal.

29. The apparatus of claim 21, wherein the power source is an RF power source.

30. The apparatus of claim 21, wherein the power source is a pulsed bias source.

31. A method for etching a feature in a stack, the stack comprising a silicon oxide layer beneath a mask, the method comprising: cooling a substrate support for supporting the stack in an etching chamber to a temperature below 0° C.; providing an etching gas, wherein the etching gas comprises a halogen-containing component and a phosphorus-containing component; providing a multi-state power having at least three states, wherein the multi-state power generates a plasma from the etching gas and provides a bias to accelerate ions from the plasma to the stack; and Features are selectively etched in the stack relative to the mask.

32. The method of claim 31 , wherein providing the multi-state power comprises: generating a primary signal, wherein the primary signal is pulsed in at least three states including a first state, a second state, and a third state; as well as An auxiliary signal is generated, wherein the auxiliary signal is provided in a pulsed manner in the first state, the second state, and the third state.

33. The method according to claim 32, wherein during the first state, the primary signal has a first primary power level and the secondary signal has a first secondary power level; wherein during the second state, the primary signal has a second primary power level and the secondary signal has a second secondary power level; and During the third state, the main signal has a third main power level and the auxiliary signal has a third auxiliary power level, wherein the first main power level is greater than the second main power level, the second main power level is greater than the third main power level, the first auxiliary power level is greater than the second auxiliary power level, and the second auxiliary power level is greater than the third auxiliary power level.

34. The method of claim 33, wherein the third primary power level and the third auxiliary power level are equal to 0 Watts.

35. The method of claim 33, wherein a duty cycle of the third state is greater than a duty cycle of the first state and a duty cycle of the second state.

36. The method of claim 32, wherein the etching gas further comprises a hydrogen-containing component.

37. The method of claim 32, wherein the mask is a carbon-containing mask.

38. The method of claim 32, wherein the etching gas is oxygen-free and free of C4F8 and C4F6.

39. The method of claim 32, wherein the etching gas further comprises at least one of HF, H2, O2, and CH4.

40. The method of claim 32, wherein cooling a substrate support for supporting the stack in an etching chamber to a temperature below 0°C further comprises: The substrate support is cooled to a temperature below -10°C.

41. The method of claim 32, wherein the mask is a carbon-containing mask and the stack comprises a plurality of alternating silicon oxide layers or silicon nitride layers.

42. The method of claim 32, wherein the phosphorus-containing component comprises at least one of PF5, PH3, PF3, PCl3, PBr3, POF3, and PI3.

43. The method according to claim 32, wherein the etching gas further comprises an inert gas, the inert gas comprising at least one of He, Ne, Ar, Kr, Xe, and N2.

44. The method of claim 32, wherein the mask is a carbon-containing mask, and wherein the stack comprises a plurality of alternating silicon oxide layers and polysilicon layers.

45. The method of claim 31 , wherein the multi-state power provides RF power.

46. ​​The method of claim 31 , wherein the multi-state power provides a bias power.

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