Voltage regulator for switching control

Abstract

In described examples, an R2R digital-to-analog converter includes a plurality of arms and a voltage regulator (110). The respective arm includes an arm switch (130) having a p-channel MOSFET (PFET) switch (132) and an n-channel MOSFET (NFET) switch (134). The voltage regulator (110) includes a differential amplifier (314), a p-ladder (308) including N cascade coupled PFETs (306) and having a first end and a second end, an n-ladder (318) including gamma * N cascade coupled NFETs (316) and having a first end and a second end, a first resistor (resistance R) (310) and a second resistor (resistance gamma * R) (312). The first p-ladder end is coupled to a first terminal of the first resistor (310). The second terminal of the first resistor (310) is coupled to an input of the differential amplifier (314) and a first terminal of the second resistor (312). A second terminal of the second resistor (312) is coupled to the first n-ladder end. An output of the differential amplifier (314) is coupled to the second n-ladder end and provides a gate voltage of the NFET switch (134).

Description

Technical Field

[0001] The present application relates generally to voltage regulation, and more particularly to regulating the voltage of a switch control terminal. Background Art

[0002] A digital-to-analog converter ("DAC") is a device that receives a digital input value or code and provides an analog output voltage that is proportional to or representative of the value of the digital input. The digital input value may conform to, for example, standard binary representation. There are various DAC architectures currently used in available devices. The choice of a particular architecture may depend on the application and performance and design metrics such as power consumption, speed, surge amplitude and energy, and the area required to implement the device. An R2R or R-2R resistor ladder is an example structure used to implement a high-bit precision DAC. Summary of the Invention

[0003] In the described example, an R2R digital-to-analog converter includes multiple arms and a voltage regulator. Each arm includes an arm switch having a p-channel MOSFET (PFET) switch and an n-channel MOSFET (NFET) switch. The voltage regulator includes a differential amplifier, a p-ladder including N cascade-connected PFETs and having a first end and a second end, an n-ladder including y×N cascade-coupled NFETs and having a first end and a second end, a first resistor (resistance R), and a second resistor (resistance y×R). The first p-ladder end is coupled to a first terminal of the first resistor. The second terminal of the first resistor is coupled to an input of the differential amplifier and a first terminal of the second resistor. The second terminal of the second resistor is coupled to the first n-ladder end. The output of the differential amplifier is coupled to the second n-ladder end and provides a gate voltage for the NFET switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is the functional block diagram and circuit diagram of an example R2R DAC.

[0005] Figure 2 Figure 2 is a functional block diagram and circuit diagram of an example model of an R2R DAC.

[0006] Figure 3 is a functional block diagram and circuit diagram of an example arm switch drive circuit including an example voltage regulator for the gate voltages of the NMOS switches of the thermometer arm and binary arm of an R2R DAC.

[0007] Figure 4 is a circuit diagram of another example R2R DAC.

[0008] Figure 5A yes Figure 1Example plot of DNL error versus code of an R2R DAC.

[0009] Figure 5B yes Figure 4 Example plot of DNL versus code for an R2R DAC.

[0010] Figure 6 is an example process for determining where to place offset resistors to enable scaling of arm switches relative to the least significant bit binary arm of an R2R resistor ladder.

[0011] Figure 7 is a functional block diagram and circuit diagram of an alternative example arm switch drive circuit including an example voltage regulator for the gate voltages of the NMOS switches of the thermometer arm and binary arm of an R2R DAC. DETAILED DESCRIPTION

[0012] In some examples, the difference between the intended DAC output for a code and the actual DAC output for that code is categorized as differential nonlinearity (DNL) or integral nonlinearity (INL). An ideal output voltage step should correspond to a change in the least significant bit of the code. DNL error is the difference between the amplitude of the ideal output voltage step between consecutive codes and the amplitude of the measured voltage step between consecutive codes. INL error is the difference between the ideal output voltage for a particular code and the measured output voltage for that code.

[0013] In an R2R resistor ladder, the on-resistance (R) between the high-side switch and the low-side switch connecting the ladder arms to the high and low voltage rails or terminals (respectively) is ON ) can cause nonlinearity. In some instances, the on-state voltage at the switch control terminal is adjusted to adjust the on-resistance of the switch. Metal oxide semiconductor field effect transistors (MOSFETs) can be used to implement such switches. Using a high-side p-channel MOSFET (PFET) and a low-side n-channel MOSFET (NFET) for the switch used to pass the high-side and low-side voltage references to the ladder arms helps match R ON The values ​​are adjusted to reduce nonlinearity. Larger high-side and low-side switch sizes make it easier to match the on-resistance of the high-side and low-side switches. Voltage regulators that regulate the gate voltages of the PFET and NFET switches can also be used to better match the on-resistance of the high-side and low-side switches, thereby enabling the use of smaller high-side and low-side switches.

[0014] In some examples, an R2R resistor ladder includes a temperature-sensing arm (also known as a thermometer arm) and a binary arm. Activating successive thermometer arms contributes equal voltages to the DAC output. The binary arms are referred to as having a most significant bit (MSB) arm and a least significant bit (LSB) arm. Activating successive binary arms (consecutively lower weight arms) from the MSB arm to the LSB arm contributes a voltage, then half that voltage, then a quarter that voltage, and so on.

[0015] Therefore, in the switches connecting consecutive binary arms to their respective voltage references, R ON By reducing the switch size by half in successive binary arms, R ON In some examples, in high-resolution DACs (DACs with a relatively large number of bits (e.g., 18 bits) of resolution), the minimum switch size allowed by the manufacturing process is reached before the lowest-weight arm. In some examples, an offset resistor added to the series resistance of the R2R ladder can be used to reduce the maximum magnitude of DNL caused by not scaling one or more LSB arms.

[0016] Figure 1 1 is a functional block diagram and circuit diagram of an example R2R DAC 100. The R2R DAC 100 is an N-bit precision DAC. The R2R DAC 100 includes a voltage source 102, an R2R resistor ladder 104, and a control circuit 106. The control circuit 106 includes a switch control 108, a voltage regulator 110, and a gate driver 112. The voltage source 102 includes a relatively high voltage reference V REFP The first output is provided to the high voltage rail or terminal 116 of the R2R resistor ladder 104 and the relatively low voltage reference V REFM The second output is provided to a low voltage rail or terminal 118 of the R2R resistor ladder 104.

[0026] In some examples, some or all components of the resistor ladder 104 and / or the control circuit 106 are included within a single integrated circuit (IC).

[0017] In some examples, voltage source 102 uses an off-chip reference generator to generate V REFP (e.g., a bandgap reference). A reference buffer is used to buffer the resulting voltage inside the chip before the voltage source 102 provides it to the high voltage rail 116. Alternatively, the voltage source 102 uses an on-chip reference generator to generate V REFP , buffering the resulting voltage using a reference buffer, and providing the buffered voltage to the high voltage rail 116. In some examples, the voltage source 102 generates V using a ground buffer internal to the chip. REFM, and provides the resulting voltage to the low voltage rail 118. The input of the ground buffer is connected to the REFGND pin. The REFGND pin is connected to the REFGRND plane on the printed circuit board (PCB). Alternatively, the low voltage rail 118 is directly connected to the REFGND pin. In some examples, the high voltage rail 116 voltage is five volts and the low voltage rail 118 voltage is zero volts.

[0018] The R2R DAC 100 has a total of N bits of accuracy and has two types of structures called arms. The first set of (thermometer) arms roughly resolves the more significant bits of the N bits, and the second set of (binary) arms refines the less significant bits of the N bits. Relatedly, these arms have inputs that receive signals from the control circuit 106. The R2R resistor ladder 104 has an output voltage terminal 114 that has a voltage V OUT The R2R resistor ladder 104 contains 2 T - 1 thermometer arm 120 and B binary arms 122, where T and B are integers and T+B=N. Overall, the R2R resistor ladder 104 includes 2 T -1+B arms. Thus, the R2R resistor ladder 104 has a number of arms, M, equal to the number of thermometer arms 120 plus the number of binary arms 122, as follows: M=2 T -1+B.

[0019] Activating the thermometer arm 120 or the binary arm 122 means coupling the output voltage terminal 114 to the high voltage rail 116 via the activated thermometer arm 120 or the binary arm 122. Deactivating the thermometer arm 120 or the binary arm 122 means coupling the output voltage terminal 114 to the low voltage rail 118 via the deactivated thermometer arm 120 or the binary arm 122. The R2R resistor ladder 104 further includes a terminating resistor 128 having a resistance of 2R, and M arm switches 130 that selectively connect the thermometer arm 120 and the binary arm 122 to the high voltage rail 116 or the low voltage rail 118.

[0020] The control circuit 106 includes a code input for receiving a code (e.g., a digital code). The control circuit 106 also includes a first set of M inputs coupled to the R2R resistor ladder 104 to control a first set of M outputs of the low-side switches of all arms of the R2R resistor ladder 104. The control circuit 106 further includes a second set of M inputs coupled to the R2R resistor ladder 104 to control a second set of M outputs of the high-side switches of all arms of the R2R resistor ladder 104. In some examples, the first set of outputs and the second set of outputs of the control circuit 106 are respective buses, each having a width of M control lines.

[0021] The code is the DAC 100 control input signal and is used to determine the R2R resistor ladder 104 control signal. The R2R resistor ladder 104 control signal is used to activate and deactivate the thermometer arm 120 and the binary arm 122. Therefore, in response to the code, the switch control 108 determines whether the combination of the thermometer arm 120 and the binary arm 122 is coupled to the high voltage rail 116 or the low voltage rail 118, and in response, the R2R resistor ladder 104 is switched on and off at V OUT A voltage representing the code is provided at 114. The switch control 108 provides a control signal to the gate driver 112 to drive the PFET switch 132 or the NFET switch 134 to couple the temperature measuring arm 120 and the binary arm 122 to the high voltage rail 116 or the low voltage rail 118, respectively. The voltage regulator 110 is used to set the voltage used by the gate driver 112 to drive the NFET switch 134. In some examples, the switch control 108, the voltage regulator 110, or the gate driver 112 are implemented as digital circuits, analog circuits, or mixed digital / analog circuits.

[0022] For purposes of explanation, it is assumed that the DAC 100 output voltage response to the input code is ideal. In some instances, in response to non-ideal behavior of the DAC 100, the thermometer arm 120 and binary arm 122 that are enabled or disabled by the R2R resistor ladder 104 control signal are different from the thermometer arm 120 and binary arm 122 that correspond to the code. Ideally, for an N-bit code corresponding to an N-bit resolution DAC 100, the T most significant bits correspond to the thermometer arm 120 and the B least significant bits correspond to the binary arm 122. Individual thermometer arms 120 correspond to code values ​​2 B , and the jth binary arm 122 corresponds to the code value 2 B-j , wherein the first binary arm 122 is the MSB binary arm 122 , and the Bth binary arm 122 is the LSB binary arm 122 .

[0023] The thermometer arm 120 includes an arm resistor 124 having a resistance 2R. Individual ones of the arm resistors 124 of the thermometer arm 120 are designated by a subscript (from 1 to 2) depending on the ordinal position of the respective thermometer arm 120 within the set of thermometer arms 120. T Thus, the arm resistors 124 of the thermometer arm 120 are numbered in the order in which the thermometer arm 120 is activated as the code increases. For example, the first arm resistor is 1241, the second is 1242, and the second is 1243. T -1) (last arm resistor 124 of thermometer arm 120) is 124 2^T-1 A first terminal of an arm resistor 124 of the thermometer arm 120 is connected to the output voltage terminal 114 .

[0024] The binary arm 122 includes an arm resistor 124 having a resistance of 2R and a connector resistor 126 having a resistance of R. To reiterate, M=2 T -1+B. Individual of the arm resistors 124 of the binary arms 122 are indices (from 2 T The individual connector resistors 126 of the binary arms 122 are numbered in subscript (from 1 to B) from the MSB binary arm 122 to the LSB binary arm 122. For example, the most significant bit (first) arm resistor 124 2^T and connector resistor 1261, next most significant bit (second) arm resistor 124 2^T+1 and connector resistor 1262, and least significant bit (B) arm resistor 124 M and connector resistor 126 B .

[0025] The connector resistors 126 of the binary arm 122 are connected in series between the voltage output terminal 114 and the first terminal of the terminating resistor 128. More specifically, the first terminal of the first connector resistor 1261 is connected to the voltage output terminal 114. The second terminal of the first connector resistor 1261 is connected to the first terminal of the second connector resistor 1262, and so on. Finally, the Bth connector resistor 126 B A second terminal of terminating resistor 128 is connected to a first terminal of terminating resistor 128 . A second terminal of terminating resistor 128 is connected to low voltage rail 118 .

[0026] The arm switch 130 includes a PFET switch 132 (high-side switch) and an NFET switch 134 (low-side switch). The arm switch 130 and the corresponding PFET switch 132 and NFET switch 134 are numbered with the same subscript as the subscript of the corresponding connection arm resistor 124. The j-th arm resistor 124 of the thermometer arm 122 j (1≤j≤2 T -1) is connected to the output voltage terminal 114. The j-th arm resistor 124 of the thermometer arm 122 j The second terminal of the j-th PFET switch 132 is connected to j The source of the jth NFET switch 134j and the drain of the jth NFET switch 134j. 2^T-1+j The first terminal of (1≤j≤B-1) is connected to the jth connector resistor 126 j and the j+1th connector resistor 126 j+1 The B-arm resistor 124 of the binary arm 122 B The first terminal is connected to the B connector resistor 126 BBetween the j-th arm resistor 124 of the binary arm 122 and the terminating resistor 128. 2^T-1+j The second terminal is connected to the (2 T -1+j) PFET switch 132 2^T-1+j The source and (2 T -1+j)NFET switch 134 2^T-1+j of the drain.

[0027] jth PFET switch 132 j The drain of (1≤j≤M) is connected to the high voltage rail 116, and the jth NFET switch 134 j The source of the jth PFET switch 132 is connected to the low voltage rail 118. j The gate of the jth NFET switch 134 is connected to a corresponding one of the M high-side control lines 134. j The drain of is connected to a corresponding one of the M low-side control lines 136 .

[0028] The thermometer arm 120 or the binary arm 122 may be coupled to V by turning on its corresponding PFET switch 132 and turning off its corresponding NFET switch 134. REFP The thermometer arm 120 or the binary arm 122 may be coupled to V by opening its corresponding PFET switch 132 and closing its corresponding NFET switch 134. REFM The thermometer arm 120 is selectively activated or deactivated in response to code to provide an analog output voltage V OUT The selective activation or deactivation of the binary arm 122 in response to the code provides the analog output voltage V OUT The start of h thermometer arms 120 to V OUT Contribution voltage, as given by Equation 1:

[0029] Thermometer Arm

[0030] The activation of at most B pairs of V in the j-th binary arm 122 specified by the code OUT Contribution voltage, as given by Equation 2:

[0031] Binary Arm

[0032] Activation and deactivation of the thermometer arm 120 and the binary arm 122 are controlled by the switch control 108 in response to codes received by the control circuit 106 .

[0033] Figure 2 yes Figure 1Functional block diagram and circuit diagram of an example resistance and voltage model 200 of the thermometer arm 120 and the binary arm 122 of the R2R DAC 100 at an intermediate code. The same reference numerals or other reference designators are used in the drawings to indicate the same or similar features (structurally and / or functionally).

[0034] Model 200 is used to describe the R ON and the R of the NFET switch 134 ON How can the difference between the R2R DAC 100 V OUT The middle code or "mid-code" is halfway between the first value of the code (zero code) and the last value of the code (full code). In some examples, the first value of the code is zero or 000...000 (N zeros), and the last value of the code is 2 N -1 or 111...111 (N ones), and the middle code is 2 N-1 -1 or 011...111 (zero followed by N-1 ones). At the intermediate code, the number in the thermometer arm 120 is rounded down by half (2 T-1 -1) is activated and the rounded-up half (2 T-1 ) are disabled. Also, all binary arms 122 are enabled, providing a voltage equal to one more active thermometer arm 120 (minus one LSB, which is negligible for the high precision R2R DAC 100 for the purposes of this model).

[0035] Model 200 includes the equivalent on-resistance (R) of the PFET switch 132 that is turned on to activate the thermometer arm 120 and the binary arm 122. ON )R SWITCH-P 202 (connected to V REFP ), the equivalent resistance R of the activated thermometer arm 120 and the binary arm 122 ARM-ON 204, the equivalent R of the NFET switch 134 that is turned on to disable the disabled thermometer arm 120 ON R SWITCH-M 206 (connected to V REFM ), and the equivalent resistance R of the deactivated thermometer arm 120 ARM-OFF 204. Corresponding to R SWITCH-P 202 parallel 2 T-1 The resistance of the PFET switch 132 connecting the thermometer arm 120 and the B binary arms 122 is R ON (PFET) / 2 T-1 . Corresponding to R SWITCH-M 206 parallel 2T-1 The resistor that turns on the NFET switch 134 is R ON (NFET) / 2 T-1 .2 T-1 The looking-in resistance of the 1 thermometer arm resistor 124 and the various resistors of the B binary arms 122 corresponds to R ARM-ON 204. Parallel 2 T-1 The resistance of the thermometer arm resistor 124 corresponds to R TH-OFF 208. R ARM-ON 204 and R TH-OFF 208 equals 2R / 2 T-1 .

[0036] V OUT This is true at zero code because all thermometer arms 120 and binary arms 122 are deactivated, causing V OUT Equal to zero (or V REFM ). V OUT This is also true in the complete code because all thermometer arms 120 and binary arms 122 are enabled, making V OUT Equal to V REFP ×(2 N -1) / 2 N (Very close to V REFP As illustrated in model 200, at the intermediate code, the voltage from high voltage rail 116 to V is generated via thermometer arm 120 and binary arm 122, which are activated. OUT The resistance of 114 should be the same as the voltage from the low voltage rail 118 to VOUT 114 via the disabled thermometer arm 120. If these resistances are equal at the intermediate code, then the thermometer arm 120 and the binary arm 122 together contribute to VOUT. OUT Contributes half of the voltage that the thermometer arm 120 and the binary arm 122 can contribute (see Equations 1 and 2). If at intermediate codes these resistances are different, then there is an INL error.

[0037] Figure 3 is a functional block diagram and circuit diagram of a circuit 300 including a circuit coupled to a gate driver 112 N The circuit 300 further includes an example voltage regulator 110, the gate driver for providing a gate voltage for the thermometer arm 120 and the NMOS switch 134 of the binary arm 122. The circuit 300 also includes the arm switch 130, the gate driver 112 for the PFET switch 132 (gate driver 112 P ), a gate driver for the NFET switch 112 (gate driver 112 N ), and switch control 108. In the example, Figure 3Voltage regulator 110, gate driver 112 P , gate driver 112 N and the switch control 108 is Figure 1 Implementation of the control circuit 106. In this example, Figure 3 Gate driver 112 P and gate driver 112 N Together for Figure 1 Implementation of the gate driver 112. Provided by the switch control 108 to the gate driver 112 P and 112 N The control signal (see Figure 1 ) determines which PMOS switches 132 or NMOS switches 134 the gate driver 112 drives to activate or deactivate the corresponding temperature measurement arm 120 or binary arm 122.

[0038] The switch control 108 includes a gate driver 112 connected to the P The first output of the input and connected to the gate driver 112 N The second output of the input of the gate driver 112 P is connected to the ground terminal 306 which is at electrical ground, and the gate driver 112 P The output of is connected to the gate of the PFET switch 132. The gate driver 112 N The voltage input receives the voltage V from the output of the voltage regulator 110 for driving the NFET switch 134 SN , as further described below. In some examples, a single voltage regulator 110 is sufficient to provide the voltage V SN So that the single gate driver 112 N Individual NFET switches 134 of the R2R resistor ladder 104 can be driven.

[0039] Gate driver 112 N The output of is connected to the gate of NFET switch 134. In response to the code, switch control 108 controls gate driver 112 P To use the voltage at the ground terminal 306 (V SS ) to drive the PFET switch 132 to activate the corresponding thermometer arm 120 or binary arm 122. Alternatively, the switch control 108 controls the gate driver 112 N To use V SN to drive the NFET switch 134 to disable the corresponding thermometer arm 120 or binary arm 122. REFP and V REFM , the voltage regulator 110 consistently provides V SNThe switch control 108 receives the digital code and controls the gate driver 112 N (For example, using a set of switches) to switch V SN Selective switching is provided to the NFET switch 134. Also, in response to the digital code, the switch control 108 controls the gate driver 112 P to provide Vss to the selective switch in PFET switch 132.

[0040] The voltage regulator 110 includes n ladder PFETs, a ground terminal 306, and a resistor R C The first resistor (R C )310, with resistance y×R C The second resistor (yR C ) 312, a first differential amplifier 314, y×n ladder NFETs 316, y×n-1 third resistors (R B resistor) 320, a current source 322, a resistor R A The fourth resistor (R A )338 and having a resistance y×R A The fifth resistor (yR A ) 340. Here, n and y are integers. In some examples, n is greater than or equal to one. In some examples, y is greater than or equal to one. In some examples, y is greater than one. The current source 322 includes a first regulator PFET 326, a resistor having a resistance of n×R B The fourth resistor (nR B ) 328, a second differential amplifier 330, n second regulator PFETs 332, and a regulator resistor 334. The current source 322 and R B The use of resistor 320 avoids the introduction of non-linearities associated with the stacked drain-source voltage of ladder NFET 316, as further described below.

[0041] As illustrated, the high voltage rail 116 is connected to the source of the first ladder PFET 3041. The first ladder PFET 3041 is one of n cascade-coupled ladder PFETs 304, each of which has an equivalent resistance R when turned on. P , where n is greater than or equal to one. Cascade coupling means that the ladder PFETs 304 are connected in series, drain to source (between the high voltage rail 116 and R C10) and their gates are connected together and to the ground terminal 306 to form a p-ladder 308 comprising n ladder PFETs 304. Thus, the ladder PFETs 304 turn on in response to the R2R DAC 100 being powered and further in response to power being provided to the high voltage rail 116. The individual ladder PFETs 304 are numbered with subscripts (from 1 to n) starting with the ladder PFET 304 closest to the high voltage rail 116.

[0042] As described above, the gate of the PFET switch 132 of the thermometer arm 120 is driven by the gate driver 112. P Using the voltage at the ground terminal 306 (V SS ) is driven to turn on. The gate of the NFET switch 134 of the thermometer arm 120 is driven by the gate driver 112 N Using the voltage V at node A 324 SN Drive, the node A is coupled to the voltage regulator 110 or forms its output. Therefore, the node 324 can also be referred to as the output 324 of the voltage regulator 110. Determine the voltage V SN , such that when the NFET switch 134 of the thermometer arm 120 or binary arm 122 is on, it has an equivalent resistance close to the equivalent resistance of the PFET switch 132 of the thermometer arm 120 or binary arm 122 that is on (described further with respect to Equation 6).

[0043] n-th ladder PFET 304 n The drain is connected to R C The first terminal of 310. R C The second terminal of 310 is connected to yR C 312 and is connected to the non-inverting input of the first differential amplifier 314. Herein, the first end of the ladder PFET 304 (of the p-ladder 308) corresponds to the first ladder PFET 3041, and the second end of the ladder PFET 304 corresponds to the nth ladder PFET 304. n .

[0044] yR C The second terminal of 312 is connected to the drain of the first ladder NFET 3161. The first ladder NFET 3161 is a transistor having an equivalent resistance R when turned on. N Thus, the ladder NFETs 316 are connected in series, drain to source (at yR C 312 and the low voltage rail 118) to form an n-ladder 318 comprising y×n ladder NFETs 316. Each of the ladder NFETs 316 is connected to yR CThe ladder NFETs 316 of the second terminals of 312 are numbered with subscripts (from 1 to y×n).

[0045] (y×n)th ladder NFET 316 yxn The source of the first ladder NFET 3161 is connected to the low voltage rail 118. The gate of the first ladder NFET 3161 is connected to the respective resistor R B y×n-1 third resistors (R B The first terminal of the first one of the resistors 320 is connected to the output terminal of the current source 322. B Individual resistors 320 are connected to the gate of the first ladder NFET 3161 from R B Resistors 3201 are numbered with subscripts (from 1 to y×n-1). Herein, the first end of the ladder NFET 316 (of the n ladder 318) corresponds to the first ladder NFET 3161, and the second end of the ladder NFET 316 corresponds to the nth ladder PFET 316. n .

[0046] First R B The second terminal of the resistor 3201 is connected to the gate of the second ladder NFET 3162 and the second R B The first terminal of resistor 3202, and so on. Thus, the gates of the adjacent ones of the n ladder NFETs 316 are connected via y×n-1 R B Resistors 320 are connected together. (y×n)th ladder NFET 316 yxn The gate is connected to the (y×n-1)th R B Resistor 320 yxn-1 The second terminal of the first differential amplifier 314 and the output of the gate driver 112 (via the output of the voltage regulator 110) N At this connection (and the output of the first differential amplifier 314, etc.) is a voltage V SN As described above, the gate driver 112 N Provides V to the gate of NFET switch 134 SN to turn on NFET switch 134 (when controlled to do so by switch control 108).

[0047] The drain-source voltage V of each of the ladder PFETs 304 is subject to manufacturing process variations. DS Ideally, the drain-source voltage V DS Ideally, they are equal or identical or substantially identical. However, as described below, there are differences in the V of the ladder PFETs 304 with increasing subscript numbers.DS The accumulated error in R B Resistor 320 is avoided in ladder NFET 316 .

[0048] The description of the current source 322 is as follows. The drain of the first regulator PFET 326 is connected to the output terminal of the current source 322. The source of the first regulator PFET 326 is connected to a resistor having a resistance of n×R B The fourth resistor (nR B ) 328 and is connected to the inverting input of the second differential amplifier 330. The current through the first regulator PFET 326 is equal to V DS / R B ; This current is set as described below. The gate of the first regulator PFET 326 is connected to the output of the second differential amplifier 330. nR B A second terminal of 328 is connected to the high voltage rail 116 .

[0049] The source of the first of the n second regulator PFETs, 3321, is connected to the high voltage rail 116. The second regulator PFETs 332 are cascade-coupled. Thus, the second regulator PFETs 332 are connected in series, drain to source (between the high voltage rail 116 and node B 336), with their gates connected together and to ground 306. The individual second regulator PFETs 332 are numbered with subscripts (1 to n), starting with the second regulator PFET 3321 closest to the high voltage rail 116. The second regulator PFETs 332 are matched to the ladder PFETs 304. In some examples, MOSFET matching includes MOSFETs having the same size or substantially the same size. In some examples, MOSFET matching includes placement-oriented matching and / or using matched dummy fingers and / or using matched interleaving, meaning that these parameters are the same or substantially the same across the matched MOSFETs.

[0050] As mentioned above, the drain-source voltage of each of the second regulator PFETs 332 is V DS , subject to the errors mentioned above and described further below. n The drain of is connected to the non-inverting input of the second differential amplifier 330 and the first terminal of the regulator resistor 334. At this connection (and the non-inverting input of the second differential amplifier 330, etc.) is a resistor with a voltage V REFP -n×V DS336. The second terminal of the regulator resistor 334 is connected to the low voltage rail 118. The resistance of the regulator resistor 334 is selected so that the source-drain current flowing through the second regulator PFET 332 is equal to the source-drain current flowing through the ladder PFET 304. This, along with the matching described above, results in the V DS becomes equal to the V of the ladder PFET 304 DS Herein, the first end of the second regulator PFET 332 corresponds to the second regulator PFET 3321 closest to the high voltage rail 116, and the second end of the second regulator PFET 332 corresponds to the nth second regulator PFET 332. n .

[0051] The second differential amplifier 330 sets the voltage at its output so that the voltage at its inverting input is equal to the voltage at node B 336, V REFP -n×V DS Therefore, V REFP With V REFP -n×V DS The difference between the cross nR B The voltage across 328 is equal to n×V DS This means that the current (I RB ) is equal to the span nR B The voltage across 328 divided by nR B The resistance of 328 is shown in Equation 3:

[0052]

[0053] With resistance R A The fourth resistor (R A ) 338 has a first terminal connected to the high voltage rail 116. A The second terminal of 338 is connected to the inverting terminal of the first differential amplifier 314 and is connected to a resistor y×R A The fifth resistor (yR A )340 first terminal. yR A The second terminal of 340 is connected to the low voltage rail 118. This part of the voltage regulator (including R A 338 and yR A 340) sets the target voltage of the inverting input of the differential amplifier 314.

[0054] Negative feedback causes the voltage at the non-inverting input of the differential amplifier 314 to become equal to (or substantially equal to) the target voltage. This causes the on-resistance (R N) becomes equal to (or substantially equal to) the on-resistance (R P The negative feedback also causes the on-resistance (R NLADDER ) becomes equal to (or substantially equal to) the on-resistance (R PLADDER ). Considering the non-ideal circuit behavior, R P With R N The difference between R PLADDER With R NLADDER The difference between φ and φ is controlled by Equations 4 to 8 (described below).

[0055] Current I RB The gate-source voltage (V GS ) balanced. The (y×n)th ladder NFET 316 yxn With gate voltage V SN and source voltage V REFM If R B If the resistor 320 does not exist, then the (y×n-1)th ladder NFET 316 yxn-1 will have a gate voltage V SN and source voltage V REFM +V DS . (y×n-2)th ladder NFET 316 yxn-2 will have a gate voltage V SN and source voltage V REFM +2×V DS And so on, except that the V DS will differ slightly, introducing successively greater errors as the V GS will be slightly different.

[0056] Through R B The current I of the resistor 320 B This cumulative error is resolved. B There is a voltage drop R across each of the resistors 320. B ×I B =R B ×V DS / R B =V DS Therefore, the (y×n-1)th ladder NFET 316 yxn-1 With gate voltage V SN +V DS and source voltage V REFM +V DS. (y×n-2)th ladder NFET 316 yxn-2 With gate voltage V SN +V DS and source voltage V REFM +2×V DS And so on, so that each (matched) ladder NFET 316 has the same gate-source voltage, and therefore the same V DS .

[0057] R PLADDER With R NLADDER The difference between is given by Equation 4:

[0058]

[0059] V OS is the offset voltage of the first differential amplifier 314 (which exists due to the non-ideal characteristics of the first differential amplifier 314). The scaling factor k makes R N With R NLADDER Therefore, k is given by Equation 5:

[0060]

[0061] If the drain-source voltages of the stacked ladder NFETs 316 are equal, then the accuracy of Equation 4 is enhanced. PLADDER -R NLADDER It can be determined from the INL target (INL design budget), as described in Equation 6:

[0062] Maximum INL = (R PLADDER -R NLADDER )×2 N / (8×R)Equation 6

[0063] In Equation 6, Maximum INL is the INL target and R is Figure 1 R is the resistance unit used in , and N is the bit resolution of the R2R DAC 100. NLADDER According to the difference R PLADDER -R NLADDER To describe, as shown in Equation 7:

[0064]

[0065] As y increases, the corresponding term in Equation 4 shifts from two (if y is equal to one) toward one. Equation 4 shows that increasing y and / or n decreases R PLADDER With R NLADDERIn some examples, as the size of a transistor decreases, its on-resistance increases, and as the size of a transistor increases, its on-resistance decreases. Thus, Equations 4, 5, and 7 show that using an offset factor y (where y is greater than one) enables the use of an R that is 2y / (1+y) times higher than without the offset factor y (equivalently, if y equals one). NLADDER Thus, the offset factor y enables the use of an NFET switch 134 size that is (1+y) / 2y times the size that would be used without the offset factor y. In some examples, if y is equal to five, the NFET switch 134 size may be 3 / 5 of the size that would be used if y were equal to one.

[0066] In some instances, the V GS Error, so n is relatively small to avoid the accumulation of corresponding nonlinearity. B The use of resistor 320 to equalize the gate-source voltage of ladder NFETs 316 enables stacking of a relatively large number of ladder NFETs 316, i.e., y can be relatively large. Therefore, the use of resistor offset y enables reduction of nonlinearity, which enables increasing the number of stacked ladder NFETs 316, thereby increasing R NLADDER (and reducing the size of the NFET switch 134), as described in Equation 7. Therefore, smaller PFET switches 132 and NFET switches 134 can be used without increasing nonlinearity due to the unequal resistance of the PFET switches 132 and NFET switches 134. In this example, y is equal to 5, n is equal to 2, and R PLADDER -R NLADDER Equal to 0.4 ohms (Ω), V DS is equal to 20 millivolts (mV), and V OS is equal to 2mV, so (using Equation 7) R NLADDER Equal to 6.7Ω.

[0067] As described above, R NLADDER is determined using Equation 7 and can be used to determine the size or width / length (W / L) ratio of the NFET switch 134. R can be used to determine the size or W / L ratio of the PFET switch 132. PLADDER By etc.

[0068] Equation 8 gives:

[0069]

[0070] In some examples, the PFET switch 132, the NFET switch 134, and the transistors in the p-ladder 308 and the n-ladder 318 operate deep in the triode region. For transistors in the triode region, V DS =IDS ×R ON Therefore, Equation 5 can be rewritten as shown in Equation 9, which relates the specific current and voltage of the arm switch 130 of the thermometer arm 120 and the binary arm 122 to the specific current and voltage of the voltage regulator 110:

[0071]

[0072] V DS_LADDER is the drain-source voltage across the turned-on PFET switch 132 or NFET switch 134 in each thermometer arm 120 and binary arm 122, and I LADDER is the current flowing through it. I LADDER Equal to V REF / (4×R), where V REF Equal to V REFP -V REFM , and R is Figure 1 R is the unit of resistance used in V DS_REGULATOR is the drain-source voltage across the turned-on ladder PFET 304 in the p-ladder 308 or the turned-on ladder NFET 316 in the n-ladder 318, and I REGULATOR is the current flowing through it. In this example, I REGULATOR Equal to I LADDER , V REF =5V, and R = 128kΩ, making I(ladder) = 10µA, V DS (ladder) is equal to 67 microvolts (μV), V DS_REGULATOR is equal to 20mV, and k is approximately 300 (20mV / 67μV), making R N Therefore, in the depicted example, ladder PFET 304 and ladder NFET 316 can be fabricated with an equivalent resistance of 2 kΩ using available process nodes. In some examples, the characteristics of each transistor are further adjusted to account for second-order effects.

[0073] Therefore, the V of the ladder NFET 316 is GS With V DS The value matching enables the voltage regulator 110 to more accurately regulate the gate voltages of the NFET switches 134 of the thermometer arm 120 and the binary arm 122 to reduce the R PLADDER With R NLADDER Furthermore, the resistance offset y enables the use of a larger number of stacked ladder NFETs 316, thereby further enabling the voltage regulator 110 to more accurately regulate the gate voltages of the NFET switches 134 of the thermometer arm 120 and the binary arm 122 to reduce R PLADDER With R NLADDER The difference between. Reduce R PLADDER With RNLADDER The difference between φ(R) and φ(V) enables the R2R resistor ladder 104 to reduce the size of the NFET switches of the thermometer arm 120 and the binary arm 122 while meeting the same nonlinear budget.

[0074] Figure 4 is a circuit diagram of an example R2R resistor ladder 400. In this example, the R2R resistor ladder 400 is Figure 1 The R2R resistor ladder 400 includes resistors corresponding to Figure 1 The structure of the R2R resistor ladder 104, in which the additional offset resistor (R OS )402 has a resistor R OS . Resistor R OS 402 has a resistor 126 coupled to the P connector P The first terminal of the resistor R OS 402 has a second terminal coupled to the (P+1)th connector resistor 126 P+1 and coupled to the first terminal of the arm resistor 124 2^T-1+P The terminals of the arm resistor are connected to the (2 T -1+P) arm switch 130 2^T-1+P In the illustrated example, P is equal to B-2, corresponding to the (B-2)th connector resistor 126 B-2 and the (M-2)th arm switch 130 M-2 In some instances, R OS 402 is implemented as the P connector resistor 126 P part of the additional resistance.

[0075] In some examples, due to the characteristics of the R2R resistor ladder 104, the (j+1)th binary arm 122 j+1 The PFET switch 132 in the arm switch 130 has the j-th binary arm 122 j The total resistance of the PFET switch 132 in the arm switch 130 is twice that of the PFET switch 132, and therefore, has half the size. Similarly, the (j+1)th binary arm 122 j+1 The NFET switch 134 in the arm switch 130 has the j-th binary arm 122 j The temperature sensing arm 120 has twice the total resistance and half the size of the NFET switches 134 in the arm switches 130. With respect to this scaling, the temperature sensing arm 120 can be considered the zeroth binary arm 122. Scaling of the PFET switches 132 and NFET switches 134 in the binary arms is performed to keep the R2R resistor ladder 104 balanced.

[0076] In some examples, doubling the resistance by halving the size of each successive PFET switch 132 / NFET switch 134 pair means that, for the smallest PFET switch 132 and NFET switch 134 (the switches on the LSB binary arm 122) to be manufactured by an available process, the largest PFET switch 132 and NFET switch 134 (the switches of the thermometer arm 120) occupy a relatively large amount of device area. In some examples, the device area limits the maximum size (and, therefore, the minimum resistance) of the PFET switch 132 and NFET switch 134.

[0077] Instead, the LSB arm switch 130 N (B binary arm 122 B In some instances, stacking MOSFETs in series in the arm switch 130 is used to compensate for the unavailability of smaller switch sizes. In some instances, due to, for example, Figure 3 Described by V GS and V DS Switch stacking results in additional DNL contribution due to other issues such as the switch stacking problem. This DNL generation problem can be compensated for with significant additional area cost, and switching speed cost can be attributed to the compensating structure.

[0078] Furthermore, as depicted, the resistance of the PFET switch 132 and the NFET switch 134 increases as the arm switch 130 index increases (in the direction of the LSB binary arm 122). DS The number of the subscripts of the binary arm 122 and the arm switch 130 also increases. As the V DS As τ increases, the accuracy of the resistance of PFET switch 132 and NFET switch 134 decreases, ie, process tolerances increase. In some instances, the switch resistance accuracy decreases enough that PFET switch 132 and NFET switch 134 operate in saturation mode rather than triode mode.

[0079] In some examples, to reduce or prevent these problems, the arm switch 130 of the (P-1)th binary arm 122 is P-1 (Pth binary arm 122 arm switch 130 P The size of the PFET switch 132 and the NFET switch 134 after the (P+1)th binary arm 122 and the arm switch 130 after the (P-1)th binary arm 122 and the arm switch 130 after the (P+ ... P-1 This is called "stop scaling", where the arm switch 130 in the (P-1) binary arm 122 P-1 The scaling down of the continuous arm switch 130 is then stopped.

[0080] In the R2R resistor ladder 400, the switch sizes are indicated by the labels "Size A," "Size 2A," "Size 4A," etc. As described above, Figure 4 In the example R2R resistor ladder 400, P is equal to B-2. Therefore, the (P-1)th binary leg 122 arm switch 130 P-1 and the less significant bit arm switch 130 (arm switch 130 P , 130 P+1 , and so on) have respective sizes corresponding to size A. In some examples, the PFET switch 132 and the NFET switch 134 have the same size corresponding to size A. In some examples, size A indicates a size of the PFET switch 132 that is different from a size of the NFET switch 134. The (P-2)th binary arm 122 arm switch 130 P-2 The PFET switch 132 and the NFET switch 134 have respective sizes corresponding to a size of 2A. The (P-3)th binary arm 122 arm switch 130 P-3 The PFET switch 132 and the NFET switch 134 have respective sizes corresponding to 4A; and so on.

[0081] Stop scaling causes the Pth and later (less significant) arm switches 130 to contribute additional DNL. In some examples, the Pth binary arm 122 contributes additional DNL due to stop scaling, and each successive arm after the Pth binary arm 122 contributes half as much DNL due to stop scaling. The DNL contribution is caused by the mismatch in the input impedance between the binary arm 122 of the stop switch size and the more significant binary arms 122.

[0082] The input impedance (R eq ) is equal to 2R plus the equivalent resistance component contributed by the corresponding arm switch 130 (R SW In a balanced R2R resistor ladder 104, where the unit resistance R is the same and the arm switches 130 follow a binary scaling rule, the R of the binary arm 122 eq The stop scaling reduces the binary arm 122 to which the stop scaling is applied (the Pth binary arm 122 M ) of R SW . R SW The difference makes the Pth binary arm 122 M R eq Lower than the R of the more significant binary arm 122 eq . R eq The difference in ∆t causes an additional DNL contribution to the stop scaling. Using an offset resistor (R OS )402 to reduce the maximum magnitude of DNL caused by stopping scaling, as described in relation to Figure 5A 、 5B and 6 further described.

[0083] Figure 5A yes Figure 1 FIG5 illustrates an example graph 500 of DNL error versus code for the R2R DAC 100. In the illustrated example, stop scaling is applied such that the DNL error plot 502 shows a relatively large maximum DNL error peak 504 at a code corresponding to the arm switch 130 to which no scaling is applied.

[0084] Figure 5B is used Figure 4 Graph 506 shows an example of DNL versus code for an R2R DAC of the R2R resistor ladder 400. Graph 506 includes a DNL error plot 508. In the illustrated example, stop scaling is applied. However, R OS 402 causes a DNL error 510 at the code corresponding to the arm switch 130 to which scaling has not been applied. This causes the DNL error range for the arm switch 130 to which scaling has not been applied to be spaced from the positive range to the negative range. As a result, the maximum magnitude of the DNL error 510 is reduced. In some examples, the sum of the pre-existing maximum DNL magnitude and the maximum DNL magnitude contributed by the descaling is halved.

[0085] Figure 6 is used to determine where to place the offset resistor R OS 402 is an example process for enabling the arm switch 130 to stop scaling relative to the least significant bit binary arm 122 of the R2R resistor ladder 104. In step 602, the V OUT In some examples, a DNL budget of 0.2 LSB or another amount less than (or much less than) one LSB is used as the DNL budget of the R2R DAC 100. In step 604, the P-th binary arm switch 130 is determined. M , so that the P-th binary arm switch 130 P and the less significant bit binary arm switch (130 P+1 , etc.) application stops scaling and simultaneously sets the offset resistor R OS 402 added to the P connector resistor 126 P , an amount of DNL less than or equal to the DNL budget will be added. In some examples, DNL can be expressed as a function of P, and P can be determined in response to the DNL budget. In some examples, P is determined empirically.

[0086] Figure 7is a functional block diagram and circuit diagram of an alternative example circuit 700 including an alternative example voltage regulator 110 for the gate voltage of the NMOS switch 134 of the thermometer arm 120 and the binary arm 122 . Figure 7 The voltage regulator 110 is similar to Figure 3 voltage regulator 110. However, Figure 7 The voltage regulator 110 does not contain Figure 3 The third resistor (R B )318 and current source 322. Figure 3 The voltage regulator 110 includes a resistor y×R C The second resistor (yR C ) 312 and n ladder 318. Therefore, the voltage regulator 110 of FIG. 700 provides R PLADDER and R NLADDER The corresponding decrease in the size of Figure 3 In some instances, such as with respect to Figure 3 As described, DNL is determined by the V GS The uncorrected mismatch contribution between

[0087] Modifications to the described examples are possible, and other examples are possible, within the scope of the claims.

[0088] In some examples, the R2R resistor ladder includes zero or greater than zero thermometer arms and two or more binary arms.

[0089] In some examples, references herein to a minimum MOSFET size refer to a MOSFET having the smallest width or length (or other) dimension available within the corresponding fabrication process.

[0090] In some examples, a resistor ladder other than an R2R resistor ladder is used. In some examples, the resistance of the connector resistor 124 or the arm resistor 126 is intentionally varied to induce an intentional DNL value or value sign to facilitate fine tuning.

[0091] In some examples, a similar current source and resistor arrangement is included to make the V GS The V of the ladder PFET used GS In some instances, this is not done because there is not enough voltage range (headroom) to do so. In some instances, there is not enough headroom to do so because the R2R resistor ladder 104 is designed to have a voltage swing from the low (lowest) rail of the corresponding IC to the high (highest) rail of the IC.

[0092] In some examples, ladder PFET 306 is matched to PFET switch 132 (or design techniques corresponding to matching are applied), and / or ladder NFET 316 is matched to NFET switch 134 (or design techniques corresponding to matching are applied). For example, matching can be applied using the same placement orientation, the same use of dummy devices, and the same use of fingers of equal size. For example, relative to the equal-sized diagram, if ladder NFET 306 is designed as a single-finger PFET with unit width and unit length, then the NFET switch is designed as a multi-finger PFET with X fingers, each of which has unit width and unit length. In some examples, X is much greater than one.

[0093] In some examples, one or more offset resistors are added between one or more pairs of connector resistors with higher subscript numbers (lower bit significance) than the Mth and (M+1)th connector resistors to further reduce the maximum magnitude of DNL caused by stop scaling.

[0094] The term "coupled" is used throughout this specification. This term encompasses any connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then in the first instance, device A is coupled to device B. Alternatively, in the second instance, if the intermediate component C does not substantially alter the functional relationship between devices A and B, then device A is coupled to device B through an intermediate component C such that device B is controlled by device A via the control signal provided by device A.

[0095] In this specification, the term "and / or" (when used in a form such as A, B and / or C) refers to any combination or subset of A, B, C, such as: (a) only A; (b) only B; (c) only C; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. In addition, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to embodiments that include any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0096] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function at the time of manufacture by the manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may occur through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0097] As used herein, the terms "terminal," "node," "interconnect," "pin," "solder ball," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection between or terminations of a device element, circuit element, integrated circuit, device, or other electronic device or semiconductor component.

[0098] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacture, for example, by an end user and / or a third party, to form the described structure.

[0099] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used with little or no change to the remaining circuitry. For example, MOSFETs (e.g., n-channel MOSFETs, nMOSFETs or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (BJTs, such as NPN or PNP), insulated gate bipolar transistors (IGBTs), junction field effect transistors (JFETs), and / or other field effect transistors (FETs, such as n-channel or p-channel FETs) may be used in place of or in combination with the devices disclosed herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs). Furthermore, the control terminal in the FET corresponds to the base on a BJT or the gate or other corresponding structure in another type of transistor.

[0100] The circuits described herein are reconfigurable to include functionality that provides functionality at least partially similar to that available before the component replacement by replacing the component. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

[0101] While some elements of the described examples may be included in an integrated circuit and other elements external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Furthermore, some or all of the features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" refers to one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0102] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. Unless otherwise stated, the words "about," "substantially," or "substantially" preceding a value mean + / - 10% of the value, or, if the value is zero, a reasonable range of values ​​around zero.

Claims

1. An integrated circuit (IC), comprising: a first resistor having a first terminal and a second terminal and having a resistance R1; N p-channel field effect transistors (ladder PFETs) coupled together as a p-ladder, each ladder PFET having a source, a drain, and a gate, wherein N is an integer greater than or equal to one, wherein if N is greater than one, the ladder PFETs are coupled together as a p-ladder such that the gates of the ladder PFETs are coupled together, the drains and sources of the ladder PFETs are cascade coupled between a first end and a second end of the p-ladder, and the second end of the p-ladder is coupled to the first terminal of the first resistor; a differential amplifier comprising a first input, a second input, and an output; a second resistor including a first terminal and a second terminal and having a resistance of y×R1, where y is an integer greater than one, and a first terminal of the second resistor coupled to the second terminal of the first resistor and the first input of the differential amplifier; as well as y×N n-channel field effect transistors (ladder NFETs) coupled together as n-ladders, each ladder NFET having a source, a drain, and a gate, the gates of the ladder NFETs coupled together, the drains and sources of the ladder NFETs coupled in cascade between a first end and a second end of the n-ladder, the first end of the n-ladder coupled to the second terminal of the second resistor, and the second end of the n-ladder coupled to the output of the differential amplifier.

2. The IC of claim 1 , further comprising: a third resistor having a first terminal, a second terminal, and a resistance R2; as well as A fourth resistor having a first terminal, a second terminal, and a resistance of y×R2, the first terminal of the fourth resistor being coupled to the second terminal of the third resistor and to the second input of the differential amplifier.

3. The IC of claim 1 , further comprising: a gate driver comprising an input and a plurality of outputs, the input of the gate driver being coupled to the output of the differential amplifier; as well as An R2R resistor ladder includes a plurality of arms coupled together, at least some of the arms respectively including a p-channel field effect transistor (PFET switch) and an n-channel field effect transistor (NFET switch), wherein the source of the NFET switch is coupled to the source of the PFET switch, and the gate of the NFET switch is coupled to a different one of the outputs of the gate driver than the gates of the NFET switches of the other arms.

4. The IC according to claim 1, further comprising y×N−1 third resistors, each of the third resistors having a resistance R2; Wherein different pairs of the ladder NFETs adjacently drain-to-source coupled within the n-ladder have respective gates coupled together via different ones of the third resistors.

5. The IC according to claim 4, wherein each of the third resistors has a first terminal and a second terminal; The IC further includes a current source having a first terminal and a second terminal, the second terminal of the current source coupled to the gate of the ladder NFET at the first end of the n-ladder and to the first terminal of one of the third resistors.

6. The IC according to claim 5, Each of the ladder NFETs is configured to have a drain-source voltage V DS ;and The current source is configured to provide a current equal to V DS Divide the current by R2.

7. The IC of claim 5 , wherein the ladder PFET is a first PFET, the p-ladder is a first p-ladder, the differential amplifier is a first differential amplifier, and the current source comprises: a second differential amplifier comprising a first input, a second input, and an output; a second PFET having a source, a drain, and a gate, the gate of the second PFET being coupled to the output of the second differential amplifier and the drain of the second PFET being coupled to the second terminal of the current source; a fourth resistor having a first terminal, a second terminal, and a resistance of N×R2, the first terminal of the fourth resistor being coupled to the first input of the second differential amplifier and the source of the second PFET; a fifth resistor having a first terminal and a second terminal; and N third PFETs, each of which has a source, a drain, and a gate, wherein if N is greater than one, the third PFETs are coupled together as a second p-ladder such that the gates of the third PFETs are coupled together, the drain and source of the third PFETs are cascade coupled between the first and second ends of the second p-ladder, and the second end of the second p-ladder is coupled to the first terminal of the fifth resistor and the second input of the second differential amplifier.

8. An integrated circuit (IC), comprising: a first resistor having a first terminal, a second terminal, and a resistance R1; N p-channel field effect transistors (ladder PFETs), each ladder PFET having a source, a drain, and a gate, wherein N is greater than or equal to one, wherein if N is greater than one, the ladder PFETs are coupled together as a p-ladder such that the gates of the ladder PFETs are coupled together, the drains and sources of the ladder PFETs are cascade coupled between a first end and a second end of the p-ladder, and the second end of the p-ladder is coupled to the first terminal of the first resistor; a differential amplifier comprising a first input, a second input, and an output; a second resistor having a first terminal, a second terminal, and a resistance y×R1, where y is an integer greater than or equal to one such that y×N is greater than one, and a first terminal of the second resistor coupled to the second terminal of the first resistor and the first input of the differential amplifier; y×N−1 third resistors, each of the third resistors having a resistance R2; and y×N n-channel field effect transistors (ladder NFETs) coupled together as n ladders, each ladder NFET having a source, a drain, and a gate, the drain and source of the ladder NFET being cascade-coupled between a first end and a second end of the n ladder, the first end of the n ladder being coupled to the second terminal of the second resistor, and the second end of the n ladder being coupled to the output of the differential amplifier; wherein different pairs of the ladder NFETs adjacently drain-to-source coupled within the n-ladder have Different ones of the third resistors couple together the respective gates.

9. The IC of claim 8, wherein y is greater than one.

10. The IC of claim 8, further comprising: a fourth resistor having a first terminal, a second terminal, and a resistance R3; as well as A fifth resistor having a first terminal, a second terminal, and a resistance of y×R2, the first terminal of the fifth resistor being coupled to the second terminal of the fourth resistor and to the second input of the differential amplifier.

11. The IC of claim 8, further comprising: a gate driver comprising an input and a plurality of outputs, the input of the gate driver being coupled to the output of the differential amplifier; An R2R resistor ladder includes a plurality of arms coupled together, at least some of the arms respectively including a p-channel field effect transistor (PFET switch) and an n-channel field effect transistor (NFET switch), wherein the source of the NFET switch is coupled to the source of the PFET switch, and the gate of the NFET switch is coupled to a different one of the outputs of the gate driver than the gates of the NFET switches of the other arms.

12. The IC according to claim 8, wherein each of the third resistors has a first terminal and a second terminal; The IC further includes a current source having a first terminal and a second terminal, the second terminal of the current source coupled to the gate of the ladder NFET at the first end of the n-ladder and to the first terminal of one of the third resistors.

13. The IC according to claim 12, Each of the ladder NFETs is configured to have a drain-source voltage V DS ;and The current source is configured to provide a current equal to V DS Divide the current by R2.

14. The IC of claim 12 , wherein the ladder PFET is a first PFET, the p-ladder is a first p-ladder, the differential amplifier is a first differential amplifier, and the current source comprises: a second differential amplifier comprising a first input, a second input, and an output; a second PFET having a source, a drain, and a gate, the gate of the second PFET being coupled to the output of the second differential amplifier and the drain of the second PFET being coupled to the second terminal of the current source; a fourth resistor having a first terminal, a second terminal, and a resistance of N×R2, the first terminal of the fourth resistor being coupled to the first input of the second differential amplifier and the source of the second PFET; a fifth resistor having a first terminal and a second terminal; and N third PFETs, each of which includes a source, a drain, and a gate, wherein if N is greater than one, the third PFETs are coupled together as a second p-ladder such that the gates of the third PFETs are coupled together, the drain and source of the third PFETs are cascade coupled between a first end and a second end of the second p-ladder, and the second end of the second p-ladder is coupled to the first terminal of the fifth resistor and the second input of the second differential amplifier.

15. A digital-to-analog converter system comprising: a gate driver comprising a first input, a second input, and a plurality of outputs; a control circuit comprising an input and an output, the output of the control circuit being coupled to the first input of the gate driver; an R2R resistor ladder comprising a plurality of arms coupled together, at least some of the arms respectively comprising a p-channel field effect transistor (PFET) switch and an n-channel field effect transistor (NFET) switch, wherein a source of the NFET switch is coupled to a source of the PFET switch, and a gate of the NFET switch is coupled to a different one of the outputs of the gate driver than gates of the NFET switches of other arms; as well as A voltage regulator comprising: a first resistor having a first terminal, a second terminal, and a resistance R1; N ladder PFETs, each ladder PFET having a source, a drain, and a gate, wherein N is an integer greater than or equal to one, wherein if N is greater than one, the ladder PFETs are coupled together as a p-ladder such that the gates of the ladder PFETs are coupled together, the drains and sources of the ladder PFETs are cascade coupled between a first end and a second end of the p-ladder, and the second end of the p-ladder is coupled to the first terminal of the first resistor; a differential amplifier comprising a first input, a second input, and an output, the output of the differential amplifier being coupled to the second input of the gate driver; a second resistor having a first terminal, a second terminal, and a resistance y×R1, where y is an integer greater than one, and a first terminal of the second resistor coupled to the second terminal of the first resistor and the first input of the differential amplifier; as well as y×N ladder NFETs coupled together as an n-ladder, each ladder NFET having a source, a drain, and a gate, the gates of the ladder NFETs coupled together, the drains and sources of the ladder NFETs cascade-coupled between a first end and a second end of the n-ladder, the first end of the n-ladder coupled to the second terminal of the second resistor, and the second end of the n-ladder coupled to the output of the differential amplifier.

16. The digital-to-analog converter system of claim 15, further comprising: a third resistor having a first terminal, a second terminal, and a resistance R2; as well as A fourth resistor having a first terminal, a second terminal, and a resistance of y×R2, the first terminal of the fourth resistor being coupled to the second terminal of the third resistor and to the second input of the differential amplifier.

17. The digital-to-analog converter system according to claim 15, further comprising y×N−1 third resistors, each of the third resistors having a resistance R2; Wherein different pairs of the ladder NFETs adjacently drain-to-source coupled within the n-ladder have respective gates coupled together via different ones of the third resistors.

18. The digital-to-analog converter system according to claim 17, wherein each of the third resistors has a first terminal and a second terminal; The digital-to-analog converter system further includes a current source having a first terminal and a second terminal, the second terminal of the current source coupled to the gate of the ladder NFET at the first end of the n-ladder and to the first terminal of one of the third resistors.

19. The digital-to-analog converter system according to claim 18, Each of the ladder NFETs is configured to have a drain-source voltage V DS ;and The current source is configured to provide a current equal to V DS Divide the current by R2.

20. The digital-to-analog converter system of claim 18, wherein the ladder PFET is a first PFET, the p-ladder is a first p-ladder, the differential amplifier is a first differential amplifier, and the current source comprises: a second differential amplifier comprising a first input, a second input, and an output; a second PFET having a source, a drain, and a gate, the gate of the second PFET being coupled to the output of the second differential amplifier and the drain of the second PFET being coupled to the second terminal of the current source; a fourth resistor having a first terminal, a second terminal, and a resistance of N×R2, the first terminal of the fourth resistor being coupled to the first input of the second differential amplifier and the source of the second PFET; a fifth resistor having a first terminal and a second terminal; and N third PFETs, each of which includes a source, a drain, and a gate, wherein if N is greater than one, the third PFETs are coupled together as a second p-ladder such that the gates of the third PFETs are coupled together, the drain and source of the third PFETs are cascade coupled between a first end and a second end of the second p-ladder, and the second end of the second p-ladder is coupled to the first terminal of the fifth resistor and the second input of the second differential amplifier.

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