Photoelectric detection device and counting circuit

Abstract

The present invention suppresses an increase in the number of state transitions during a counting period. The photoelectric detection device includes: light receiving units arranged in a matrix in a row direction and a column direction and outputting pulses generated in response to incidence of photons; and a counting circuit that counts the pulses output from the light receiving unit. The counting circuit includes a plurality of 2-bit Johnson counters that cause a state transition based on a transition input. And the second bit of the counting output of the front-stage 2-bit Johnson counter is used as the conversion input of the rear-stage 2-bit Johnson counter. Each 2-bit Johnson counter includes flip-flops connected in two stages, and in each of the plurality of 2-bit Johnson counters, an inverted value of an output of a latter stage flip-flop may be used as an input of a preceding stage flip-flop.

Description

Technical Field

[0001] The present invention relates to a photodetection device and a counting circuit. More specifically, the present invention relates to a photodetection device and a counting circuit in which 2-bit Johnson counters are connected in multiple stages. Background Art

[0002] Counting circuits are used for various types of counting, including counting photons, particles, pulses, and time. For example, an image sensor has been proposed that counts the number of photons incident on a photodiode during an exposure period and outputs the photon count value as a signal value (for example, see Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2019-129338 Summary of the Invention

[0006] Problems to be solved by the present invention

[0007] However, in the above-described conventional technology, since a binary counter is used as a counting circuit, the number of state transitions at the time of counting is large, and there is a possibility that power consumption increases.

[0008] The present technology has been made in view of such circumstances, and an object thereof is to suppress an increase in the number of state transitions at the time of counting.

[0009] Solution to the problem

[0010] The present technology was developed to address the aforementioned issues. A first aspect of the present technology is a photodetection device comprising: light receiving elements arranged in a matrix in row and column directions and outputting pulses generated in response to incident photons; and a counting circuit for counting the pulses output from the light receiving elements. The counting circuit includes a plurality of 2-bit Johnson counters whose states transition based on a transition input, and the second bit of the count output of the preceding 2-bit Johnson counter serves as a transition input for the succeeding 2-bit Johnson counter. This effectively increases the state transition cycle of the succeeding 2-bit Johnson counter compared to the preceding 2-bit Johnson counter.

[0011] Furthermore, in the first aspect, each of the 2-bit Johnson counters may include flip-flops connected in two stages, and in each of the plurality of 2-bit Johnson counters, an inverted value of the output of the flip-flop at the subsequent stage may be used as an input to the flip-flop at the preceding stage. This provides an effect of configuring a 2-bit Johnson counter using flip-flops connected in two stages.

[0012] Furthermore, in the first aspect, the photodetection device may further include an inverter connected between the output of the subsequent-stage flip-flop and the input of the preceding-stage flip-flop. This allows the inverted value of the output of the subsequent-stage flip-flop to be used as the input of the preceding-stage flip-flop.

[0013] Furthermore, in the first aspect, each of the 2-bit Johnson counters may include flip-flops connected in two stages. In each of the plurality of 2-bit Johnson counters, a value held in the flip-flop at the subsequent stage, which is an inverted value of the output of the flip-flop at the subsequent stage, may be used as an input to the flip-flop at the preceding stage. This provides an advantage of configuring the 2-bit Johnson counter using flip-flops connected in two stages, and suppressing rewriting of the value held in the counting circuit.

[0014] Furthermore, in each of the plurality of 2-bit Johnson counters in the first aspect, a value held in a flip-flop at a preceding stage as an inverted value of the output of the flip-flop at the preceding stage and a value held in a flip-flop at a succeeding stage as an inverted value of the output of the flip-flop at the succeeding stage can be used as the output of the counting circuit. This provides an effect of configuring a 2-bit Johnson counter using flip-flops connected in two stages, and outputting the value held in the counting circuit as the count value.

[0015] In addition, in the first aspect, the flip-flop at the preceding stage may include a first latch circuit and a second latch circuit connected at a subsequent stage to the first latch circuit, and the flip-flop at the subsequent stage may include a third latch circuit and a fourth latch circuit connected at a subsequent stage to the third latch circuit. This results in an effect of configuring a 2-bit Johnson counter using flip-flops connected in two stages.

[0016] In addition, in the first aspect, the first latch circuit may include: a first inverting circuit that inverts the input; a second inverting circuit that is connected in reverse parallel to the first inverting circuit and inverts the input based on the transition input; and a first switch circuit that is connected at the front stage of the first inverting circuit and opens and closes based on the transition input, and the second latch circuit may include: a third inverting circuit that inverts the input; a fourth inverting circuit that is connected in reverse parallel to the third inverting circuit and inverts the input based on the transition input; and a second switch circuit that is connected at the front stage of the third inverting circuit and opens and closes based on the transition input. The third latch circuit may include: a fifth inverting circuit that inverts the input; a sixth inverting circuit that is connected in reverse parallel to the fifth inverting circuit and inverts the input based on the transition input; and a third switch circuit that is connected at the preceding stage of the fifth inverting circuit and opens and closes based on the transition input, while the fourth latch circuit may include: a seventh inverting circuit that inverts the input; an eighth inverting circuit that is connected in reverse parallel to the seventh inverting circuit and inverts the input based on the transition input; and a fourth switch circuit that is connected at the preceding stage of the seventh inverting circuit and opens and closes based on the transition input. This brings about the effect of alternately repeating state transition and latch holding based on the transition input in each flip-flop.

[0017] In addition, in the first aspect, each of the first and fifth inverter circuits may be a NAND circuit to which a reset signal is input, each of the third and seventh inverter circuits may be an inverter, each of the second, fourth, sixth, and eighth inverter circuits may be a clocked inverter, and each of the first to fourth switch circuits may be a transmission gate. This provides an effect of alternately repeating state transition and latch retention based on a transition input while enabling the count value to be reset.

[0018] In the first aspect, the photodetection device may include a capacitor connected to an input terminal of a trigger at a preceding stage. This stabilizes the value of the feedback path for the 2-bit Johnson counter.

[0019] Furthermore, in the first aspect, the capacitance value of the capacitor can be larger than the capacitance value of the capacitor added to the output of the first switching circuit. This has the effect of enabling feedback from the flip-flop at the subsequent stage to the flip-flop at the preceding stage in each 2-bit Johnson counter, and suppressing rewriting of the value held in the counting circuit.

[0020] In the first aspect, the capacitor may be a metal capacitor, a gate capacitor whose gate is connected to the input terminal of the flip-flop at the previous stage, or a gate capacitor whose source / drain is connected to the input terminal of the flip-flop at the previous stage. This has the effect of adding a capacitor to the input terminal of the flip-flop at the previous stage.

[0021] In the first aspect, the capacitor may be a variable capacitor having a variable capacitance value. This allows the defect rate to be estimated by extrapolation based on the relationship between the capacitance and the defect rate.

[0022] In addition, in the first aspect, each of the first and fifth inverter circuits may be a NAND circuit to which a reset signal is input, each of the third and seventh inverter circuits may be an inverter, the first switch circuit and each of the second, fourth, sixth, and eighth inverter circuits may be a clocked inverter, and each of the second to fourth switch circuits may be a transmission gate. This provides an effect of using the value held in the subsequent-stage flip-flop as the inverted value of the output of the subsequent-stage flip-flop as the input of the preceding-stage flip-flop while suppressing an increase in the number of components.

[0023] In the first aspect, each of the first and fifth inverter circuits may be a NAND circuit to which a reset signal is input, each of the third and seventh inverter circuits may be an inverter, each of the second, fourth, and sixth inverter circuits may be a clocked inverter, the eighth inverter circuit may be a series circuit of an inverter and a transmission gate, and each of the first to fourth switch circuits may be a transmission gate. This provides an effect of performing latch holding based on a transition input.

[0024] In addition, in the first aspect, each of the first and fifth inverter circuits may be a NAND circuit to which a reset signal is input, each of the third and seventh inverter circuits may be an inverter, each of the second and sixth inverter circuits may be a clocked inverter, each of the fourth and eighth inverter circuits may be a series circuit of an inverter and a transmission gate, and each of the first to fourth switch circuits may be a transmission gate. This achieves the effect of using the value held in the subsequent-stage flip-flop as the inverted value of the output of the subsequent-stage flip-flop as the input of the preceding-stage flip-flop while ensuring layout symmetry.

[0025] Furthermore, in the first aspect, the pulse generated by the incidence of photons can be input to the first stage of the 2-bit Johnson counter. This brings about the effect of counting the number of photons incident on the light receiving unit.

[0026] Furthermore, in the first aspect, the number of states can be given as 4 n , where n is the number of stages of the 2-bit Johnson counter. This has the effect of increasing the number of states compared to the Johnson counter, where the output of the flip-flop in the last stage is fed back to the input of the flip-flop in the first stage.

[0027] In the first aspect, the counting circuit may be provided below the light receiving unit. This provides an effect of forming a counting circuit for each light receiving unit while suppressing an increase in the planar size of the imaging device.

[0028] Furthermore, a second aspect is a counting circuit including a plurality of 2-bit Johnson counters, the states of which transition based on a transition input, wherein the second bit of the count output of the preceding 2-bit Johnson counter serves as the transition input of the succeeding 2-bit Johnson counter. This has the effect of making the cycle of state transition of the succeeding 2-bit Johnson counter longer than the cycle of state transition of the preceding 2-bit Johnson counter. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 2 is a block diagram showing a configuration example of a camera employing the imaging device according to the first embodiment.

[0030] Figure 2 is a block diagram showing a configuration example of the solid-state imaging device according to the first embodiment.

[0031] Figure 3 is a circuit diagram showing a configuration example of a pixel according to the first embodiment.

[0032] Figure 4 is a block diagram showing a configuration example of a counting circuit according to the first embodiment.

[0033] Figure 5 is a circuit diagram showing a configuration example of a 2-bit Johnson counter according to the first embodiment.

[0034] Figure 6 is a timing chart showing the output operation of the counting circuit according to the first embodiment.

[0035] Figure 7 is a circuit diagram showing a configuration example of a counting circuit according to the second embodiment.

[0036] Figure 8 is a timing chart showing the output operation and internal state of the counting circuit according to the second embodiment.

[0037] Figure 9 : is a diagram illustrating a comparison between a state transition of a counting circuit according to the second embodiment and a state transition in a comparative example.

[0038] Figure 10 is a circuit diagram showing a configuration example of a counting circuit according to the third embodiment.

[0039] Figure 11 is a circuit diagram showing a first example of a counting circuit according to the fourth embodiment.

[0040] Figure 12 : is a circuit diagram showing an example of a capacitor in a return path of a counting circuit according to a fourth embodiment.

[0041] Figure 13 is a circuit diagram illustrating an example of a change in potential in a return path of a counting circuit according to a fourth embodiment.

[0042] Figure 14 is a circuit diagram showing a second example of the counting circuit according to the fourth embodiment.

[0043] Figure 15 is a circuit diagram showing a third example of the counting circuit according to the fourth embodiment.

[0044] Figure 16 is a circuit diagram showing a fourth example of the counting circuit according to the fourth embodiment.

[0045] Figure 17 is a plan view showing a layout example of a counter circuit according to the fourth embodiment.

[0046] Figure 18 is a circuit diagram showing a configuration example of a counting circuit according to a fifth embodiment.

[0047] Figure 19 is a plan view showing a layout example of a 2-bit Johnson counter according to the fifth embodiment.

[0048] Figure 20 is a circuit diagram showing a configuration example of a counting circuit according to a sixth embodiment.

[0049] Figure 21 is a plan view showing a layout example of a 2-bit Johnson counter according to the sixth embodiment.

[0050] Figure 22 is a circuit diagram showing a configuration example of a counting circuit according to a seventh embodiment.

[0051] Figure 23 is a perspective view showing a layout example of a solid-state imaging device according to an eighth embodiment.

[0052] Figure 24 is a perspective view showing a layout example of a solid-state imaging device according to a ninth embodiment.

[0053] Figure 25 is a circuit diagram showing a configuration example of a pixel according to a tenth embodiment.

[0054] Figure 26 is a block diagram showing a configuration example of a distance measuring device according to an eleventh embodiment.

[0055] Figure 27 is a block diagram showing a schematic configuration example of a vehicle control system.

[0056] Figure 28 is an explanatory diagram illustrating an example of an installation position of an imaging unit. DETAILED DESCRIPTION

[0057] Hereinafter, a mode for carrying out the present technology (hereinafter referred to as an embodiment) will be described. The description will be given in the following order.

[0058] 1. First Embodiment (Example in which the second bit of the count output of the 2-bit Johnson counter at the preceding stage is used as the transition input of the 2-bit Johnson counter at the succeeding stage)

[0059] 2. Second Embodiment (Example in which the output of the clocked inverter of the latch circuit at the subsequent stage of the flip-flop at the subsequent stage is fed back to the flip-flop at the preceding stage in a 2-bit Johnson counter)

[0060] 3. Third Embodiment (Example in which a clocked inverter is used for the input of a preceding latch circuit of a flip-flop at the preceding stage in a 2-bit Johnson counter)

[0061] 4. Fourth Embodiment (Example of Feedback in Which the Output of the Clocked Inverter of the Post-Stage Latch Circuit of the Flip-Flop at the Post-Stage is Fed Back to the Flip-Flop at the Previous Stage and a Capacitor is Added to a 2-Bit Johnson Counter)

[0062] 5. Fifth Embodiment (Example in which the output of the inverter serving as the input of the transmission gate of the subsequent latch circuit of the flip-flop at the subsequent stage is fed back to the flip-flop at the preceding stage in a 2-bit Johnson counter)

[0063] 6. Sixth Embodiment (Example of Using a Transmission Gate and an Inverter in Place of a Latch Circuit Following a Flip-Flop at a Previous Stage and a Clocked Inverter Following a Flip-Flop at a Next Stage in a 2-Bit Johnson Counter)

[0064] 7. Seventh Embodiment (Example in which a value held in a flip-flop as an inverted value of an output of a flip-flop is used as an output of a counting circuit)

[0065] 8. Eighth Embodiment (Example in which a pixel array unit of a solid-state imaging device is provided on an upper chip and a circuit array unit is provided on a lower chip)

[0066] 9. Ninth Embodiment (Example in which a Solid-State Imaging Device is Formed on One Chip)

[0067] 10. Tenth Embodiment (Example in which a light-receiving element of each pixel is provided on an upper chip and a circuit unit is provided on a lower chip)

[0068] 11. Eleventh Embodiment (Example of Distance Measuring Device Using a Counting Circuit)

[0069] 12. Application examples for mobile objects

[0070] <1. First embodiment>

[0071] Figure 1 2 is a block diagram showing a configuration example of a camera employing the imaging device according to the first embodiment.

[0072] In the drawing, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to each other via a bus 108. It should be noted that the imaging device 100 can be used alone, can be incorporated into a portable terminal (e.g., a smartphone), or can be incorporated into an authentication device or a monitoring device.

[0073] The optical system 101 allows light from a subject to enter the solid-state imaging device 102 and forms an image of the subject on a light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focusing lens, a zoom lens, a stop, etc. The optical system 101 may include a plurality of lenses such as a wide-angle lens, a standard lens, and a telephoto lens.

[0074] The solid-state imaging device 102 converts light from an object into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. The solid-state imaging device 102 may be, for example, an event-based visual sensor. The light received by the solid-state imaging device 102 may be visible light, near-infrared light (NIR), short-wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0075] The imaging control unit 103 controls imaging of the solid-state imaging device 102 based on a command from the operation unit 107. At this time, the imaging control unit 103 can control exposure conditions, imaging timing, and the like of the solid-state imaging device 102.

[0076] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing unit 104 may include an application processor that performs processing based on software.

[0077] The storage unit 105 stores captured images captured by the solid-state imaging device 102, and stores imaging parameters and the like of the solid-state imaging device 102. In addition, the storage unit 105 may store a program for operating the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0078] The display unit 106 displays a captured image and displays various types of information supporting imaging operations. The display unit 106 may be a liquid crystal display or an organic electroluminescence (EL) display.

[0079] The operation unit 107 provides a user interface for operating the imaging apparatus 100. The operation unit 107 may include, for example, buttons, dials, and switches provided in the imaging apparatus 100. The operation unit 107 may be implemented as a touch panel together with the display unit 106.

[0080] Figure 2 is a block diagram showing a configuration example of the solid-state imaging device according to the first embodiment.

[0081] In the drawing, the solid-state imaging device 102 includes a control unit 112, a pixel array unit 111, and a signal processing unit 113. These circuits may be arranged in a single semiconductor substrate, or may be arranged in a multi-layer substrate.

[0082] In the pixel array unit 111, the pixels 110 are arranged in a linear pattern in the row and column directions. The pixels 110 output the result of the pulse count generated according to the incidence of photons as pixel data. At this time, the pixels 110 may include a light receiving unit and a counting circuit. The counting circuit may be arranged below the light receiving unit. The light receiving unit may include a single photon avalanche diode (SPAD). The control unit 112 selects rows in sequence in synchronization with the vertical synchronization signal. The control unit 112 may include an arbitration circuit that arbitrates the selection of a row including pixels 110 in which an event has been detected. The signal processing unit 113 performs various types of signal processing on the image data in which the pixel data is arranged. The signal processing unit 113 may include a row scanner that scans the columns. The signal processing unit 113 may include an arbitration circuit that arbitrates the selection of a column including pixels 110 in which an event has been detected.

[0083] Figure 3 is a circuit diagram showing a configuration example of a pixel according to the first embodiment.

[0084] In the drawing, the pixel 110 includes a SPAD 121 , a quenching resistor 122 , an inverter 123 , and a counting circuit 124 .

[0085] SPAD 121 detects photons one by one. At this point, SPAD 121 can amplify current based on avalanche amplification. However, in SPAD 121, a reverse voltage higher than the breakdown voltage is set. At this point, the amplification factor of avalanche amplification is theoretically infinite. Therefore, SPAD 121 can generate a saturated output current that is independent of the number of photons incident per unit time and can detect photons one by one.

[0086] Quenching resistor 122 forcibly stops avalanche amplification of SPAD 121. Quenching resistor 122 can use the resistance component of a MOS transistor. In this case, the resistance value of quenching resistor 122 can be set based on the control signal CNT applied to the gate of the MOS transistor. A reverse voltage higher than the breakdown voltage is set for SPAD 121 via quenching resistor 122. Therefore, when a current flows through SPAD 121 due to avalanche amplification, the voltage applied to SPAD 121 decreases due to the voltage drop across quenching resistor 122, and avalanche amplification stops.

[0087] The inverter 123 generates a pulse PL based on the cathode voltage during the avalanche amplification operation of the SPAD 121 and outputs the pulse PL to the counting circuit 124 .

[0088] The counting circuit 124 counts the pulses PL output from the inverter 123. The counting circuit 124 includes a plurality of 2-bit Johnson counters, whose states change based on the transition input. In this case, the counting circuit 124 can use the second bit of the count output of the 2-bit Johnson counter at the preceding stage as the transition input of the 2-bit Johnson counter at the subsequent stage.

[0089] The pixel 110 may be formed in a multi-layer chip. In this case, the SPAD 121 may be formed in an upper chip 126 , and the quenching resistor 122 , the inverter 123 , and the counting circuit 124 may be formed in a lower chip 125 .

[0090] The lower chip 125 and the upper chip 126 can be directly bonded to each other. In this case, pad electrodes 127 and 128 can be formed in the lower chip 125 and the upper chip 126, respectively. The pad electrode 127 is connected to the quenching resistor 122 and the inverter 123. The pad electrode 128 is connected to the SPAD 121. The pad electrodes 127 and 128 can be arranged facing each other. In the direct bonding of the lower chip 125 and the upper chip 126, hybrid bonding can be used. In this case, the pad electrodes 127 and 128 can be Cu-Cu connected. The material of the semiconductor substrate used for the lower chip 125 and the upper chip 126 can be Si, InGaAs or InP.

[0091] Figure 42 is a block diagram showing an example of a configuration of a counting circuit according to the first embodiment. In the figure, 2-bit Johnson counters 201 to 203 are connected in a three-stage configuration as an example of a counting circuit, but any configuration may be employed as long as 2-bit Johnson counters are connected in n stages (n is an integer of 2 or greater).

[0092] In the drawing, the counting circuit 124 includes a plurality of 2-bit Johnson counters 201 to 203. A pulse PL is input to the 2-bit Johnson counter 201 as a transition input S, and count values ​​Q1 and Q2 are output from the 2-bit Johnson counter 201. The count value Q2 of the second bit of the 2-bit Johnson counter 201 at the preceding stage is input to the 2-bit Johnson counter 202 as a transition input S, and count values ​​Q3 and Q4 are output from the 2-bit Johnson counter 202. The count value Q4 of the second bit of the 2-bit Johnson counter 202 at the preceding stage is input to the 2-bit Johnson counter 203 as a transition input S, and count values ​​Q5 and Q6 are output from the 2-bit Johnson counter 203.

[0093] The 2-bit Johnson counter 201 includes flip-flops 211 and 221 and an inverter 291. The flip-flop 221 is connected to the subsequent stage of the flip-flop 211, and the inverter 291 is connected to the subsequent stage of the flip-flop 221. The data output Q of the flip-flop 221 is fed back to the data input D of the flip-flop 211 via the inverter 291. A pulse PL is input as a transition input S of each of the flip-flops 211 and 221.

[0094] The 2-bit Johnson counter 202 includes flip-flops 212 and 222 and an inverter 292. The flip-flop 222 is connected to the subsequent stage of the flip-flop 212, and the inverter 292 is connected to the subsequent stage of the flip-flop 222. The data output Q of the flip-flop 222 is fed back to the data input D of the flip-flop 212 via the inverter 292. The count value Q2 of the second bit of the 2-bit Johnson counter 201 at the preceding stage is input as the transition input S of each of the flip-flops 212 and 222.

[0095] The 2-bit Johnson counter 203 includes flip-flops 213 and 223 and an inverter 293. The flip-flop 223 is connected to the subsequent stage of the flip-flop 213, and the inverter 293 is connected to the subsequent stage of the flip-flop 223. The data output Q of the flip-flop 223 is fed back to the data input D of the flip-flop 213 via the inverter 293. The count value Q4 of the second bit of the 2-bit Johnson counter 202 at the preceding stage is input as the transition input S of each of the flip-flops 213 and 223.

[0096] Figure 5: is a circuit diagram showing a configuration example of a 2-bit Johnson counter according to the first embodiment. Figure 4 A configuration example of a 2-bit Johnson counter 201 in FIG.

[0097] In the drawing, the flip-flop 211 includes latch circuits 131 and 132. The latch circuit 132 is connected to the subsequent stage of the latch circuit 131. The flip-flop 221 includes latch circuits 141 and 142. The latch circuit 142 is connected to the subsequent stage of the latch circuit 141.

[0098] Latch circuit 131 includes a transmission gate 151, a NAND circuit 152, and a clocked inverter 153. A reset signal RS is input to a first input terminal of NAND circuit 152, and transmission gate 151 is connected to a second input terminal of NAND circuit 152. Clocked inverter 153 is connected in antiparallel to NAND circuit 152. Count value Q2 is input to transmission gate 151 via inverter 291. Clock CK and inverted clock CKB are input to transmission gate 151 and clocked inverter 153 as conversion inputs. Clock CK and inverted clock CKB have opposite phases. A pulse PL can be input as clock CK.

[0099] Latch circuit 132 includes a transmission gate 161, an inverter 162, and a clocked inverter 163. Transmission gate 161 is connected to the input terminal of inverter 162. Clocked inverter 163 is connected in antiparallel to inverter 162. The output of NAND circuit 152 is input to transmission gate 161. Clock CK and inverted clock CKB are input to transmission gate 161 and clocked inverter 163 as conversion inputs.

[0100] Latch circuit 141 includes a transmission gate 171, a NAND circuit 172, and a clocked inverter 173. A reset signal RS is input to a first input terminal of NAND circuit 172, and transmission gate 171 is connected to a second input terminal of NAND circuit 172. Clocked inverter 173 is connected in antiparallel to NAND circuit 172. The output of inverter 162 is input to transmission gate 171. Clock CK and an inverted clock CKB are input to transmission gate 171 and clocked inverter 173 as conversion inputs.

[0101] Latch circuit 142 includes a transmission gate 181, an inverter 182, and a clocked inverter 183. Transmission gate 181 is connected to the input terminal of inverter 182. Clocked inverter 183 is connected in antiparallel to inverter 182. The output of NAND circuit 172 is input to transmission gate 181. The output of inverter 182 is input to inverter 291. Clock CK and inverted clock CKB are input to transmission gate 181 and clocked inverter 183 as conversion inputs.

[0102] The clock CK and the inverted clock CKB input to each of the latch circuits 131 and 141 and the clock CK and the inverted clock CKB input to each of the latch circuits 132 and 142 have phases opposite to each other.

[0103] Note that transmission gates 151, 161, 171, and 181 are examples of switch circuits described in the claims. NAND circuits 152 and 172 and inverters 162 and 182 are examples of first inverter circuits described in the claims. Clocked inverters 153, 163, 173, and 183 are examples of second inverter circuits described in the claims.

[0104] Figure 6 1 is a timing chart showing the output operation of the counting circuit according to Embodiment 1. Note that the drawing shows an example in which the pulse PL is periodically input to the counting circuit 124 at 1 / 4 of the period PE of the count value Q2.

[0105] In the drawing, a pulse PL is periodically input to a 2-bit Johnson counter 201 as a transition input S at 1 / 4 of a period PE, and count values ​​Q1 and Q2 are periodically output from the 2-bit Johnson counter 201 at the period PE. At this time, the count values ​​Q1 and Q2 are output with phases shifted from each other by 1 / 4 of the period PE.

[0106] At period PE, the count value Q2 of the 2-bit Johnson counter 201 is periodically input to the 2-bit Johnson counter 202 as a transition input S, and at period 4PE, count values ​​Q3 and Q4 are periodically output from the 2-bit Johnson counter 202. At this time, the count values ​​Q3 and Q4 are output with phases shifted from each other by period PE.

[0107] The count value Q4 of the 2-bit Johnson counter 202 is periodically input to the 2-bit Johnson counter 203 as a transition input S at a period of 4PE, and the count values ​​Q5 and Q6 are periodically output from the 2-bit Johnson counter 203 at a period of 16PE. At this time, the count values ​​Q5 and Q6 are output with their phases shifted from each other by a period of 4PE.

[0108] As described above, in the first embodiment, the count value Q2 of the second bit of the two-bit Johnson counter 201 is set as the transition input of the two-bit Johnson counter 202. Furthermore, the count value Q4 of the second bit of the two-bit Johnson counter 202 is set as the transition input of the two-bit Johnson counter 203. As a result, the transition period of the two-bit Johnson counter 202 can be set to four times the transition period of the two-bit Johnson counter 201, and the transition period of the two-bit Johnson counter 203 can be set to 16 times the transition period of the two-bit Johnson counter 201. Therefore, the number of state transitions during counting by the counting circuit can be reduced, and the power consumption of the counting circuit can be reduced.

[0109] Furthermore, the number of states of connecting 2-bit Johnson counters in n stages is increased by 2 n On the other hand, the number of states of a normal (2×n)-bit Johnson counter is given by 2×n. Therefore, the number of states of a 2-bit Johnson counter connected in n stages can be made larger than the number of states of a normal (2×n)-bit Johnson counter.

[0110] The following describes variations of the counting circuit. In the following variations, a configuration example of a first-stage 2-bit Johnson counter used in the counting circuit will be described. However, in each variation, the configuration example of the first-stage 2-bit Johnson counter can also be applied to the subsequent-stage 2-bit Johnson counter.

[0111] <2. Second embodiment>

[0112] In the first embodiment described above, the second bit of the count output of the 2-bit Johnson counter at the preceding stage is used as the transition input of the 2-bit Johnson counter at the succeeding stage. In this second embodiment, in the 2-bit Johnson counter used in each stage of the counting circuit, the output of the clocked inverter of the latch circuit at the succeeding stage of the flip-flop at the succeeding stage is fed back to the flip-flop at the preceding stage.

[0113] Figure 7 is a circuit diagram showing a configuration example of a counting circuit according to Embodiment 2. It should be noted that although the drawing shows a counting circuit in which 2-bit Johnson counters are connected in two stages, conversely, the counting circuit can be configured by connecting 2-bit Johnson counters in n stages.

[0114] In the drawing, the counting circuit includes 2-bit Johnson counters 301 and 302 . The 2-bit Johnson counter 302 is connected to the subsequent stage of the 2-bit Johnson counter 301 .

[0115] The inverter 291 of the 2-bit Johnson counter 201 in the above-described first embodiment is removed from the 2-bit Johnson counter 301 . The other configuration of the 2-bit Johnson counter 301 is similar to that of the 2-bit Johnson counter 201 in the above-described first embodiment.

[0116] Here, the inverted count value QB2 of the 2-bit Johnson counter 301 is input to the transmission gate 151. The inverted count value QB2 of the 2-bit Johnson counter 301 is output from the clocked inverter 183. At this time, in the 2-bit Johnson counter 301, the value (inverted count value QB2) held in the flip-flop 221 at the subsequent stage, which is the inverted value of the output of the flip-flop 221 at the subsequent stage, is used as the input of the flip-flop 211 at the preceding stage. Furthermore, in the 2-bit Johnson counter 302, the value (inverted count value QB4) held in the flip-flop 222 at the subsequent stage, which is the inverted value of the output of the flip-flop 222 at the subsequent stage, is used as the input of the flip-flop 212 at the preceding stage.

[0117] The 2-bit Johnson counter 302 includes flip-flops 212 and 222. The flip-flop 212 includes latch circuits 231 and 232. The latch circuit 232 is connected to the subsequent stage of the latch circuit 231. The flip-flop 222 includes latch circuits 241 and 242. The latch circuit 242 is connected to the subsequent stage of the latch circuit 241.

[0118] The latch circuit 231 includes a transmission gate 251, a NAND circuit 252, and a clocked inverter 253. A reset signal RS is input to a first input terminal of the NAND circuit 252, and the transmission gate 251 is connected to a second input terminal of the NAND circuit 252. The clocked inverter 253 is connected in antiparallel to the NAND circuit 252. The count value Q4 is input to the transmission gate 251 via the inverter 283. The count value Q2 and the inverted count value QB2 are input as conversion inputs to the transmission gate 251 and the clocked inverter 253. The count value Q2 and the inverted count value QB2 have opposite phases to each other.

[0119] Latch circuit 232 includes a transmission gate 261, an inverter 262, and a clocked inverter 263. Transmission gate 261 is connected to the input terminal of inverter 262. Clocked inverter 263 is connected in antiparallel to inverter 262. The output of NAND circuit 252 is input to transmission gate 261. Count value Q2 and inverted count value QB2 are input to transmission gate 261 and clocked inverter 263 as conversion inputs.

[0120] Latch circuit 241 includes a transmission gate 271, a NAND circuit 272, and a clocked inverter 273. A reset signal RS is input to a first input terminal of NAND circuit 272, and transmission gate 271 is connected to a second input terminal of NAND circuit 272. Clocked inverter 273 is connected in antiparallel to NAND circuit 272. The output of inverter 262 is input to transmission gate 271. Count value Q2 and inverted count value QB2 are input as conversion inputs to transmission gate 271 and clocked inverter 273.

[0121] Latch circuit 242 includes a transmission gate 281, an inverter 282, and a clocked inverter 283. Transmission gate 281 is connected to the input terminal of inverter 282. Clocked inverter 283 is connected in antiparallel to inverter 282. The output of NAND circuit 272 is input to transmission gate 281. The output of inverter 282 is input to clocked inverter 283. Count value Q2 and inverted count value QB2 are input to transmission gate 281 and clocked inverter 283 as conversion inputs.

[0122] The count value Q2 and the inverted count value QB2 input to each of the latch circuits 231 and 241 and the count value Q2 and the inverted count value QB2 input to each of the latch circuits 232 and 242 have phases opposite to each other.

[0123] The counting circuit is reset based on the reset signal RS. Here, when the counting circuit performs the counting operation, the reset signal RS is set to a high level. At this time, the NAND circuits 152, 172, 252, and 272 operate as inverters.

[0124] Figure 8 1 is a timing diagram illustrating the output operation and internal state of the counting circuit according to the second embodiment. Note that q1 to q4 represent the state values ​​of the outputs of latch circuits 131, 141, 231, and 241, respectively. qb1 to qb4 are inverted state values ​​obtained by inverting the state values ​​q1 to q4.

[0125] In the accompanying drawings, in a 2-bit Johnson counter 301, transmission gates 151, 161, 171, and 181 and clocked inverters 153, 163, 173, and 183 are opened and closed according to a clock CK. At this time, when transmission gates 151 and 171 and clocked inverters 163 and 183 are closed, transmission gates 161 and 181 and clocked inverters 153 and 173 are opened. When transmission gates 161 and 181 and clocked inverters 153 and 173 are closed, transmission gates 151 and 171 and clocked inverters 163 and 183 are opened.

[0126] Here, it is assumed that the transmission gates 151 and 171 and the clocked inverters 163 and 183 are closed, and the transmission gates 161 and 181 and the clocked inverters 153 and 173 are open. At this time, data is input to the latch circuits 131 and 141 in a state where the data is latched and held in the latch circuits 132 and 142.

[0127] Next, assume that the transmission gates 161 and 181 and the clocked inverters 153 and 173 are closed, and the transmission gates 151 and 171 and the clocked inverters 163 and 183 are opened. At this time, data is input to the latch circuits 132 and 142 in a state where the data is latched and held in the latch circuits 131 and 141.

[0128] As described above, in the 2-bit Johnson counter 301, according to the cycle of the clock signal CK, the count value Q1 changes based on the state value q1, the state value q2 changes based on the count value Q1, and the count value Q2 changes based on the state value q2. In addition, the count value Q2 is fed back to the input of the 2-bit Johnson counter 301 via the clocked inverter 183, and the state value q1 changes based on the count value Q2. As a result, the 2-bit Johnson counter 301 can perform a 2-bit counting operation according to the cycle of the clock signal CK.

[0129] In the 2-bit Johnson counter 302, the transmission gates 251, 261, 271, and 281 and the clocked inverters 253, 263, 273, and 283 are opened and closed according to the count value Q2. At this time, when the transmission gates 251 and 271 and the clocked inverters 263 and 283 are closed, the transmission gates 261 and 281 and the clocked inverters 253 and 273 are opened. When the transmission gates 261 and 281 and the clocked inverters 253 and 273 are closed, the transmission gates 251 and 271 and the clocked inverters 263 and 283 are opened.

[0130] Here, when the transmission gates 251 and 271 and the clocked inverters 263 and 283 are closed, the transmission gates 261 and 281 and the clocked inverters 253 and 273 are opened. At this time, data is input to the latch circuits 231 and 241 in a state where the data is latched and held in the latch circuits 232 and 242.

[0131] Next, assuming that the transmission gates 261 and 281 and the clocked inverters 253 and 273 are closed, and the transmission gates 251 and 271 and the clocked inverters 263 and 283 are open, the data is input to the latch circuits 232 and 242 while being latched and held in the latch circuits 231 and 241.

[0132] As described above, in 2-bit Johnson counter 302, count value Q3 transitions based on state value q3, state value q4 transitions based on count value Q3, and count value Q4 transitions based on state value q4, depending on the cycle of count value Q2. Furthermore, count value Q4 is fed back to the input of 2-bit Johnson counter 302 via clocked inverter 283, and state value q3 transitions based on count value Q4. Therefore, 2-bit Johnson counter 302 can perform a count operation that is two bits higher than the count operation of 2-bit Johnson counter 301, depending on the cycle of count value Q2.

[0133] Figure 9 : is a diagram showing a comparison between the state transition of the counting circuit according to the second embodiment and the state transition in the comparative example. Note that in the drawing, the state transition of a 4-bit counter is taken as an example.

[0134] In FIG. a, the number NST of states of a normal 4-bit Johnson counter is 2×4=8. On the other hand, in FIG. b, the number NST of states of a 2-bit Johnson counter connected in two stages is 24=16. Therefore, the number of states of a 2-bit Johnson counter connected in two stages can be made larger than the number of states of a normal 4-bit Johnson counter.

[0135] As described above, in the second embodiment, the 2-bit Johnson counter 301 feeds back the output of the clock-controlled inverter 183, and the 2-bit Johnson counter 302 feeds back the output of the clock-controlled inverter 283. As a result, the inverters 291 and 292 in the first embodiment can be made unnecessary, and the circuit area can be reduced.

[0136] <3. Third embodiment>

[0137] In the above-described second embodiment, the transmission gate 151 is provided at the input of the latch circuit 131 of the 2-bit Johnson counter 301. In the third embodiment, a clocked inverter is provided at the input of the first-stage latch circuit of the 2-bit Johnson counter.

[0138] Figure 10 is a circuit diagram showing a configuration example of a counting circuit according to the third embodiment.

[0139] In the figure, the 2-bit Johnson counter 501 includes a flip-flop 511 instead of the flip-flop 211 of the 2-bit Johnson counter 301 in the second embodiment. The flip-flop 511 includes a latch circuit 531 instead of the latch circuit 131 in the second embodiment. The latch circuit 132 is connected to the subsequent stage of the latch circuit 531.

[0140] The latch circuit 531 includes a clocked inverter 583 instead of the transmission gate 151 in the second embodiment described above. The count value Q2 of the 2-bit Johnson counter 501 is input to the second input terminal of the NAND circuit 152 via the clocked inverter 583. The other configurations of the 2-bit Johnson counter 501 in the third embodiment are similar to those of the 2-bit Johnson counter 301 in the second embodiment described above.

[0141] As described above, in the third embodiment, the clocked inverter 583 is provided at the input terminal of the latch circuit 531 of the first stage of the 2-bit Johnson counter 501. As a result, data can be prevented from being rewritten through the feedback path input to the clocked inverter 583, and the stability of the operation of the counting circuit can be improved.

[0142] <4. Fourth embodiment>

[0143] In the above-described second embodiment, the output of the clocked inverter 183 is fed back to the input of the latch circuit 131 in the 2-bit Johnson counter 301. In the fourth embodiment, a capacitor is connected to the feedback path of the 2-bit Johnson counter.

[0144] Figure 11 is a circuit diagram showing a first example of a counting circuit according to the fourth embodiment.

[0145] In the accompanying drawings, this counter circuit includes a capacitor 601 in addition to the counter circuit of the second embodiment described above. Capacitor 601 is connected to the feedback path input to transmission gate 151. Capacitor 601 may be a metal capacitor in which a dielectric layer is sandwiched between metal layers. The remaining structure of the counter circuit of the fourth embodiment is the same as that of the counter circuit of the second embodiment described above.

[0146] Figure 12 is a circuit diagram showing an example of a capacitor in a feedback path of a counting circuit according to a fourth embodiment.

[0147] In this figure, a feedback path of the counting circuit is provided from the output of the clocked inverter 183 to the input of the transmission gate 151. At this time, a capacitor X is added to the feedback path. In addition, a capacitor Y is added to the output of the transmission gate 151.

[0148] Figure 13 : is a circuit diagram showing an example of potential changes in a feedback path of a counting circuit according to a fourth embodiment.

[0149] In a of the drawing, capacitor X is equivalently added to the input side of the transmission gate 151, and capacitor Y is equivalently added to the output side of the transmission gate 151. At this time, when the transmission gate 151 is closed, the input side of the transmission gate 151 is at a low level, and the output side of the transmission gate 151 is at a high level.

[0150] Here, as shown in b of the drawing, the potential on the input side of the transmission gate 151 when the transmission gate 151 is short-circuited due to the phase shift of the clock signal CK is V0. At this time, assuming that the potential on the output side of the transmission gate 151 is V1, the following relational expression is established for the potential V0 and the capacitors X and Y.

[0151] Y·V1=X·V0+Y·V0

[0152] Therefore, the potential V0 is given by the following formula.

[0153] V0=V1 / (1+X / Y)

[0154] By setting the capacitance value of the capacitor 601 according to the above equation in such a manner as to satisfy the relationship of X>Y, the potential V0 on the input side of the transfer gate 151 can be stabilized.

[0155] Figure 14 is a circuit diagram showing a second example of the counting circuit according to the fourth embodiment.

[0156] In the drawing, in this counter circuit, a gate capacitor 602 is used as the capacitor 601 of the first example of the counter circuit in the fourth embodiment described above. The other structures of the second embodiment of the counter circuit of the fourth embodiment are the same as those of the first embodiment of the counter circuit of the fourth embodiment described above.

[0157] The gate capacitor 602 may be implemented as a MOS transistor. In this case, the gate of the MOS transistor may be connected to the input side of the transmission gate 151. The source potential, drain potential, and substrate potential of the MOS transistor may be set to the ground potential.

[0158] Figure 15 is a circuit diagram showing a third example of the counting circuit according to the fourth embodiment.

[0159] In the drawing, in this counter circuit, a gate capacitor 602 is used as the capacitor 601 of the first example of the counter circuit in the fourth embodiment. The other structures of the third example of the counter circuit in the fourth embodiment are the same as those of the first example of the counter circuit in the fourth embodiment.

[0160] Gate capacitor 602 can be implemented as a MOS transistor. In this case, the source and drain of the MOS transistor can be connected to the input side of transmission gate 151. The gate potential of the MOS transistor can be set to the power supply potential VDD. The substrate potential of the MOS transistor can be set to the ground potential. As a result, the capacitance of gate capacitor 602 can be increased when the return path of the counting circuit is at a low level.

[0161] Figure 16 is a circuit diagram showing a fourth example of the counting circuit according to the fourth embodiment.

[0162] In the drawing, this counter circuit uses a variable capacitor 610 instead of the capacitor 601 of the first embodiment of the counter circuit of the fourth embodiment. The remaining structure of the fourth example of the counter circuit of the fourth embodiment is the same as that of the first example of the counter circuit of the fourth embodiment.

[0163] The variable capacitor 610 includes a plurality of capacitors 611 to 613. Switches 621 to 623 are connected in series to the capacitors 611 to 613, respectively. The series circuit of the capacitors 611 to 613 and the switches 621 to 623 can be connected in parallel to each other on the input side of the transmission gate 151. Each of the capacitors 611 to 613 can be a metal capacitor or a gate capacitor. At this time, by changing the number of switches 621 to 623 in the on state, the capacitance value of the variable capacitor 610 can be changed. Here, by changing the capacitance value of the variable capacitor 610, defect acceleration verification can be performed, through which the defect rate can be estimated by extrapolation based on the relationship between capacitance and defect rate. In the defect acceleration verification, the stability of the counting circuit can be improved while optimizing the capacitance value of the variable capacitor 610 and suppressing the reduction in the operating speed of the counting circuit.

[0164] Figure 17 1 is a plan view showing a layout example of a counter circuit according to Embodiment 4. Note that in the drawing, a layout example of the transfer gate 151, the clocked inverter 183, the capacitor 601, and wiring connected thereto is shown.

[0165] In the drawing, impurity diffusion layers D1 and D2 are formed on a semiconductor substrate 450. The impurity diffusion layers D1 and D2 are device-isolated from each other via a device isolation layer 451.

[0166] On the semiconductor substrate 450, a gate electrode G1 is provided to separate the impurity diffusion layer D1. This forms the transfer gate 151. Furthermore, on the semiconductor substrate 450, gate electrodes G2 and G3 are provided to separate the impurity diffusion layer D2. This forms the clocked inverter 183.

[0167] Furthermore, metal layers M1 to M13 are formed on semiconductor substrate 450. Metal layers M1 and M12 can be used to input clock signal CK. Metal layers M2 and M6 can be used to provide power supply voltage. Metal layer M11 can be used to provide ground potential. Metal layer M3 can serve as the output wiring for transmission gate 151. Metal layer M4 can serve as the output wiring for transmission gate 161. Metal layer M5 can be used to input reset signal RS. Metal layer M7 can serve as the input wiring for transmission gate 151. When the widths of metal layers M3 and M7 are made equal, the length of metal layer M7 can be made longer than that of metal layer M3. Therefore, capacitor 601 can be added to the feedback path in a manner that satisfies the relationship X>Y. Metal layer M8 can be used to input the inverted clock signal CKB. Metal layer M9 can serve as the output wiring for inverter 162. Metal layer M10 can serve as the output wiring for clocked inverter 173. Metal layer M13 can serve as the output wiring for inverter 182. The material of the metal layers M1 to M13 and the wiring layers H1 and H2 may be Al or Cu.

[0168] As described above, in the fourth embodiment, the capacitor 601 is connected to the feedback path of the 2-bit Johnson counter 401. As a result, data can be prevented from being rewritten via the feedback path input to the transmission gate 151, and the stability of the operation of the counting circuit can be improved.

[0169] <5. Fifth embodiment>

[0170] In the second embodiment described above, the clocked inverter 183 is provided to the latch circuit 142 of the 2-bit Johnson counter 301, and the clocked inverter 183 is connected in antiparallel to the inverter 182. In this fifth embodiment, a series circuit of a transmission gate and an inverter is provided to the latch circuit at the subsequent stage of the flip-flop at the subsequent stage of the 2-bit Johnson counter, and the series circuit is connected in antiparallel to the inverter 182.

[0171] Figure 18 is a circuit diagram showing a configuration example of a counting circuit according to a fifth embodiment.

[0172] In the figure, the 2-bit Johnson counter 701 includes a flip-flop 712 instead of the flip-flop 221 of the 2-bit Johnson counter 301 in the second embodiment. The flip-flop 712 includes a latch circuit 742 instead of the latch circuit 142 in the second embodiment. The latch circuit 742 is connected to the subsequent stage of the latch circuit 141.

[0173] The latch circuit 742 includes an inverter 783 and a transmission gate 784 instead of the clocked inverter 183 in the second embodiment. The output of the inverter 783 is connected to the input of the transmission gate 784. The series circuit of the inverter 783 and the transmission gate 784 is connected in antiparallel to the inverter 182. The other configurations of the 2-bit Johnson counter 701 in the fifth embodiment are similar to those of the 2-bit Johnson counter 301 in the second embodiment.

[0174] Figure 19 is a plan view showing a layout example of a 2-bit Johnson counter according to the fifth embodiment.

[0175] In the accompanying drawings, P-type impurity diffusion layers P11 to P13, P21 to P23, and N-type impurity diffusion layers N11 to N13, N21 to N23 are formed on a semiconductor substrate 750. The P-type impurity diffusion layers P11 to P13 are symmetrically arranged with the N-type impurity diffusion layers N11 to N13. The P-type impurity diffusion layers P21 to P23 and the N-type impurity diffusion layers N21 to N23 are arranged symmetrically with each other. The P-type impurity diffusion layers P11 to P13 and P21 to P23, and the N-type impurity diffusion layers N11 to N13 and N21 to N23 are device-isolated from each other via a device isolation layer 751.

[0176] On semiconductor substrate 750, gate electrode G11 is provided to separate P-type impurity diffusion layer P11, gate electrode G21 is provided to separate P-type impurity diffusion layer P21, and gate electrode G31 is provided to separate N-type impurity diffusion layers N11 and N21. At this point, transfer gates 151 and 171 are formed.

[0177] On semiconductor substrate 750, gate electrode G12 is provided to separate P-type impurity diffusion layer P11 from N-type impurity diffusion layer N11, and gate electrode G13 is provided to separate P-type impurity diffusion layer P11. Furthermore, gate electrode G22 is provided to separate P-type impurity diffusion layer P21 from N-type impurity diffusion layer N21, and gate electrode G23 is provided to separate P-type impurity diffusion layer P21. Furthermore, gate electrode G33 is provided to separate N-type impurity diffusion layers N11 and N21 on semiconductor substrate 750. At this point, clocked inverters 153 and 173 are formed.

[0178] Gate electrodes G14 and G15 are provided on the semiconductor substrate 750 so as to separate the P-type impurity diffusion layer P11 and the N-type impurity diffusion layer N11. At this time, the NAND circuit 172 is formed.

[0179] On the semiconductor substrate 750, gate electrodes G24 and G25 are provided so as to separate the P-type impurity diffusion layer P21 and the N-type impurity diffusion layer N21. At this time, the NAND circuit 152 is formed.

[0180] A gate electrode G16 is provided on the semiconductor substrate 750 so as to separate the P-type impurity diffusion layer P12 and the N-type impurity diffusion layer N12. At this time, the transfer gate 181 is formed.

[0181] A gate electrode G17 is provided on the semiconductor substrate 750 so as to separate the P-type impurity diffusion layer P12 and the N-type impurity diffusion layer N12. At this time, a transfer gate 784 is formed.

[0182] On the semiconductor substrate 750, the gate electrode G26 is provided to separate the P-type impurity diffusion layer P22, and the gate electrode G36 is provided to separate the N-type impurity diffusion layer N22. At this time, the transfer gate 161 is formed.

[0183] A gate electrode G18 is provided on the semiconductor substrate 750 so as to separate the P-type impurity diffusion layer P13 and the N-type impurity diffusion layer N13. In this case, an inverter 783 is formed.

[0184] A gate electrode G19 is provided on the semiconductor substrate 750 so as to separate the P-type impurity diffusion layer P13 and the N-type impurity diffusion layer N13. At this time, the inverter 182 is formed.

[0185] On semiconductor substrate 750, gate electrode G27 is provided to separate P-type impurity diffusion layer P23, gate electrode G37 is provided to separate N-type impurity diffusion layer N23, and gate electrode G28 is provided to separate N-type impurity diffusion layer N23 and P-type impurity diffusion layer P23. In this manner, clocked inverter 163 is formed.

[0186] On the semiconductor substrate 750, the gate electrode G29 is provided so as to separate the N-type impurity diffusion layer N23 and the P-type impurity diffusion layer P23. In this case, the inverter 162 is formed.

[0187] Here, a channel region is formed under each of the gate electrodes G11 to G19, G21 to G29, G33, G36, and G37. In addition, a contact 752 is formed in each of the gate electrodes G11 to G19, G21 to G29, G31, G33, G36, and G37.

[0188] The semiconductor substrate 750 may be made of Si, InGaAs, or InP. The device isolation layer 751 may be made of SiO 2 . The gate electrodes G11 to G19 , G21 to G29 , G31 , G33 , G36 , and G37 may be made of polysilicon.

[0189] As described above, in the fifth embodiment, a series circuit of a transmission gate 784 and an inverter 783 is provided to the latch circuit 742 of the 2-bit Johnson counter 701, and this series circuit is connected in antiparallel to the inverter 182. Therefore, the count value Q2 of the 2-bit Johnson counter 701 can be fed back to the input of the transmission gate 151 via the inverter 783, and the stability of the operation of the counting circuit can be improved. Furthermore, the inverter 291 in the first embodiment can be eliminated, and the circuit area can be reduced.

[0190] <6. Sixth embodiment>

[0191] In the fifth embodiment described above, a series circuit of a transmission gate 784 and an inverter 783 is provided to the latch circuit 742 of the 2-bit Johnson counter 701, and the series circuit is connected in antiparallel to the inverter 182. In this sixth embodiment, in the 2-bit Johnson counter, a series circuit of a transmission gate and an inverter is provided for a latch circuit at a subsequent stage of a flip-flop at a preceding stage and a latch circuit at a subsequent stage of a flip-flop at a subsequent stage.

[0192] Figure 20 is a circuit diagram showing a configuration example of a counting circuit according to a sixth embodiment.

[0193] In the figure, the 2-bit Johnson counter 801 includes a flip-flop 811 instead of the flip-flop 211 of the 2-bit Johnson counter 701 in the fifth embodiment. The flip-flop 811 includes a latch circuit 832 in place of the latch circuit 132 in the fifth embodiment. The latch circuit 832 is connected to the subsequent stage of the latch circuit 131.

[0194] In place of the clocked inverter 163 in the fifth embodiment described above, the latch circuit 832 includes an inverter 883 and a transmission gate 884. The output of the inverter 883 is connected to the input of the transmission gate 884. A series circuit of the inverter 883 and the transmission gate 884 is connected in antiparallel to the inverter 162. The remaining configuration of the 2-bit Johnson counter 801 in the sixth embodiment is similar to that of the 2-bit Johnson counter 701 in the fifth embodiment described above.

[0195] Figure 21 is a plan view showing a layout example of a 2-bit Johnson counter according to the sixth embodiment.

[0196] In the accompanying drawings, P-type impurity diffusion layers P41 to P43 and P51 to P53, and N-type impurity diffusion layers N41 to N43 and N51 to N53 are formed in a semiconductor substrate 850. The P-type impurity diffusion layers P41 to P43 and the N-type impurity diffusion layers N41 to N43 are arranged symmetrically with each other. The P-type impurity diffusion layers P51 to P53 and the N-type impurity diffusion layers N51 to N53 are arranged symmetrically with each other. The P-type impurity diffusion layers P41 to P43 and the P-type impurity diffusion layers P51 to P53 are arranged symmetrically with each other. The N-type impurity diffusion layers N41 to N43 and the N-type impurity diffusion layers N51 to N53 are arranged symmetrically with each other. The P-type impurity diffusion layers P41 to P43 and P51 to P53, and the N-type impurity diffusion layers N41 to N43 and N51 to N53 are device-isolated from each other via a device isolation layer 851.

[0197] On semiconductor substrate 850, gate electrode G41 is provided to separate P-type impurity diffusion layer P41, gate electrode G51 is provided to separate P-type impurity diffusion layer P51, and gate electrode G61 is provided to separate N-type impurity diffusion layers N41 and N51. At this point, transfer gates 151 and 171 are formed.

[0198] On semiconductor substrate 850, gate electrode G42 is provided to separate P-type impurity diffusion layer P41 from N-type impurity diffusion layer N41. Gate electrode G43 is provided to separate P-type impurity diffusion layer P41. Gate electrode G52 is provided to separate P-type impurity diffusion layer P51 from N-type impurity diffusion layer N51. Furthermore, gate electrode G53 is provided to separate P-type impurity diffusion layer P51, and gate electrode G63 is provided to separate N-type impurity diffusion layers N41 and N51. At this point, clocked inverters 153 and 173 are formed.

[0199] Gate electrodes G44 and G45 are provided on the semiconductor substrate 850 so as to separate the P-type impurity diffusion layer P41 and the N-type impurity diffusion layer N41. At this time, the NAND circuit 172 is formed.

[0200] Gate electrodes G54 and G55 are provided on the semiconductor substrate 850 so as to separate the P-type impurity diffusion layer P51 and the N-type impurity diffusion layer N51. At this time, the NAND circuit 152 is formed.

[0201] Gate electrodes G46 and G47 are provided on the semiconductor substrate 850 so as to separate the P-type impurity diffusion layers P42 and P52 and the N-type impurity diffusion layers N42 and N52. At this time, the transfer gates 161, 181, 784, and 884 are formed.

[0202] A gate electrode G48 is provided on the semiconductor substrate 850 so as to separate the P-type impurity diffusion layer P43 and the N-type impurity diffusion layer N43. At this time, an inverter 783 is formed.

[0203] A gate electrode G49 is provided on the semiconductor substrate 850 so as to separate the P-type impurity diffusion layer P43 and the N-type impurity diffusion layer N43. At this time, the inverter 182 is formed.

[0204] On the semiconductor substrate 850, a gate electrode G58 is provided so as to isolate the N-type impurity diffusion layer N53 from the P-type impurity diffusion layer P53. At this time, an inverter 883 is formed.

[0205] On the semiconductor substrate 850, a gate electrode G59 is provided so as to isolate the N-type impurity diffusion layer N53 from the P-type impurity diffusion layer P53. At this time, the inverter 162 is formed.

[0206] Here, a channel region is formed below the gate electrodes G41 to G49, G51 to G59, G61, and G63. In addition, a contact 852 is formed in each of the gate electrodes G41 to G49, G51 to G59, G61, and G63.

[0207] As described above, in the sixth embodiment, the series circuit of the transmission gate 884 and the inverter 883 is provided to the latch circuit 832 of the 2-bit Johnson counter 801, and the series circuit of the transmission gate 784 and the inverter 783 is provided to the latch circuit 742. Therefore, the configurations of the flip-flop 811 at the preceding stage and the flip-flop 712 at the succeeding stage of the 2-bit Johnson counter 801 can be made equal to each other, and the layout can be symmetrical.

[0208] <7. Seventh embodiment>

[0209] In the second embodiment described above, in the 2-bit Johnson counter 301 used in each stage of the counting circuit, the output of the clocked inverter 183 of the latch circuit 142 at the subsequent stage of the flip-flop 221 at the subsequent stage is fed back to the flip-flop 211 at the preceding stage. In this seventh embodiment, the value held in each flip-flop as the inverted value of the output of the flip-flop is used as the output of the counting circuit in each of the plurality of 2-bit Johnson counters.

[0210] Figure 22 is a circuit diagram showing a configuration example of a counting circuit according to a seventh embodiment.

[0211] In the figure, transmission gates 450, 451, and 452 are added to the counting circuit. The number of transmission gates 451 and 452 can be as many as the number of bits in the counting circuit. In this case, the inverted count value corresponding to each bit of the counting circuit is input to each of transmission gates 451 and 452. For example, in the 2-bit Johnson counter 301, the inverted count value Q1B is input to transmission gate 451, and the inverted count value Q2B is input to transmission gate 452.

[0212] The outputs of the transmission gates 451 and 452 are connected to the transmission gate 450, and the count value CAO of the counting circuit is output from the transmission gate 450. The other structures of the counting circuit of the seventh embodiment are the same as those of the counting circuit of the second embodiment described above.

[0213] As described above, in the seventh embodiment, the value held in each flip-flop, which is the inverted value of the flip-flop output, is used as the output of each counting circuit in the plurality of 2-bit Johnson counters. Thus, while forming a 2-bit Johnson counter using flip-flops connected in two stages, the value held in the counting circuit can be output as the count value.

[0214] <8. Eighth embodiment>

[0215] In the first embodiment described above, the second bit of the count output of the 2-bit Johnson counter at the preceding stage is used as the conversion input of the 2-bit Johnson counter at the succeeding stage. In this eighth embodiment, a pixel array unit in which light-receiving elements are arranged is provided on the upper chip, and a circuit array unit in which a circuit unit including a counting circuit configured by connecting 2-bit Johnson counters in n stages is provided on the lower chip.

[0216] Figure 23 1 is a perspective view showing an example of the layout of a solid-state imaging device according to an eighth embodiment. Note that in FIG. a, the overall configuration of the solid-state imaging device is shown. FIG. b shows an enlarged view of the pixel 922 and circuit unit 912 of the solid-state imaging device.

[0217] In FIG. a, the solid-state imaging device includes a light receiving chip 920 and a circuit chip 910. The light receiving chip 920 is stacked on the circuit chip 910. The light receiving chip 920 and the circuit chip 910 are electrically connected to each other through a connection unit such as a via. For the electrical connection between the light receiving chip 920 and the circuit chip 910, a bump can be used, or direct bonding including Cu-Cu connection can be used.

[0218] Pixel array unit 921 is formed on light receiving chip 920. Pixel array unit 921 is provided with a plurality of pixels 922. Pixels 922 can be arranged in rows and columns. In each pixel 922, as shown in b in the figure, a light receiving element 923 is formed. Light receiving element 923 can be a SPAD or a photodiode.

[0219] In addition, as shown in FIG. b, a circuit array unit 911 is formed on the circuit chip 910. The circuit array unit 911 is provided with a plurality of circuit units 912. Each circuit unit 912 can be provided for a corresponding pixel in the pixels 922. Like the arrangement of the pixels 922, the circuit units 912 can be arranged in the row direction and the column direction in marriage.

[0220] In each circuit unit 912, as shown in b in the figure, a front end 913, a distribution circuit 914, a plurality of counters 915, and a peripheral circuit 916 are formed. The front end 913 can serve as an interface with the light receiving element 923. At this time, when a SPAD is used as the light receiving element 923, the front end 913 can enable the SPAD to be quenched or recharged. In addition, the front end 913 inputs the signal detected by the light receiving element 923 to the distribution circuit 914. The distribution circuit 914 distributes the output of the pixel 922 to multiple paths.

[0221] The counter 915 counts the pulses output from the light receiving element 923. The number of counters 915 can be set to the same number as the number of paths to which the output is distributed by the distribution circuit 914. As the counter 915, any of the counting circuits according to the first to sixth embodiments described above can be used. The peripheral circuit 916 can control the operation of the pixel 922 and control the output of the count value counted by the counter 915.

[0222] As described above, in the eighth embodiment described above, the light receiving chip 920 provided with the light receiving element 923 and the circuit chip 910 provided with the counter 915 are stacked. Therefore, the area of ​​the light receiving element 923 can be increased while suppressing an increase in chip size, and the sensitivity can be improved while reducing the size of the solid-state imaging device.

[0223] <9. Ninth embodiment>

[0224] In the eighth embodiment described above, a solid-state imaging device including a counting circuit configured by connecting 2-bit Johnson counters in n stages is formed on a single chip. In the ninth embodiment, a solid-state imaging device including a counting circuit configured by connecting 2-bit Johnson counters in n stages is formed on a single chip.

[0225] Figure 24 is a perspective view showing a layout example of a solid-state imaging device according to a ninth embodiment.

[0226] In the drawing, the solid-state imaging device includes a semiconductor chip 931. A light receiving element 923, a front end 913, a distribution circuit 914, a plurality of counters 915, and a peripheral circuit 916 are formed on the semiconductor chip 931. At this time, the light receiving element 923, the front end 913, the distribution circuit 914, the plurality of counters 915, and the peripheral circuit 916 are arranged flatly.

[0227] As described above, in the ninth embodiment, the light receiving element 923 and the counter 915 are flatly provided on the semiconductor chip 931. Therefore, the semiconductor chip 931 on which the light receiving element 923 and the counter 915 are formed can be cut from the same wafer, and the manufacture of the solid-state imaging device can be made efficient.

[0228] <10. Tenth embodiment>

[0229] In the ninth embodiment, a pixel array unit including a SPAD is provided on an upper chip, and a circuit array unit including a counting circuit configured by connecting 2-bit Johnson counters in n stages is provided on a lower chip. In the tenth embodiment, a light receiving element for each pixel is provided on an upper chip, and a circuit unit is provided on a lower chip.

[0230] Figure 25 is a circuit diagram showing a configuration example of a pixel according to a tenth embodiment.

[0231] In the drawing, the solid-state imaging device includes an upper chip 954 and a lower chip 950. The upper chip 954 is stacked on the lower chip 950.

[0232] On the upper chip 954, a SPAD 955 is formed for each pixel. On the lower chip 950, a control circuit 951 and a circuit unit 952 are formed. The circuit unit 952 includes a limiter transistor 942, an inverter 943, a recharge transistor 941, and a detection circuit 953. As the limiter transistor 942 and the recharge transistor 941, for example, a P-channel metal oxide semiconductor (pMOS) transistor is used.

[0233] The anode of the SPAD 955 is connected to a predetermined potential lower than the power supply voltage VDD, and the cathode is connected to the limiter transistor 942 .

[0234] A limiter transistor 942 and a recharge transistor 941 are connected in series between a power supply voltage VDD and a cathode of the SPAD 955 , with the recharge transistor 941 on the power supply voltage VDD side. A detection node 944 is provided for connecting the limiter transistor 942 and the recharge transistor 941 .

[0235] The control signal CLIP from the control circuit 951 is input to the gate of the clipping transistor 942. The control signal XRST from the control circuit 951 is input to the gates of the recharge transistor 941 and the inverter 943. The inverter 943 inverts the control signal XRST and supplies the inverted signal to the detection circuit 953.

[0236] The detection circuit 953 detects the incidence of photons and generates a pulse signal PL. The detection circuit 953 includes a pMOS transistor 961, an n-channel MOS (nMOS) transistor 962, and inverters 963 and 964.

[0237] A pMOS transistor 961 and an nMOS transistor 962 are connected in series between the power supply voltage VDD and the ground voltage, with the pMOS transistor 961 on the power supply voltage VDD side. The gate of the pMOS transistor 961 is connected to the detection node 944, and the inverted signal from the inverter 943 is input to the gate of the nMOS transistor 962.

[0238] The inverter 963 inverts the potential of the connection node 965 between the pMOS transistor 961 and the nMOS transistor 962. The inverter 964 inverts the inverted signal from the inverter 963 and supplies the inverted signal as the pulse signal PL to the counter. A counter is provided for each pixel. The counter can be formed in the circuit unit 952. As the counter, any of the counting circuits described in the first to sixth embodiments can be used.

[0239] Furthermore, setting information for controlling the pixels is input to the control circuit 951. This setting information includes setting values ​​for the measurement period and the number of cycles. Here, the measurement period is the period during which photon incidence is measured, and the number of cycles indicates the number of times control within the measurement period is repeated. Because measurement is performed during exposure, when the setting value for the measurement period is A and the setting value for the number of cycles is a, A×a is the same value as during exposure.

[0240] During the measurement cycle, the control circuit 951 sets the control signal CLIP to a high level and then to a low level. During the period in which the control signal CLIP is at a high level during the measurement cycle (hereinafter referred to as a standby period), the detection node 944 is disconnected from the cathode of the SPAD 955. On the other hand, during the period in which the control signal CLIP is at a low level during the measurement cycle (hereinafter referred to as a connection period), the detection node 944 is connected to the SPAD 955.

[0241] When a photon is incident during the standby period, avalanche multiplication occurs in the SPAD 955, and the cathode potential drops to a certain potential. The limiter transistor 942 connects the detection node 944 to the SPAD 955 in the subsequent connection period. Therefore, when a photon is incident during the standby period, charge is transferred to the detection node 944 during the connection period, and the pulse signal PL becomes high.

[0242] Furthermore, control circuit 951 sets control signal XRST to a low level after a predetermined period of time has passed since the predetermined charging start time during the connection period. Consequently, recharge transistor 941 supplies power supply voltage VDD to detection node 944. Because detection node 944 is connected to the cathode, a recharge operation is performed to return the cathode potential to power supply voltage VDD. Furthermore, detection circuit 953 is initialized by low-level control signal XRST.

[0243] As described above, in the tenth embodiment described above, the SPAD 955 of each pixel is provided on the upper chip 954, and the circuit unit 952 is provided on the lower chip 950. Therefore, the area of ​​the SPAD 955 can be increased while suppressing an increase in chip size, and the sensitivity can be improved while reducing the size of the solid-state imaging device.

[0244] <11. Eleventh embodiment>

[0245] In the first embodiment described above, a counting circuit configured by connecting 2-bit Johnson counters in n stages is used for the solid-state imaging device. In this eleventh embodiment, a counting circuit configured by connecting 2-bit Johnson counters in n stages is used for the distance measuring device.

[0246] Figure 26 is a block diagram showing a configuration example of a distance measuring device according to an eleventh embodiment.

[0247] In the drawings, the distance measuring device 1000 captures a distance image based on, for example, time of flight (ToF). The distance image may be generated from a distance pixel signal based on the distance from the distance measuring device 1000 to each pixel in the depth direction of the object 1001.

[0248] The distance measuring device 1000 includes a light emitting device 1100 and an imaging device 1200. The light emitting device 1100 has a light emitting control unit 1101 and a light emitting unit 1102.

[0249] The light emitting control unit 1101 controls the light radiation pattern of the light emitting unit 1102 under the control of the control unit 1202. The light emitting unit 1102 emits light within a predetermined wavelength range under the control of the light emitting control unit 1101. The predetermined wavelength range may be an infrared range. The light emitting unit 1102 may be a laser diode or a light emitting diode.

[0250] The imaging device 1200 receives reflected light for each pixel, which is light radiated from the light emitting device 1100 and reflected from the object 1001, and generates a distance image. The imaging device 1200 includes an imaging unit 1201, a control unit 1202, a storage unit 1203, and a display unit 1204. The imaging unit 1201 includes an optical system 1211, a light receiving unit 1221, and a signal processing unit 1231.

[0251] The optical system 1211 forms an image of incident light on a light receiving surface of the light receiving unit 1221. Note that the optical system 1211 may include a lens, a filter, an aperture, and the like.

[0252] The light receiving unit 1221 receives reflected light reflected by the subject 1001. The light receiving unit 1221 can be a SPAD or a photodiode. Under the control of the control unit 1202, the light receiving unit 1221 receives the reflected light from the object 1001 and provides the generated pixel signal to the signal processing unit 1231. The pixel signal represents a digital count value obtained by counting the time from the time the light emitting device 1100 irradiates the radiation light to the time the light receiving unit 1221 receives the radiation light. A light emission timing signal indicating the timing at which the light emitting unit 1102 emits light is also provided from the control unit 1202 to the light receiving unit 1221. As a counting circuit that counts the time until the light receiving unit 1221 receives light, any counting circuit according to the first to sixth embodiments described above can be used.

[0253] Under the control of control unit 1202, signal processing unit 1231 processes the pixel signal provided by light receiving unit 1221. For example, based on the pixel signal provided by light receiving unit 1221, signal processing unit 1231 detects the distance from each pixel to the object and generates a distance image indicating the distance from each pixel to the object. For example, signal processing unit 1231 obtains the time from the time when light emitting unit 1102 emits light to the time when each pixel of light receiving unit 1221 receives light multiple times. Signal processing unit 1231 creates a histogram corresponding to the obtained time. Then, by detecting the peak of the histogram, signal processing unit 1231 determines the time until the light emitted from light emitting unit 1102 reflects from object 1001 and returns. Furthermore, signal processing unit 1231 performs calculations based on the determined time and the speed of light to obtain the distance to the object. Signal processing unit 1231 provides the generated distance image to control unit 1202.

[0254] The control unit 1202 controls the light emitting control unit 1101 and the light receiving unit 1221. For example, the control unit 1202 provides a radiation signal to the light emitting control unit 1101 and provides a light emitting timing signal to the light receiving unit 1221. The light emitting unit 1102 emits radiation light according to the radiation signal. The light emitting timing signal can be a radiation signal provided to the light emitting control unit 1101. In addition, the control unit 1202 provides the distance image obtained from the imaging unit 1201 to the display unit 1204 and causes the display unit 1204 to display the distance image. In addition, the control unit 1202 stores the distance image obtained from the imaging unit 1201 in the storage unit 1203. The control unit 1202 may include a processor such as a central processing unit (CPU) or a graphics processing unit (GPU). In addition, the control unit 1202 may include a hardware circuit such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

[0255] Display unit 1204 displays a distance image, a user interface screen, and the like. Display unit 1204 may be a liquid crystal display device or an organic EL display device. Storage unit 1203 stores a distance image, setting information for distance measurement, and the like. Storage unit 1203 may include a semiconductor memory such as static random access memory (SRAM) or dynamic random access memory (DRAM), or may include a storage device such as a hard disk device or a solid-state drive (SSD).

[0256] As described above, in the above-described eleventh embodiment, the counting circuit configured by connecting 2-bit Johnson counters in n stages is used for the distance measuring device 1000. Therefore, the power consumption of the counting operation at the time of distance measurement can be reduced.

[0257] <12. Application Examples of Mobile Objects>

[0258] The technology according to the present disclosure (the present technology) can be applied to various types of products. For example, the technology according to the present disclosure can also be implemented as a device installed on any type of mobile body (such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, an unmanned aerial vehicle, a ship, and a robot).

[0259] Figure 27 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0260] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 27 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated as the functional configuration of the integrated control unit 12050.

[0261] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating the vehicle's drive force, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, a braking device for generating the vehicle's braking force, and the like.

[0262] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as the headlights, backup lights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a mobile device serving as a key substitute or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0263] The vehicle exterior information detection unit 12030 detects information outside the vehicle, including information about the vehicle control system 12000. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receives the captured image. Furthermore, the vehicle exterior information detection unit 12030 can also detect objects such as people, vehicles, obstacles, signs, and text on the road, or detect their distance based on the received image.

[0264] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output the electrical signal as an image or as information about the measured distance. The light received by imaging unit 12031 can be visible light or invisible light such as infrared light.

[0265] The in-vehicle information detection unit 12040 detects information about the vehicle interior. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's condition. For example, the driver state detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or determine whether the driver is dozing off.

[0266] The microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or shock absorption for the vehicle, follow-up driving based on a following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from a lane, and the like.

[0267] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generation device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, which enables the vehicle to travel automatically without relying on the driver's operation, etc.

[0268] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the vehicle exterior information acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights to switch from high beam to low beam based on the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030, thereby performing cooperative control to prevent glare.

[0269] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Figure 27 In the example of FIG, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0270] Figure 28 is a diagram showing an example of the installation position of the imaging unit 12031.

[0271] exist Figure 28 , imaging unit 12031 includes imaging units 12101 , 12102 , 12103 , 12104 and 12105 .

[0272] Imaging units 12101, 12102, 12103, 12104, and 12105 are disposed, for example, at locations within the interior of vehicle 12100, such as the front nose, side-view mirrors, rear bumper, rear door, and the upper portion of the windshield. Imaging unit 12101 disposed within the vehicle's front nose and imaging unit 12105 disposed within the upper portion of the windshield primarily capture images of the front of vehicle 12100. Imaging units 12102 and 12103 disposed within the side-view mirrors primarily capture images of the sides of vehicle 12100. Imaging unit 12104 disposed within the rear bumper or rear door primarily captures images of the rear of vehicle 12100. Imaging unit 12105 disposed within the upper portion of the windshield primarily detects vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0273] By the way, Figure 28The following describes examples of imaging ranges for imaging units 12101 through 12104. Imaging range 12111 represents the imaging range of imaging unit 12101, which is located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located on the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, which is located on the rear bumper or rear door. For example, a bird's-eye view image of vehicle 12100 viewed from above can be obtained by superimposing image data captured by imaging units 12101 through 12104.

[0274] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0275] For example, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111 to 12114 and the temporal change in that distance (relative speed to vehicle 12100) based on the distance information obtained from imaging units 12101 to 12104. This can then extract objects that are on the path of vehicle 12100 and traveling in a direction substantially similar to vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, microcomputer 12051 can pre-set a following distance to maintain a position ahead of the preceding vehicle and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), and the like. This enables coordinated control for autonomous driving, enabling the vehicle to travel autonomously without relying on driver input or other operations.

[0276] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can classify 3D object data related to 3D objects into 3D object data for two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other 3D objects, extract the classified 3D object data, and use the extracted 3D object data for automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as those that are visually recognizable by the driver of vehicle 12100 and those that are difficult for the driver of vehicle 12100 to visually recognize. Microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and therefore a collision possibility exists, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering via drive system control unit 12010. Microcomputer 12051 can thus assist driving to avoid collisions.

[0277] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. Microcomputer 12051 can, for example, identify pedestrians by determining whether a pedestrian exists in images captured by imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from images captured by imaging units 12101 to 12104, which function as infrared cameras, and performing pattern matching on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. When microcomputer 12051 determines that a pedestrian exists in the images captured by imaging units 12101 to 12104 and identifies the pedestrian, audio / video output unit 12052 controls display unit 12062 to display a square outline for emphasis superimposed on the identified pedestrian. Audio / video output unit 12052 can also control display unit 12062 to display an icon representing the pedestrian at a desired location.

[0278] An example of a vehicle control system to which the technology of the present disclosure can be applied has been described above. The technology of the present disclosure can be applied to imaging unit 12031 among the aforementioned components. Specifically, for example, the aforementioned solid-state imaging device can be applied to imaging unit 12031. By applying the technology of the present disclosure to vehicle control system 12000, power consumption can be reduced.

[0279] It should be noted that the above-mentioned embodiments illustrate examples for embodying the present technology, and the matters in the embodiments and the matters specifying the present invention in the claims have a corresponding relationship. Similarly, the corresponding matters specifying the present invention in the claims have a corresponding relationship with the corresponding matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be implemented by making various modifications to the embodiments without departing from the scope of the present technology. In addition, the effects described in this specification are merely examples and are not limited, and other effects can be provided.

[0280] It should be noted that the present technology can also have the following configurations.

[0281] (1) A photoelectric detection device comprising:

[0282] Light receiving units arranged in a matrix in row and column directions and outputting pulses generated according to incidence of photons; and

[0283] The counting circuit counts the pulses output from the light receiving unit, wherein

[0284] The counting circuit includes:

[0285] Multiple 2-bit Johnson counters with state changes based on transition inputs, and

[0286] The second bit of the count output of the 2-bit Johnson counter at the preceding stage is used as a conversion input of the 2-bit Johnson counter at the succeeding stage.

[0287] (2) The photodetection device according to (1), wherein

[0288] The 2-bit Johnson counters each include flip-flops connected in two stages, and

[0289] In each of the plurality of 2-bit Johnson counters, an inverted value of an output of a flip-flop at a subsequent stage is used as an input of a flip-flop at a preceding stage.

[0290] (3) The photoelectric detection device according to (2), further comprising:

[0291] An inverter is connected between the output of the flip-flop at the subsequent stage and the input of the flip-flop at the preceding stage.

[0292] (4) The photodetection device according to (1), wherein

[0293] The 2-bit Johnson counters each include flip-flops connected in two stages, and

[0294] In each of the plurality of 2-bit Johnson counters, a value held in a flip-flop at a subsequent stage as an inverted value of an output of the flip-flop at a subsequent stage is used as an input of a flip-flop at a preceding stage.

[0295] (5) The photodetection device according to (4), wherein

[0296] In each of multiple 2-bit Johnson counters, a value held in a flip-flop at a preceding stage as an inverted value of the output of the flip-flop at a preceding stage and a value held in a flip-flop at a succeeding stage as an inverted value of the output of the flip-flop at a succeeding stage are used as outputs of a counting circuit.

[0297] (6) The photodetection device according to (4) or (5), wherein

[0298] The triggers at the front end include:

[0299] a first latch circuit, and

[0300] The second latch circuit is connected to the subsequent stage of the first latch circuit, and

[0301] The triggers at the back end include:

[0302] a third latch circuit, and

[0303] The fourth latch circuit is connected to a subsequent stage of the third latch circuit.

[0304] (7) The photodetection device according to (6), wherein

[0305] The first latch circuit comprises:

[0306] The first inverting circuit inverts the input.

[0307] a second inverting circuit connected in antiparallel to the first inverting circuit and inverting the input based on the transition input; and

[0308] a first switch circuit connected at a preceding stage of the first inverter circuit and opening and closing based on a transition input,

[0309] The second latch circuit comprises:

[0310] The third inverting circuit inverts the input.

[0311] a fourth inverting circuit connected in antiparallel to the third inverting circuit and inverting the input based on the transition input, and

[0312] a second switch circuit connected at a preceding stage of the third inverter circuit and opening and closing based on a transition input,

[0313] The third latch circuit comprises:

[0314] The fifth inverting circuit inverts the input.

[0315] a sixth inverter circuit connected in antiparallel to the fifth inverter circuit and inverting the input based on the transition input, and

[0316] a third switch circuit connected at a preceding stage of the fifth inverter circuit and opening and closing based on a transition input, and

[0317] The fourth latch circuit comprises:

[0318] The seventh inverting circuit inverts the input.

[0319] an eighth inverter circuit connected in antiparallel to the seventh inverter circuit and inverting the input based on the transition input, and

[0320] and a fourth switch circuit connected at a preceding stage of the seventh inverter circuit and opening and closing based on a transition input.

[0321] (8) The photodetection device according to (7), wherein

[0322] The first phaser circuit and the fifth inverter circuit are NAND circuits to which reset signals are input.

[0323] Each of the third phaser circuit and the seventh inverter circuit is an inverter,

[0324] Each of the second inverter circuit, the fourth inverter circuit, the sixth inverter circuit, and the eighth inverter circuit is a clocked inverter, and

[0325] Each of the first to fourth switching circuits is a transmission gate.

[0326] (9) The photoelectric detection device according to (8), further comprising:

[0327] A capacitor is connected to the input terminal of the trigger at the previous stage.

[0328] (10) The photoelectric detection device according to (9), wherein

[0329] The capacitance value of the capacitor is larger than the capacitance value of the capacitor added to the output of the first switching circuit.

[0330] (11) The photodetection device according to (9) or (10), wherein

[0331] The capacitor is a metal capacitor, a gate capacitor whose gate is connected to the input terminal of a flip-flop at a previous stage, or a gate capacitor whose source / drain is connected to the input terminal of a flip-flop at a previous stage.

[0332] (12) The photodetection device according to any one of (9) to (11), wherein

[0333] The capacitor is a variable capacitor whose capacitance value can be changed.

[0334] (13) The photodetection device according to (7), wherein

[0335] The first inverter circuit and the fifth inverter circuit are both NAND circuits to which a reset signal is input.

[0336] Each of the third and seventh inverter circuits is an inverter,

[0337] Each of the first switching circuit and the second inverter circuit, the fourth inverter circuit, the sixth inverter circuit, and the eighth inverter circuit is a clocked inverter, and

[0338] Each of the second to fourth switch circuits is a transmission gate.

[0339] (14) The photodetection device according to (7), wherein

[0340] The first inverter circuit and the fifth inverter circuit are both NAND circuits to which a reset signal is input.

[0341] Each of the third inverter circuit and the seventh inverter circuit is an inverter,

[0342] Each of the second inverter circuit, the fourth inverter circuit, and the sixth inverter circuit is a clocked inverter,

[0343] The eighth inverter circuit is a series circuit of an inverter and a transmission gate, and

[0344] Each of the first to fourth switching circuits is a transmission gate.

[0345] (15) The photodetection device according to (7), wherein

[0346] The first inverter circuit and the fifth inverter circuit are both NAND circuits to which a reset signal is input.

[0347] Each of the third inverter circuit and the seventh inverter circuit is an inverter,

[0348] Each of the second inverter circuit and the sixth inverter circuit is a clocked inverter,

[0349] Each of the fourth inverter circuit and the eighth inverter circuit is a series circuit of an inverter and a transmission gate, and

[0350] Each of the first to fourth switching circuits is a transmission gate.

[0351] (16) The photodetection device according to any one of (1) to (15), wherein

[0352] The transition input of the flip-flop at the preceding stage and the transition input of the flip-flop at the succeeding stage have opposite phases to each other.

[0353] (17) The photodetection device according to any one of (1) to (16), wherein

[0354] The pulse generated by the incidence of photons is input to the first stage of a 2-bit Johnson counter.

[0355] (18) The photodetection device according to any one of (1) to (17), wherein

[0356] The number of states is given as 4 n , where n is the number of stages of the 2-bit Johnson counter.

[0357] (19) The photodetection device according to any one of (1) to (18), wherein

[0358] The counting circuit is provided below the light receiving unit.

[0359] (20) A counting circuit comprising:

[0360] Multiple 2-bit Johnson counters whose states change based on the transition inputs, where

[0361] The second bit of the count output of the 2-bit Johnson counter at the preceding stage is used as a conversion input of the 2-bit Johnson counter at the succeeding stage.

[0362] (21) A photoelectric detection device comprising:

[0363] Light-emitting element;

[0364] a light receiving element that outputs a pulse generated in response to incident photons; and

[0365] The counting circuit counts the pulses output from the light receiving element, wherein

[0366] The counting circuit includes:

[0367] Multiple 2-bit Johnson counters with state changes based on transition inputs, and

[0368] The second bit of the count output of the 2-bit Johnson counter at the preceding stage is used as a conversion input of the 2-bit Johnson counter at the succeeding stage.

[0369] (22) The photodetection device according to any one of (1) to (19), wherein

[0370] The state transition period of the 2-bit Johnson counter at the subsequent stage is four times the state transition period of the 2-bit Johnson counter at the preceding stage.

[0371] (23) The photodetection device according to any one of (1) to (19), wherein

[0372] The light receiving unit includes a single photon avalanche diode (SPAD).

[0373] Reference Symbol List

[0374] 100 Imaging Device

[0375] 101 Optical System

[0376] 102 Solid-state imaging device

[0377] 103 Imaging Control Unit

[0378] 104 Image Processing Unit

[0379] 105 storage unit

[0380] 106 display units

[0381] 107 operating unit

[0382] 108 bus

[0383] 110 pixels

[0384] 111 pixel array unit

[0385] 112 control unit

[0386] 113 Signal Processing Unit

[0387] 121 SPAD

[0388] 122 Quenching resistor

[0389] 123 Inverter

[0390] 124 Counting Circuit

[0391] 125 lower chip

[0392] 126 upper chip

[0393] 127,128 Pad electrodes

[0394] 131, 132, 141, 142 latch circuits

[0395] 201 to 203 2-digit Johnson counter

[0396] 211, 221, 212, 222, 213, 223 triggers

[0397] 162, 182, 262, 282 inverters

[0398] 151, 161, 171, 181, 251, 261, 271, 281 transmission gates

[0399] 153, 163, 173, 183, 253, 263, 273, 283 Clocked Inverters

[0400] 152, 172, 252, 272 NAND circuits.

Claims

1. A photoelectric detection device comprising: Light receiving units arranged in a matrix in row and column directions and outputting pulses generated according to incidence of photons; as well as a counting circuit for counting the pulses output from the light receiving unit, wherein The counting circuit comprises: A plurality of 2-bit Johnson counters have their states transitioned based on a transition input, and the second bit of a count output of a 2-bit Johnson counter at a preceding stage is used as a transition input of a 2-bit Johnson counter at a succeeding stage.

2. The photoelectric detection device according to claim 1, wherein The 2-bit Johnson counters each include flip-flops connected in two stages, and in each of the plurality of the 2-bit Johnson counters, an inverted value of an output of a flip-flop at a subsequent stage is used as an input of a flip-flop at a preceding stage.

3. The photoelectric detection device according to claim 2, further comprising: An inverter is connected between the output of the flip-flop at the subsequent stage and the input of the flip-flop at the preceding stage.

4. The photoelectric detection device according to claim 1, wherein The 2-bit Johnson counters each include flip-flops connected in two stages, and in each of the plurality of 2-bit Johnson counters, a value held in a flip-flop at a subsequent stage as an inverted value of an output of the flip-flop at the subsequent stage is used as an input to a flip-flop at a preceding stage.

5. The photoelectric detection device according to claim 4, wherein: In each of the plurality of 2-bit Johnson counters, a value held in the flip-flop at the preceding stage as an inverted value of the output of the flip-flop at the preceding stage and a value held in the flip-flop at the succeeding stage as an inverted value of the output of the flip-flop at the succeeding stage are used as outputs of the counting circuit.

6. The photoelectric detection device according to claim 4, wherein: The trigger at the front stage includes: a first latch circuit, and A second latch circuit is connected at a subsequent stage of the first latch circuit, and the trigger at the subsequent stage includes: a third latch circuit, and The fourth latch circuit is connected to the subsequent stage of the third latch circuit.

7. The photodetection device according to claim 6, wherein: The first latch circuit comprises: The first inverting circuit inverts the input. a second inverting circuit connected in antiparallel to the first inverting circuit and inverting an input based on the transition input; and a first switch circuit connected at a preceding stage of the first inverter circuit and opening and closing based on the transition input, The second latch circuit includes: The third inverting circuit inverts the input. a fourth inverting circuit connected in antiparallel to the third inverting circuit and inverting an input based on the transition input, and a second switch circuit connected at a preceding stage of the third inverter circuit and opening and closing based on the transition input, The third latch circuit includes: The fifth inverting circuit inverts the input. a sixth inverter circuit connected in antiparallel to the fifth inverter circuit and inverting an input based on the transition input, and a third switch circuit connected at a preceding stage of the fifth inverter circuit and opening and closing based on the transition input, and The fourth latch circuit includes: The seventh inverting circuit inverts the input. an eighth inverter circuit connected in antiparallel to the seventh inverter circuit and inverting an input based on the transition input, and A fourth switch circuit is connected at a preceding stage of the seventh inverter circuit and is opened and closed based on the transition input.

8. The photodetection device according to claim 7, wherein: The first inverter circuit and the fifth inverter circuit are NAND circuits to which a reset signal is input. Each of the third inverter circuit and the seventh inverter circuit is an inverter, each of the second inverter circuit, the fourth inverter circuit, the sixth inverter circuit, and the eighth inverter circuit is a clocked inverter, and Each of the first to fourth switching circuits is a transmission gate.

9. The photoelectric detection device according to claim 8, further comprising: A capacitor is connected to the input terminal of the trigger at the previous stage.

10. The photoelectric detection device according to claim 9, wherein The capacitance value of the capacitor is larger than the capacitance value of a capacitor added to the output of the first switching circuit.

11. The photoelectric detection device according to claim 9, wherein The capacitor is a metal capacitor, a gate capacitor whose gate is connected to the input terminal of the flip-flop at the previous stage, or a gate capacitor whose source / drain is connected to the input terminal of the flip-flop at the previous stage.

12. The photoelectric detection device according to claim 9, wherein The capacitor is a variable capacitor whose capacitance value can be changed.

13. The photoelectric detection device according to claim 7, wherein: The first inverter circuit and the fifth inverter circuit are both NAND circuits to which a reset signal is input. Each of the third inverter circuit and the seventh inverter circuit is an inverter, each of the first switch circuit, the second inverter circuit, the fourth inverter circuit, the sixth inverter circuit, and the eighth inverter circuit is a clocked inverter, and Each of the second to fourth switching circuits is a transmission gate.

14. The photoelectric detection device according to claim 7, wherein: Each of the first inverter circuit and the fifth inverter circuit is a NAND circuit to which a reset signal is input. Each of the third inverter circuit and the seventh inverter circuit is an inverter, Each of the second inverter circuit, the fourth inverter circuit, and the sixth inverter circuit is a clocked inverter, The eighth inverter circuit is a series circuit of an inverter and a transmission gate, and Each of the first to fourth switching circuits is a transmission gate.

15. The photoelectric detection device according to claim 7, wherein The first inverter circuit and the fifth inverter circuit are NAND circuits to which a reset signal is input. Each of the third inverter circuit and the seventh inverter circuit is an inverter, Each of the second inverter circuit and the sixth inverter circuit is a clocked inverter, Each of the fourth inverter circuit and the eighth inverter circuit is a series circuit of an inverter and a transmission gate, and Each of the first to fourth switching circuits is a transmission gate.

16. The photoelectric detection device according to claim 2, wherein: The transition input of the flip-flop at the preceding stage and the transition input of the flip-flop at the succeeding stage have opposite phases to each other.

17. The photoelectric detection device according to claim 1, wherein A pulse generated by the incidence of the photon is input to the first stage of the 2-bit Johnson counter.

18. The photoelectric detection device according to claim 1, wherein The number of states is given as 4 n , where n is the number of stages of the 2-bit Johnson counter.

19. The photoelectric detection device according to claim 1, wherein The counting circuit is provided below the light receiving unit.

20. A counting circuit comprising: Multiple 2-bit Johnson counters with state changes based on the transition input, where The second bit of the count output of the 2-bit Johnson counter at the preceding stage is used as a conversion input of the 2-bit Johnson counter at the succeeding stage.

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