Semiconductor light-emitting element and method for manufacturing semiconductor light-emitting element

Abstract

The invention provides a semiconductor light-emitting element and a method for manufacturing the semiconductor light-emitting element, which can efficiently separate hydrogen from a p-type semiconductor layer. The semiconductor light-emitting element is characterized by being provided with: a growth substrate (11); a plurality of columnar semiconductor layers including an n-type core layer (15) provided upright in the vertical direction with respect to the main surface of the growth substrate (11), and an active layer (16) disposed on the outer periphery of the n-type core layer (15); a plurality of p-type semiconductor layers (17) disposed on the outer periphery of the columnar semiconductor layer and connected to each other to be integrated; and a removal region formed by removing a portion of the integrated plurality of p-type semiconductor layers (17).

Description

Technical Field

[0001] The present invention relates to a semiconductor light emitting element and a method for manufacturing the semiconductor light emitting element. Background Art

[0002] Semiconductor light-emitting devices emit light through the recombination of holes and electrons in the active layer. Traditionally, flat, thin well layers have been used as active layers. In contrast, recent development has seen significant growth in semiconductor light-emitting devices with three-dimensional nanostructures. Patent Document 1 discloses an example of a semiconductor light-emitting device with such a structure.

[0003] The main body of the semiconductor light emitting element disclosed in Patent Document 1 is formed of a thin wire structure called a nanowire. Figure 8 FIG. 5 is a diagram showing a conventional semiconductor light emitting element 50 that is a simplified representation of the semiconductor light emitting element of Patent Document 1. Figure 8 (a) represents a longitudinal section view, Figure 8 (b) shows the cross-sectional view. Figure 8 As shown in (a), a semiconductor light-emitting element 50 includes a growth substrate 51, a base layer 52, a mask 53, an n-type core layer 54 grown in a hexagonal prism shape, an active layer (light-emitting layer) 55 formed around the n-type core layer 54, a p-type semiconductor layer 56 formed around the active layer 55, a tunnel junction layer 57 formed around the p-type semiconductor layer 56, and a buried semiconductor layer 58. The portion consisting of the n-type core layer 54, the active layer 55, the p-type semiconductor layer 56, and the tunnel junction layer 57 is generally referred to as a nanowire. The buried semiconductor layer 58 buries the nanowire. This structure enables uniform current injection into the light-emitting layer. Furthermore, multiple nanowires are connected by the buried semiconductor layer 58 to ensure strength.

[0004] Here, the p-type semiconductor layer 56 and the p+ layer of the tunnel junction layer 57 (hereinafter sometimes collectively referred to as the "p-type semiconductor layer") of the semiconductor light-emitting element 50 need to be activated by desorbing hydrogen. Mg (magnesium), a dopant contained in the p-type semiconductor layer, is inactivated by hydrogen passivation. Therefore, heat treatment is required to desorb hydrogen and activate the Mg. To this end, the p-type semiconductor layer is exposed midway through the process and annealed. However, the p-type semiconductor layer is covered by the n-type buried semiconductor layer 58 and the n+ layer of the tunnel junction layer 57, so hydrogen cannot be effectively desorbed, and therefore sufficient activation cannot be achieved. If activation is insufficient, the layer becomes highly resistive, and the device efficiency of the semiconductor light-emitting element 50 is reduced. In this regard, in the semiconductor light-emitting element of Patent Document 1, a removal region is provided at the top of the semiconductor light-emitting element to expose the p-type semiconductor layer, and hydrogen is desorbed from this removal region. Prior art literature Patent Literature

[0005] Patent Document 1: Japanese Patent Publication No. 2022-040676 Summary of the Invention Problems to be solved by the invention

[0006] As described above, in the semiconductor light-emitting element and its manufacturing method disclosed in Patent Document 1, the upper portion of the p-type semiconductor layer is exposed and annealed. In this case, since the nanowires are independent, the upper portion of the p-type semiconductor layer of all nanowires must be exposed. In this method, hydrogen is desorbed from the upper portion. However, due to the small exposed area of ​​the nanowire structure, the annealing process tends to be prolonged in order to fully activate the lower portion of the nanowire structure.

[0007] Therefore, the present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor light emitting element capable of efficiently desorbing hydrogen from a p-type semiconductor layer and a method for manufacturing the semiconductor light emitting element. Means for solving problems

[0008] In order to solve the above-mentioned problems, the semiconductor light-emitting element of the present invention is characterized in that it comprises: a growth substrate; a plurality of columnar semiconductor layers, including an n-type core layer upright in a direction perpendicular to the main surface of the growth substrate, and an active layer arranged at the periphery of the n-type core layer; a plurality of p-type semiconductor layers arranged at the periphery of the columnar semiconductor layer, connected to each other and integrated; and a removal area, which is formed by removing a portion of the integrated plurality of p-type semiconductor layers.

[0009] In such a semiconductor light emitting element of the present invention, a removal region is provided in which a portion of a plurality of p-type semiconductor layers arranged on the periphery of the columnar semiconductor layer and connected to each other and integrated is removed, thereby enabling efficient desorption of hydrogen from the p-type semiconductor layer.

[0010] Furthermore, in one embodiment of the present invention, each of the plurality of p-type semiconductor layers forms a cone extending downward in the vertical direction, and the plurality of p-type semiconductor layers are connected to each other at a lower portion of the cone.

[0011] In addition, in one embodiment of the present invention, it is characterized in that it further comprises: a base layer formed on the growth substrate and continuous with the n-type core layer; and an opening portion surrounded by a connection portion connecting the p-type semiconductor layers to each other, and the p-type semiconductor layer is not configured in the opening portion.

[0012] In addition, in one embodiment of the present invention, it is characterized in that it also has an embedded semiconductor layer, which is arranged on the periphery of the p-type semiconductor layer, and in the removal area, the layer from the upper surface of the embedded semiconductor layer to the base layer is removed, exposing the end face of the p-type semiconductor layer from the removal area.

[0013] In one embodiment of the present invention, a tunnel junction layer is further provided, the tunnel junction layer being arranged between the p-type semiconductor layer and the buried semiconductor layer, and an end face of the tunnel junction layer is exposed from the removed region.

[0014] In order to solve the above-mentioned problems, the manufacturing method of the semiconductor light-emitting element of the present invention is characterized in that it includes: a mask forming process, forming a mask having a plurality of openings on a growth substrate; a columnar semiconductor layer forming process, using selective growth to form an n-type core layer in the openings, and forming an active layer on the periphery of the n-type core layer, thereby forming a columnar semiconductor layer; a p-type semiconductor layer forming process, forming a p-type semiconductor layer on the periphery of the columnar semiconductor layer; a buried semiconductor layer forming process, forming a buried semiconductor layer on the growth substrate in a manner of burying the p-type semiconductor layer; a removal area forming process, removing a portion of the p-type semiconductor layer and a portion of the buried semiconductor layer to expose the p-type semiconductor layer; and an activation process, annealing the entirety to activate the p-type semiconductor layer.

[0015] In addition, one embodiment of the present invention is characterized in that it also includes a tunnel junction layer forming process, in which a tunnel junction layer is formed on the periphery of the p-type semiconductor layer, the buried semiconductor layer is formed in a manner of burying the tunnel junction layer, the tunnel junction layer is further exposed in the removal area forming process, and the tunnel junction layer is further activated in the activation process. Effects of the Invention

[0016] The present invention can provide a semiconductor light emitting element capable of efficiently desorbing hydrogen from a p-type semiconductor layer and a method for manufacturing the semiconductor light emitting element. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 These are diagrams of a semiconductor light emitting element according to a first embodiment, wherein (a) is a plan view and (b) is a longitudinal sectional view. Figure 2 These are diagrams of a semiconductor light emitting element according to a first embodiment, wherein (a) is a plan view, (b) is a longitudinal sectional view, (c) is a transverse sectional view, and (d) is a longitudinal sectional view. Figure 3It is a longitudinal cross-sectional view of the method for manufacturing a semiconductor light-emitting element according to the first embodiment, wherein (a) represents a base layer forming step, (b) represents a mask forming step, (c) represents an opening forming step, (d) represents a columnar semiconductor layer forming step, and (e) represents a p-type semiconductor layer / tunnel junction layer forming step. Figure 4 These are longitudinal cross-sectional views of a method for manufacturing a semiconductor light emitting element according to a first embodiment, wherein (a) shows a buried semiconductor layer forming step, (b) shows a removal region forming / activation step, and (c) shows an electrode forming step. Figure 5 It is a top view showing the wafer according to the first embodiment. Figure 6 These are diagrams showing SEM images of a p-type semiconductor layer of the semiconductor light emitting element according to the first embodiment, (a) being a plan view and (b) being a perspective view. Figure 7 These are diagrams of a semiconductor light emitting element according to a second embodiment, wherein (a) is a plan view, (b) is a longitudinal sectional view, (c) is a transverse sectional view, and (d) is a longitudinal sectional view. Figure 8 1 and 2 are diagrams of a conventional semiconductor light emitting element, wherein (a) is a longitudinal sectional view and (b) is a transverse sectional view. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Identical or equivalent components, parts, and processes shown in the various figures are denoted by the same reference numerals, and duplicate descriptions are omitted as appropriate. Furthermore, the materials and values ​​cited in the following description are merely examples and are not intended to be limiting.

[0019] (First embodiment) Reference Figures 1 to 6 The semiconductor light emitting element and a method for manufacturing the semiconductor light emitting element according to this embodiment will be described. Figure 1 (a) is a top view of the semiconductor light emitting element 10 of this embodiment. Figure 1 (b) is a longitudinal sectional view taken along the cutting line AA shown in (a). Figure 1 As shown in FIG. 1 , the semiconductor light emitting element 10 includes a base layer 13 , a buried semiconductor layer 19 , a cathode electrode 20 , and an anode electrode 21 . The cathode electrode 20 is formed on the base layer 13 , and the anode electrode 21 is formed on the buried semiconductor layer 19 .

[0020] like Figure 1As shown in (b), the semiconductor light emitting element 10 includes a growth substrate 11, a buffer layer 12, a base layer 13, a mask 14, an n-type core layer 15, an active layer 16, a p-type semiconductor layer 17, a tunnel junction layer 18, a buried semiconductor layer 19, a cathode electrode 20, and an anode electrode 21. An opening 14a is formed in the mask 14.

[0021] The growth substrate 11 is a generally flat plate-shaped member made of a material capable of growing semiconductor crystals. While there are no particular limitations on the growth substrate 11, in this embodiment, a single-crystal c-plane sapphire substrate is used. The growth substrate 11 can be any single-crystal substrate made of a material used to grow a semiconductor single crystal layer via a buffer layer 12, described later. When the semiconductor light-emitting element 10 is composed of a nitride-based semiconductor, a c-plane sapphire substrate is preferred. However, this is not limiting and other heterogeneous substrates, such as Si, may also be used.

[0022] The buffer layer 12 is formed between the growth substrate 11 and the base layer 13 (described later) to mitigate the lattice mismatch between the two. When a c-plane sapphire substrate is used as the growth substrate 11, the buffer layer 12 is preferably made of undoped GaN. However, this is not limiting; AlN, AlGaN, and other materials may also be used. Alternatively, the growth substrate 11 may be constructed of a single material without the buffer layer 12.

[0023] The base layer 13 is a single crystal semiconductor layer formed on the growth substrate 11 or the buffer layer 12, and is preferably composed of a multilayer structure including undoped GaN with a thickness of several μm and an n-type semiconductor layer (not shown) such as an n-type contact layer on top. The n-type contact layer is a semiconductor layer doped with n-type impurities, for example, n-type Al doped with Si. 0.05 Ga 0.95 N et al.

[0024] Mask 14 is a layer made of a dielectric material formed on the surface of base layer 13. The material for mask 14 is selected from a material that makes it difficult for semiconductor crystals to grow through mask 14, and preferably includes SiO2, SiNx, Al2O3, etc. Mask 14 has a plurality of openings 14a formed therein, and a semiconductor layer can be grown from the base layer 13 partially exposed through the openings 14a.

[0025] The n-type core layer 15 is a hexagonal-prism-shaped semiconductor layer selectively grown on the base layer 13 exposed from the opening 14 a of the mask 14 , and is composed of, for example, GaN doped with an n-type impurity.

[0026] The active layer (light-emitting layer) 16 is a semiconductor layer grown around the n-type core layer 15. For example, a multi-quantum well active layer can be constructed by stacking five periods of 5nm-thick GaInN quantum well layers and 10nm-thick GaN barrier layers. While a multi-quantum well active layer is used here, a single quantum well structure or a bulk active layer is also possible. The active layer 16 is formed on the side and top surfaces of the n-type core layer 15, ensuring a sufficient area for the active layer 16. In this embodiment, the portion consisting of the n-type core layer 15 and the active layer 16 is referred to as a "columnar semiconductor layer."

[0027] The p-type semiconductor layer 17 is a semiconductor layer grown on the periphery of the active layer 16 and is composed of, for example, GaN doped with p-type impurities. The p-type semiconductor layer 17 covers the side and top surfaces of the active layer 16. Figure 1 As shown in (b), it is formed into a trapezoidal shape in a longitudinal cross-section (hereinafter referred to as a cone). In other words, the p-type semiconductor layer 17 is formed by covering each columnar semiconductor layer. In addition, in this embodiment, the top of the cone is flat for illustration, but as described later, the top can also be pointed. Moreover, the p-type semiconductor layers 17 of each columnar semiconductor layer are partially connected to each other at their lower parts. That is, the p-type semiconductor layers 17 divided into a plurality of parts are formed by extending the hem in a manner of being connected and integrated at their lower parts. By forming a double heterostructure with the n-type core layer 15, the active layer 16 and the p-type semiconductor layer 17, the carriers can be well sealed in the active layer 16, thereby increasing the probability of light-emitting recombination.

[0028] Here, if Figure 8 As shown in (a), in the conventional semiconductor light-emitting element 50, the p-type semiconductor layer 56 is separated for each nanowire. However, as described above, the p-type semiconductor layer 17 of the semiconductor light-emitting element 10 of this embodiment is formed integrally and connected to each other. Therefore, in the semiconductor light-emitting element 10 of this embodiment, hydrogen in the p-type semiconductor layer 17 of one columnar semiconductor layer can migrate to the p-type semiconductor layer 17 of an adjacent columnar semiconductor layer. Therefore, by exposing a portion of the integrated p-type semiconductor layer 17 and performing an annealing process, the entire p-type semiconductor layer 17 can be activated. This also applies to the p+ layer of the tunnel junction layer 18 described later. The structure of the p-type semiconductor layer 17 will be described in detail later.

[0029] The tunnel junction layer 18 is a semiconductor layer grown on the periphery of the p-type semiconductor layer 17, and has a double-layer structure in which a p+ layer doped with p-type impurities at a high concentration on the inside and an n+ layer doped with n-type impurities at a high concentration on the outside are grown in sequence. The p+ layer is a semiconductor layer doped with p-type impurities at a high concentration, and can be, for example, a layer with a thickness of 5 nm and a Mg concentration of 2×10 20cm -3 The n+ layer can be made of GaN with a thickness of 10 nm and a Si concentration of 2×10 20 cm -3 GaN. A tunnel junction is formed by these p+ and n+ layers. That is, the tunnel junction layer 18 of this embodiment is composed of a double layer of p+ and n+ layers. As described above, it is preferable to also activate the p+ layer of the tunnel junction layer 18.

[0030] The buried semiconductor layer 19 is a semiconductor layer formed to cover the upper surface and side surfaces of the tunnel junction layer 18. The material of the buried semiconductor layer 19 is, for example, n-type GaN.

[0031] Figure 1 The cathode electrode 20 shown in (b) is a negative electrode for supplying current to the semiconductor light emitting element 10. Figure 1 As shown, the cathode electrode 20 is formed on the exposed n-type base layer 13. More specifically, it is composed of a stacked structure of a metal material and a pad electrode that are in ohmic contact with the exposed base layer 13. The anode electrode 21 is a positive electrode for supplying current to the semiconductor light emitting element 10. The anode electrode 21 is formed on a portion of the buried semiconductor layer 19 and is composed of a stacked structure of a metal material and a pad electrode that are in ohmic contact with the outermost surface of the buried semiconductor layer 19. In addition, the anode electrode 21 can also be a transparent electrode extending in a manner covering substantially the entire buried semiconductor layer 19. In addition, as needed, an insulating protective film (passivation film) can also be provided to cover a specified surface of the semiconductor light emitting element 10. The insulating protective film protects the semiconductor light emitting element 10 from the influence of the external environment such as moisture.

[0032] Reference Figure 2 The structural features of the p-type semiconductor layer 17 of the semiconductor light emitting element 10 of this embodiment will be described in more detail. Figure 2 (a) is a top view of the semiconductor light emitting element 10. Figure 2 (b) is a longitudinal sectional view taken along the cutting line BB shown in (a). Figure 2 (c) is a cross-sectional view of a portion cut at a position corresponding to P1 shown in (b). Figure 2 (d) is a longitudinal sectional view taken along the cutting line CC shown in (a).

[0033] like Figure 2 As shown in (a), the surface of the semiconductor light emitting element 10 is covered by the buried semiconductor layer 19. Figure 2 (a) also shows the outer shape of the tunnel junction layer 18. The outer shape of the p-type semiconductor layer 17 is substantially the same as that of the tunnel junction layer 18. Figure 2As shown in (b) , when the semiconductor light emitting element 10 is cut in the arrangement direction of the columnar semiconductor layers (n-type core layer 15 and active layer 16 ), the p-type semiconductor layer 17 is continuously and integrally formed.

[0034] Figure 2 (c) is a cross-sectional view of the columnar semiconductor layer cut halfway in the height direction. Figure 2 As shown in (c), the active layer 16 surrounds the n-type core layer 15, and the active layer 16 is covered by the p-type semiconductor layer 17. The p-type semiconductor layer 17 is surrounded by the tunnel junction layer 18. The outer shape of the p-type semiconductor layer 17 reflects the shape of the hexagonal n-type core layer 15 and becomes a roughly hexagonal shape. Here, in this embodiment, the configuration of the columnar semiconductor layer in a plan view is set to a triangular lattice shape. Therefore, as shown in FIG. Figure 2 As shown in (c), the position of a columnar semiconductor layer in a certain row is shifted by half a columnar semiconductor layer from the position of an adjacent columnar semiconductor layer.

[0035] The p-type semiconductor layer 17 grows around the columnar semiconductor layer, and adjacent p-type semiconductor layers 17 are bonded to each other. In the triangular lattice arrangement, the vertices of the p-type semiconductor layers 17 of adjacent columnar semiconductor layers are bonded to each other. Figure 2 As shown in (c), an opening 22a and a connecting portion 23a are formed in the p-type semiconductor layer 17. In the opening 22a, the buried semiconductor layer 19 is formed from the upper surface to the mask 14. In the opening 22a, the current injected from the anode electrode 21 directly reaches the mask 14, making current injection into the active layer 16 more efficient around the opening 22a. The connecting portion 23a is referred to as the portion where adjacent p-type semiconductor layers 17 contact each other. Figure 2 (d) is a longitudinal sectional view of the opening 22 a and the connection portion 23 a .

[0036] Reference Figures 3 to 5 A method for manufacturing the semiconductor light emitting element 10 of this embodiment will be described. Figure 3 (a), (b), (c), (d), and (e) are longitudinal cross-sectional views showing a base layer forming step, a mask forming step, an opening forming step, a columnar semiconductor layer forming step, and a p-type semiconductor layer / tunnel junction layer forming step, respectively. Figure 4 (a), (b), and (c) are longitudinal cross-sectional views showing the embedded semiconductor layer forming step, the removal region forming / activation step, and the electrode forming step, respectively. While the semiconductor light-emitting element 10 is manufactured using a semiconductor wafer having multiple element formation regions, the following description focuses on a single element formation region.

[0037] First, in Figure 3In the base layer formation step shown in (a), as an example, a buffer layer 12 composed of GaN and a base layer 13 composed of GaN and AlGaN are grown on a growth substrate 11 composed of a sapphire single crystal using metal organic chemical vapor deposition (MOCVD). As mentioned above, a substrate composed of a single material, such as n-type GaN, may also be used as the growth substrate 11.

[0038] Then, in Figure 3 In the mask forming step shown in (b), a mask 14 made of SiO 2 having a film thickness of approximately 30 nm is deposited on the base layer 13 by sputtering.

[0039] Then, in Figure 3 In the opening forming step shown in (c), a fine pattern forming method of nanoimprint lithography is used to form an opening 14 a having a diameter of about 150 nm.

[0040] Then, in Figure 3 In the columnar semiconductor layer formation step shown in (d), an n-type core layer 15 composed of GaN is first grown on the base layer 13 exposed from the opening 14a by selective growth using MOCVD. The growth conditions for the n-type core layer 15 include, for example, using TMG and ammonia as raw material gases, a growth temperature of 1050°C, a V / III ratio of 10, and a pressure of 900 hPa using hydrogen as a carrier gas.

[0041] Next, an active layer 16 consisting of five cycles of 5-nm-thick GaInN quantum well layers and 10-nm-thick GaN barrier layers is formed using MOCVD on the side surfaces and top surface of the n-type core layer 15. The growth conditions for the active layer 16 include, for example, a growth temperature of 800°C, a V / III ratio of 3000, a pressure of 1000 hPa using nitrogen as the carrier gas, and TMG, TMI (TriMethylIndium), and ammonia as the raw material gases.

[0042] Then, in Figure 3 In the p-type semiconductor layer formation step (e) of the p-type semiconductor layer / tunnel junction layer formation step, p-type semiconductor layer 17 composed of GaN doped with p-type impurities is formed. As described above, p-type semiconductor layer 17 of semiconductor light-emitting element 10 of this embodiment is formed into a downwardly extending pyramidal shape. Preferably, the cross-sectional shape of this pyramid is hexagonal.

[0043] The cone is formed by gradually thickening the p-type semiconductor layer from the top to the bottom. More specifically, the cone is formed as follows. Figure 8The growth conditions for the hexagonal p-type semiconductor layer 56 shown in (a) are relatively low temperature and low V / III ratio. The growth conditions for the p-type semiconductor layer 56 are, for example, a growth temperature of approximately 950°C and a V / III ratio of approximately 1000. In this case, the growth conditions for the p-type semiconductor layer 17 are, for example, a growth temperature of approximately 850°C to 900°C and a V / III ratio of approximately 500 to 800. The pressure at this time is set to approximately 300 hPa using hydrogen as a carrier gas, and TMG, Cp2Mg (bisCycropentadienyl Magnesium), and ammonia are used as raw material gases. The top of the cone can be a flat c-plane or have no surface and be pointed. By forming the p-type semiconductor layer 17 into a cone, the tunnel junction layer 18 and buried semiconductor layer 19, described later, can be formed while suppressing the generation of voids.

[0044] Next, in the tunnel junction layer formation step, a tunnel junction layer 18 is formed covering the side and upper surfaces of the p-type semiconductor layer 17. The growth conditions of the tunnel junction layer 18 are, for example, a growth temperature of 800°C, a V / III ratio of 3000, and a pressure of 500 hPa when nitrogen is used as a carrier gas. In the tunnel junction layer formation step, a layer having a thickness of 5 nm and a Mg concentration of 2×10 20 cm -3 The p+ layer is composed of GaN with a thickness of 10 nm and a Si concentration of 2×10 20 cm -3 The tunnel junction layer 18 of the n+ layer composed of GaN is grown in sequence.

[0045] Then, in Figure 4 In the buried semiconductor layer forming step shown in (a), a buried semiconductor layer 19 composed of n-type GaN is grown, and the outer periphery and upper surface of the tunnel junction layer 18 are buried by the buried semiconductor layer 19. TMG, silane and ammonia are used as raw material gases in the growth of the buried semiconductor layer 19. In addition, for the convenience of illustration, Figure 4 In (a), the p-type semiconductor layer 17 is shown exposed from both end surfaces. However, in reality, the periphery of the p-type semiconductor layer 17 is covered by the buried semiconductor layer 19 .

[0046] Then, in Figure 4 In the removal region forming step of the removal region forming / activation step shown in (b), the upper surface of the embedded semiconductor layer 19 is selectively etched to the upper surface of the base layer 13 to form a removal region X so as to expose the base layer 13. At this time, an exposed portion Y is formed on the end face after removal. In the exposed portion Y, the mask 14, the p-type semiconductor layer 17, and the tunnel junction layer 18 are exposed. As the etching in this step, dry etching is used, for example. Figure 4(b) illustrates a method of removing a portion of the stacked semiconductor layer, but the present invention is not limited thereto. A removal region may be formed over the entire periphery of the semiconductor layer to form a terraced semiconductor layer on the underlying layer 13. This allows for more efficient annealing, which will be described later.

[0047] After the removal region X is formed, an activation step is performed to desorb hydrogen from the p-type semiconductor layer 17 and the p+ layer of the tunnel junction layer 18 exposed from the exposed portion, thereby performing an activation process. The activation process method is not limited, but one example is a heat treatment (annealing) at 600°C in an air atmosphere. While this embodiment illustrates a heat treatment in an air atmosphere, any heat treatment may be used as long as it is capable of activating the p-type semiconductor layer and is performed in an atmosphere free of atomic hydrogen.

[0048] Then, in Figure 4 In the electrode forming step shown in (c), a cathode electrode 20 is formed on the surface of the base layer 13 exposed in the removed region X, and an anode electrode 21 is formed on the embedded semiconductor layer 19. In this embodiment, the anode electrode 21 is formed on a portion of the embedded semiconductor layer 19. However, as described above, an electrode using ITO or the like may be formed on substantially the entire upper surface of the embedded semiconductor layer 19.

[0049] Figure 5 The figure shows the finished semiconductor wafer 30. The shape of the semiconductor wafer is generally circular, but Figure 5 The case of a rectangle is illustrated in . Figure 5 As shown, multiple semiconductor light-emitting elements 10 are formed on a semiconductor wafer 30. When the semiconductor light-emitting elements 10 are viewed from above, the embedded semiconductor layer 19, cathode electrode 20, and anode electrode 21 can be seen. The semiconductor wafer 30 is cut along scribe lines (not shown) between the semiconductor light-emitting elements 10 to separate them into individual semiconductor light-emitting elements 10 (element separation). The size of the separated chips is, for example, 0.5 mm x 0.5 mm. The semiconductor light-emitting elements 10 are then mounted in a package or the like as needed for practical use.

[0050] In the semiconductor light-emitting element 10 of this embodiment, when a voltage is applied between the cathode electrode 20 and the anode electrode 21, current flows in the order of anode electrode 21 → buried semiconductor layer 19 → tunnel junction layer 18 → p-type semiconductor layer 17 → active layer 16 → n-type core layer 15 → base layer 13 → cathode electrode 20, and light is emitted by recombination of luminescent light in the active layer 16. The light generated in the active layer 16 is extracted to the outside of the semiconductor light-emitting element 10.

[0051] In the semiconductor light-emitting element 10 of this embodiment, an active layer 16 is formed on the periphery of an n-type core layer 15, and a p-type semiconductor layer 17 and a tunnel junction layer 18 are further formed on the periphery of the active layer 16, which is then buried in a buried semiconductor layer 19. Therefore, the current injected from the anode electrode 21 is injected from the buried semiconductor layer 19 through the tunnel junction layer 18 and into the active layer 16 from the sidewalls of the p-type semiconductor layer 17 as a tunnel current. The resistance of the current injection through the tunnel junction layer 18 is low, allowing for good current injection. In addition, the buried semiconductor layer 19, as an n-type semiconductor layer, diffuses current more easily than a p-type semiconductor layer, allowing for current injection from the entire tunnel junction layer 18. As a result, the current injected from the anode electrode 21 is injected into the active layer 16 not only from the top surface of the active layer 16, but also from the entire side surface. As a result, good current injection into the active layer 16 is possible, achieving a high current density and improving the external quantum efficiency.

[0052] Reference Figure 6 An example of the semiconductor light emitting element 10 of this embodiment will be described. Figure 6 This is a SEM (Scanning Electron Microscope) image of a semiconductor light emitting element 10 that is in the process of being manufactured. Figure 6 (a) is a top view of the pyramidal p-type semiconductor layer 17. Figure 6 (b) is a perspective view. However, the tunnel junction layer 18 and the buried semiconductor layer 19 are not formed. Figure 6 As shown in (a), the plurality of p-type semiconductor layers 17 are connected by connecting portions 23a, and an opening 22a is formed surrounded by three connecting portions 23a. As described above, the base layer 13 is exposed from the opening 22a.

[0053] exist Figure 6 As shown in (a), the semipolar plane (101-1) appears on the slope S of the p-type semiconductor layer 17 in the pyramid. During the aforementioned manufacturing process, if the growth time of the p-type semiconductor layer 17 is extended, the diameter and height of the pyramid increase while maintaining the appearance of this semipolar plane. Furthermore, while a c-plane initially appears at the top T of the pyramid, as the growth time is extended, the c-plane shrinks, eventually leading to a pointed top T. In other words, the c-plane disappears, leaving only the aforementioned semipolar plane.

[0054] As described above in detail, the semiconductor light emitting element and the method for manufacturing the semiconductor light emitting element of the present embodiment can provide a semiconductor light emitting element and a method for manufacturing the semiconductor light emitting element capable of efficiently desorbing hydrogen from a p-type semiconductor layer.

[0055] (Second embodiment) Reference Figure 7A semiconductor light emitting element 10A according to this embodiment will be described. Figure 7 (a) is a top view of the semiconductor light emitting element 10A. Figure 7 (b) is a longitudinal sectional view taken along the cutting line DD shown in (a). Figure 7 (c) is a cross-sectional view of a portion cut at a position corresponding to P2 shown in (b). Figure 7 (d) is a longitudinal sectional view taken along the cutting line EE shown in (a). Figure 7 As shown in (a), the surface of the semiconductor light emitting element 10A is covered with the buried semiconductor layer 19 . Figure 7 (a) also shows the outer shape of the tunnel junction layer 18 . The outer shape of the p-type semiconductor layer 17 is substantially the same as that of the tunnel junction layer 18 .

[0056] The semiconductor light emitting element 10A is a semiconductor light emitting element 10 in which the arrangement of the columnar semiconductor layers is modified. That is, in the semiconductor light emitting element 10, the arrangement of the columnar semiconductor layers is set to a triangular lattice arrangement (see Figure 2 ), but in the semiconductor light emitting element 10A, they are arranged in a quadrilateral lattice shape.

[0057] like Figure 7 As shown in (b), when the semiconductor light emitting element 10A is cut in the arrangement direction of the columnar semiconductor layers, the p-type semiconductor layer 17 is continuously and integrally formed.

[0058] Figure 7 (c) is a cross-sectional view of the columnar semiconductor layer (n-type core layer 15 and active layer 16) cut halfway in the height direction. When viewed in the cross-sectional view, the active layer 16 surrounds the n-type core layer 15, and the active layer 16 is covered by the p-type semiconductor layer 17. The p-type semiconductor layer 17 is surrounded by the tunnel junction layer 18. Here, as described above, in the semiconductor light emitting element 10A, the configuration of the columnar semiconductor layer in the top view is set to a square lattice. Therefore, as Figure 7 As shown in (c), the p-type semiconductor layers 17 of adjacent columns of columnar semiconductor layers are arranged at the same position, and are not shifted as in the semiconductor light emitting element 10 .

[0059] The p-type semiconductor layer 17 grows around the columnar semiconductor layer, so adjacent p-type semiconductor layers 17 are bonded. In the four-sided lattice configuration, the sides and vertices of adjacent p-type semiconductor layers 17 are bonded. Figure 7As shown in (c), an opening 22b and a connecting portion 23b are formed in the p-type semiconductor layer 17. In the opening 22b, the buried semiconductor layer 19 is formed from the upper surface to the mask 14. In the opening 22b, the current injected from the anode electrode 21 directly reaches the mask 14, making current injection into the active layer 16 more efficient around the opening 22b. The connecting portion 23b is referred to as the region where adjacent p-type semiconductor layers 17 contact each other. Figure 7 (d) is a longitudinal sectional view of the opening 22b and the connection portion 23b.

[0060] As described above, according to the semiconductor light emitting element and the method for manufacturing the semiconductor light emitting element of the present embodiment, it is also possible to provide a semiconductor light emitting element and a method for manufacturing the semiconductor light emitting element capable of efficiently desorbing hydrogen from a p-type semiconductor layer.

[0061] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining technical means disclosed in different embodiments are also included in the technical scope of the present invention.

[0062] This international application claims priority based on Japanese Patent Application No. 2023-041444, filed on March 15, 2023, and incorporates the entire contents of Japanese Patent Application No. 2023-041444 into this international application.

[0063] The above descriptions of specific embodiments of the present invention are provided for illustrative purposes only. They are not intended to be exhaustive, nor are they intended to limit the present invention to the embodiments described. It will be apparent to those skilled in the art that many variations and modifications can be made based on the above descriptions. Description of reference numerals:

[0064] 10, 10A: semiconductor light-emitting element; 11: growth substrate; 12: buffer layer; 13: base layer; 14: mask; 14a: opening; 15: n-type core layer; 16: active layer; 17: p-type semiconductor layer; 18: tunnel junction layer; 19: buried semiconductor layer; 20: cathode electrode; 21: anode electrode; 22a, 22b: opening; 23a, 23b: connection; 30: semiconductor wafer; 50: semiconductor light-emitting element; 51: growth substrate; 52: base layer; 53: mask; 54: n-type core layer; 55: active layer; 56: p-type semiconductor layer; 57: tunnel junction layer; 58: buried semiconductor layer; P1, P2: position; S: slope; T: top; X: removed area; Y: exposed part.

Claims

1. A semiconductor light emitting element, characterized in that: have: growth substrate; a plurality of columnar semiconductor layers including an n-type core layer vertically extending from the main surface of the growth substrate and an active layer disposed on the periphery of the n-type core layer; A plurality of p-type semiconductor layers are arranged on the periphery of the columnar semiconductor layer and are connected to each other to form an integrated whole; as well as The removal region is formed by removing a portion of the integrated plurality of p-type semiconductor layers.

2. The semiconductor light emitting element according to claim 1, wherein The plurality of p-type semiconductor layers each form a cone extending downward in the vertical direction, and the plurality of p-type semiconductor layers are connected to each other at a lower portion of the cone.

3. The semiconductor light emitting element according to claim 1, wherein The semiconductor light emitting element further comprises: a base layer formed on the growth substrate and continuous with the n-type core layer; and The opening is surrounded by a connection portion where the p-type semiconductor layers are connected to each other. The p-type semiconductor layer is not arranged in the opening.

4. The semiconductor light emitting element according to claim 3, wherein The semiconductor light emitting element further includes a buried semiconductor layer, wherein the buried semiconductor layer is arranged on the periphery of the p-type semiconductor layer. In the removal region, a layer from the upper surface of the buried semiconductor layer to the base layer is removed, An end surface of the p-type semiconductor layer is exposed from the removed area.

5. The semiconductor light emitting element according to claim 4, wherein The semiconductor light emitting element further includes a tunnel junction layer, wherein the tunnel junction layer is arranged between the p-type semiconductor layer and the buried semiconductor layer. The end surface of the tunnel junction layer is also exposed from the removed area.

6. A method for manufacturing a semiconductor light emitting element, characterized in that: include: a mask forming step of forming a mask having a plurality of openings on the growth substrate; a columnar semiconductor layer forming step of forming an n-type core layer in the opening by selective growth and forming an active layer on the periphery of the n-type core layer, thereby forming the columnar semiconductor layer; A p-type semiconductor layer forming step of forming a p-type semiconductor layer on the periphery of the columnar semiconductor layer; a buried semiconductor layer forming step of forming a buried semiconductor layer on the growth substrate in a manner of burying the p-type semiconductor layer; a removal region forming step of removing a portion of the p-type semiconductor layer and a portion of the buried semiconductor layer to expose the p-type semiconductor layer; as well as In the activation step, the entire structure is annealed to activate the p-type semiconductor layer.

7. The method for manufacturing a semiconductor light emitting element according to claim 6, wherein: The method for manufacturing a semiconductor light emitting element further includes a tunnel junction layer forming step, in which a tunnel junction layer is formed on the periphery of the p-type semiconductor layer. The buried semiconductor layer is formed in a manner of burying the tunnel junction layer, In the removal region forming step, the tunnel junction layer is further exposed. In the activation step, the tunnel junction layer is further activated.

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