Edge device-based feature data processing method and related device

Abstract

The application belongs to the technical field of edge computing, and provides a feature data processing method based on an edge device and related equipment. The processor of the edge device is deployed with a neural network model, the neural network model comprises a convolution network and a probability normalization function, and the method comprises the following steps: obtaining feature data to be processed; performing convolution operation on the feature data based on the convolution network to obtain a feature vector of the feature data; in the case of replacing an exponential formula in the probability normalization function with a Taylor expansion formula, performing normalization operation on a feature value in the feature vector based on the probability normalization function to obtain a probability distribution corresponding to the feature data, and the probability distribution is used for classifying the feature data. The technical scheme provided by the application can improve the processing efficiency of the edge device for feature data.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of edge computing, and particularly relates to a feature data processing method based on an edge device and related equipment. BACKGROUND

[0002] With the rapid development of artificial intelligence and Internet of Things technologies, more and more edge devices, such as intelligent cameras, intelligent sensors, wearable devices, etc., have the ability of real-time data collection and preliminary intelligent processing. In order to improve service efficiency and protect data security, the demand for local processing and instant decision-making of data is increasing. Neural networks, especially convolutional neural networks (CNN), have shown excellent performance in feature extraction, data dimension reduction, classification and recognition, and have been gradually deployed on various edge devices to realize end-side intelligence.

[0003] In neural networks, a probability normalization function (such as a Softmax function) is widely used for normalization of feature vectors and output of probability distributions. However, the exponential operation in the probability normalization function consumes a large amount of computing hardware resources, and is limited by the computing power, storage space and energy consumption of edge devices, etc., making the probability normalization function a major bottleneck for efficient feature processing of edge devices. Therefore, how to improve the processing efficiency of edge devices for feature data has become a technical problem to be solved. SUMMARY

[0004] Embodiments of the present application provide a feature data processing method based on an edge device, an apparatus, a computer program product, a computer-readable storage medium and an electronic device, which can improve the processing efficiency of edge devices for feature data to a certain extent.

[0005] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0006] According to a first aspect of embodiments of the present application, a feature data processing method based on an edge device is provided, a processor of the edge device is deployed with a neural network model, the neural network model includes a convolution network and a probability normalization function, and the method includes: obtaining feature data to be processed; performing convolution operation on the feature data based on the convolution network to obtain a feature vector of the feature data; in a case where an exponential expression in the probability normalization function is replaced with a Taylor expansion expression, performing normalization operation on a feature value in the feature vector based on the probability normalization function to obtain a probability distribution corresponding to the feature data, the probability distribution being used for classifying the feature data.

[0007] In some embodiments of the present application, based on the foregoing scheme, before the normalization operation is performed on the feature values in the feature vector based on the probability normalization function, the method further comprises: determining a Taylor expansion formula of a target order for the probability normalization function processing each feature value in the feature vector, the Taylor expansion formula of the target order being used to replace an exponential formula in the probability normalization function, the target order being adapted to the size of the each feature value.

[0008] In some embodiments of the present application, based on the foregoing scheme, the target order is positively correlated with the size of the each feature value.

[0009] In some embodiments of the present application, based on the foregoing scheme, the determining of the Taylor expansion formula of the target order for the probability normalization function processing each feature value in the feature vector comprises: determining a target operation expansion instruction from a plurality of pre-defined operation expansion instructions according to each feature value in the feature vector; and determining a Taylor expansion formula of a corresponding target order for the probability normalization function processing the each feature value according to the target operation expansion instruction.

[0010] In some embodiments of the present application, based on the foregoing scheme, the determining of the target operation expansion instruction from the plurality of pre-defined operation expansion instructions according to each feature value in the feature vector comprises: if the each feature value falls into a first feature value interval, determining a first operation expansion instruction in the plurality of pre-defined operation expansion instructions as the target operation expansion instruction, the first operation expansion instruction corresponding to a target order of N order; and if the each feature value falls into a second feature value interval, determining a second operation expansion instruction in the plurality of pre-defined operation expansion instructions as the target operation expansion instruction, the second operation expansion instruction corresponding to a target order of M order, where M is greater than N, and the minimum value of the second feature value interval is greater than the maximum value of the first feature value interval.

[0011] In some embodiments of the present application, based on the foregoing scheme, the N order is 6 order, and the M order is 9 order.

[0012] In some embodiments of the present application, based on the foregoing scheme, the target operation expansion instruction is used to directly call a probability normalization function to perform the normalization operation on the each feature value.

[0013] In some embodiments of the present application, based on the foregoing scheme, the processor comprises a first calculation module and a second calculation module, wherein the first calculation module is configured to calculate the first order formula to the Nth order formula in the Taylor expansion formula, and the second calculation module is configured to calculate the (N+1)th order formula to the Mth order formula in the Taylor expansion formula; in the process of normalizing the feature values in the feature vector based on the probability normalization function, the method further comprises: if the target order is N, calling the first calculation module to calculate the Nth order Taylor expansion formula; if the target order is M, calling the first calculation module and the second calculation module to calculate the Mth order Taylor expansion formula.

[0014] In some embodiments of the present application, based on the foregoing scheme, the first calculation module comprises N calculation units, and the calling of the first calculation module to calculate the Nth order Taylor expansion formula comprises: calling each calculation unit in the first calculation module to calculate each order formula in the Nth order Taylor expansion formula in parallel.

[0015] In some embodiments of the present application, based on the foregoing scheme, the second calculation module comprises M-N calculation units, and the calling of the first calculation module and the second calculation module to calculate the Mth order Taylor expansion formula comprises: calling each calculation unit in the first calculation module and each calculation unit in the second calculation module to calculate each order formula in the Mth order Taylor expansion formula in parallel.

[0016] In some embodiments of the present application, based on the foregoing scheme, the normalization operation on the feature values in the feature vector based on the probability normalization function comprises: based on the probability normalization function, performing normalization operation on each feature value in the feature vector in parallel.

[0017] According to a second aspect of the embodiments of the present application, the processor of the edge device is deployed with a neural network model, the neural network model comprises a convolution network and a probability normalization function, and the device comprises: an acquisition unit configured to acquire feature data to be processed; a first operation unit configured to perform convolution operation on the feature data based on the convolution network to obtain a feature vector of the feature data; and a second operation unit configured to perform normalization operation on feature values in the feature vector based on the probability normalization function in the case of replacing an exponential formula in the probability normalization function with a Taylor expansion formula, to obtain a probability distribution corresponding to the feature data, wherein the probability distribution is used for classifying the feature data.

[0018] According to a third aspect of the embodiments of the present application, a computer program product is provided, which comprises computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to enable a computer device having the processor to perform operations implemented by the method according to the first aspect described above.

[0019] According to a fourth aspect of the embodiments of the present application, a computer readable storage medium is provided, which stores at least one computer program instruction, and the at least one computer program instruction is loaded and executed by a processor to enable the computer readable storage medium to perform operations implemented by the method according to the first aspect described above.

[0020] According to a fifth aspect of the embodiments of the present application, an electronic device is provided, which comprises one or more processors and one or more memories, and the one or more memories store at least one computer program instruction, and the at least one computer program instruction is loaded and executed by the one or more processors to enable the electronic device to perform operations implemented by the method according to the first aspect described above.

[0021] Based on the technical solutions proposed in the present application, the exponential expression of the probability normalization function in the neural network model is replaced by the Taylor expansion expression, which can significantly improve the processing efficiency of the edge device on the feature data. Specifically, the operation of the exponential expression has a large overhead on hardware, especially on the hardware without floating point or on the edge device sensitive to energy consumption, while the polynomial form of the Taylor expansion is more suitable for hardware implementation. In this way, complex exponential operations are avoided, which can greatly reduce the demand for operation resources and energy consumption, and thus the processing efficiency of the edge device on the feature data can be improved.

[0022] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0024] Figure 1 a flow chart of the feature data processing method based on the edge device in the embodiments of the present application is shown;

[0025] Figure 2 a block diagram of the feature data processing device based on the edge device in the embodiments of the present application is shown;

[0026] Figure 3 A structural schematic diagram of an electronic device in the embodiments of the present application is shown. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative effort belong to the scope of protection of the present application.

[0028] In addition, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a sufficient understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or can employ other methods, components, devices, steps, etc. In other cases, well-known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring the aspects of the present application.

[0029] The block diagrams shown in the drawings are only functional entities, which do not necessarily have to correspond to physically independent entities. That is, these functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. It should be noted that in the drawings, some components in the drawings are omitted for the sake of brevity and adaptability to ensure the simplicity of the drawings.

[0030] The flowcharts shown in the drawings are only exemplary illustrations, which do not necessarily include all the contents and operations / steps, and do not necessarily be executed in the described order. For example, some operations / steps can be further decomposed, and some operations / steps can be combined or partially combined, so that the actual execution order can be changed according to the actual situation.

[0031] In the description of the present application, it should be understood that the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "multiple" is two or more.

[0032] In order for those skilled in the art to better understand the present application, first, the technical concepts and application background related to the present application are briefly described.

[0033] Edge device: refers to a computing device or terminal deployed at the edge of a network, close to data sources or user terminals, capable of performing data collection, preprocessing, analysis or preliminary decision-making locally. The edge device has limited or constrained computing resources, storage capacity and energy consumption budget, and is usually used to reduce network transmission delay, reduce bandwidth consumption, protect data privacy or meet real-time requirements. The edge device described in this application can include but is not limited to the following device types: smart camera, access control device, smart home controller, industrial sensor gateway, vehicle terminal (automotive electronic unit), unmanned aerial vehicle flight control and vision processing module, wearable device (such as smart watch, fitness tracker), mobile robot, local understanding module of smart speaker, remote monitoring camera, portable medical device, and miniaturized edge computing node deployed on edge gateway or edge server, etc.

[0034] Neural network model: refers to a parameterized function model composed of a plurality of interconnected computing units (i.e. neurons or nodes) in a specific topological structure, used for feature extraction, transformation and mapping of input feature data, thereby realizing classification, regression, detection, segmentation, generation or other artificial intelligence tasks. The neural network model includes but is not limited to Convolutional Neural Network (CNN), Recurrent Neural Network (RNN), Long Short-Term Memory Network (LSTM), Gated Recurrent Unit (GRU), Transformer, Graph Neural Network (GNN), and combinations or derivatives of the above structures. In this invention, the neural network model at least contains a convolutional network structure and a probability normalization function as part of its composition, used to extract feature vectors and map them to probabilistic outputs or normalized feature representations.

[0035] Probability normalization function: refers to a mathematical mapping function that converts the real number form output (usually called logits or feature values) of a neural network model (or other numerical processing module) into a normalized vector with probabilistic meaning. The function transforms each element of the input vector, so that each component of the output vector is non-negative and the sum of all components is 1, so that it can be interpreted as a discrete probability distribution. Common probability normalization functions include the Softmax function, the normalized exponential function, and the variant of the logit transformation followed by normalization.

[0036] Exponential expression (exponential function): refers to the power function with natural constant e (approximately equal to 2.718281828…) as the base, whose mapping definition for real number input z is exp(z) = ez The core computing unit commonly used in a probability normalization function (e.g., a Softmax function).

[0037] Taylor expansion (Taylor series) formula: a mathematical expression for expressing an analytic real function or complex function near a point as a power series about the point, i.e., an approximate expression of the real function or complex function, which can have different expressions according to different orders.

[0038] In a neural network, a probability normalization function is widely used for normalization of a feature vector and output of a probability distribution. However, the exponential operation in the probability normalization function consumes a large amount of computing hardware resources, and is limited by the computing power, storage space, and energy consumption of an edge device, etc., so that the probability normalization function becomes a bottleneck for efficient feature processing of the edge device. In this case, the application provides a feature data processing method based on an edge device to improve the processing efficiency of the edge device for feature data.

[0039] The implementation details of the technical solutions of the embodiments of the application are described below:

[0040] Referring to Figure 1 , a flowchart of a feature data processing method based on an edge device in the embodiments of the application is shown, which can be executed by a device with computing processing function, wherein a neural network model is deployed in a processor of the edge device, and the neural network model includes a convolution network and a probability normalization function.

[0041] In the application, the processor can include any one of a Field Programmable Gate Array (FPGA), a Graphics Processing Unit (GPU), a Google Tensor Processing Unit (TPU), and an Application-Specific Integrated Circuit (ASIC).

[0042] Referring to Figure 1 , the feature data processing method based on an edge device includes steps 110 to 130, which are described in detail as follows:

[0043] In step 110, feature data to be processed is acquired.

[0044] In the application, the feature data can be image feature data, voice feature data, or sensor data collected by an industrial sensor. Specifically, the application does not make too many limitations.

[0045] In the present application, the feature data to be processed can be acquired by the edge device through its internal perception module (such as a camera, a sensor, a microphone, etc.) to collect raw data in real time. For example, a smart camera can take video frames, a smart sensor can collect environmental parameters such as temperature, humidity, and pressure, and a voice device can acquire voice sampling data. The acquired data can be a single image, a time series signal, or other dimensional raw feature input, serving as input data for subsequent neural network model processing.

[0046] Referring to Figure 1 In step 120, the feature data is subjected to convolution operation based on the convolution network, to obtain a feature vector of the feature data.

[0047] In the present application, the processor of the edge device can perform convolution operation on the acquired feature data to be processed through the convolution network in the locally deployed neural network model.

[0048] Specifically, the edge device first receives or collects raw data (such as images, voices, or sensor signals, etc.), and then inputs the data into the convolution network. The convolution network extracts local spatial features for the input data through multiple convolution layers, and converts useful information in the data into a feature vector through convolution kernel sliding window operation. The feature vector highly condenses the main features of the raw data, laying a foundation for subsequent probability normalization and classification operations. For example, in the edge camera scenario, the collected images will first be subjected to feature extraction through the convolution layers of the convolution neural network, to generate a feature vector that can reflect the content of the images, for subsequent intelligent recognition and decision-making. By directly completing this process at the edge device end, the real-time performance and security of data processing can be improved, and the dependence on cloud resources can be reduced.

[0049] Referring to Figure 1 In step 130, in the case where the exponential expression in the probability normalization function is replaced by the Taylor expansion expression, the feature values in the feature vector are subjected to normalization operation based on the probability normalization function, to obtain a probability distribution corresponding to the feature data, which is used for classifying the feature data.

[0050] In the present application, for example, the probability normalization function is a Softmax function, i.e., formula (1):

[0051] (1)

[0052] wherein x j represents the jth feature value in the feature vector; s represents that the feature vector includes s feature values, i.e., the dimension of the feature vector.

[0053] Further, in the case of replacing the exponential formula in the Softmax function with the Taylor expansion formula, the Softmax function is as follows Formula (2):

[0054] (2)

[0055] Wherein, n represents the order of the Taylor expansion formula.

[0056] In the present application, the probability distribution obtained by performing normalization operation on the feature values based on the probability normalization function can be used for classifying the feature data. For example, taking the intelligent camera for traffic sign recognition as an example, after the image data collected by the intelligent camera is extracted by the neural network, a 5-dimensional feature vector is obtained. After performing normalization operation on each feature value in the feature vector, the probability distribution is:

[0057] P = [0.23, 0.15, 0.08, 0.31, 0.23].

[0058] Since 0.31 is the largest, it can be determined that the image collected by the intelligent camera belongs to the fourth type of traffic sign.

[0059] Based on the technical solutions proposed in the present application, replacing the exponential formula of the probability normalization function in the neural network model with the Taylor expansion formula can significantly improve the processing efficiency of the edge device for feature data. Specifically, the operation of the exponential formula has a large overhead on hardware, especially on hardware without floating point or on edge devices sensitive to energy consumption, while the Taylor expansion formula is composed of polynomial addition and multiplication, and the polynomial form is more suitable for hardware implementation. In this way, complex exponential operations are avoided, which can greatly reduce the demand for computing resources and energy consumption, and thus improve the processing efficiency of the edge device for feature data.

[0060] In the present application, before performing normalization operation on the feature values in the feature vector based on the probability normalization function, the following step 131 can also be performed:

[0061] Step 131, determine the Taylor expansion formula of the target order for the probability normalization function of each feature value in the feature vector, the Taylor expansion formula of the target order is used to replace the exponential formula in the probability normalization function, and the target order is adapted to the size of each feature value.

[0062] In the present application, before the normalization operation is performed on each feature value, the numerical range of each feature value can be detected first, and then the Taylor expansion formula of the target order is determined for the probability normalization function processing each feature value. For example, the feature vector is [x1, x2, x3, x4], and the Taylor expansion formula of the target order can be determined for the probability normalization function processing x1, x2, x3, and x4, respectively.

[0063] In some embodiments of the present application, the target order is positively correlated with the size of each feature value.

[0064] In the present application, in the probability normalization link of the neural network model, replacing the exponential formula in the probability normalization function with the Taylor expansion formula is an efficient approximation method. The order of Taylor expansion directly determines the accuracy of the approximate calculation of the exponential formula. The larger the feature value, the greater the error between the low-order Taylor expansion formula and the exponential formula, and therefore, a higher order is needed to ensure the accuracy of the approximation. Conversely, for smaller feature values, a low-order Taylor expansion is sufficient to meet the accuracy requirement. Therefore, by positively correlating the target order with the size of each feature value as a constraint, the allocation of computational resources can be optimized while ensuring the overall calculation accuracy, and the energy efficiency ratio on the edge device can be improved.

[0065] Specifically, first, the absolute value of each feature value x can be analyzed, and then the feature value x is mapped to a predetermined interval according to a pre-designed partition rule, and each interval is associated with an optimal target order n. The larger the feature value, the higher the approximate order n allocated, thereby realizing the positive correlation between the target order n and the size of the feature value.

[0066] For example, for the feature vector x = [0.05, 0.9, 2.1, 3.2], the Taylor expansion formula of order 4 can be used to replace the exponential formula in the probability normalization function for 0.05, the Taylor expansion formula of order 6 can be used to replace the exponential formula in the probability normalization function for 0.9, the Taylor expansion formula of order 9 can be used to replace the exponential formula in the probability normalization function for 2.1, and the Taylor expansion formula of order 12 can be used to replace the exponential formula in the probability normalization function for 3.2.

[0067] In the present application, the target order is positively correlated with the size of each eigenvalue, and the order of Taylor expansion is flexibly and dynamically allocated according to the actual value of the eigenvalue. For larger eigenvalues, higher order polynomials are used to improve the approximation accuracy, and for smaller eigenvalues, lower order polynomials are used to save computing resources. In this way, not only the accuracy and stability of the probability normalization operation can be effectively guaranteed, but also the resource utilization and energy consumption of the edge device can be significantly optimized, the overall efficiency and real-time performance of feature data processing can be improved, and it is especially suitable for edge computing scenarios with limited computing power, sensitive to time delay and energy consumption, and needing to balance operation speed and resource constraints.

[0068] In one specific embodiment of the present application, the Taylor expansion formula with a target order determined for the probability normalization function processing each eigenvalue in the feature vector can be executed according to the following steps 1311 to step 1312:

[0069] Step 1311, according to each eigenvalue in the feature vector, determine a target operation expansion instruction from a plurality of pre-defined operation expansion instructions.

[0070] Step 1312, according to the target operation expansion instruction, determine the Taylor expansion formula with the corresponding target order for the probability normalization function processing each eigenvalue.

[0071] In the present application, a plurality of pre-defined operation expansion instructions can be designed, and each instruction corresponds to a Taylor expansion formula of different order. These expansion instructions can be software functions, hardware micro-instructions, or pre-compiled units in operator library.

[0072] In the present application, the operation expansion instruction can be an expansion instruction based on the design of RISCV architecture. RISCV architecture is an open, modular, and reduced instruction set computing (RISC) architecture specification. RISCV defines a set of basic instructions, optional extensions, and ABI (application binary interface) specifications for software / hardware interoperability, which can be implemented in processor cores, microcontrollers, system-on-chip (SoC), and related tool chains.

[0073] For example, for Taylor expansion formulas of different orders, expansion instructions can be designed respectively to enable the processor to complete the exp(x) approximation operation of the corresponding order through one instruction. These expansion instructions can be defined in the custom instruction space of RISCV architecture and implemented by software and hardware collaboration, supporting both software calling and efficient execution at the hardware level, greatly improving instruction dispatching and pipeline efficiency. By dynamically selecting different RISCV expansion instructions, the processor can flexibly adapt to the operation requirements of each eigenvalue, significantly reducing the overall computing load and energy consumption while ensuring the approximation accuracy.

[0074] In the embodiment, the target operation extension instruction is determined from the plurality of predefined operation extension instructions according to each eigenvalue in the eigenvalue vector, which can be performed according to the following steps 13111 to 13112:

[0075] In step 13111, if the each eigenvalue falls into a first eigenvalue interval, a first operation extension instruction of the plurality of predefined operation extension instructions is determined as the target operation extension instruction, and the target order corresponding to the first operation extension instruction is N order.

[0076] In step 13112, if the each eigenvalue falls into a second eigenvalue interval, a second operation extension instruction of the plurality of predefined operation extension instructions is determined as the target operation extension instruction, and the target order corresponding to the second operation extension instruction is M order, where M is greater than N, and the minimum value of the second eigenvalue interval is greater than the maximum value of the first eigenvalue interval.

[0077] In the present application, according to the actual distribution characteristics of the eigenvalues, the intervals can be divided into two or more non-overlapping eigenvalue intervals. For example, the first eigenvalue interval is [a, b], and the second eigenvalue interval is (b, c], where a, b, and c are real numbers, and the minimum value of the second interval is greater than the maximum value of the first interval, ensuring no overlap.

[0078] For each eigenvalue interval, a predefined operation extension instruction at the hardware / software level can be defined. For example, Table 1.

[0079] Table 1: Predefined operation extension instructions

[0080]

[0081] In the present application, as shown in Table 1 above, the first operation extension instruction (such as RISCV custom instruction or software specific function, etc.) corresponds to N order Taylor expansion formula with lower precision requirement. The second operation extension instruction corresponds to M order Taylor expansion formula (M>N) with higher precision to compensate for the approximation error caused by the large eigenvalue interval. For example, eigenvalue x=3.1 falls into the first eigenvalue interval (0, 5], and the first operation extension instruction (such as VSOFTMAX) is called. Eigenvalue x=6.6 falls into the second eigenvalue interval (5, 10], and the second operation extension instruction (such as VSOFTMAX6) is called.

[0082] In the present application, by dynamically mapping the characteristic value interval with the order of Taylor expansion formula, combined with multiple predefined operation expansion instructions, each characteristic value can adopt the most suitable approximate calculation path, which can significantly improve the adaptability and calculation efficiency of the probability normalization function. This scheme can intelligently select lower or higher order Taylor expansion according to the actual amplitude of the characteristic value, optimize resource utilization and improve energy efficiency, while considering numerical accuracy to avoid approximation errors caused by large amplitude characteristic values. At the same time, this technical scheme has good software and hardware adaptability, can be directly mapped to expansion instructions in RISCV and other architectures or implemented through software scheduling, and is suitable for various computing platforms, effectively improving the overall performance and practical value of probability normalization operation in power-constrained scenarios such as edge devices and chip ends.

[0083] In the present application, the target operation expansion instruction can be used to directly call the probability normalization function to normalize each characteristic value.

[0084] The target operation expansion instruction proposed in the present application is not only a simple arithmetic operation instruction, but also a special hardware unit that can be directly mapped and integrated into a processor (such as RISCV architecture). These instructions are designed as highly composite single instructions, which can complete all core operation steps required by the probability normalization function at one time, such as addition, subtraction, multiplication, division, etc., and then realize efficient normalization processing for each input characteristic value.

[0085] Traditional normalization operation generally relies on step-by-step calling of high-level software library functions. For each characteristic value, the software needs to call multiple arithmetic functions in turn (such as calculating exp(x), accumulating summation, and then doing normalization division, etc.), involving multiple parameter passing, instruction distribution and memory access operations, which can easily lead to system call delay, pipeline blockage and calculation efficiency decline. Especially in edge devices or power-constrained embedded systems, frequent function jumps can become a performance bottleneck.

[0086] In contrast, the present application integrates the core processes of probability normalization operation (such as efficient approximation of exp(x), multi-step accumulation and step-by-step normalization, etc.) into a "full-featured hardware instruction". When the processor executes this instruction, it does not need to rely on software library functions, but directly calls the underlying hardware unit to complete all necessary operations including addition, subtraction, multiplication, division, etc. This can greatly reduce the additional overhead caused by instruction calling and context switching, and realize fast normalization calculation in a single cycle or a few cycles. By directly mapping the target operation extension instruction to the processor hardware unit, the operation delay of normalization calculation can be greatly reduced, the performance bottleneck caused by traditional library function calling can be avoided, and extremely fast data processing and throughput can be realized, improving the processing efficiency of feature data of edge devices. At the same time, this scheme simplifies the software stack and code maintenance work, so that developers do not need to pay attention to the details of the underlying normalization implementation, which helps to improve the simplicity and robustness of the application. Relying on hardware instruction level parallelism and pipeline scheduling, the resource utilization rate of the calculation unit can also be fully utilized, improving the energy efficiency and calculation density. In addition, this instruction has good platform adaptability and scalability, and can be flexibly integrated into various embedded devices, AI chips and edge computing platforms to meet the efficient normalization operation needs in diversified scenarios.

[0087] In the present application, the processor can include a first calculation module and a second calculation module, wherein the first calculation module is used to operate the first order formula to the Nth order formula in the Taylor expansion formula, and the second calculation module is used to operate the N+1th order formula to the Mth order formula in the Taylor expansion formula.

[0088] Further, in the present application, in the process of normalizing the feature values in the feature vector based on the probability normalization function, the following steps 132 to 133 can be performed:

[0089] Step 132, if the target order is N order, the first calculation module is called to operate the N order Taylor expansion formula.

[0090] Step 133, if the target order is M order, the first calculation module and the second calculation module are called to operate the M order Taylor expansion formula.

[0091] In the present application, in order to improve the adaptability and operation efficiency of the probability normalization function, the first calculation module and the second calculation module specially for Taylor expansion formula calculation can be introduced inside the processor. This architecture design allows dynamic selection of Taylor expansion formulas of different orders according to the amplitude or accuracy requirements of actual feature values, to realize reasonable scheduling of operation resources and performance optimization.

[0092] Specifically, the first calculation module is used to efficiently process the calculation of the first order to the Nth order in the Taylor expansion, which usually covers the approximate accuracy requirement of most common input data in normalization. For the case of target order N, only the first calculation module needs to be called to complete the entire Taylor expansion operation, which not only ensures the calculation accuracy, but also maximizes the reduction of hardware resources and energy consumption.

[0093] When the normalization operation requires higher accuracy and needs to be extended to Mth order (M>N) Taylor expansion, the first calculation module and the second calculation module can be called simultaneously. The first calculation module is responsible for the parallel or pipeline processing of the first order to the Nth order formula, and the second calculation module is specially responsible for the supplementary calculation of the N+1th order to the Mth order formula. This division not only makes the overall calculation process highly parallelized, significantly shortens the overall time of high-order expansion, but also enables on-demand and dynamic allocation of hardware resources, avoiding the waste of high-order calculation capability in low-precision scenarios.

[0094] In addition, the above scheme also realizes efficient hardware reuse design to further improve resource utilization and reduce hardware cost. Specifically, for the Taylor expansion calculation unit, the operations of the first order to the Nth order formula are uniformly implemented by shared hardware units, and there is no need to design independent calculation paths for each order. When higher-precision normalization operation is needed, only a set of dedicated operation paths for the N+1th order to the Mth order formula needs to be added based on the original shared unit. In this way, the basic calculation hardware can be reused, and only limited hardware resources are additionally invested for the high-order part. Compared with the way of separately expanding the calculation unit for each order, about LUT hardware resources can be saved, the overall chip area and power consumption are effectively reduced, and the scalability and cost performance of the processor are improved.

[0095] In the present application, the first calculation module can include N calculation units, and the second calculation module can include M-N calculation units.

[0096] In the present application, in order to further optimize the hardware implementation efficiency of the Taylor expansion formula, the first calculation module and the second calculation module in the processor both adopt a highly parallel structure design, thereby significantly improving the throughput and response speed of the normalization operation.

[0097] Further, the operation of the Nth order Taylor expansion formula by calling the first calculation module can be performed according to the following steps 1321:

[0098] Step 1321, each calculation unit in the first calculation module is called to operate each order formula in the Nth order Taylor expansion formula in parallel.

[0099] Specifically, the first calculation module is composed of N calculation units, each of which corresponds to one order term in the Taylor expansion formula. When the normalization operation of the N-order Taylor expansion formula is required, each order formula is assigned to the corresponding N calculation units, and all calculation units can perform their respective operation tasks in parallel within the same clock cycle.

[0100] For example, for the 6-order Taylor expansion formula "1+x+x² / 2!+x 4 / 4!+x 5 / 5!+x 6 / 6!", six calculation units in the first calculation module can be invoked to perform parallel operations on the formulas "x", "x² / 2!", "x 4 / 4!", "x 5 / 5!", and "x 6 / 6!" respectively. Through this parallel processing mechanism, the delay bottleneck caused by serialized calculation can be effectively avoided, greatly improving the overall operation efficiency of N-order expansion.

[0101] Further, the operation of the M-order Taylor expansion formula by invoking the first calculation module and the second calculation module can be performed according to the following steps 1331:

[0102] Step 1331: Invoke each calculation unit in the first calculation module and each calculation unit in the second calculation module to perform parallel operations on each order formula in the M-order Taylor expansion formula.

[0103] When the target operation order is further increased to M order (M>N), in addition to the first calculation module, a second calculation module is also enabled. The second calculation module is composed of M-N calculation units, which are responsible for processing the formulas from the N+1 order to the M order in the Taylor expansion formula. Similarly, all calculation units can operate in parallel and cooperate with the first calculation module to complete the calculation of all orders of the M-order Taylor expansion formula. That is, the N calculation units in the first calculation module and the M-N calculation units in the second calculation module are invoked at the same time to perform parallel calculations on the order terms they are responsible for, and finally the normalization operation of the M-order Taylor expansion formula is quickly completed.

[0104] Through the above parallel hardware architecture design, the present scheme can flexibly schedule the calculation resources according to the required Taylor expansion order, effectively balancing the calculation performance and hardware utilization. When the operation order is low, only the first calculation module needs to be enabled to meet the demand; while in high-precision scenarios, through the cooperative parallelism of the two modules, both high efficiency and easy integration and expansion are ensured. In addition, the independent calculation of each order formula also facilitates subsequent hardware optimization, fault isolation and dynamic management, further improving the reliability and maintainability of feature data processing.

[0105] In the present application, the normalization operation on the feature values in the feature vector based on the probability normalization function can also be performed according to the following step 134:

[0106] Step 134, based on the probability normalization function, the normalization operation is performed on each feature value in the feature vector in parallel.

[0107] In the present application, further, in order to improve the overall normalization operation efficiency, the normalization operation of the feature vector can also use parallel processing mechanism.

[0108] Specifically, when the probability normalization is needed for each feature value in the feature vector, not only the high parallel calculation is realized between the Taylor expansion formulas of each order, but also the parallel operation mechanism is introduced between the components of the feature vector. That is, for each feature value in the input feature vector, the normalization operation can be performed in parallel based on the probability normalization function (such as Softmax, etc.). In this way, each component of the feature vector can be assigned to an independent processing unit or operation path, and each processing unit independently completes the corresponding normalization calculation task, thereby realizing the synchronous normalization output of the whole vector.

[0109] This double parallel design, on the one hand, performs the operation of each order term of Taylor expansion in parallel through a large number of parallel calculation units, and on the other hand, realizes multi-path concurrent processing at the component level of the feature vector, which can greatly improve the throughput of the overall normalization task and effectively reduce the delay in the batch data processing scenario. At the same time, this design is very suitable for hardware acceleration implementation, such as deployment on FPGA, ASIC, or special AI chips, which can fully utilize the multi-path data path to realize large-scale, low-delay parallel normalization processing.

[0110] In addition, this scheme makes the normalization module have excellent scalability. No matter how the dimension of the feature vector is expanded, the normalization hardware can expand the number of processing units horizontally as needed, and flexibly adapt to various actual application requirements, including neural network inference, signal processing, data mining and other scenarios, greatly improving the performance and versatility of the overall processing system.

[0111] In order to enable those skilled in the art to better understand the present application, the present application will be described in conjunction with a specific example and its test data.

[0112] In one specific embodiment of the present application, the specific values of the feature value interval and the target order number can be designed according to Table 2 as follows:

[0113] Table 2 Predefined operation expansion instruction example

[0114]

[0115] In the present application, according to the design as shown in Table 2, 512 groups of feature vectors are normalized to obtain the test results as shown in Table 3:

[0116] Table 3 Test results

[0117]

[0118] In the present application, it can be seen from the test results in Table 3 that the delay of the 6-order Taylor expansion scheme is only 0.0000025 seconds, the energy efficiency is 0.5 μJ / inference, and the accuracy is 98.8%; the delay of the 9-order Taylor expansion scheme is slightly higher (0.0000028 seconds), but the accuracy is improved to 99.1%, and the energy efficiency is only 0.7 μJ / inference; compared with the traditional exponential formula, whether the 6-order or 9-order Taylor expansion is significantly better than the exponential scheme, under the premise of ensuring high accuracy, the delay is reduced by more than 40%, and the energy consumption is saved by 40-60%.

[0119] The present scheme realizes hardware acceleration of normalization operation through RISCV extension instructions, greatly simplifies the calling mode, saves multiple layers of function encapsulation, and improves the development efficiency by about 40%; supports dynamic switching of 6-order and 9-order Taylor expansion, under the premise of ensuring controllable accuracy (error less than 0.3% in 9-order mode, and accuracy up to standard in small range in 6-order mode), the 6-order mode saves about 25% of LUT resources compared with the fixed 9-order scheme, and is flexible and adaptive to different power consumption requirements. At the same time, the hardware single instruction can process addition, subtraction, multiplication and division operations in parallel, which is 3 times faster than the traditional loop scheme, and the minimum delay is reduced to 3 cycles; by reusing 0-6 order calculation units, the high-order mode only supplements 7-9 order paths, further saving about 20% of hardware resources, realizing the perfect combination of high efficiency and high flexibility.

[0120] In the present application, the default order can be statically set by software through the order configuration register, which is convenient for adopting the optimal resource configuration in fixed scenarios such as speech recognition.

[0121] In the present application, in the alternative algorithm aspect, the Taylor expansion scheme can be replaced by a 6-order Chebyshev approximation scheme, which can achieve comparable accuracy to the Taylor expansion, but will increase the hardware multiplier resource consumption by about 15%;

[0122] In the present application, the switching of 2 / 4 / 8-order Taylor expansion formula can be supported by the piecewise exponential lookup table method, which has high flexibility, but the BRAM resource occupation is about 40% higher than that of the present scheme.

[0123] The device embodiment of the present application is introduced below, which can be used to execute the feature data processing method based on an edge device in the above-mentioned embodiments of the present application. A neural network model is deployed in the processor of the edge device, and the neural network model includes a convolution network and a probability normalization function. For details not disclosed in the device embodiment of the present application, please refer to the above-mentioned embodiments of the feature data processing method based on an edge device.

[0124] Referring to Figure 3 , a block diagram of the feature data processing device based on an edge device in the embodiments of the present application is shown.

[0125] As Figure 3 shown, the feature data processing device based on an edge device 200 according to the embodiments of the present application includes an acquisition unit 201, a first operation unit 202, and a second operation unit 203.

[0126] The acquisition unit 201 is configured to acquire feature data to be processed. The first operation unit 202 is configured to perform convolution operation on the feature data based on the convolution network to obtain a feature vector of the feature data. The second operation unit 203 is configured to perform normalization operation on a feature value in the feature vector based on the probability normalization function in the case of replacing an exponential algorithm in the probability normalization function with a Taylor expansion algorithm to obtain a probability distribution corresponding to the feature data, which is used for classifying the feature data.

[0127] In some embodiments of the present application, based on the foregoing scheme, the device further includes a determination unit configured to determine a Taylor expansion algorithm of a target order for a probability normalization function processing each feature value in the feature vector before performing normalization operation on the feature value in the feature vector based on the probability normalization function. The Taylor expansion algorithm of the target order is used to replace the exponential algorithm in the probability normalization function, and the target order is adapted to the size of the each feature value.

[0128] In some embodiments of the present application, based on the foregoing scheme, the target order is positively correlated with the size of the each feature value.

[0129] In some embodiments of the present application, based on the foregoing scheme, the determination unit is configured to determine a target operation expansion instruction from a plurality of pre-defined operation expansion instructions according to the each feature value in the feature vector, and determine a Taylor expansion algorithm of a corresponding target order for the probability normalization function processing the each feature value according to the target operation expansion instruction.

[0130] In some embodiments of the present application, based on the foregoing scheme, the determining unit is configured to: if each of the feature values falls into a first feature value interval, determine a first operation extension instruction of a plurality of predefined operation extension instructions as the target operation extension instruction, the target order corresponding to the first operation extension instruction being N order; and if each of the feature values falls into a second feature value interval, determine a second operation extension instruction of the plurality of predefined operation extension instructions as the target operation extension instruction, the target order corresponding to the second operation extension instruction being M order, where M is greater than N, and the minimum value of the second feature value interval is greater than the maximum value of the first feature value interval.

[0131] In some embodiments of the present application, based on the foregoing scheme, the N order is 6 order, and the M order is 9 order.

[0132] In some embodiments of the present application, based on the foregoing scheme, the target operation extension instruction is used to directly call a probability normalization function to perform normalization operation on each of the feature values.

[0133] In some embodiments of the present application, based on the foregoing scheme, the processor comprises a first calculation module and a second calculation module, where the first calculation module is configured to perform operation on the first order algorithm to the N order algorithm in the Taylor expansion algorithm, and the second calculation module is configured to perform operation on the N+1 order algorithm to the M order algorithm in the Taylor expansion algorithm, and the second operation unit 203 is configured to: in the process of performing normalization operation on the feature values in the feature vector based on the probability normalization function, if the target order is N order, call the first calculation module to perform operation on the N order Taylor expansion algorithm; and if the target order is M order, call the first calculation module and the second calculation module to perform operation on the M order Taylor expansion algorithm.

[0134] In some embodiments of the present application, based on the foregoing scheme, the first calculation module comprises N calculation units, and the second operation unit 203 is configured to: call each calculation unit in the first calculation module to perform operation on each order algorithm in the N order Taylor expansion algorithm in parallel.

[0135] In some embodiments of the present application, based on the foregoing scheme, the second calculation module comprises M-N calculation units, and the second operation unit 203 is configured to: call each calculation unit in the first calculation module and each calculation unit in the second calculation module to perform operation on each order algorithm in the M order Taylor expansion algorithm in parallel.

[0136] In some embodiments of the present application, based on the foregoing scheme, the second operation unit 203 is configured to perform normalization operation on each feature value in the feature vector in parallel based on the probability normalization function.

[0137] Based on the same inventive concept, the embodiments of the present application provide a computer program product, which comprises computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to enable a computer device having the processor to perform operations implemented by the edge device based feature data processing method as described above.

[0138] Based on the same inventive concept, the embodiments of the present application provide a computer readable storage medium, which stores at least one computer program instruction, the at least one computer program instruction is loaded and executed by a processor to enable the processor to perform operations implemented by the edge device based feature data processing method as described above.

[0139] Based on the same inventive concept, the embodiments of the present application further provide an electronic device, which refers to Figure 3 , which shows a structural schematic diagram of the electronic device in the embodiments of the present application, the electronic device comprises one or more memories 304, one or more processors 302, and at least one computer program (computer program instructions) stored in the memory 304 and executable on the processor 302, and the processor 302 implements the edge device based feature data processing method as described above when executing the computer program.

[0140] In the above-mentioned edge device based feature data processing method, Figure 3 , a bus architecture (represented by bus 300), the bus 300 can include any number of interconnected buses and bridges, the bus 300 links various circuits including one or more processors represented by processor 302 and memory represented by memory 304. The bus 300 can also link various other circuits such as peripheral devices, voltage stabilizers and power management circuits, which are well known in the art, and therefore, they will not be further described herein. The bus interface 305 provides an interface between the bus 300 and the receiver 301 and the transmitter 303. The receiver 301 and the transmitter 303 can be the same element, i.e. a transceiver, which provides a unit for communicating with various other devices on a transmission medium. The processor 302 is responsible for managing the bus 300 and general processing, while the memory 304 can be used to store data used by the processor 302 in performing operations.

[0141] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transferred over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items prefaced by "comprising" to indicate a disjunctive list means each single item in the list has been recited before "or" one or more additional disjunctive items also have been recited. However, "or" in such a phrase does not mean that the list is inclusive of at least one of the items. Further, as used herein, "comprising" is to be interpreted as including the more restrictive terms "consisting of" and "consisting essentially of."

[0142] In several embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. Among them, the above-mentioned device embodiments are only schematic, for example, the division of the units can be a logical function division, and other division manners can be used in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed units can be indirect coupling or communication connection through some interfaces, units or modules, and can be electrical or other forms.

[0143] The units described as separate components can or can not be physically separated, and the components of the control device can or can not be physical units, i.e. can be located in one place or can be distributed on a plurality of units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0144] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer program instructions.

[0145] The above merely provides an example of the present application, and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall fall into the scope of claims of the present application.

Claims

1. An edge device-based feature data processing method, characterized by, A neural network model is deployed in a processor of the edge device, the neural network model comprising a convolution network and a probability normalization function, and the method comprises: obtaining feature data to be processed; performing convolution operation on the feature data based on the convolution network to obtain a feature vector of the feature data; in a case where an exponential expression in the probability normalization function is replaced by a Taylor expansion expression, determining a target operation expansion instruction from a plurality of pre-defined operation expansion instructions according to each feature value in the feature vector; wherein if the each feature value falls into a first feature value interval, a first operation expansion instruction in the plurality of pre-defined operation expansion instructions is determined as the target operation expansion instruction, and a target order corresponding to the first operation expansion instruction is Nth order; if the each feature value falls into a second feature value interval, a second operation expansion instruction in the plurality of pre-defined operation expansion instructions is determined as the target operation expansion instruction, and a target order corresponding to the second operation expansion instruction is Mth order, where M is greater than N, and a minimum value of the second feature value interval is greater than a maximum value of the first feature value interval; determining a Taylor expansion expression of a corresponding target order for the probability normalization function processing the each feature value according to the target operation expansion instruction, the Taylor expansion expression of the target order being used to replace the exponential expression in the probability normalization function, and the target order being adapted to the size of the each feature value; performing normalization operation on the feature value in the feature vector based on the probability normalization function to obtain a probability distribution corresponding to the feature data, and the probability distribution being used for classifying the feature data; the processor comprises a first calculation module and a second calculation module, the first calculation module comprises N calculation units, the first calculation module is used for performing operation on 1st order expression to Nth order expression in the Taylor expansion expression, the second calculation module comprises M-N calculation units, the second calculation module is used for performing operation on N+1th order expression to Mth order expression in the Taylor expansion expression, and in the process of performing normalization operation on the feature value in the feature vector based on the probability normalization function, if the target order is Nth order, each calculation unit in the first calculation module is called to perform operation on each order expression in the Nth order Taylor expansion expression in parallel, and if the target order is Mth order, each calculation unit in the first calculation module and each calculation unit in the second calculation module are called to perform operation on each order expression in the Mth order Taylor expansion expression in parallel.

2. The method of claim 1, wherein, The target order is positively correlated with the size of the each feature value.

3. The method of claim 1, wherein, The Nth order is 6th order, and the Mth order is 9th order.

4. The method of claim 1, wherein, The target operation expansion instruction is used for directly calling the probability normalization function to perform normalization operation on the each feature value.

5. The method of claim 1, wherein, The normalization operation on the feature value in the feature vector based on the probability normalization function comprises: performing normalization operation on each feature value in the feature vector in parallel based on the probability normalization function.

6. An edge device based feature data processing apparatus, characterized by, The processor of the edge device is deployed with a neural network model, the neural network model comprises a convolution network and a probability normalization function, and the device comprises: An acquisition unit is configured to acquire feature data to be processed. A first operation unit is configured to perform convolution operation on the feature data based on the convolution network to obtain a feature vector of the feature data. A second operation unit is configured to determine a target operation expansion instruction from a plurality of pre-defined operation expansion instructions according to each feature value in the feature vector in a case where an exponential expression in the probability normalization function is replaced by a Taylor expansion expression; if the each feature value falls into a first feature value interval, a first operation expansion instruction in the plurality of pre-defined operation expansion instructions is determined as the target operation expansion instruction, and a target order corresponding to the first operation expansion instruction is N order; if the each feature value falls into a second feature value interval, a second operation expansion instruction in the plurality of pre-defined operation expansion instructions is determined as the target operation expansion instruction, and a target order corresponding to the second operation expansion instruction is M order, where M is greater than N, and a minimum value of the second feature value interval is greater than a maximum value of the first feature value interval; a Taylor expansion expression of a corresponding target order is determined for the probability normalization function processing the each feature value according to the target operation expansion instruction, the Taylor expansion expression of the target order is used to replace the exponential expression in the probability normalization function, and the target order is adapted to the size of the each feature value; and a normalization operation is performed on the feature value in the feature vector based on the probability normalization function to obtain a probability distribution corresponding to the feature data, and the probability distribution is used to classify the feature data. The processor comprises a first calculation module and a second calculation module, the first calculation module comprises N calculation units, the first calculation module is configured to perform operation on a first order expression to an N order expression in the Taylor expansion expression, the second calculation module comprises M-N calculation units, the second calculation module is configured to perform operation on an N+1 order expression to an M order expression in the Taylor expansion expression, and in the process of performing normalization operation on the feature value in the feature vector based on the probability normalization function, if the target order is N order, each calculation unit in the first calculation module is called to perform operation on each order expression in the N order Taylor expansion expression in parallel; and if the target order is M order, each calculation unit in the first calculation module and each calculation unit in the second calculation module are called to perform operation on each order expression in the M order Taylor expansion expression in parallel.

7. A computer program product, characterised in that, The computer program product comprises computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to enable a computer device with the processor to perform the method of any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one program code, the at least one program code is loaded and executed by the processor to implement the operations performed by the method of any one of claims 1 to 5.

9. An electronic device, comprising: The electronic device includes one or more processors and one or more memories, the one or more memories store at least one program code, the at least one program code is loaded and executed by the one or more processors to implement the method of any one of claims 1 to 5.

Images