Simulation method, device and equipment of multi-core system on chip, and readable storage medium

Abstract

The application provides a simulation method and device of a multi-core system on chip, electronic equipment and a computer readable storage medium, comprising: obtaining a simulation design file of each first processor core in the multi-core system on chip; the simulation design file is written by a preset hardware compiling language; compiling the simulation design file of each first processor core to obtain a dynamic link library comprising a dynamic link file corresponding to each first processor core; the dynamic link file is written by a preset software compiling language; connecting the dynamic link library with a top module of the multi-core system on chip to realize simulation of the multi-core system on chip; the top module of the multi-core system on chip is used for realizing interconnection between modules of the multi-core system on chip, external interface definition and global control. The processor core model in the dynamic link library can be integrated with the system on chip, full system function simulation is realized, and the simulation efficiency of the multi-core system on chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a simulation method and device of a multi-core system on chip, an electronic device and a computer readable storage medium. BACKGROUND

[0002] Before the chip is physically implemented, the multi-core system on chip of the chip can be simulated and verified, and the abnormality in multi-core cooperation can be reproduced through simulation to locate the defects of hardware design or software algorithm.

[0003] In the related art, the hardware behavior of the multi-core system on chip can be simulated through field programmable gate array or Parallax simulation resources, or the logic behavior, timing characteristics or system running process of the hardware can be simulated through software tools to implement simulation and verification of the multi-core system on chip.

[0004] However, the simulation and verification method of the multi-core system on chip in the related art consumes more resources and has low simulation efficiency. SUMMARY

[0005] Embodiments of the present application provide a simulation method and device of a multi-core system on chip, an electronic device and a computer readable storage medium to solve the problems in the related art.

[0006] In a first aspect, a simulation method of a multi-core system on chip is provided, and the method comprises the following steps:

[0007] Obtaining simulation design files of each first processor core in the multi-core system on chip; the simulation design files are written by using a preset hardware compilation language;

[0008] Compiling the simulation design files of each first processor core to obtain a dynamic link library comprising dynamic link files corresponding to each first processor core; the dynamic link files are written by using a preset software compilation language;

[0009] Connecting the dynamic link library with a top module of the multi-core system on chip to implement simulation of the multi-core system on chip; the top module of the multi-core system on chip is used to implement interconnection between modules of the multi-core system on chip, external interface definition and global control.

[0010] In a second aspect, a simulation device of a multi-core system on chip is provided, and the device comprises an obtaining module, a compiling module and a simulation module.

[0011] The obtaining module is configured to obtain simulation design files of each first processor core in the multi-core system on chip; the simulation design files are written by using a preset hardware compilation language;

[0012] The compiling module is configured to compile the simulation design file of each first processor core to obtain a dynamic link library including dynamic link files corresponding to each first processor core; and the dynamic link files are written by using a preset software compiling language;

[0013] The simulation module is configured to connect the dynamic link library with a top module of the multi-core system on chip to implement simulation of the multi-core system on chip; and the top module of the multi-core system on chip is configured to implement interconnection between modules of the multi-core system on chip, external interface definition and global control.

[0014] In a third aspect, an electronic device is provided, including a processor;

[0015] a memory for storing the processor-executable instructions;

[0016] The processor is configured to execute the instructions to implement the method of the first aspect.

[0017] In a fourth aspect, a computer-readable storage medium is provided, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method of the first aspect.

[0018] The embodiment of the present application can reduce compatibility problems caused by code style differences, facilitate version control and document management by obtaining the simulation design file of each first processor core in the multi-core system on a chip, and limiting the simulation design file to be written by a preset hardware compiling language. The hardware description language can accurately depict the timing logic, pipeline structure and instruction set behavior of the processor core, and ensure the consistency of the simulation model and the physical implementation. The simulation design file of each first processor core is compiled to obtain a dynamic link library including the dynamic link files corresponding to each first processor core, and the dynamic link file is limited to be written by a preset software compiling language, so that the simulation design file can be compiled into a dynamic link library, the software packaging of the hardware model is realized by the preset software compiling language, and the processor core can be integrated with the software test platform. The dynamic link library includes the dynamic link file, that is, the target language model, and the multi-core system on a chip is simulated by running the target language model, which can reduce the hardware resources consumed by simulation, and the dynamic link library supports on-demand loading at runtime, allows flexible replacement of the processor core model during simulation without recompiling the entire system, which can further reduce the resources consumed by simulation, and can adapt to various simulation tools to solve the difference in hardware language support of different simulation tools, realize the standardization of the verification process. The software compiling language has high execution efficiency, and the dynamic link library can accelerate the function verification of the processor core. Finally, the dynamic link library is connected with the top module of the multi-core system on a chip, the top module defines the interconnection relationship between modules through a bus protocol, the processor core model in the dynamic link library is integrated with the system on a chip, the full-system function simulation is realized, and the simulation efficiency of the multi-core system on a chip is improved.

[0019] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0021] Figure 1 is a step flow chart of a simulation method of a multi-core system on a chip provided by the embodiment of the present application;

[0022] Figure 2 is an architecture schematic diagram of a multi-core system on a chip provided by the embodiment of the present application;

[0023] Figure 3 is a step flowchart of another simulation method of a multi-core system on chip provided by an embodiment of the present application;

[0024] Figure 4 is a simulation model integration schematic diagram of a multi-core system on chip provided by an embodiment of the present application;

[0025] Figure 5 is a simulation structure schematic diagram of a multi-core system on chip provided by an embodiment of the present application;

[0026] Figure 6 is a block diagram of a simulation device of a multi-core system on chip provided by an embodiment of the present application;

[0027] Figure 7 is a block diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0029] The terms "first", "second", and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a category, and are not limited to the number of objects, for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects. The term "multiple" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0030] Before the chip is physically implemented, the multi-core system on chip of the chip can be simulated and verified, and the exception in multi-core cooperation can be reproduced through simulation to locate the defects of hardware design or software algorithm.

[0031] In the related art, the hardware behavior of a multi-core system-on-chip can be simulated by using a field-programmable gate array or a Parlay simulation resource, or the logic behavior, timing characteristics or system running process of the hardware can be simulated by using a software tool to implement simulation verification of the multi-core system-on-chip.

[0032] However, the simulation verification method for the multi-core system-on-chip in the related art consumes a large amount of resources and has low simulation efficiency.

[0033] Exemplarily, the hardware behavior of a multi-core system-on-chip is simulated by using a field-programmable gate array or a Parlay simulation resource. A target hardware design is mapped to a field-programmable gate array (FPGA) chip, and a hardware prototype is constructed by using the programmable logic resources of the FPGA to directly run the software (for example, an operating system and an application program) of the target system and simulate the running environment of the real hardware. The target hardware design can include register transfer level (RTL) code of a multi-core system-on-chip (SoC).

[0034] In this background, the embodiment of the present application provides a simulation method of a multi-core system-on-chip, which can reduce the resources consumed by simulation and improve the simulation efficiency.

[0035] Figure 1 is a step flowchart of a simulation method of a multi-core system-on-chip provided by the embodiment of the present application. As shown in Figure 1 , the method can include steps 101-103.

[0036] Step 101: Obtain a simulation design file of each first processor core in the multi-core system-on-chip.

[0037] In the embodiment of the present application, the multi-core system-on-chip includes a plurality of first processor cores (cores). Figure 2 is an architecture schematic diagram of a multi-core system-on-chip provided by the embodiment of the present application. As shown in Figure 2As shown, the multi-core system on chip includes a multi-core cluster, a network on chip bus (NOC BUS), a memory-mapped input / output (MMIO), a double data rate (DDR) memory, a flexible network on chip (FLEX NOC) which can represent a network on chip technology with specific characteristics and functions. The multi-core cluster includes a plurality of processor cores, which can be 16, 32 or 64. The simulation design file is written in a preset hardware compilation language. For example, the simulation design file can include register transfer level (RTL) code written in a preset hardware description language, which describes the internal structure and behavior of the processor core, i.e., the RTL code of the processor core. The preset hardware description language can include Verilog hardware description language (Verilog) or VHSIC hardware description language (VHDL). The RTL code of the processor core can cover the core functions of the processor's instruction set architecture, data path, control logic, memory hierarchy, etc. through the description of combinational logic and sequential logic.

[0038] For example, the RTL code of the processor core can describe the instruction decoder, the immediate number generator, the register file, the data path, the control logic, the instruction memory and the cache controller of the processor core. When describing the instruction decoder, the content of the RTL code can include instruction format, decoding logic (such as addition, subtraction, load or store, etc.), decoding processing for special instructions (such as interrupt instructions, privileged instructions, etc.). The instruction format can include register (R) type instructions, immediate (I) type instructions and jump (J) type instructions. The R type instructions are mainly used for operations between registers (such as addition, logical operation), and need to specify multiple registers; the I type instructions are mainly used for operations between registers and immediate numbers or memory access instructions (such as loading data), and need to include an immediate number; the J type instructions are mainly used for unconditional jump instructions, and need to include a jump target address. The content of the RTL code describing the immediate number generator can include immediate number field extraction logic and expansion logic (such as expanding a 12-bit immediate number to 32 bits) of different types of instructions.

[0039] Step 102, compile the simulation design file of each first processor core to obtain a dynamic link library including a dynamic link file corresponding to each first processor core.

[0040] In the embodiments of the present application, the dynamic link file is written by a preset software compiling language. The simulation design file of each first processor core can be compiled by a simulator (for example, a verilator simulator), the RTL of each first processor core is compiled into a target language model, and then the target language model of each first processor core is processed to obtain a dynamic link library including the target language model corresponding to each first processor core, that is, a dynamic link library including the dynamic link file corresponding to each first processor core. The target language can include C language or C++ language, etc. The target language model can be understood as an abstract model written by a software compiling language and compiled into a dynamic link library, which is usually a transaction level or a functional level model.

[0041] Exemplarily, the simulation design file can be preprocessed first, for example, expanding header files, processing macro definitions, etc. Then a hardware description language compiler, for example, a verilog compiled simulator (VCS), a Questa simulator, a ModelSim, etc. can be used to compile the simulation design file. The compiler will convert the hardware description language code into an intermediate representation, that is, a dynamic link file. For example, a gate level netlist or an abstract simulation model (such as a C language model or a C++ language model). After compilation, a target file corresponding to the processor core can be generated. These target files contain executable code or simulatable model data of the processor core. The above dynamic link file is a kind of target file, which contains unresolved external symbol references. These symbol references point to functions, variables, etc. defined in other modules or libraries. During simulation runtime, the dynamic linker will load the corresponding modules or libraries into memory according to these symbol references, and resolve the symbol references, so that the program can be executed correctly. The dynamic link library is a collection of multiple dynamic link files. It is a shareable binary file that contains code and data that can be dynamically loaded and linked at runtime by multiple programs or modules. When generating a dynamic link library, a linker is needed to link each target file together and specify some linking options, such as generating position-independent code (PIC), etc. In the Linux system, the file extension of the dynamic link library is.so, and in the Windows system, the file extension of the dynamic link library is.dll.

[0042] In step 103, the dynamic link library is connected with the top module of the multi-core system on a chip to realize simulation of the multi-core system on a chip.

[0043] In the embodiments of the present application, the multi-core system on a chip includes a top module. The top module of the multi-core system on a chip is used to realize interconnection between modules of the multi-core system on a chip, external interface definition and global control.

[0044] Exemplarily, the multi-core SoC contains multiple modules with different functions, such as a central processing unit (CPU) core, a graphic processing unit (GPU), a neural network processing unit (NPU), a memory controller, various peripheral interfaces, and the like. A top-level module is responsible for connecting and integrating these modules according to design requirements, so that they can communicate and work together. Exemplarily, the CPU core is connected with the memory controller through a high-speed bus to ensure that the CPU can quickly access data in the memory; various peripheral interfaces are connected with a system bus to realize communication with external devices. The above high-speed bus can include an advanced extensible interface (AXI) of an advanced microcontroller bus architecture (AMBA); the above peripheral interface can include a universal serial bus (USB), an Ethernet, and the like.

[0045] The simulation design file of each first processor core in the multi-core system on chip is acquired, and it is defined that the simulation design file is written by a preset hardware compiling language, so that compatibility problems caused by code style differences can be reduced, and version control and document management are facilitated. The hardware description language can accurately depict the timing logic, pipeline structure and instruction set behavior of the processor core, and ensure the consistency of the simulation model and the physical implementation. The simulation design file of each first processor core is compiled to obtain a dynamic link library including dynamic link files corresponding to each first processor core, and it is defined that the dynamic link files are written by a preset software compiling language, so that the simulation design file can be compiled into the dynamic link library, the software packaging of the hardware model is realized by the preset software compiling language, and the processor core can be integrated with the software test platform. The dynamic link library includes the dynamic link files, i.e. the target language model, and the multi-core system on chip is simulated by running the target language model, which can reduce the hardware resources consumed by simulation, and the dynamic link library supports on-demand loading at runtime, allows flexible replacement of the processor core model during simulation without recompiling the entire system, which can further reduce the resources consumed by simulation, and can adapt to various simulation tools to solve the difference in hardware language support of different simulation tools and realize the standardization of the verification process. The software compiling language has high execution efficiency, and the dynamic link library can accelerate the function verification of the processor core. Finally, the dynamic link library and the top module of the multi-core system on chip are connected, the interconnection relationship between the modules is defined by the bus protocol, the processor core model in the dynamic link library is integrated with the system on chip, the full-system function simulation is realized, and the simulation efficiency of the multi-core system on chip is improved.

[0046] Figure 3 is a step flow chart of another simulation method of a multi-core system on chip provided by the embodiment of the present application. As shown in Figure 3 the method can include steps 301-303.

[0047] Step 301, acquiring simulation design files of each first processor core in a multi-core system on chip; the simulation design files are written by a preset hardware compiling language.

[0048] Step 302, compiling the simulation design files of each first processor core to obtain a dynamic link library including dynamic link files corresponding to each first processor core; the dynamic link files are written by a preset software compiling language.

[0049] Step 303, connecting the dynamic link library and the top module of the multi-core system on chip to realize simulation of the multi-core system on chip; the top module of the multi-core system on chip is used to realize interconnection between modules of the multi-core system on chip, definition of external interfaces and global control.

[0050] The specific implementation of steps 301-303 above can be referred to the aboveFigure 1 Embodiments, which will not be described again here.

[0051] Optionally, the simulation method of the multi-core system on chip can further include steps 304-306.

[0052] Step 304, selecting any first processor core from the processor cores of the multi-core system on chip as a second processor core.

[0053] Step 305, performing hardware simulation on the second processor core according to the simulation design file of the second processor core to obtain a hardware simulation model of the second processor core.

[0054] In the embodiments of the present application, for steps 304-305, any first processor core can be selected from the processor cores of the multi-core system on chip as a second processor core. The simulation design file of the selected second processor core is compiled and simulated by a hardware simulation tool to finally generate a hardware simulation model of the processor core. The hardware simulation model can be understood as a register transfer level model written based on a hardware description language, which accurately describes the logical structure, signal timing and data flow of the circuit (such as register rollover, combinational logic calculation, etc.), and is a hardware level model close to physical implementation. The simulation process simulates the logical behavior of the processor core (such as instruction execution, register read / write, interrupt response, etc.), and can output timing waveforms, log files, etc. for analysis. The hardware simulation model is a digital abstraction of the physical behavior of the processor core, which can be used for subsequent functional verification, performance analysis or system-level integration.

[0055] For example, the RTL code written in Verilog / VHDL can be used to accurately simulate its timing and logical behavior in a simulator. The simulation design file of the second processor core is compiled using a simulation tool to convert the hardware description language code into a format that the simulation tool can understand and execute. Syntax errors and logical errors in the code will be checked during the compilation process, and if there are errors, they need to be corrected in time. In order to comprehensively verify the function of the second processor core, a test platform needs to be written. The test platform is a piece of code that generates excitation signals and monitors the output response of the processor core to verify whether it runs according to the expected function. The test platform can be written in hardware description language or other languages supported by the simulation tool.

[0056] The compiled simulation design file and the test platform are loaded into the simulation tool together, simulation parameters (such as simulation time, clock frequency, etc.) are set, and then the simulation is started. The simulation tool simulates the operation of the second processor core according to the excitation signal generated by the test platform, and outputs the simulation results such as waveform diagram, log file, etc. By viewing the simulation results such as waveform diagram, log file, etc., whether the function of the second processor core is correct, whether there is a timing problem, a logic error, etc. If a problem is found, the simulation design file or the test platform needs to be returned for modification, and then the simulation is performed again until the function of the second processor core meets the design requirements. After the simulation verification is passed, the simulation tool may generate a corresponding hardware simulation model, which can be used for subsequent system-level simulation, performance analysis, or collaborative simulation with other components, etc.

[0057] In step 306, the hardware simulation model of the second processor core is connected with the top module of the multi-core system on a chip, and the dynamic link library is connected with the top module of the multi-core system on a chip, so as to realize the simulation of the multi-core system on a chip.

[0058] In the embodiments of the present application, the hardware simulation model of the second processor core and the dynamic link library can be distinguished according to the compilation language (for example, the compilation language of the hardware simulation model of the second processor core is a hardware compilation language, and the compilation language of the dynamic link library is a software compilation language), the file form (for example, the file form of the hardware simulation model of the second processor core is a source code file, and the file form of the dynamic link library is a binary library file), the core information, the interface form, etc.

[0059] Exemplarily, Figure 4 is a simulation model integration schematic diagram of a multi-core system on a chip provided by an embodiment of the present application. As shown in Figure 4As shown, the hardware simulation model of the second processor core is connected with the top module of the multi-core system on chip through a hardware interface module (interface), and the dynamic link library of the first processor core is connected with the top module of the multi-core system on chip through an interconnection interface module (INTF), so as to realize simulation of the multi-core system on chip. The hardware simulation model of the second processor core is connected with the top module of the multi-core system on chip through the interface, and it can also be understood that the hardware simulation model of the second processor core is integrated into the SoC through the interface. The interface is a hardware interface module defined in a hardware description and verification language (SystemVerilog, HDVL), which includes signal ports (such as clock, reset, data bus, control signal, etc.) and interaction protocols. The hardware simulation model of the second processor core can be connected with the interface of the top module through its own port, so as to realize direct interconnection of signals. For example, the data input port of the hardware simulation model of the second processor core is connected to the data bus signal of the top interface, and the interrupt output port of the hardware simulation model of the second processor core is connected to the interface of the top interrupt controller, so that the signal timing is strictly matched (for example, clock edge synchronization, setup or hold time meets the constraints).

[0060] In this embodiment, any first processor core is selected from the processor cores of the multi-core system on chip as the second processor core, and a hardware simulation model of the second processor core is obtained by performing hardware simulation on the second processor core according to the simulation design file of the second processor core. Hardware simulation can verify the functional correctness of the processor core in the design stage, such as detecting hardware-level problems such as instruction execution conflict and interrupt response delay, avoiding fatal defects found after physical chip tape-out, and greatly reducing iteration cost. Selecting one processor core as a real core for hardware simulation can quickly determine whether the problem is caused by the core itself (such as design defects) or the interaction between cores (such as bus conflict), simplify the debugging process, and improve simulation efficiency. Before the chip is taped out, the functional correctness of the processor core can be comprehensively verified through the hardware simulation model. The hardware simulation model of the second processor core is connected with the top module of the multi-core system on chip, and the dynamic link library is connected with the top module of the multi-core system on chip, so as to realize simulation of the multi-core system on chip. The hardware simulation model can be directly used for new simulation verification, reducing repeated development work and improving design efficiency.

[0061] Optionally, the above step 302 can include sub-steps 3021-3022.

[0062] Sub-step 3021: performing bit width splitting on the first hardware signal in the simulation design file of each first processor core to obtain a processed simulation design file.

[0063] In the embodiment of the present application, the first hardware signal can represent a top-level hardware signal of the first processor core, and the top-level hardware signal is a hardware interface signal for interaction between the first processor core and a core hardware signal (for example, a data bus, an address bus, a memory controller, etc.) of an external module. By bit-width splitting (for example, splitting a 32-bit signal into four 8-bit signals), the adaptation of the wide-bit signal and the narrow-bit interface can be realized at the functional level, without the need to modify the underlying hardware logic, thereby ensuring that the processor core model can work with external modules of different bit widths.

[0064] Sub-step 3022: Compiling the processed simulation design file corresponding to each first processor core to obtain a dynamic link library including a dynamic link file corresponding to each first processor core.

[0065] In the embodiment of the present application, the processed simulation design file is adapted to the hardware interface, and its data structure can be consistent with a hardware description language (HDL) interface of a top-level module of the SoC at the bit level. Compiling the processed simulation design file corresponding to each first processor core can be understood as using an automated tool chain (for example, a script, a compiler plug-in, or a special tool) to compile and package the processed simulation design file to obtain a dynamic link file of each first processor core. The dynamic link files of the first processor cores are linked into a dynamic link library, for example, a plurality of object files are linked into a.so or.dll file.

[0066] In the embodiment, the first hardware signal in the simulation design file of each first processor core is split by bit width to obtain a processed simulation design file, and then the processed simulation design file corresponding to each first processor core is compiled to obtain a dynamic link library including a dynamic link file corresponding to each first processor core. This can make the interface of the dynamic link file completely match the signal bit width and structure in the HDL simulator, and facilitate data exchange through a direct programming interface (DPI). Meanwhile, the consistent interface logic can reduce the adaptation cost of cross-stage verification, reduce resource waste caused by excessive bit width, and reduce the situation of simulation failure caused by mismatched bit width.

[0067] Optionally, sub-step 3021 can include sub-steps 30211-30212.

[0068] Sub-step 30211: Determining a first bit width of the first hardware signal, a second bit width matched with the dynamic link file, and a numerical relationship between the first bit width and the second bit width.

[0069] In the embodiments of the present application, the first bit width is the inherent bit width of the first hardware signal, which is determined by the hardware design of the first processor core and can be extracted from the original simulation design file of each first processor core.

[0070] The second bit width can represent the signal bit width adapted to the dynamic link file, and needs to match the bit width requirements of the interface functions of the dynamic link library and external modules (such as peripherals and other processor cores). The second bit width is determined by the application scenario of the dynamic link file, mainly based on the interface requirements of external modules, the processing capacity of software functions (for example, the uint8_t type in C language corresponds to 8 bits), simulation efficiency requirements, etc.

[0071] The numerical relationship between the first bit width and the second bit width can be understood as: the first bit width = N x the second bit width, where N is a positive integer, that is, the first bit width is an integer multiple of the second bit width, for example, 32 = 4 x 8, at this time N = 4, which ensures that the signal can be completely split without bit loss.

[0072] The sub-step 30212 splits the first hardware signal into a plurality of second hardware signals according to the numerical relationship between the first bit width and the second bit width, to obtain a processed simulation design file; the bit width of each second hardware signal is the second bit width.

[0073] In the embodiments of the present application, based on the numerical relationship determined in the first step: the first bit width = N x the second bit width, the first hardware signal can be split into N independent second hardware signals according to the bit sequence, the bit width of each second hardware signal is the second bit width, and the signal definition, connection logic and interaction protocol in the simulation design file are updated.

[0074] For example, the first hardware signal is 32-bit data_bus[31:0], the first bit width = 32, and the second bit width is 8; after splitting the first hardware signal, four 8-bit second hardware signals are obtained; the simulation design file is updated synchronously, and the read-write logic of the original signal is changed to operation on the sub-signals and the connection with the external module is adjusted.

[0075] The embodiment determines a first bit width of the first hardware signal, a second bit width matched with the dynamic link file, and a numerical relationship between the first bit width and the second bit width, splits the first hardware signal into a plurality of second hardware signals according to the numerical relationship between the first bit width and the second bit width, and obtains a processed simulation design file, so that function parameter transmission can be facilitated, the splitting feasibility can be improved, the second hardware signals after splitting can be directly connected with external modules of different bit widths, and the second hardware signals after splitting can be ensured to be completely consistent with the original first hardware signal according to the bit sequence, so that the signal function is ensured to be unchanged before and after splitting, logic errors caused by bit sequence disorder are reduced, function loss is avoided, the verification of the numerical relationship can ensure that all bits of the first hardware signal can be completely split into the second hardware signals without bit loss or redundancy, the integrity of the signal function is ensured, a quantitative basis is provided for splitting, consistency is ensured, and the problem of incompatibility between the signal after subsequent splitting and the interface can be avoided, and additional bit width conversion logic is reduced.

[0076] Optionally, the step 303 can include a sub-step 3031.

[0077] The sub-step 3031 connects the dynamic link library and the multi-core system on chip through the interconnection interface module to implement simulation on the multi-core system on chip.

[0078] In the embodiment of the application, the interconnection interface module is used to realize the consistency of the compiled language of the dynamic link library and the multi-core system on chip. The core function of the interconnection interface module can be understood as a translation layer, which realizes the consistency of the compiled language of the dynamic link library and the multi-core system on chip by unifying the data type, adapting the interaction mode, and synchronizing the timing model, and then completes the connection of the dynamic link library and the multi-core system on chip to support system-level simulation.

[0079] For example, the INTF can abstract the processor core as a C function by calling the C language model of the dynamic link library, import the C language model top-level abstraction function of the processor core and the integrated signal of the SoC in a direct programming interface for C (DPI-C) mode for intercommunication, and the INTF module also samples the integrated signal of the SoC to send data to the C language model of the processor core.

[0080] The embodiment connects the dynamic link library and the multi-core system on chip through the interconnection interface module, can ignore the underlying timing details, improve the simulation speed, and make the dynamic link library and the hardware module (for example, an RTL core and a peripheral) directly interact through the INTF module as a translation layer to realize collaborative simulation of hardware behavior and software running. The dynamic link library can also include software logic, such as an operating system kernel and a driver.

[0081] Optionally, the above-mentioned sub-step 3031 can include sub-steps 30311-30313.

[0082] Sub-step 30311, sampling, by the interconnection interface module, a first integrated signal of the multi-core system on chip, and sending the first integrated signal to the dynamic link library.

[0083] In the embodiments of the present application, the INTF can capture the first integrated signal of the multi-core SoC in real time through the standardized interface, and the first integrated signal can include clock, data bus, control instruction, etc., such as memory access request, interrupt trigger signal, cache coherence message, etc. The first integrated signal sampled is sent to the dynamic link library.

[0084] Sub-step 30312, generating a first response signal according to the first integrated signal.

[0085] In the embodiments of the present application, the C / C++ code in the dynamic link library, i.e. the C language model or test platform logic of the processor core, can perform logical processing on the received first integrated signal to generate a corresponding response signal. After receiving the signal through the interface, the dynamic link library can call the algorithm model (for example, digital signal processing, control logic) written in C / C++ to generate the response signal. For example, in photovoltaic system simulation, the dynamic link library can implement a maximum power point tracking algorithm to calculate the optimal duty cycle.

[0086] Illustratively, when the dynamic link library receives a memory write request, it can update the simulated memory array in the C language model of the dynamic link library; when the dynamic link library receives an interrupt request, it can set the interrupt flag bit in the C language model and prepare to return the interrupt vector; when the dynamic link library receives a cache invalidation request, it can mark the corresponding cache line as invalid in the C language model; when the dynamic link library receives a performance event, it can record a log or trigger a debugging action.

[0087] Sub-step 30313, obtaining, by the interconnection interface module, the first response signal, and obtaining the simulation test result of the multi-core system on chip according to the first response signal.

[0088] In the embodiments of the present application, after the C language model generates a response signal, the response signal can be written back to the interconnection interface module through a reverse DPI call. The response signal generated by the dynamic link library can be returned to the multi-core SoC through the INTF to update the simulation state. For example, in vehicle dynamics simulation, the dynamic link library simulates sensor feedback, and the INTF injects the signal into the control module of the SoC to verify the closed-loop control logic. The dynamic link library can also have built-in assertion checks to automatically compare simulation output with expected results. For example, the simulation tool ModelSim of HDL can call dynamic link library functions through a foreign language interface (FLI) interface to report functional errors in real time and improve test coverage.

[0089] The simulation test results described above can be obtained in various ways, for example, by waveform analysis to view whether the signal timing meets the expected simulation test results; by log output, C language model output debug information to obtain simulation test results; by coverage statistics, statistics of the number of times of triggering various events, such as interrupt frequency, cache hit rate, etc., to obtain simulation test results.

[0090] In the embodiments, the interconnection interface module samples the first integrated signal of the multi-core system on a chip, and sends the first integrated signal to the dynamic link library, generates a first response signal according to the first integrated signal, acquires the first response signal through the interconnection interface module, and obtains the simulation test results of the multi-core system on a chip according to the first response signal. The correctness of the hardware logic and the effectiveness of the software logic can be verified at the same time, the lengthy logic written in the hardware description language is avoided, and the development difficulty of the verification platform is reduced. The interconnection interface module can sample the key signals inside the multi-core SoC, and in combination with the dynamic link library, can quickly locate hidden logic vulnerabilities, can simulate real-time feedback of software to hardware events in a real environment, makes the simulation closer to the actual running scene, and the test results have more reference value.

[0091] Optionally, the substep 30311 can include substeps 303111-303113.

[0092] The substep 303111 samples, through the interconnection interface module, a first integrated signal of a multi-core system on a chip.

[0093] In the embodiments of the present application, the first integrated signal exists in the hardware description language environment, such as Verilog / SystemVerilog. The interconnection interface module can capture the timing, value or state of these signals at a preset frequency (such as system clock division) or triggering condition (such as signal jump, abnormal event) through hardware connection or logic port.

[0094] Sub-step 303112, converting the compiling language of the first integrated signal into a compiling language matching the dynamic link library to obtain a second integrated signal.

[0095] In the embodiment of the present application, the signal on the hardware side is usually in the format of hardware description language, and is expressed as bit vector, register value, timing signal and other hardware native data structures. The dynamic link library on the software side is usually written in software general programming language (such as C language, C++ and the like), and depends on integer, structure, array and other software data types. The dynamic link library is generated by C / C++ compilation and can only understand the data types of C / C++, and cannot recognize the hardware description language. The mapping of hardware format to software format is realized through the interface tool, so that the compiling language of the first integrated signal is compatible with the dynamic link library, and the second integrated signal is obtained.

[0096] Exemplarily, the 32-bit bit vector [31:0] of Verilog can be converted into uint32_t integer of C language; and the active period and transition edge of the hardware timing signal are converted into a time stamp + state marker structure body recognizable by software.

[0097] Sub-step 303113, sending the second integrated signal to the dynamic link library.

[0098] In the embodiment of the present application, the converted second integrated signal can be transmitted to the dynamic link library by the INTF module in the manner of DPI-C.

[0099] Exemplarily, in the simulation environment, the C function is directly called through the DPI-C interface, and the second integrated signal is transmitted into the dynamic link library as a function parameter.

[0100] The embodiment samples the first integrated signal of the multi-core system on a chip through the interconnection interface module, converts the compiling language of the first integrated signal into a compiling language matching the dynamic link library to obtain a second integrated signal, and sends the second integrated signal to the dynamic link library. The hardware native signal can be mapped into a format processable by software, so that the dynamic link library can correctly analyze the signal meaning, and generate a targeted response signal based on the signal content, and then the interconnection interface module acts on the SoC, so that real-time interactive verification is realized.

[0101] Optionally, the above sub-step 30313 can include sub-steps 303131-303133.

[0102] Sub-step 303131, obtaining the first response signal through the interconnection interface module.

[0103] In the embodiment of the present application, the interconnection interface module receives the first response signal from the dynamic link library, and the first response signal is the software-side feedback generated by the dynamic link library after processing the second integrated signal, which may include control instructions, verification incentives or state markers, etc.

[0104] The substep 303132 converts the compiled language of the first response signal into a compiled language matched with the multi-core system on a chip to obtain a second response signal.

[0105] In the embodiment of the present application, the first response signal is data in a general programming language format, and the hardware logic of the multi-core system on a chip is implemented based on a hardware compiled language, which can only recognize hardware native formats such as bit vectors, register signals and timing pulses. The mapping from the software format to the hardware format can be realized through the interface tool.

[0106] For example, the int control_cmd = 5 (decimal) in C language can be converted into 8'b00000101 (8-bit bit vector) in Verilog; and the address + data in the software structure can be split into address bus signals and data bus signals recognizable by hardware.

[0107] The substep 303133 obtains the simulation test result of the multi-core system on a chip according to the second response signal.

[0108] In the embodiment of the present application, after receiving the second response signal, the multi-core system on a chip can finally output quantifiable simulation test results through the execution or state change of the hardware logic.

[0109] In this embodiment, the first response signal is obtained through the interconnection interface module, and the compiled language of the first response signal is converted into a compiled language matched with the multi-core system on a chip to obtain a second response signal, and then the simulation test result of the multi-core system on a chip is obtained according to the second response signal. This can ensure correct analysis of the software feedback by the hardware, reduce verification deviation caused by signal distortion, and improve the interactivity, accuracy and efficiency of the simulation test.

[0110] Figure 5 is a simulation structure schematic diagram of a multi-core system on a chip provided by the embodiment of the present application. As shown in Figure 5 , Figure 5 a 16-core SOC is schematically shown, the simulation design file of the 16 processor cores can be compiled to obtain a dynamic link library including dynamic link files corresponding to the processor cores, the dynamic link library is connected with the top module of the multi-core system on a chip, and the simulation of the multi-core system on a chip can be realized. One processor core can also be selected for hardware simulation, and the other cores are software models, the simulation of 16 cores can be realized without real 16-core resources, which can greatly reduce resource consumption.

[0111] In summary, the embodiment of the present application can reduce compatibility problems caused by code style differences, facilitate version control and document management by obtaining the simulation design files of each first processor core in the multi-core system on a chip and limiting the simulation design files to be written in a preset hardware compilation language. The hardware description language can accurately depict the timing logic, pipeline structure and instruction set behavior of the processor core, ensuring the consistency of the simulation model and the physical implementation. By compiling the simulation design files of each first processor core, a dynamic link library including dynamic link files corresponding to each first processor core is obtained, and the dynamic link files are limited to be written in a preset software compilation language. The simulation design files can be compiled into a dynamic link library, and the software packaging of the hardware model is realized through the preset software compilation language, so that the processor core can be integrated with the software test platform. The dynamic link library includes dynamic link files, i.e. target language models, and running the target language models can simulate the multi-core system on a chip, which can reduce the hardware resources consumed by simulation. The dynamic link library supports on-demand loading at runtime, allowing flexible replacement of processor core models during simulation without the need to recompile the entire system, which can further reduce the resources consumed by simulation and adapt to multiple simulation tools, solving the difference in hardware language support of different simulation tools and realizing the standardization of the verification process. The software compilation language has high execution efficiency, and the dynamic link library can accelerate the functional verification of the processor core. Finally, the dynamic link library is connected with the top module of the multi-core system on a chip, the top module defines the interconnection relationship between modules through a bus protocol, integrates the processor core model in the dynamic link library with the system on a chip, realizes full-system functional simulation, and improves the simulation efficiency of the multi-core system on a chip.

[0112] The embodiment of the present application also provides a simulation device of a multi-core system on a chip, Figure 6 is a block diagram of a simulation device of a multi-core system on a chip provided by the embodiment of the present application. As shown in the figure, the simulation device 600 of the multi-core system on a chip can include an acquisition module 601, a compilation module 602 and a simulation module 603. Figure 6 The acquisition module 601 is configured to acquire simulation design files of each first processor core in the multi-core system on a chip; the simulation design files are written in a preset hardware compilation language.

[0113] The acquisition module 601 is configured to acquire simulation design files of each first processor core in the multi-core system on a chip; the simulation design files are written in a preset hardware compilation language.

[0114] The compilation module 602 is configured to compile the simulation design files of each first processor core to obtain a dynamic link library including dynamic link files corresponding to each first processor core; the dynamic link files are written in a preset software compilation language.

[0115] The simulation module 603 is configured to connect the dynamic link library and the top module of the multi-core system on a chip to implement simulation of the multi-core system on a chip.

[0116] Optionally, as shown in Figure 6 The simulation device 600 of the multi-core system on a chip can further include a selection module 604.

[0117] The selection module 604 is configured to select any first processor core from the processor cores of the multi-core system on a chip as a second processor core. The simulation module 603 is further configured to perform hardware simulation on the second processor core according to the simulation design file of the second processor core to obtain a hardware simulation model of the second processor core. The simulation module 603 is specifically configured to connect the hardware simulation model of the second processor core and the top module of the multi-core system on a chip, and connect the dynamic link library and the top module of the multi-core system on a chip to implement simulation of the multi-core system on a chip.

[0118] Optionally, the compilation module 602 is specifically configured to perform bit width splitting on the first hardware signal in the simulation design file of each first processor core to obtain a processed simulation design file, and compile the processed simulation design file corresponding to each first processor core to obtain the dynamic link library including the dynamic link files corresponding to each first processor core.

[0119] Optionally, the compilation module 602 is specifically configured to determine a first bit width of the first hardware signal, a second bit width matched with the dynamic link file, and a numerical relationship between the first bit width and the second bit width, split the first hardware signal into a plurality of second hardware signals according to the numerical relationship between the first bit width and the second bit width to obtain the processed simulation design file, and set a bit width of each second hardware signal to the second bit width.

[0120] Optionally, the multi-core system on a chip includes an interconnection interface module. The simulation module 603 is specifically configured to connect the dynamic link library and the multi-core system on a chip through the interconnection interface module to implement simulation of the multi-core system on a chip. The interconnection interface module is configured to implement consistency of a compilation language of the dynamic link library and the multi-core system on a chip.

[0121] Optionally, the simulation module 603 is specifically configured to sample a first integrated signal of the multi-core system on a chip through the interconnection interface module, send the first integrated signal to the dynamic link library, generate a first response signal according to the first integrated signal, obtain the first response signal through the interconnection interface module, and obtain a simulation test result of the multi-core system on a chip according to the first response signal.

[0122] Optionally, the simulation module 603 is specifically configured to acquire the first integrated signal of the multi-core system on chip through the interconnection interface module; convert the compiled language of the first integrated signal into a compiled language matched with the dynamic link library to obtain a second integrated signal; and send the second integrated signal to the dynamic link library.

[0123] Optionally, the simulation module 603 is specifically configured to acquire the first integrated signal of the multi-core system on chip through the interconnection interface module; convert the compiled language of the first integrated signal into a compiled language matched with the dynamic link library to obtain a second integrated signal; and send the second integrated signal to the dynamic link library.

[0124] For the apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and relevant parts refer to the parts described in the method embodiments.

[0125] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0126] For the apparatus in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be described in detail here.

[0127] The embodiments of the present application also provide a simulation apparatus of a multi-core system on chip, including a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors to perform the method in one or more embodiments described above.

[0128] The embodiments of the present application also provide an electronic device. Referring to Figure 7 , Figure 7 is a block diagram of an electronic device 700 according to an exemplary embodiment. The electronic device 700 can be, for example, a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, and the like.

[0129] Referring to Figure 7 , the electronic device 700 can include one or more of the following components: a processing component 702, a memory 704, a power supply component 706, a multimedia component 708, an audio component 710, an input / output (I / O) interface 712, a sensor component 714, and a communication component 716.

[0130] The processing component 702 generally controls the overall operations of the electronic device 700, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 702 can include one or more processors 720 to execute instructions and to complete all or part of steps of the above-described methods. In addition, the processing component 702 can include one or more modules to facilitate interaction between the processing component 702 and other components. For example, the processing component 702 can include a multimedia module to facilitate the interaction between the multimedia component 708 and the processing component 702.

[0131] The memory 704 is used to store various types of data to support operations of the electronic device 700. Examples of these data include instructions for any application or method operating on the electronic device 700, contact data, phonebook data, messages, pictures, multimedia, and so on. The memory 704 can be implemented by any type of volatile or non-volatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), programmable read only memory (PROM), read only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0132] The power component 706 provides power to various components of the electronic device 700. The power component 706 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 700.

[0133] The multimedia component 708 includes a screen providing an output interface between the electronic device 700 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes the touch panel, the screen can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide, and a gesture on the touch panel. The touch sensors can not only sense a boundary of a touching or sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, the multimedia component 708 includes a front camera and / or a rear camera. The front camera and / or the rear camera can receive external multimedia data when the electronic device 700 is in an operation mode, such as a shooting mode or a multimedia mode. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0134] The audio component 710 is configured to output and / or input audio signals. For example, the audio component 710 includes a microphone (MIC) for receiving an external audio signal when the electronic device 700 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 704 or transmitted via the communication component 716. In some embodiments, the audio component 710 also includes a speaker for outputting audio signals.

[0135] The I / O interface 712 provides an interface between the processing component 702 and peripheral interface modules, which can be a keypad, a click wheel, buttons, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0136] The sensor component 714 includes one or more sensors for providing status assessments of various aspects of the electronic device 700. For example, the sensor component 714 can detect an open / closed position of the electronic device 700, relative positioning of components, such as a display and a keypad of the electronic device 700, a change of position of the electronic device 700 or a component of the electronic device 700, presence or absence of user contact with the electronic device 700, orientation or acceleration / deceleration of the electronic device 700, and temperature changes of the electronic device 700. The sensor component 714 can include an orientation sensor, an acceleration sensor, a proximity sensor, a gesture sensor, a biometric sensor, a temperature / humidity sensor, an illumination sensor, and / or an interaction sensor. The sensor component 714 can further include an electronic component, for example, a camera, a microphone, and / or a user input interface, to measure a physical quantity or to generate a user interface.

[0137] The communication component 716 is configured to facilitate wired or wireless communication between the electronic device 700 and other devices. The electronic device 700 can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G, or 5G, or a combination thereof. In an example embodiment, the communication component 716 receives a broadcast signal or broadcast-related information from an external broadcasting management system via a broadcast channel. In an example embodiment, the communication component 716 further includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technology.

[0138] In an example embodiment, the electronic device 700 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic elements, for implementing the methods provided by the embodiments of the present application.

[0139] In an example embodiment, a non-transitory computer-readable storage medium including instructions, such as the memory 704 including instructions, is also provided, which can be executed by the processor 720 of the electronic device 700 to complete the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0140] The embodiments of the present application also provide a computer program product, comprising a computer program, which is executed by a processor to implement the method described in the above embodiments.

[0141] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The specification and examples given are exemplary only and the true scope and spirit of the application is indicated by the following claims. It will be appreciated by persons skilled in the art that numerous variations and / or modifications can be made to the application as described above without departing from the scope or spirit of the application. It is intended that all such variations and / or modifications be included within the scope of the application. The specification and examples given are exemplary only and the true scope and spirit of the application is indicated by the following claims.

[0142] It should be understood that the application is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is limited only by the claims that follow.

Claims

1. A simulation method of a multi-core system on chip, characterized by, The multi-core system-on-chip comprises a plurality of first processor cores and a top-level module, and the method comprises: obtaining simulation design files of each first processor core in the multi-core system-on-chip; the simulation design files are written by using a preset hardware compiling language; compiling the simulation design files of each first processor core to obtain a dynamic link library comprising dynamic link files corresponding to each first processor core; the dynamic link files are written by using a preset software compiling language; connecting the dynamic link library and the top-level module of the multi-core system-on-chip to realize simulation of the multi-core system-on-chip; the top-level module of the multi-core system-on-chip is used to realize interconnection between modules of the multi-core system-on-chip, definition of an external interface, and global control; the method further comprises: selecting any first processor core from each processor core of the multi-core system-on-chip as a second processor core; performing hardware simulation on the second processor core according to a simulation design file of the second processor core to obtain a hardware simulation model of the second processor core; the connecting of the dynamic link library and the top-level module of the multi-core system-on-chip to realize simulation of the multi-core system-on-chip comprises: connecting the hardware simulation model of the second processor core and the top-level module of the multi-core system-on-chip, and connecting the dynamic link library and the top-level module of the multi-core system-on-chip to realize simulation of the multi-core system-on-chip.

2. The method of claim 1, wherein, the compiling of the simulation design files of each first processor core to obtain a dynamic link library comprising dynamic link files corresponding to each first processor core comprises: performing bit-width splitting on a first hardware signal in the simulation design file of each first processor core to obtain a processed simulation design file; compiling the processed simulation design file corresponding to each first processor core to obtain a dynamic link library comprising dynamic link files corresponding to each first processor core.

3. The method of claim 2, wherein, the bit-width splitting of the first hardware signal in the simulation design file of each first processor core to obtain a processed simulation design file comprises: determining a first bit width of the first hardware signal, a second bit width matched with the dynamic link file, and a numerical relationship between the first bit width and the second bit width; according to the numerical relationship between the first bit width and the second bit width, splitting the first hardware signal into a plurality of second hardware signals to obtain a processed simulation design file; the bit width of each second hardware signal is the second bit width.

4. The method of claim 1, wherein, The multi-core system-on-chip comprises an interconnection interface module, and the connecting of the dynamic link library and the top-level module of the multi-core system-on-chip to realize simulation of the multi-core system-on-chip comprises: connecting the dynamic link library and the multi-core system-on-chip through the interconnection interface module to realize simulation of the multi-core system-on-chip; the interconnection interface module is used to realize consistency of compiling languages of the dynamic link library and the multi-core system-on-chip.

5. The method of claim 4, wherein, the connecting of the dynamic link library and the multi-core system-on-chip through the interconnection interface module to realize simulation of the multi-core system-on-chip comprises: sampling, by the interconnection interface module, a first integrated signal of the multi-core system on chip, and sending the first integrated signal to the dynamic link library; generating a first response signal according to the first integrated signal; obtaining, by the interconnection interface module, the first response signal, and obtaining a simulation test result of the multi-core system on chip according to the first response signal.

6. The method of claim 5, wherein, The sampling, by the interconnection interface module, a first integrated signal of the multi-core system on chip, and sending the first integrated signal to the dynamic link library, comprises: sampling, by the interconnection interface module, a first integrated signal of the multi-core system on chip; converting a compiling language of the first integrated signal into a compiling language matched with the dynamic link library to obtain a second integrated signal; sending the second integrated signal to the dynamic link library.

7. The method of claim 5, wherein, The obtaining, by the interconnection interface module, the first response signal, and obtaining a simulation test result of the multi-core system on chip according to the first response signal, comprises: obtaining, by the interconnection interface module, the first response signal; converting a compiling language of the first response signal into a compiling language matched with the multi-core system on chip to obtain a second response signal; obtaining a simulation test result of the multi-core system on chip according to the second response signal.

8. An emulation apparatus of a multi-core system on a chip, characterized by comprising: The multi-core system on chip comprises a plurality of first processor cores and a top-level module, and the apparatus comprises: an obtaining module configured to obtain a simulation design file of each of the first processor cores in the multi-core system on chip; the simulation design file is written in a preset hardware compiling language; a compiling module configured to compile the simulation design file of each of the first processor cores to obtain a dynamic link library comprising a dynamic link file corresponding to each of the first processor cores; the dynamic link file is written in a preset software compiling language; a simulation module configured to connect the dynamic link library with the top-level module of the multi-core system on chip to implement simulation of the multi-core system on chip; the top-level module of the multi-core system on chip is configured to implement interconnection between modules of the multi-core system on chip, external interface definition, and global control; the obtaining module is further configured to select any first processor core as a second processor core from the processor cores of the multi-core system on chip; the simulation module is further configured to perform hardware simulation on the second processor core according to the simulation design file of the second processor core to obtain a hardware simulation model of the second processor core; the simulation module is specifically configured to connect the hardware simulation model of the second processor core with the top-level module of the multi-core system on chip, and connect the dynamic link library with the top-level module of the multi-core system on chip to implement simulation of the multi-core system on chip.

9. An electronic device, comprising: comprises: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement the method of any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is enabled to perform the method of any one of claims 1 to 7.

Images