Macro-cell layout method and device for integrated circuit design, medium and product

Abstract

The invention relates to a macro cell layout method and device for integrated circuit design, a medium and a product. The macro cell layout method is applied to a legalization stage of macro cell layout and comprises the following steps: acquiring an initialized layout, and performing global layout on the initialized layout to obtain an initial layout which is provided with a boundary and comprises a plurality of macro cells; preset constraint conditions corresponding to the initial layout are provided, the preset constraint conditions comprise a minimum spacing constraint and a prohibited spacing constraint, whether violations exist between adjacent macro-cells and between the macro-cells and boundaries or not is determined according to the preset constraint conditions, and the types of the violations comprise exclusive violations and attractive violations; according to the initial layout, generating free layout space distribution for macro units to move, and calculating free layout space of the macro units in the moving direction; based on the free layout space, the violation and the type of the violation, the displacement of the macro unit is calculated, and the initial layout is optimized.

Description

Technical Field

[0001] The present invention relates to the field of chip layout technology, and in particular to a macro cell layout method, device, medium and product for integrated circuit design. Background Art

[0002] In modern chip design, macrocells primarily include memories and custom IP cores. Due to their large size and position-sensitive nature, their layout must simultaneously meet multiple constraints, including pre-placed locations, boundary alignment, and minimum spacing. The traditional layout process typically consists of three phases: global placement, legalization, and detailed placement. The core task of the legalization phase is to eliminate overlap between modules while preserving the optimal global layout characteristics (such as line length and timing) as much as possible and satisfying all physical constraints.

[0003] Chip layout legalization de-overlaps and legalizes standard cells or macro cells in a chip based on a given layout and the constraints that the layout must comply with, while optimizing for minimal layout changes. With the continuous shrinking of process nodes and the increase in design complexity, existing legalization algorithms face challenges such as "difficulty in efficiently removing high-density overlaps," "lack of compatibility with complex constraints," and "unmet edge compactness requirements." Summary of the Invention

[0004] In order to solve the technical problem that in the legalization stage of macro cell layout, when moving macro cells to remove overlap between macro cells, multiple layout constraints cannot be met, thereby affecting the global layout optimization results, the present invention provides a macro cell layout method, equipment, medium and product for integrated circuit design.

[0005] The solution to the technical problem of the present invention is to provide a macro cell layout method for integrated circuit design, which is applied to the legalization stage of macro cell layout. The macro cell layout method includes the following steps: obtaining an initialization layout, performing global layout on the initialization layout, and obtaining an initial layout with a boundary and including a plurality of macro cells; providing preset constraints corresponding to the initial layout, the preset constraints including a minimum spacing constraint and a prohibited spacing constraint, and determining whether there are violations between adjacent macro cells and between the macro cells and the boundaries based on the preset constraints, and the types of the violations including repulsion violations and attraction violations; based on the initial layout, generating a distribution of free layout spaces available for the macro cells to move, and calculating the free layout spaces of the macro cells in the moving direction; calculating the displacement of the macro cells based on the free layout spaces, the violations, and the types of the violations, and optimizing the initial layout.

[0006] Preferably, the violation is defined as the overlapping area calculated between adjacent macro units and between the macro unit and the boundary, and the macro unit that generates the overlapping area is the violation object; determining whether there is a violation between adjacent macro units and between the macro unit and the boundary based on the preset constraint conditions includes the following steps: obtaining the preset constraint conditions, the minimum spacing constraint and the prohibited spacing constraint corresponding to the repulsion violation and the attraction violation respectively; calculating the distance between adjacent macro units and between the macro unit and the boundary based on the preset constraint conditions, and judging whether there is the repulsion violation or the attraction violation.

[0007] Preferably, the preset constraint condition is defined as a minimum spacing constraint. If the spacing between adjacent macro units and between the macro unit and the boundary is less than the preset minimum spacing, then the repulsion violation exists; or, the preset constraint condition is defined as a prohibited spacing constraint. If the spacing between adjacent macro units and between the macro unit and the boundary is less than the preset prohibited spacing and there are no pins on the corresponding adjacent edges, then the attraction violation exists; or, the preset constraint condition is defined as a minimum spacing constraint and a prohibited spacing constraint and the preset minimum spacing is greater than the preset prohibited spacing. If the spacing between adjacent macro units and between the macro unit and the boundary is less than the preset prohibited spacing, then the repulsion violation exists; if it is greater than or equal to the preset prohibited spacing and less than the preset minimum spacing, then the attraction violation exists.

[0008] Preferably, the free layout space distribution is obtained by subtracting the occupied area and prohibited placement area of ​​the macro unit from the placement area of ​​the macro unit; calculating the free layout space of the macro unit in the moving direction includes the following steps: obtaining the free layout space distribution; scanning from the macro unit to the boundary to obtain the projection line segment of the occupied area of ​​the macro unit in the moving direction, and the moving direction includes four directions: up, down, left and right; when the free layout space distribution completely accommodates the scanning length of the projection line segment, the free layout space of the macro unit in each direction is calculated.

[0009] Preferably, based on the idle layout space, the violation and the type of the violation, the displacement of the macro unit is calculated, and the initial layout is optimized, including the following steps: based on the type of the violation and the state of the violation object, the contribution displacement of the violation to the violation object is calculated, the contribution displacement refers to the movement distance that the two violation objects need to bear respectively to eliminate the violation, and the state of the violation object includes fixed and movable; each of the moving directions of the macro unit is projected line segment scanned to obtain the average idle layout space of the macro unit; based on the average idle layout space and the placement area boundary of the macro unit, the anchor point is calculated, and all macro units are sorted from near to far according to the right-angle distance between the macro unit and the anchor point; the displacement of the macro unit is calculated in order, and the macro unit is moved.

[0010] Preferably, the contribution displacement of the violation to the violation object is calculated according to the type of the violation and the state of the violation object, including the following steps: respectively calculating the total amount of overlap o of the violation in the horizontal and vertical directions, evenly allocating it to the overlapping violation objects, and generating the contribution displacement in opposite directions. ,in, , Defined as the vector modulus, recording the minimum contribution displacement combination and the second minimum contribution displacement combination; adjusting the minimum contribution displacement and the second minimum contribution displacement according to the status of the violating object; adjusting the minimum contribution displacement and the second minimum contribution displacement according to the free layout space of the violating object.

[0011] Preferably, the displacement of the macro unit is calculated in order traversal, and the macro unit is moved, including the following steps: judging whether the contribution displacements generated by the two violations to the same macro unit are in the same direction in the horizontal and vertical directions; if they are in the same direction, the two violations are located on a single side of the macro unit; if they are in opposite directions, they are located on both sides of the macro unit; when the violations are located on a single side of the macro unit, the maximum contribution displacement is taken as the displacement of the macro unit; when the violations are located on both sides of the macro unit, the maximum contribution displacement of the side with more violations is taken as the displacement of the macro unit; and calculating the displacement of the macro unit. After that, traverse all violations and recalculate the contribution displacement of each violation to another macro unit that generates this violation. ,satisfy .

[0012] The present invention also provides a computer device, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above-mentioned macro cell layout method.

[0013] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above-mentioned macro cell layout method when executed by a processor.

[0014] The present invention also provides a computer program product, comprising a computer program, which implements the steps of the above macrocell layout method when executed by a processor.

[0015] Compared with the prior art, the macrocell layout method, device, medium and product for integrated circuit design provided by the present invention have the following advantages: 1. An embodiment of the present invention provides a macrocell layout method for integrated circuit design, which is applied to the legalization stage of macrocell layout. Chip layout legalization is to ensure that macrocells comply with physical design rules or various constraints set by users of automated design tools based on a given global layout. The macrocell layout method identifies repulsion violations and attraction violations between adjacent macrocells and between macrocells and boundaries through preset constraint conditions. Combined with the free layout space of the macrocells in the direction of movement, the macrocell displacement is calculated and the initial layout is optimized. After completing the global layout, a de-overlapping operation can be performed on the macrocells to minimize the layout variation while strictly complying with the minimum spacing constraint and the prohibited spacing constraint, thereby obtaining a solution with a small layout variation and complying with the spacing and boundary constraints.

[0016] It can be understood that the macro cell layout method can realize de-overlapping of macro cells of any size in a two-dimensional space, the layout space detection mechanism can calculate the free layout space of the macro cell in the moving direction, and the local de-overlapping operation is guaranteed to skip the local optimum through the layout space detection mechanism, compared with the traditional two-dimensional de-overlapping algorithm, and has stronger robustness and convergence, and has a smaller layout change amount in the case of completely removing the overlap.

[0017] 2、The macro cell layout method provided by the embodiment of the application, the violation is defined as the overlap area calculated between adjacent macro cells or between the macro cell and the boundary, the macro cell generating the overlap area is the violation object, and the preset constraint condition is combined, wherein the minimum spacing constraint corresponds to the repulsion violation, and the prohibited spacing constraint corresponds to the attraction violation, whether the repulsion violation or the attraction violation exists is judged by calculating the distance between adjacent macro cells and the distance between the macro cell and the boundary, and through this design, the violation and the type of the violation can be accurately identified, and accurate violation judgment basis is provided for subsequent calculation of the displacement of the macro cell and optimization of the initial layout.

[0018] 3、The macro cell layout method provided by the embodiment of the application, the preset constraint condition is pre-set, and the legal layout of the chip needs to satisfy the minimum spacing constraint and / or the prohibited spacing constraint, the judgment standard of different violation types under different preset constraint conditions is defined in detail, and accurate violation judgment basis is provided for subsequent calculation of the displacement of the macro cell and optimization of the initial layout.

[0019] 4、The macro cell layout method provided by the embodiment of the application, the free layout space distribution is obtained by removing the occupied area and the prohibited placement area of the macro cell from the placeable area of the macro cell, and the free layout space is calculated from the free layout space distribution and the occupied area of the macro cell. The macro cell in the two-dimensional case has free layout spaces in four directions of up, down, left and right, the projection line segment of the occupied area of the macro cell in the moving direction is obtained by scanning from the macro cell to the boundary, the scanning length of the projection line segment can be completely accommodated by the free layout space distribution, and the free layout space in this direction is obtained, and then the free layout spaces in which the macro cell can move in each direction can be determined, and accurate space basis is provided for subsequent calculation of the displacement of the macro cell and optimization of the initial layout.

[0020] 5、The macro cell layout method provided by the embodiment of the application, the contribution displacement of the violation to the violation object is calculated according to the type of the violation and the state of the violation object, the anchor point is calculated in combination with the average free layout space of the macro cell and the placement area boundary, all macro cells are sorted from near to far, and the displacement of the macro cell is calculated in sequence, and then the moving distance of the macro cell can be reasonably determined, the moving conflict can be avoided, and the initial layout can be effectively optimized to eliminate the violation.

[0021] 6. In the macrocell layout method provided in an embodiment of the present invention, the contribution displacement refers to the movement distance that two violating objects need to each move to eliminate the violation. The total amount of overlap of the violations in the horizontal and vertical directions is calculated and evenly distributed to generate the contribution displacement. The minimum contribution displacement combination and the second minimum contribution displacement combination are recorded. The minimum contribution displacement and the second minimum contribution displacement are adjusted based on the status of the violating objects and the free layout space. Through this design, an adaptive displacement basis can be provided for the displacement calculation and initial layout optimization of the macrocell, so as to better eliminate violations.

[0022] 7. In the macrocell layout method provided by the embodiment of the present invention, the contribution displacement directions of two violations to the same macrocell are determined to determine whether the two violations are located on one side or both sides of the macrocell, and the maximum contribution displacement is correspondingly selected as the displacement of the macrocell. , and recalculate the contribution displacement of another macrocell that produces this violation to meet The conditions can reasonably determine the displacement of the macro unit and effectively eliminate violations, so as to facilitate the subsequent optimization of the initial layout.

[0023] 8. An embodiment of the present invention further provides a computer device comprising a memory, a processor, and a computer program stored on the memory, wherein the processor executes the computer program to implement the steps of the aforementioned macrocell layout method. It should be noted that this computer device has the same beneficial effects as the aforementioned macrocell layout method and is not further described here.

[0024] 9. An embodiment of the present invention further provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the steps of the aforementioned macrocell layout method. It should be noted that this computer-readable storage medium has the same beneficial effects as the aforementioned macrocell layout method and is not further described here.

[0025] 10. An embodiment of the present invention further provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the aforementioned macrocell layout method. It should be noted that this computer program product has the same beneficial effects as the aforementioned macrocell layout method and is not further described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 It is a flowchart of steps S1 to S4 in a macro cell layout method for integrated circuit design provided by an embodiment of the present invention.

[0028] Figure 2 It is a flowchart of steps S21 to S22 in a macro cell layout method for integrated circuit design provided by an embodiment of the present invention.

[0029] Figure 3 It is a flowchart of steps S31 to S33 in a macro cell layout method for integrated circuit design provided by an embodiment of the present invention.

[0030] Figure 4 It is a flowchart of steps S41 to S44 in a macro cell layout method for integrated circuit design provided by an embodiment of the present invention.

[0031] Figure 5 It is a flowchart of steps S411 to S413 in a macro cell layout method for integrated circuit design provided by an embodiment of the present invention.

[0032] Figure 6 It is a flowchart of steps S441 to S444 in a macro cell layout method for integrated circuit design provided by an embodiment of the present invention.

[0033] Figure 7 This is a schematic diagram of the initial layout of the macro cell before legalization.

[0034] Figure 8 This is a schematic diagram of the macrocell layout after legalization using commercial tools.

[0035] Figure 9 This is a schematic diagram of a macro cell layout after legalization of a macro cell layout method for integrated circuit design provided by an embodiment of the present invention.

[0036] Figure 10 It is a schematic diagram of a framework of a computer device provided by an embodiment of the present invention.

[0037] Figure 11 It is a schematic diagram of a framework of a computer-readable storage medium provided by an embodiment of the present invention.

[0038] Figure 12 It is a schematic diagram of the framework of a computer program product provided by an embodiment of the present invention.

[0039] Description of the accompanying drawings: 1. Computer equipment; 11. Storage; 12. Processor; 2. Computer-readable storage medium; 3. Computer program products; 100. Computer program. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and implementation examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0041] In the embodiments provided herein, it should be understood that "B corresponding to A" means that B is associated with A and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B based solely on A; B can also be determined based on A and / or other information.

[0042] It should be understood that references to "one embodiment" or "an embodiment" throughout this specification mean that specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present invention. Therefore, the appearance of "in one embodiment" or "in an embodiment" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Those skilled in the art should also be aware that the embodiments described in this specification are all optional embodiments, and the actions and modules involved are not necessarily required for the present invention.

[0043] In various embodiments of the present invention, it should be understood that the size of the serial numbers of the above-mentioned processes does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0044] The flow charts and block diagrams in the accompanying drawings of the present invention illustrate the possible implementation architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementation schemes, the functions marked in the box can also occur in a different order than those marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which is determined based on the functions involved. It should be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0045] Existing legalization algorithms face the following key challenges: High-density overlap is difficult to remove efficiently: Global layouts typically allow for temporary overlap between modules to optimize the objective function. However, in areas with dense macrocells, traditional constraint graph-based or force-directed methods may fail to converge quickly due to high computational complexity or cause excessive module displacement, disrupting the global optimization results. Insufficient compatibility of complex constraints: Restrictions such as pre-placed macrocells, spacing constraints, and boundary constraints significantly reduce the space available for module movement. While existing legalization methods can handle some constraints, they may still be unable to find legal solutions in extremely congested scenarios. The demand for edge compactness is not met: In industrial practice, it is often necessary to push macro cells to the edge of the chip or place macro cells compactly to form a regular core area for standard cell layout and routing, but most legalization algorithms do not incorporate this goal into the optimization framework.

[0046] Further understanding reveals that macrocell overlap removal can be modeled as a two-dimensional optimal rectangle removal problem: given boundary constraints, spacing constraints, and the initial states of all rectangles, the total movement of the rectangles is minimized while removing all overlap. This problem can theoretically be modeled as a mixed integer programming problem for solution. However, mixed integer programming is theoretically NP-hard (non-deterministic polynomial) and its worst-case solution time increases exponentially with the problem size. Fast solutions such as branch-and-bound and cutting plane methods can only handle smaller problems, while heuristic algorithms such as simulated annealing and genetic algorithms cannot guarantee the quality of the solution. Alternatively, it can be modeled as a one-dimensional removal problem within multiple rows. However, assigning each macrocell to its corresponding row and using the greedy strategy of the intra-row removal algorithm can easily lead to the layout falling into a local optimum rather than a global optimum, resulting in a large total movement of the macrocells.

[0047] In view of this, embodiments of the present invention provide a macrocell layout method, device, medium, and product for integrated circuit design. The technical solution of the present invention will be described in detail below.

[0048] See also Figure 1 An embodiment of the present invention provides a macrocell layout method for integrated circuit design, which is applied to the legalization stage of macrocell layout. The macrocell layout method includes the following steps: S1: Obtain an initialization layout, perform global layout on the initialization layout, and obtain an initial layout with boundaries and including a number of macro units; S2: providing preset constraints corresponding to the initial layout, the preset constraints including minimum spacing constraints and prohibited spacing constraints, and determining whether there are violations between adjacent macro cells and between macro cells and boundaries based on the preset constraints. Violation types include repulsion violations and attraction violations. S3: Based on the initial layout, generate the free layout space distribution for macro unit movement and calculate the free layout space of the macro unit in the movement direction; S4: Based on the free layout space, violations and violation types, calculate the displacement of the macro unit and optimize the initial layout.

[0049] The macrocell layout method provided in the embodiment of the present invention is applied to the legalization stage of macrocell layout. In particular, chip layout legalization is to make the macrocell conform to physical design rules or various constraints set by the user of the automated design tool based on a given global layout.

[0050] It can be understood that the macro unit layout method identifies the repulsion violations and attraction violations between adjacent macro units and between macro units and boundaries through preset constraints, and calculates the displacement of the macro units and optimizes the initial layout based on the free layout space of the macro units in the moving direction. After completing the global layout, the macro units can be de-overlapped to minimize the layout changes while strictly complying with the minimum spacing constraints and prohibited spacing constraints, and a solution with a small layout change and meeting the spacing constraints and boundary constraints can be obtained.

[0051] It should be noted that the macro unit layout method of the present invention can achieve de-overlapping of macro units of any size in two-dimensional space. The idle layout space of the macro unit in the moving direction can be calculated through the layout space detection mechanism. The moving range of the macro unit is constrained by the idle layout space calculation, ensuring that while calculating the displacement of the macro unit and optimizing the initial layout, violations can be eliminated without causing new conflicts, so as to ensure that the local de-overlapping operation skips the local optimum. Compared with the traditional two-dimensional de-overlapping algorithm, it has stronger robustness and convergence, and has a smaller layout change when the overlap is completely removed. It solves the technical problem that in the legalization stage of the macro unit layout, when moving the macro unit to remove the mutual overlap between the macro units, multiple layout constraints cannot be met, thereby affecting the global layout optimization results.

[0052] Specifically, in step S1, an initialization layout is obtained by a layout tool based on physical design rules. After performing a global layout, an initial layout that is uniform overall and has partial overlap is obtained.

[0053] In step S2, the preset constraints refer to the boundary constraints and spacing constraints of the macrocells, specifically including minimum spacing constraints and prohibited spacing constraints. In the initial layout, there are standard cells and wire nets that are closely connected to the macrocells. The main purpose of the minimum spacing constraint is to reserve a certain amount of placement and routing space for these standard cells and wire nets, reducing congestion and optimizing timing; the main purpose of the prohibited spacing constraint is to ensure that when there are no pins on the adjacent edges between adjacent macrocells, the adjacent edges between adjacent macrocells are placed closely together, and when there are no pins on the edges close to the boundaries of the macrocells, the macrocells are placed close to the boundaries, thereby reducing unnecessary layout resource waste. The specific constraints used in the legalization stage can be pre-specified based on actual needs. The macrocell layout method of the embodiment of the present invention can minimize the total movement of the macrocells after removing the overlap between the macrocells after the initial layout of the macrocells and the boundary constraints and spacing constraints of the macrocells are given; the violations of the embodiment of the present invention are the overlap areas calculated between adjacent macrocells and between macrocells and boundaries. The types of violations include repulsive violations and attractive violations.

[0054] In step S3, a distribution of free layout space available for macrocell movement is generated based on the initial layout, which can be used to calculate the free layout space of the macrocell in the direction of movement. In step S4, the free layout space, violations, and violation types are used to calculate the displacement of the macrocell and optimize the initial layout. Violations determined in step S2 based on preset constraints are then removed, and a de-overlapping operation is performed on the macrocell to minimize layout changes. After optimizing the initial layout, a macrocell layout with no overlap violations and minimal total macrocell movement is output, where no overlap violations means that the macrocell layout satisfies both the minimum spacing constraint and the prohibited spacing constraint.

[0055] In an embodiment of the present invention, the violation is an overlapped area calculated between adjacent macro cells or between a macro cell and a boundary, and the macro cell generating the overlapped area is defined as a violation object.

[0056] For further information, see Figure 2 , determining whether there are violations between adjacent macro cells or between macro cells and boundaries based on preset constraints, including the following steps: S21: obtaining preset constraint conditions, wherein the minimum spacing constraint and the prohibited spacing constraint correspond to the repulsion violation and the attraction violation respectively; S22: Calculate the distances between adjacent macro units and between a macro unit and a boundary according to preset constraints, and determine whether there is a repulsion violation or an attraction violation.

[0057] In the macrocell layout method provided in an embodiment of the present invention, the minimum spacing constraint corresponds to a repulsion violation, and the prohibited spacing constraint corresponds to an attraction violation. By calculating the distance between adjacent macrocells and the distance between a macrocell and a boundary, it is determined whether a repulsion violation or an attraction violation exists. Through this design, violations and their types can be accurately identified, providing an accurate violation judgment basis for subsequent calculation of macrocell displacements and optimization of the initial layout.

[0058] In step S21, the minimum spacing constraint corresponds to the repulsive violation, requiring that the spacing between adjacent macrocells and between a macrocell and a boundary be greater than or equal to a preset minimum spacing. The prohibited spacing constraint corresponds to the attractive violation, requiring that the spacing between adjacent macrocells and between a macrocell and a boundary be less than a preset prohibited spacing, and that, when no pins exist on the corresponding adjacent edges, the macrocells be placed close to the adjacent macrocells or boundary. Both the preset minimum spacing and the preset prohibited spacing can be set using automated design tools.

[0059] In step S22, the minimum spacing constraint corresponds to a repulsive violation. A repulsive violation is defined as the actual overlapping area between violating objects and the overlapping area between violating objects calculated based on the preset minimum spacing in the minimum spacing constraint. The actual overlapping area refers to the area of ​​actual physical overlap, while the overlapping area refers to the area that does not satisfy the minimum spacing constraint. When faced with a repulsive violation, the violating objects need to be repelled to remove the overlap. The prohibited spacing constraint corresponds to an attractive violation. An attractive violation is defined as the non-overlapping area calculated based on the preset prohibited spacing in the prohibited spacing constraint when there is no actual overlapping area between the violating objects. When faced with an attractive violation, the violating objects need to be brought closer to remove the violation.

[0060] In some embodiments, the preset constraint is defined as a minimum spacing constraint. If the spacing between adjacent macro units or between a macro unit and a boundary is less than the preset minimum spacing, an exclusion violation exists; or, the preset constraint is defined as a prohibited spacing constraint. If the spacing between adjacent macro units or between a macro unit and a boundary is less than the preset prohibited spacing and no pins exist on the corresponding adjacent edges, an attraction violation exists; or, the preset constraint is defined as a minimum spacing constraint and a prohibited spacing constraint and the preset minimum spacing is greater than the preset prohibited spacing. If the spacing between adjacent macro units or between a macro unit and a boundary is less than the preset prohibited spacing, an exclusion violation exists; if it is greater than or equal to the preset prohibited spacing and less than the preset minimum spacing, an attraction violation exists.

[0061] In the macro cell layout method provided by an embodiment of the present invention, the preset constraint conditions are pre-set. There are situations where the legal layout of the chip needs to meet the minimum spacing constraint and / or the prohibited spacing constraint. By specifically defining the judgment criteria for different violation types under different preset constraint conditions, an accurate violation judgment basis is provided for the subsequent calculation of the macro cell displacement and the optimization of the initial layout.

[0062] As a first implementation, when the preset constraint condition is specified as only a minimum spacing constraint, the spacing between adjacent macro units and between a macro unit and a boundary is required to be greater than or equal to the preset minimum spacing to eliminate exclusion violations.

[0063] As a second implementation method, when the preset constraint condition is only specified as a minimum spacing constraint, if the spacing between adjacent macro units or between a macro unit and a boundary is less than the preset prohibited spacing and there are no pins on the corresponding adjacent edges, the macro unit needs to be placed close to the adjacent macro unit or boundary to eliminate the attraction violation.

[0064] As a third implementation, when the preset constraint specifies both a minimum spacing constraint and a prohibited spacing constraint, the preset minimum spacing must be greater than the preset prohibited spacing, and the prohibited spacing constraint takes precedence. Specifically, if the spacing between adjacent macrocells or between a macrocell and a boundary is less than the preset prohibited spacing, a repulsion violation is determined to exist, and the first implementation is applied to eliminate the repulsion violation. If the spacing between adjacent macrocells or between a macrocell and a boundary is greater than or equal to the preset prohibited spacing and less than the preset minimum spacing, an attraction violation is determined to exist, and the second implementation is applied to eliminate the attraction violation.

[0065] In some embodiments, the free layout space distribution is obtained by subtracting the occupied area and prohibited placement area of ​​the macro unit from the placement area of ​​the macro unit. In some embodiments, if spacing constraints are provided when executing the macro unit layout method, the minimum spacing constraint in the preset constraints is taken into account, and the occupied area of ​​the macro unit is first expanded outward to half of the preset minimum spacing between macro units, and then the prohibited placement area of ​​the macro unit is expanded into the placement area of ​​the macro unit to the preset minimum spacing between the macro unit and the boundary.

[0066] See also Figure 3 , calculate the free layout space of the macro unit in the moving direction, including the following steps: S31: Obtaining free layout space distribution; S32: Scan from the macro unit to the boundary to obtain the projection line segment of the occupied area of ​​the macro unit in the moving direction, and the moving direction includes four directions: up, down, left, and right; S33: When the free layout space distribution completely accommodates the scan length of the projection line segment, the free layout space of the macro unit in each direction is calculated.

[0067] In the macro unit layout method provided in an embodiment of the present invention, the free layout space distribution is obtained by subtracting the occupied area and prohibited placement area of ​​the macro unit from the placement area of ​​the macro unit, and the free layout space is calculated by the free layout space distribution obtained in step S31 and the occupied area of ​​the macro unit.

[0068] It can be understood that in the two-dimensional case, there is idle layout space in the four directions of up, down, left and right for the macro unit. In steps S32 and S33, by scanning from the macro unit to the boundary, the projection line segment of the occupied area of ​​the macro unit in the moving direction is obtained. The distribution of idle layout space can completely accommodate the scanning length of the projection line segment, which is the idle layout space in this direction. Then, the idle layout space that the macro unit can move in various directions can be determined, providing an accurate spatial basis for the subsequent calculation of the displacement of the macro unit and the optimization of the initial layout.

[0069] See also Figure 4 , based on the free layout space, violations and violation types, the displacement of the macro cells is calculated and the initial layout is optimized, including the following steps: S41: Calculate the displacement contribution of the violation to the violating object based on the violation type and the state of the violating object. The displacement contribution refers to the distance that each of the two violating objects needs to move to eliminate the violation. The states of the violating objects include fixed and movable. S42: Perform projection line segment scanning on each moving direction of the macro unit to obtain the average free layout space of the macro unit; S43: Calculate an anchor point based on the average free layout space and the placement area boundary of the macro unit, and sort all macro units from near to far according to the right-angle distance between the macro unit and the anchor point; S44: Calculate the displacement of the macro unit in order and move the macro unit.

[0070] In the macro unit layout method provided in the embodiment of the present invention, the contribution displacement of the violation to the violation object is calculated based on the type of violation and the status of the violation object, and then the anchor point is calculated in combination with the average free layout space of the macro unit and the placement area boundary. All macro units are sorted from near to far, and the displacement of the macro units is calculated in order. Therefore, the movement distance of the macro unit can be reasonably determined, movement conflicts can be avoided, and the initial layout can be effectively optimized to eliminate violations.

[0071] Specifically, in step S41, the possible displacement directions of the violating objects are up, down, left, and right. To eliminate the violation, the two violating objects need to move in opposite directions horizontally or vertically. To minimize the displacement of the violating objects, a local greedy strategy is used to select the two directions with the smallest total movement in the horizontal and vertical dimensions.

[0072] In step S42, the projection line segments are scanned in each moving direction of the macro unit to obtain the average free layout space of the macro unit. The average free layout space in the four directions is recorded as In step S43, the anchor point is calculated by the average free layout space of all macro units and the boundary of the macro unit placement area, and the coordinates of the lower left corner and the upper right corner of the macro unit placement area boundary are set as , the calculation formula of anchor point coordinates: , After the anchor point is calculated, all macro units are sorted from near to far according to the right angle distance between the macro unit and the anchor point. In step S44, the displacement of the macro units is calculated in order according to the sorting from near to far between the macro units, and the macro units are moved.

[0073] See also Figure 5 , based on the violation type and the state of the violating object, calculate the displacement contributed by the violation to the violating object, including the following steps: S411: Calculate the total amount of overlap o of violations in the horizontal and vertical directions respectively, and evenly distribute it to the overlapping violation objects, generating contribution displacements in opposite directions ,in, , Defined as the vector modulus, recording the minimum contribution displacement combination and the second minimum contribution displacement combination; S412: Adjusting the minimum contribution displacement and the second minimum contribution displacement according to the status of the violating object; S413: Adjust the minimum contribution displacement and the second minimum contribution displacement according to the free layout space of the violating object.

[0074] In the macrocell layout method provided by an embodiment of the present invention, the contribution displacement refers to the distance that two violating objects need to move to eliminate the violation. The total amount of horizontal and vertical overlap of the violations is calculated and evenly distributed to generate the contribution displacement. The minimum contribution displacement combination and the second minimum contribution displacement combination are recorded. The minimum contribution displacement and the second minimum contribution displacement are adjusted based on the status of the violating objects and the free layout space. Through this design, an adaptive displacement basis can be provided for the displacement calculation and initial layout optimization of the macrocell, thereby better eliminating violations.

[0075] In step S411, The formula followed by the contribution displacement is to evenly distribute the total amount of overlap o to the overlapping violating objects, resulting in contribution displacements in opposite directions. If the violation type is a repulsive violation, the direction of the contribution displacement is from the violation to the violating object; if the violation type is an attractive violation, the direction of the contribution displacement is from the violating object to the violation. When recording the minimum contribution displacement combination and the second minimum contribution displacement combination, if the horizontal direction is the minimum contribution displacement combination, the vertical direction is the second minimum contribution displacement combination; if the vertical direction is the minimum contribution displacement combination, the horizontal direction is the second minimum contribution displacement combination.

[0076] In step S412, the minimum contribution displacement and the second minimum contribution displacement are adjusted according to the status of the violating objects. If one of the violating objects is in a fixed state, the displacement of the violating object is reversely superimposed on the other overlapping violating object to ensure that the total displacement can eliminate overlap.

[0077] In step S413, the minimum contribution displacement and the next minimum contribution displacement are adjusted based on the free layout space of the violating object. If the free layout space corresponding to the minimum contribution displacement direction is insufficient, but the free layout space in the next minimum contribution displacement direction is sufficient, the next minimum contribution displacement is considered the minimum contribution displacement. If the free layout space in both the minimum contribution displacement and the next minimum contribution displacement direction is insufficient, the minimum contribution displacement is adjusted to 0.

[0078] See also Figure 6 , calculate the displacement of the macro unit in order and move the macro unit, including the following steps: S441: Determine whether the displacements contributed by the two violations to the same macro unit are in the same direction in the horizontal and vertical directions. If so, the two violations are located on one side of the macro unit; if not, the two violations are located on both sides of the macro unit. S442: When the violation is located on one side of the macro unit, the maximum contribution displacement is taken as the displacement of the macro unit; S443: When the violations are located on both sides of the macro unit, the maximum contribution displacement of the side with more violations is taken as the displacement of the macro unit; S444: Calculate the displacement of the macro unit After that, iterate over all violations and recalculate the contribution displacement of each violation to another macro unit that generates this violation. ,satisfy .

[0079] In the macrocell layout method provided by the embodiment of the present invention, the contribution displacement directions of two violations to the same macrocell are determined to determine whether the two violations are located on one side or both sides of the macrocell, and the maximum contribution displacement is correspondingly selected as the displacement of the macrocell. , and recalculate the contribution displacement of another macrocell that produces this violation to meet The conditions can reasonably determine the displacement of the macro unit and effectively eliminate violations, so as to facilitate the subsequent optimization of the initial layout.

[0080] Specifically, in step S441, if the displacements contributed by two violations to the same macro unit are in the same direction in the horizontal or vertical dimension, then the two violations are considered to be located on a single side of the same macro unit; if the displacements contributed by two violations to the same macro unit are in opposite directions in the horizontal or vertical dimension, then the two violations are considered to be located on both sides of the same macro unit.

[0081] In step S442, if all violations of a single macro unit are located on a single side, the maximum contribution displacement among these violations is taken as the displacement of the macro unit; in step S443, if the violations of a single macro unit are located on both sides, the maximum contribution displacement of the side with more violations is taken as the displacement of the macro unit.

[0082] In step S444, the displacement of a macro unit is calculated through steps S441 to S443. After that, it is necessary to traverse all violations of the macro unit and recalculate the contribution displacement of each violation to another macro unit that produces this violation. , the formula for macro unit displacement must be satisfied: In this formula, if it is equal to, the violation can be removed, and the displacement of the macro unit is the maximum contribution displacement of the violation. If it is greater than, the violation can be removed but the displacement of the macro unit is slightly more, and the displacement of the macro unit is not the maximum contribution displacement of the violation.

[0083] The following will further explain the technical solutions and technical effects of the macro cell layout method in conjunction with exemplary embodiments. It should be noted that the exemplary embodiments are only used to explain the present invention and do not limit the scope of application of the present invention.

[0084] Table 1. Design use case information corresponding to the global layout as input using TSMC 28nm and SMIC 14nm physical design rules.

[0085] Understandably, chip layout legalization requires maintaining the optimization results of the global layout as much as possible. Therefore, the optimization goal of this method is to minimize the layout change. The exemplary embodiment uses the total displacement of the macrocell as an indicator to measure the layout change. A comparative test with complete overlap removal was performed using the macrocell layout method of the present invention and mainstream commercial tools in the technical field, yielding the following results: Table 2. Comparative test results of total displacement of macro units (unit: μm)

[0086] As shown in Table 2, the macro cell layout method of the technical scheme of the present application can find a solution with better total displacement compared with mainstream commercial tools. In particular, based on a TSMC 28nm design (Design 1), an extreme constraint condition is set for comparison test with mainstream commercial tools: the preset minimum distance of macro cell to the left and right side boundaries is set to 100 μm, wherein, Figure 7 is the initial layout, Figure 8 is the layout after legalization of the mainstream commercial tool, Figure 9 is the layout after legalization of the macro cell layout method of the technical scheme of the present application. As shown in Table 2, Figures 7 to 9 compared with the mainstream commercial tool, the technical scheme of the present application is more complete in processing extreme constraints, and can find a legal solution under the condition of meeting extreme constraints.

[0087] Referring to Figure 10 , the embodiment of the present application further provides a computer device 1 comprising a storage 11, a processor 12 and a computer program 100 stored on the storage 11, wherein the processor 12 executes the computer program 100 to realize the steps of the macro cell layout method of the integrated circuit design described in the above embodiment.

[0088] It can be understood that the computer device 1 provided by the embodiment of the present application can realize the macro cell layout method of the integrated circuit design described in the above embodiment when the processor 12 executes the computer program 100, and the computer device 1 provided by the embodiment of the present application has the same beneficial effects as the macro cell layout method provided by the above embodiment.

[0089] In some embodiments, the computer device 1 is a computer device applied to chip layout technical field, including but not limited to global layout of an initial layout, obtaining an initial layout with boundaries and comprising a plurality of macro cells, determining whether there is a violation between adjacent macro cells and between the macro cell and the boundary according to a preset constraint condition, and calculating the displacement of the macro cell and optimizing the initial layout, which will not be described here, and theoretically, the method steps involved in the technical scheme of the present application can be realized by participating in control of the computer device 1, and the related parameters involved can also be adjusted by the computer device 1, wherein the related parameters include but are not limited to preset minimum distance, preset prohibited distance, minimum contribution displacement and next minimum contribution displacement and the like.

[0090] In some embodiments, the processor 12 provided in the embodiments of the present invention is a general-purpose processor, which is a microprocessor or any conventional processor, such as a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, which can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application.

[0091] In some embodiments, the method steps disclosed in the embodiments of the present application can be implemented by a hardware processor, or by a combination of hardware and software modules in the processor.

[0092] See also Figure 11 The embodiment of the present invention further provides a computer-readable storage medium 2 on which a computer program 100 is stored. When the computer program 100 is executed by a processor, the steps of the above-mentioned macro cell layout method are implemented.

[0093] It can be understood that the computer-readable storage medium 2 provided in the embodiment of the present invention stores a computer program 100 , and the computer program 100 can be called by a processor to execute the macrocell layout method for integrated circuit design described in the above embodiment.

[0094] It should be noted that the computer-readable storage medium 2 provided in the embodiment of the present invention has the same beneficial effects as the macro unit layout method provided in the above embodiment, and will not be described in detail here.

[0095] Specifically, the computer-readable storage medium 2 may include at least one type of storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory, a random access memory (RAM), a static random access memory (SRAM), a programmable read-only memory (PROM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic memory, a disk, an optical disk, etc.

[0096] In some embodiments, the computer-readable storage medium 2 includes a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs, and modules.

[0097] Specifically, the computer-readable storage medium 2 provided in an embodiment of the present invention has storage space for a computer program 100 that executes any method steps in the above-mentioned macro unit layout method, and these programs can be read from or written into one or more computer program products.

[0098] In some embodiments, the computer program 100 may be compressed in a suitable form.

[0099] See also Figure 12 The embodiment of the present invention further provides a computer program product 3, comprising a computer program 100, which implements the steps of the above-mentioned macro cell layout method when executed by a processor.

[0100] It can be understood that the computer program product 3 provided in the embodiment of the present invention includes a computer program 100, and the computer program 100 can be called by a processor to execute the macro cell layout method for integrated circuit design described in the above embodiment, which will not be described in detail here.

[0101] The above is a detailed introduction to the macro unit layout method, device, medium and product of an integrated circuit design disclosed in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention. Any modifications, equivalent replacements and improvements made within the principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A macrocell layout method for integrated circuit design, applied to the legalization stage of macrocell layout, characterized in that: The macrocell placement method includes the following steps: Acquire an initialization layout, perform global layout on the initialization layout, and obtain an initial layout having a boundary and including a plurality of macro units; Providing preset constraints corresponding to the initial layout, the preset constraints including a minimum spacing constraint and a prohibited spacing constraint, and determining whether there are violations between adjacent macro units and between the macro units and the boundaries based on the preset constraints, wherein the types of the violations include repulsion violations and attraction violations; Generating a distribution of free layout spaces available for movement of the macro unit based on the initial layout, and calculating the free layout spaces of the macro unit in the movement direction; Based on the free layout space, the violations and the types of the violations, the displacement of the macro unit is calculated, and the initial layout is optimized.

2. The macrocell layout method according to claim 1, wherein: The violation is defined as an overlapped area calculated between adjacent macro units and between the macro unit and the boundary, and the macro unit generating the overlapped area is a violation object; Determining whether there are violations between adjacent macro units or between the macro unit and the boundary according to the preset constraint condition comprises the following steps: Acquire the preset constraint conditions, wherein the minimum spacing constraint and the prohibited spacing constraint correspond to the repulsion violation and the attraction violation respectively; The distances between adjacent macro units and between the macro unit and the boundary are calculated according to the preset constraint conditions to determine whether the repulsion violation or the attraction violation exists.

3. The macrocell layout method according to claim 2, wherein: The preset constraint condition is defined as a minimum spacing constraint, and if the spacing between adjacent macro units or between the macro unit and the boundary is less than the preset minimum spacing, then the exclusion violation occurs; Alternatively, the preset constraint condition is defined as a prohibited spacing constraint, and if the spacing between adjacent macro units or between the macro unit and the boundary is less than the preset prohibited spacing and there is no pin on the corresponding adjacent edge, then the attraction violation occurs; Alternatively, the preset constraint conditions are defined as a minimum spacing constraint and a prohibited spacing constraint and the preset minimum spacing is greater than the preset prohibited spacing. If the spacing between adjacent macro units and between the macro unit and the boundary is less than the preset prohibited spacing, then the repulsion violation occurs; if it is greater than or equal to the preset prohibited spacing and less than the preset minimum spacing, then the attraction violation occurs.

4. The macrocell layout method according to claim 2 or 3, wherein: The free layout space distribution is obtained by subtracting the occupied area and prohibited placement area of ​​the macro unit from the placement area of ​​the macro unit; Calculating the free layout space of the macro unit in the moving direction includes the following steps: Obtaining the free layout space distribution; Scanning from the macro unit to the boundary, obtaining a projection line segment of the occupied area of ​​the macro unit in the moving direction, wherein the moving direction includes four directions: up, down, left, and right; When the free layout space distribution completely accommodates the scan length of the projection line segment, the free layout space of the macro unit in each direction is calculated.

5. The macrocell layout method according to claim 4, wherein: Calculating the displacement of the macro cell based on the free layout space, the violation, and the type of the violation, and optimizing the initial layout, including the following steps: Calculating, based on the violation type and the state of the violating object, a contribution displacement of the violation to the violating object, where the contribution displacement refers to the distance that each of the two violating objects needs to move to eliminate the violation. The states of the violating objects include fixed and movable. Performing projection line segment scanning on each of the moving directions of the macro unit to obtain an average free layout space of the macro unit; Calculating an anchor point based on the average free layout space and the placement area boundary of the macro unit, and sorting all macro units from near to far according to the right-angle distance between the macro unit and the anchor point; The displacement of the macro unit is calculated by traversing in order, and the macro unit is moved.

6. The macrocell layout method according to claim 5, wherein: Calculating the displacement contributed by the violation to the violation object according to the type of the violation and the state of the violation object includes the following steps: Calculate the total amount of overlap o of the violations in the horizontal and vertical directions respectively, and evenly distribute them to the overlapping violation objects to generate the contribution displacement in the opposite direction ,in, , Defined as the vector modulus, record the minimum contribution displacement combination and the second minimum contribution displacement combination; Adjusting the minimum contribution displacement and the second minimum contribution displacement according to the state of the violating object; The minimum contribution displacement and the second minimum contribution displacement are adjusted according to the free layout space of the violating object.

7. The macrocell layout method according to claim 6, wherein: Calculating the displacement of the macro unit in order and moving the macro unit includes the following steps: Determine whether the displacements contributed by the two violations to the same macro unit are in the same direction in the horizontal and vertical directions; if so, the two violations are located on one side of the macro unit; if so, the two violations are located on both sides of the macro unit; When the violation is located on one side of the macro unit, the maximum contribution displacement is taken as the displacement of the macro unit; When the violations are located on both sides of the macro unit, the maximum contribution displacement of the side with a larger number of violations is taken as the displacement of the macro unit; Calculate the displacement of the macro unit After that, traverse all violations and recalculate the contribution displacement of each violation to another macro unit that generates this violation. ,satisfy .

8. A computer device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the macro cell placement method according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computer program implements the steps of the macro cell placement method according to any one of claims 1 to 7.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the steps of the macro cell placement method according to any one of claims 1 to 7.

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