Heterogeneous hybrid half-bridge power module layout optimization design method

Abstract

The invention provides a heterogeneous hybrid half-bridge power module layout optimization design method, which comprises the steps that a heterogeneous hybrid half-bridge power module single-bridge arm topological structure model is constructed, and the single-bridge arm topological structure model comprises a SiC MOSFET device and a Si IGBT device; determining stray inductance influencing the gate voltage of the hybrid device based on the heterogeneous hybrid half-bridge power module single-bridge arm topological structure model; constructing a heterogeneous hybrid half-bridge power module physical model; performing simulation analysis on the heterogeneous hybrid half-bridge power module physical model, and determining the optimization priority of the stray inductance; and determining a layout optimization design scheme of the hybrid half-bridge power module based on the optimization priority of the stray inductance. According to the method provided by the invention, the complexity of multi-target collaborative optimization is effectively reduced. According to the research strategy, the development efficiency is remarkably improved while the design precision is guaranteed, and a systematic solution is provided for parasitic parameter optimization of the hybrid power module.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a method for optimizing the layout of a heterogeneous hybrid half-bridge power module. Background Art

[0002] Si IGBT (silicon-based insulated gate bipolar transistor) devices have the advantages of low cost, high voltage resistance, and a wide range of applications, making them more suitable for traditional industries and medium- and low-frequency, high-power applications. SiC MOSFET (silicon carbide metal oxide semiconductor field-effect transistor) devices are characterized by high-speed switching, low loss, and high efficiency, and perform better in high-frequency, high-temperature, and high-efficiency scenarios, but they are relatively expensive. To address the shortcomings of single devices and combine the advantages of both devices, a Si IGBT / SiC MOSFET hybrid device structure has been proposed, consisting of a large-capacity Si IGBT and a small-capacity SiC MOSFET in parallel. While the hybrid device has low cost, it also has the advantages of high current carrying capacity, high switching frequency, low conduction loss, and high redundancy.

[0003] In high-power applications, the rated current of discrete power devices is too small, so multiple chips are often packaged together in a power module. Within the power module, the chips are electrically connected through bonding wires and the copper layer of the DBC (Direct Bonded Copper) board. Stray inductance poses many hazards to the switching process of power devices, mainly affecting the current trajectory, resulting in excessive voltage and current stress, and increasing losses. Hybrid devices use two different devices in parallel. In addition to the switching transient process being disturbed by stray inductance, the steady-state commutation process will also be affected to a certain extent. Its switching process is more sensitive to stray inductance. In order to reduce the impact of stray inductance, precise layout design is crucial.

[0004] Research on reducing the stray inductance of each pole in hybrid devices has made some progress, but most work has not delved into the impact of each pole's stray inductance, nor has it clearly defined optimization priorities. Simultaneously optimizing each pole's stray inductance significantly increases design complexity and time costs, and in practical applications, it's difficult to achieve optimal optimization for all stray inductances simultaneously. Therefore, precise layout optimization of each pole's inductance remains a pressing issue. Summary of the Invention

[0005] In order to overcome the above technical defects, the present application provides a method for optimizing the layout design of a heterogeneous hybrid half-bridge power module. To achieve the above objectives, the present application is implemented according to the following technical solutions:

[0006] The present application provides a layout optimization design method for a heterogeneous hybrid half-bridge power module, including:

[0007] Constructing a single-arm topology structure model of a heterogeneous hybrid half-bridge power module, wherein the single-arm topology structure model includes a SiC MOSFET device and a Si IGBT device;

[0008] Determining the stray inductance that affects the gate voltage of the hybrid device based on the single-arm topology model of the heterogeneous hybrid half-bridge power module;

[0009] Construct a physical model of a heterogeneous hybrid half-bridge power module;

[0010] Performing simulation analysis on the physical model of the heterogeneous hybrid half-bridge power module to determine the optimization priority of the stray inductance;

[0011] Based on the optimization priority of the stray inductance, an optimized design scheme for the hybrid half-bridge power module layout is determined.

[0012] Optionally, the determining of the stray inductance affecting the gate voltage of the hybrid device based on the single-arm topology structure model of the heterogeneous hybrid half-bridge power module, wherein the stray inductance includes a first-stage stray inductance and a second-stage stray inductance, comprises:

[0013] Analyze the single-leg topology model of the heterogeneous hybrid half-bridge power module during the turn-on process to determine the first-stage stray inductance that affects the gate voltage of the SiC MOSFET device;

[0014] The single-arm topology structure model of the heterogeneous hybrid half-bridge power module during the commutation process is analyzed by formula to determine the second-stage stray inductance that affects the gate voltage of the Si IGBT device.

[0015] Optionally, performing formula analysis on the single-arm topology structure model of the heterogeneous hybrid half-bridge power module during the turn-on process to determine the first-stage stray inductance affecting the gate voltage of the SiC MOSFET device includes:

[0016] Performing formula analysis on the single-arm topology structure model of the heterogeneous hybrid half-bridge power module during the turn-on process to determine a first load current flowing through the SiC MOSFET device and a first gate voltage of the SiC MOSFET device;

[0017] A first-stage stray inductance affecting a gate voltage of a SiC MOSFET device is determined based on the first load current and the first gate voltage.

[0018] Optionally, performing formula analysis on the single-arm topology structure model of the heterogeneous hybrid half-bridge power module during the commutation process to determine the second-stage stray inductance affecting the gate voltage of the Si IGBT device includes:

[0019] Performing formula analysis on the single-arm topology structure model of the heterogeneous hybrid half-bridge power module during the commutation process to determine a second load current flowing through the Si IGBT device and a second gate voltage of the Si IGBT device;

[0020] A second-stage stray inductance affecting the gate voltage of the Si IGBT device is determined based on the second load current and the second gate voltage.

[0021] Optionally, the first-level stray inductance includes a drain inductance and a source inductance, and the second-level stray inductance includes a drain inductance, a source inductance, a collector inductance, and an emitter inductance.

[0022] Optionally, the performing simulation analysis on the physical model of the heterogeneous hybrid half-bridge power module to determine the optimization priority of the stray inductance includes:

[0023] The physical model of the heterogeneous hybrid half-bridge power module is input into LTspice software for simulation analysis, and it is determined that the drain inductance and the source inductance are the first optimization priority, and the collector inductance and the emitter inductance are the second optimization priority.

[0024] Optionally, determining a hybrid half-bridge power module layout optimization design scheme based on the optimization priority of the stray inductance includes:

[0025] Based on the drain inductance and the source inductance being the first priority for optimization, the hybrid device is arranged vertically on the DBC board, and the upper surface of the SiC MOSFET device and the upper surface of the SiIGBT device are connected to the same DBC board through bonding wires.

[0026] This application has the following beneficial effects:

[0027] The method proposed in this application effectively reduces the complexity of multi-objective collaborative optimization. This research strategy significantly improves development efficiency while ensuring design accuracy, providing a systematic solution for optimizing the parasitic parameters of hybrid power modules. While ensuring that the commutation process does not deteriorate, the proposed layout optimization design method significantly improves the transient characteristics of the module switch, effectively reduces switching losses, and provides a strong guarantee for the reliable operation of the hybrid module under high-speed switching conditions.

[0028] In addition to the above-described purposes, features and advantages, the present application has other purposes, features and advantages. The present application will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of this application. The exemplary embodiments and descriptions of this application are intended to explain this application and do not constitute an improper limitation on this application. In the accompanying drawings:

[0030] Figure 1 This is a flow chart of a method for optimizing the layout of a heterogeneous hybrid half-bridge power module provided in an embodiment of the present application;

[0031] Figure 2 This is a schematic diagram of a single-arm topology structure model of a heterogeneous hybrid half-bridge power module provided in an embodiment of the present application;

[0032] Figure 3 Schematic diagram of a physical model of a heterogeneous hybrid half-bridge power module provided in an embodiment of the present application;

[0033] Figure 4 This is a schematic diagram of a traditional layout design provided in an embodiment of the present application. Figure 4 (a) is a schematic diagram of the 3D model of the traditional layout scheme. Figure 4 (b) is a schematic diagram of the chip layout of the traditional solution;

[0034] Figure 5 Schematic diagram of the optimized layout solution provided in the embodiment of the present application. Figure 5 (a) is a schematic diagram of the 3D model of the optimized layout scheme. Figure 5 (b) Schematic diagram of the chip layout of the optimized layout scheme;

[0035] Figure 6 1 is a waveform diagram of the upper bridge arm hybrid device being turned on under two layout schemes during the experimental simulation provided by the embodiment of the present application;

[0036] Figure 7 1 is a shutdown waveform diagram of the upper bridge arm hybrid device under two layout schemes during the experimental simulation provided by the embodiment of the present application;

[0037] Figure 8 1 is a commutation waveform diagram of the upper bridge arm hybrid device under two layout schemes during the experimental simulation provided by the embodiment of the present application;

[0038] Figure 9 1 is a waveform diagram of the turn-on state of the lower bridge arm hybrid device under two layout schemes during the experimental simulation provided by the embodiment of the present application;

[0039] Figure 10 1 is a shutdown waveform diagram of the lower bridge arm hybrid device under two layout schemes during the experimental simulation provided by the embodiment of the present application;

[0040] Figure 11These are commutation waveforms of the lower arm hybrid device under two layout schemes during the experimental simulation provided by the embodiments of the present application. DETAILED DESCRIPTION

[0041] The embodiments of the present application are described in detail below with reference to the accompanying drawings, but the present application can be implemented in many different ways as defined and covered by the claims.

[0042] It should be noted that the terms "first", "second", "third", etc. in the claims, description and drawings of the present application are used to distinguish similar objects and are not used to describe a specific order or sequence. The data used in this way are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than that illustrated or described herein. In addition, the terms "including", "having" and their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] In order to solve the above problems raised in the background technology, Figure 1 As shown, this application proposes a layout optimization design method for a heterogeneous hybrid half-bridge power module, including:

[0044] Step S101: constructing a single-arm topology structure model of a heterogeneous hybrid half-bridge power module;

[0045] like Figure 2 As shown, the single-arm topology structure model of the heterogeneous hybrid half-bridge power module in this application includes SiCMOSFET devices ( Figure 2 blue part) and Si IGBT devices ( Figure 2 Generally speaking, a half-bridge module includes two topological structure models: the upper and lower bridge arms. Since the upper and lower bridge arms have the same structure, a single bridge arm topological structure is generally selected as the object for analysis.

[0046] Step S102: determining the stray inductance that affects the gate voltage of the hybrid device based on the single-arm topology structure model of the heterogeneous hybrid half-bridge power module;

[0047] There are multiple stray inductances in the main circuit of the single-arm topology model, for example, the leakage inductance L D , source inductance L S , collector inductance L C , emitter inductance L E and the stray inductance of the gate drive circuit L GThese inductors have varying effects on the switching characteristics of the half-bridge module. However, the priority of these stray inductances varies depending on the operating process. Therefore, analysis is performed during the turn-on and commutation processes to determine the stray inductances appropriate for each specific operating process.

[0048] The single-arm topology model during the turn-on process is analyzed using formulas to determine the first-stage stray inductance that affects the gate voltage of the SiCMOSFET device. The first-stage stray inductance is the stray inductance that affects the current characteristics during the turn-on process. The specific process for determining the first-stage stray inductance is as follows:

[0049] First, a formula analysis is performed on the single-arm topology structure model to determine a first load current flowing through the SiC MOSFET device and a first gate voltage of the SiC MOSFET device;

[0050] During the turn-on phase, since the SiC MOSFET device turns on first and then turns off, the switching waveform of the hybrid device composed of Si IGBT and SiC MOSFET is mainly determined by the SiC MOSFET device. The magnitude of the first load current flowing through the SiC MOSFET device is:

[0051] I MOSFET =G fs_MOSFET [U GS -U TH ] (1)

[0052] Where, I MOSFET represents the first load current flowing through the SiC MOSFET, U TH Indicates the gate turn-on voltage of SiC MOSFET, U GS Represents the first gate voltage of SiC MOSFET, G fs_MOSFET represents the transconductance of the SiC MOSFET.

[0053] Write the KCL (Kirchhoff's current law) and KVL (Kirchhoff's voltage law) equations for each circuit of the SiC MOSFET device:

[0054]

[0055] Where R G_MOSFET represents the gate resistance of SiC MOSFET, U G Indicates the high-level driving voltage value. G Represents the gate drive current of SiCMOSFET, C GS 、C GD with C DS Represents the parasitic capacitance of the SiC MOSFET device itself.

[0056] Combining (1)-(4), the first gate voltage U GS To summarize:

[0057]

[0058] in:

[0059]

[0060] Therefore, from the contents of formulas (1)-(6), that is, according to the first load current I MOSFET and the first gate voltage U GS , the first stray inductance that affects the gate voltage of SiC MOSFET is determined to be the drain inductance L D , source inductance L S , which in turn affects the current trajectory of SiCMOSFET during the switching process.

[0061] Next, a formula analysis is performed on the single-arm topology structure model of the heterogeneous hybrid half-bridge power module during the commutation process to determine the second-stage stray inductance that affects the gate voltage of the Si IGBT device. The second-stage stray inductance is the stray inductance that affects the current characteristics during the commutation process.

[0062] First, a formula analysis is performed on the single-arm topology structure model to determine a second load current flowing through the Si IGBT device and a second gate voltage of the Si IGBT device;

[0063] When the SiC MOSFET device is fully turned on, it appears in the circuit in the form of on-resistance. At this time, the load current in the power circuit flows entirely through the SiC MOSFET device. As the turn-on delay ends, the load current is commutated from the SiC MOSFET device circuit to the Si IGBT circuit. The magnitude of the second load current flowing into the Si IGBT device is:

[0064]

[0065] Where U GE Represents the second gate voltage of Si IGBT, I IGBT represents the second load current flowing through the Si IGBT, G fs_IGBT Represents the transconductance of the Si IGBT.

[0066] Write the KCL and KVL equations for the commutation circuit and each circuit in the Si device:

[0067]

[0068] Where R G_IGBTIndicates the gate resistance of Si IGBT, U G_IGBT Indicates the high-level driving voltage value of Si IGBT. G_IGBT Represents the gate drive current of Si IGBT. C GE 、C GC with C CE Represents the parasitic capacitance of the Si IGBT device itself.

[0069] Combining equations (7)-(11), the differential equation related to gate voltage can be summarized as:

[0070]

[0071] in:

[0072]

[0073] Therefore, from the contents of formulas (7)-(11), that is, according to the second load current I IGBT and the second gate voltage U GE , it is determined that the second-level stray inductance that affects the gate voltage of the Si IGBT is the drain inductance L D , source inductance L S , collector inductance L C , emitter inductance L E , which in turn affects the current trajectory of the Si IGBT.

[0074] Step S103: constructing a physical model of a heterogeneous hybrid half-bridge power module;

[0075] After determining the first-stage and second-stage stray inductances, since four different stray inductors are involved, it is obviously not realistic to consider multiple stray inductances simultaneously when optimizing the layout. Therefore, it is necessary to build a physical model of the heterogeneous hybrid half-bridge power module to determine the priority of the stray inductances.

[0076] This application uses high-power Si IGBT devices (SC75N12I8HA) and low-power SiC MOSFET devices (IV1Q12030BDG) to build a physical model of a heterogeneous hybrid half-bridge power module.

[0077] The voltage and current rating of the high-power Si IGBT device (SC75N12I8HA) is 1200V / 120A, and its chip size specifications are shown in the figure. The voltage and current rating of the low-power SiC MOSFET device (IV1Q12030BDG) is 1200V / 58A, and its chip size specifications are shown in the figure. Figure 3 As shown in (a), the SiIGBT device is 11 mm long and 6.8 mm wide; Figure 3As shown in (b), the SiCMOSFET device is 5.235mm long and 3.885mm wide.

[0078] A half-bridge power module primarily consists of a DBC substrate, power semiconductor chips, bonding wires, power terminals, and a housing. The DBC substrate, in turn, consists of an upper copper layer, a lower copper layer, and an intermediate insulating ceramic layer. The DBC intermediate ceramic layer is 0.4 mm thick, while the upper and lower copper layers are 0.35 mm thick, 60 mm long, and 36 mm wide. The diameter parameters for the bond wire modeling are shown in Table 1. To ensure high current carrying capacity for the power bond wires, their diameter is set to 12 mils. Driver and Kelvin bond wires carry less current and, due to chip pad size limitations, their diameter can be set to 5 mils.

[0079] Table 1 Bonding wire diameters

[0080]

[0081] Step S104: performing simulation analysis on the physical model of the heterogeneous hybrid half-bridge power module to determine the optimization priority of the stray inductance;

[0082] Input the physical model of the heterogeneous hybrid half-bridge power module into the LTspice software for simulation analysis, and the corresponding simulation results can be obtained. The simulation results are analyzed as follows: The source inductance L S and the drain inductance L D It affects both the switching waveform of the hybrid device and the commutation process. The increase in its value will not only prolong the turn-on and turn-off time of the hybrid device, but also increase the commutation time of the hybrid device and increase the switching loss of the hybrid device. E and collector inductance L C It only has a significant impact on the commutation process, and its impact on the commutation process is the same as L S With L D The gate inductance is only for the switch U GS There is an impact, and because it is much smaller than the gate resistance, the impact is limited. Therefore, the drain inductance and the source inductance are optimized as the first priority, and the collector inductance and emitter inductance are optimized as the second priority. In module design, the priority should be to reduce L S With L D , followed by L E With L C , and finally the gate inductor L G_Si_ With L G_SiC .

[0083] Step S105: determining a hybrid half-bridge power module layout optimization design scheme based on the optimization priority of the stray inductance.

[0084] Since it has been confirmed that the first priority of the above-mentioned stray inductance is the drain inductance and the source inductance, the present application is improved on the basis of the traditional layout scheme. The traditional layout scheme is: the hybrid device is arranged horizontally on the DBC board, and the upper surfaces of the SiC device and the Si device are connected in parallel through bonding wires.

[0085] The layout optimization design proposed in this application improves the division of the upper copper layer on the DBC board, the placement of the chip, and the length of the bond wires, while retaining all other structural features. The optimized hybrid device is arranged vertically on the DBC board, with the top surfaces of the SiC and Si devices connected to the same DBC board via bond wires for parallel connection. The ends of the bond wires do not directly connect the top surfaces of the two devices.

[0086] Experimental simulation

[0087] In order to demonstrate the effect of the layout optimization scheme proposed in this application, a comparison is made between the traditional layout scheme and the optimized layout scheme of this application.

[0088] Traditional layout solution 1: Figure 4 As shown, it is a traditional layout design. Figure 4 (a) is the 3D model of the traditional layout scheme. Figure 4 (b) is the chip layout of the traditional layout scheme. The three power terminals are placed in the middle of the entire module. The Si / SiC hybrid device of the upper half bridge arm is placed at the upper end of the DBC board, and the hybrid device of the lower half bridge arm is placed at the lower end of the DBC board. This half-bridge module adopts the Kelvin connection method to reduce the coupling between the drive circuit and the main circuit. The gate and Kelvin emitter of a single device are connected to the copper plates at the upper and lower ends through bonding wires. The output terminals of the Si device and the SiC device are connected through bonding wires to achieve parallel connection. Since the current flowing through the Kelvin bonding wire and the gate bonding wire is small, their diameter is selected as 5mil during modeling. To ensure the current carrying capacity of the remaining bonding wires, the diameter of the remaining bonding wires is all 12mil.

[0089] ANSYS Q3D software was used to extract the stray inductance. The measurement results at the commonly used operating frequency of 20 kHz were uniformly analyzed. The stray inductance extraction results of the upper bridge arm are as follows:

[0090] Table 1 Parasitic parameters of upper bridge arm of scheme 1

[0091] parameter SiC devices Si devices <![CDATA[L D (L C ) / nH]]> 10.33316 12.85650 <![CDATA[L S (L E ) / nH]]> 20.81575 13.58191 <![CDATA[L total / nH]]> 31.14891 26.43841

[0092] The results of the stray inductance extraction of the lower bridge arm are as follows:

[0093] Table 2 Parasitic parameters of the bridge arm of scheme 1

[0094] parameter SiC devices Si devices <![CDATA[L D (L C ) / nH]]> 19.04651 11.83990 <![CDATA[L S (L E ) / nH]]> 15.17143 10.33800 <![CDATA[L total / nH]]> 34.21794 22.17790

[0095] The optimized layout scheme 2 proposed in this application

[0096] To improve switching performance and enhance hybrid device stability during high-speed switching, layout optimization is required to improve the hybrid's transient switching trajectory and steady-state commutation time. The magnitude of stray inductance in the module is primarily influenced by bond wire length and the relative position of the device to the terminals. Longer bond wires and greater distances from the power terminals increase stray inductance, making these factors a starting point for optimizing the layout design.

[0097] For the main optimization goal L D and L S , here we propose the second optimization layout scheme, such as Figure 5 As shown in the figure, unlike the traditional layout scheme 1, the high-side hybrid device in scheme 2 is placed on the left end of the DBC board, while the low-side hybrid device is placed on the right end. As can be seen from the layout diagram, the distance between the drain and source of the SiC MOSFET device and the power terminals is significantly shortened. Furthermore, the length of the bond wires in the loop between the drain and source and the power terminals is also reduced.

[0098] The results of the stray inductance extraction of the upper bridge arm are as follows:

[0099] Table 3 Parasitic parameters of upper bridge arm of scheme 2

[0100] parameter SiC devices Si devices <![CDATA[L D (L C ) / nH]]> 10.27140 9.86630 <![CDATA[L S (L E ) / nH]]> 16.71132 16.09060 <![CDATA[L total / nH]]> 26.98272 25.9569

[0101] The results of the stray inductance extraction of the lower bridge arm are as follows:

[0102] Table 4 Parasitic parameters of the lower bridge arm of Scheme 2

[0103] parameter SiC devices Si devices <![CDATA[L D (L C ) / nH]]> 11.26702 11.32592 <![CDATA[L S (L E ) / nH]]> 11.72722 10.43504 <![CDATA[L total / nH]]> 22.99424 21.76096

[0104] Comparison of the two solutions

[0105] For the two layout design schemes, in the upper bridge arm, L C , L D , L S Both have decreased. D Since the distance between the drain and drain power terminals of the Si IGBT device is almost unchanged, it is only reduced by 0.6%. S The reduction is 19.7%, which is due to the source of the SiC device being closer to the source power terminal. And after optimization, the source bonding wire is shortened; L C Compared with the first solution, it is reduced by 23.26%, which is because the distance between the Si device and the collector power terminal is shortened. As the distance between the Si device and the emitter power terminal increases, L EHowever, the total stray inductance of the hybrid device is still reduced by 4.6477nH, and the focus of optimization is on L D , L S There has been a significant reduction. Therefore, the stray inductance of the upper bridge arm in Scheme 2 is improved compared to Scheme 1. The reduction in overall inductance also improves the commutation time of the hybrid device. The reduction in the stray inductance of the SiC branch helps improve the transient switching trajectory of the hybrid device, thereby ensuring the safety and stability of the hybrid device under high-speed switching conditions. The optimization results of the stray inductance parameters in the upper bridge arm of Scheme 2 compared to Scheme 1 are shown in Table 5 below. Positive values ​​indicate a decrease in stray inductance compared to Scheme 1, while negative values ​​indicate an increase in stray inductance.

[0106] Table 5 Optimization results of upper arm parasitic parameters of scheme 2

[0107]

[0108]

[0109] In the lower bridge arm, the distance and relative position between the Si device and the collector and emitter terminals in Scheme 2 and Scheme 1 do not change, and the length of the connecting bonding wire does not change, so L C and L E The main optimization goal L D and L S In the second scheme, both are reduced, among which L S Reduced by 22.7%, L D The reduction was 40.84%, due to the SiC device's source being closer to the source and drain power terminals and the optimized shortening of the source bond wire. The hybrid's total stray inductance was also reduced by 11.64091nH. As with the upper arm, the reduction in overall inductance improves the hybrid's commutation time. The reduction in the SiC branch's stray inductance improves the hybrid's transient switching trajectory, ensuring safe and stable operation under high-speed switching conditions. The optimization results for the lower arm stray inductance parameters for Scheme 2 compared to Scheme 1 are shown in Table 6 below:

[0110] Table 6 Optimization results of parasitic parameters of the lower bridge arm of Scheme 2

[0111]

[0112] Switching characteristics optimization

[0113] The extracted spurious parameters were imported into LTspice for a dual-pulse simulation test. The simulation results of the two layout schemes are shown below.

[0114] Figure 6 、 Figure 7 、 Figure 8 The following are the turn-on, turn-off and commutation waveforms of the upper bridge arm hybrid device under the two layout schemes. D The rise and fall rates are faster, and the turn-on and turn-off times are significantly reduced; the turn-on and turn-off losses are also reduced. This is because the drain inductance (L D ) and the source inductance (L S ) is significantly improved compared to Solution 1.

[0115] The commutation waveforms show only a slight increase in the commutation rate, and minimal changes in commutation losses. This is because, while the optimized solution reduces the stray inductance of the MOS branch in the upper arm, the stray inductance of the IGBT branch increases. Because the hybrid device is driven by switching the MOS transistor on first and then off, the increase in the IGBT branch's stray parameters does not deteriorate the hybrid device's transient switching trajectory, but does increase the total inductance of the commutation loop.

[0116] Figure 9 、 Figure 10 、 Figure 11 The following diagrams show the turn-on, turn-off, and commutation waveforms of the lower-arm hybrid device under the two layout schemes. The turn-on and turn-off waveforms show that, similar to the upper-arm hybrid device, the turn-on and turn-off transient trajectories of the hybrid device in Scheme 2 are improved, resulting in reduced transient losses. The commutation waveforms show a significant increase in the commutation rate and a decrease in commutation losses. This is because the optimized scheme not only reduces the stray inductance of the MOS branch in the lower-arm, but also optimizes the total stray inductance of the IGBT branch. This reduction in the total stray inductance of the hybrid device results in a faster commutation rate and reduced commutation time. This allows the IGBT to withstand high currents earlier, facilitating its conductivity modulation and reducing losses during the conduction process.

[0117] Overall, Scheme 2 achieves significant improvements in stray inductance parameters compared to Scheme 1. While maintaining a stable or even optimized commutation process, Scheme 2 effectively optimizes the device's turn-on and turn-off transient trajectories. This improvement not only helps reduce device losses but also provides a strong guarantee for the safe and reliable operation of the hybrid device in high-speed switching scenarios.

[0118] In summary, the method proposed in this application effectively reduces the complexity of multi-objective collaborative optimization. This research strategy significantly improves development efficiency while ensuring design accuracy, and provides a systematic solution for optimizing the parasitic parameters of hybrid power modules. Under the premise of ensuring that the commutation process does not deteriorate, the proposed layout optimization design method significantly improves the transient characteristics of the module switch, effectively reduces the switching loss, and provides a strong guarantee for the reliable operation of the hybrid module under high-speed switching conditions.

[0119] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A layout optimization design method for a heterogeneous hybrid half-bridge power module, characterized in that: include: Constructing a single-arm topology structure model of a heterogeneous hybrid half-bridge power module, wherein the single-arm topology structure model includes a SiC MOSFET device and a Si IGBT device; Determining the stray inductance that affects the gate voltage of the hybrid device based on the single-arm topology model of the heterogeneous hybrid half-bridge power module; Construct a physical model of a heterogeneous hybrid half-bridge power module; Performing simulation analysis on the physical model of the heterogeneous hybrid half-bridge power module to determine the optimization priority of the stray inductance; Based on the optimization priority of the stray inductance, an optimized design scheme for the hybrid half-bridge power module layout is determined.

2. The method according to claim 1, characterized in that The method of determining the stray inductance affecting the gate voltage of the hybrid device based on the single-arm topology structure model of the heterogeneous hybrid half-bridge power module, wherein the stray inductance includes the first-stage stray inductance and the second-stage stray inductance, comprises: Analyze the single-leg topology model of the heterogeneous hybrid half-bridge power module during the turn-on process to determine the first-stage stray inductance that affects the gate voltage of the SiC MOSFET device; The single-arm topology structure model of the heterogeneous hybrid half-bridge power module during the commutation process is analyzed by formula to determine the second-stage stray inductance that affects the gate voltage of the Si IGBT device.

3. The method according to claim 2, characterized in that The formula analysis of the single-arm topology structure model of the heterogeneous hybrid half-bridge power module during the turn-on process to determine the first-stage stray inductance affecting the gate voltage of the SiC MOSFET device includes: Performing formula analysis on the single-arm topology structure model of the heterogeneous hybrid half-bridge power module during the turn-on process to determine a first load current flowing through the SiC MOSFET device and a first gate voltage of the SiC MOSFET device; A first-stage stray inductance affecting a gate voltage of a SiC MOSFET device is determined based on the first load current and the first gate voltage.

4. The method according to claim 2, characterized in that The formula analysis of the single-arm topology structure model of the heterogeneous hybrid half-bridge power module during the commutation process to determine the second-stage stray inductance affecting the gate voltage of the Si IGBT device includes: Performing formula analysis on the single-arm topology structure model of the heterogeneous hybrid half-bridge power module during the commutation process to determine a second load current flowing through the Si IGBT device and a second gate voltage of the Si IGBT device; A second-stage stray inductance affecting the gate voltage of the Si IGBT device is determined based on the second load current and the second gate voltage.

5. The method according to claim 3, characterized in that The first-level stray inductance includes a drain inductance and a source inductance, and the second-level stray inductance includes a drain inductance, a source inductance, a collector inductance, and an emitter inductance.

6. The method according to claim 5, characterized in that The performing simulation analysis on the physical model of the heterogeneous hybrid half-bridge power module to determine the optimization priority of the stray inductance includes: The physical model of the heterogeneous hybrid half-bridge power module is input into LTspice software for simulation analysis, and it is determined that the drain inductance and the source inductance are the first optimization priority, and the collector inductance and the emitter inductance are the second optimization priority.

7. The method according to claim 6, characterized in that The step of determining a hybrid half-bridge power module layout optimization design scheme based on the optimization priority of the stray inductance includes: Based on the drain inductance and the source inductance being the first priority for optimization, the hybrid device is arranged vertically on the DBC board, and the upper surface of the SiC MOSFET device and the upper surface of the Si IGBT device are connected to the same DBC board through bonding wires.

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