Method for improving filling performance of high aspect ratio etched structure and semiconductor structure

Abstract

The application discloses a method for improving filling performance of high aspect ratio etching structure and a semiconductor structure. The method comprises the following steps: providing a substrate with a high aspect ratio etching structure on one side surface, the sidewall of the high aspect ratio etching structure has a first inclination angle of 88 degrees to 90 degrees; performing first processing on the top of the sidewall to form a chamfer; performing second processing on the sidewall to smooth the morphology of the chamfer and smooth the sidewall; performing third processing on the sidewall to make the sidewall incline in the same direction to have a second inclination angle of 84 degrees to 87 degrees; the first pressure, the second pressure and the third pressure increase in sequence, so that the processed sidewall has a horn-shaped morphology which inclines and bends inward from the top to the bottom. The application can solve the problems of incomplete filling, poor heat dissipation performance and unstable electrical connection in the prior art, and meets the requirements of high-performance devices on electrical connection and heat dissipation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor processing, in particular to a method for improving filling performance of high aspect ratio etching structure and a semiconductor structure. BACKGROUND

[0002] With the development of electronic devices, especially in high-performance integrated circuits, micro-electro-mechanical systems, image sensors and power electronic devices, silicon-based materials are increasingly widely used. Via technology with high aspect ratio plays a crucial role in these devices, which is used to realize electrical connection between multiple layers of circuits, heat management, light conduction and other functions. In order to improve the performance of the device, especially in high-power and high-density integrated circuits, higher requirements are put forward for the structure and filling effect of the via.

[0003] At present, most of the traditional via deep silicon etching methods adopt a vertical hole wall design, but with the miniaturization of device critical dimensions and the increase of aspect ratio, this design may have problems such as incomplete filling, poor heat dissipation performance, unstable electrical connection, etc. in some applications. Therefore, it is necessary to study a new method for improving the filling performance of high aspect ratio etching structure, which can meet the high performance requirements while overcoming the above-mentioned defects in the prior art. SUMMARY

[0004] The purpose of the present application is to overcome the above-mentioned problems existing in the prior art, and to provide a method for improving the filling performance of high aspect ratio etching structure and a semiconductor structure, which can meet the high performance requirements while overcoming the problems of incomplete filling, poor heat dissipation performance, unstable electrical connection, etc. existing in the prior art.

[0005] To achieve the above-mentioned purpose, the technical solutions of the present application are as follows:

[0006] According to the first aspect of the present application, the embodiments of the present application provide a method for improving the filling performance of high aspect ratio etching structure, which comprises the following steps in sequence:

[0007] (a) providing a substrate with a high aspect ratio etching structure on one side surface; the sidewall of the high aspect ratio etching structure has a first inclination angle of 88 degrees to 90 degrees;

[0008] (b) using a first process gas and a first pressure to perform a first treatment on the top of the sidewall to form a chamfer, so that the top width of the high aspect ratio etching structure is expanded from a first width to a second width;

[0009] (c) using a second process gas and a second pressure to perform a second treatment on the sidewall to smooth the morphology of the chamfer and smooth the sidewall;

[0010] (d) using a third process gas and a third pressure, performing a third treatment on the sidewall to make the sidewall symmetrical tilt to have a second tilt angle of 84 degrees to 87 degrees, and to make the top width of the high aspect ratio etching structure expand from the second width to a third width;

[0011] wherein the first process gas comprises an oxidizing gas, the second process gas comprises an oxidizing gas and a fluorocarbon gas, the third process gas comprises a sulfur-fluorine gas and a fluorocarbon gas, and the first pressure, the second pressure and the third pressure are sequentially increased to make the processed sidewall have a horn-shaped morphology that is curved inward from top to bottom.

[0012] In some embodiments, the angle of the chamfer is 5 degrees to 30 degrees.

[0013] In some embodiments, the providing a substrate having a high aspect ratio etching structure on a side surface specifically comprises:

[0014] providing a substrate, wherein the substrate material comprises silicon;

[0015] forming a plurality of mask patterns on a side surface of the substrate;

[0016] performing a first etching process and periodically and cyclically etching the exposed surface of the substrate through the mask patterns to form a high aspect ratio etching structure on a side surface of the substrate.

[0017] In some embodiments, after the side surface of the substrate is completely exposed by removing the mask patterns, the first treatment, the second treatment and the third treatment are sequentially performed.

[0018] In some embodiments, the first treatment is performed by executing a second etching process and using the first process gas and the first pressure, the second treatment is performed by executing a third etching process and using the second process gas and the second pressure, and the third treatment is performed by executing a fourth etching process and using the third process gas and the third pressure.

[0019] In some embodiments, when the second etching process is performed, the first process gas comprises O2, the flow rate is 10 sccm to 180 sccm, the first pressure is 10 mtorr to 50 mtorr, the temperature is 10°C to 60°C, and the time is 4s to 15s.

[0020] In some embodiments, when performing the third etching process, the second process gas comprises O2 and CF4, the flow rate of O2 is 10sccm-150sccm, the flow rate of CF4 is 10sccm-150sccm, the second pressure is 15mtorr-90mtorr, the temperature is 10℃-60℃, and the time is 4s-15s.

[0021] In some embodiments, when performing the fourth etching process, the third process gas comprises SF6 and C4F8, the flow rate of SF6 is 10sccm-200sccm, the flow rate of C4F8 is 10sccm-200sccm, the third pressure is 110mtorr-180mtorr, the temperature is 10℃-60℃, and the time is 10s-80s.

[0022] In some embodiments, the first etching process comprises periodic cycle steps formed by deposition steps and etching steps in sequence, the fourth process gas used in the deposition steps comprises C4F8, the fifth process gas used in the etching steps comprises SF6, and the high aspect ratio etching structure is formed by alternately depositing a passivation layer using C4F8 and etching using SF6.

[0023] In some embodiments, when performing the first etching process, the first oblique angle is 88 degrees-89 degrees and the sidewall roughness is reduced by gradually reducing the lateral etching amount of the substrate in each of the periodic cycle steps.

[0024] In some embodiments, when performing the first etching process, the flow rate of C4F8 is 10sccm-1000sccm, the flow rate of SF6 is 10sccm-1000sccm, the temperature is 10℃-60℃, the pressure is 1mtorr-100mtorr, the source power is 100W-3000W, and the bias power is 10W-200W.

[0025] According to a second aspect of the present application, the embodiments of the present application further provide a semiconductor structure comprising a high aspect ratio etching structure, wherein the high aspect ratio etching structure is processed by using the method for improving the filling performance of a high aspect ratio etching structure according to any one of the embodiments of the first aspect.

[0026] The embodiments of the present application can have / at least have the following advantages:

[0027] (1) The present application forms a high aspect ratio etching structure with a side wall having a smaller inclination angle (second inclination angle) by sequentially performing first processing, second processing and third processing on the side wall of the high aspect ratio etching structure on the substrate surface with a certain inclination angle (first inclination angle), which can realize the required depth by using the pre-formed high aspect ratio etching structure, ensure the stability of the depth and the uniformity of the size, and ensure the reasonable balance of the etching rate and the selection ratio, avoid the problem of uneven depth and width, and provide a stable reference for the subsequent processing process; on this basis, by sequentially performing first processing, second processing and third processing, the top width can be expanded, the smoothness of the top of the high aspect ratio etching structure can be effectively improved, the top can be ensured to be free of sharp corners, and the roughness of the side wall can be repaired to achieve an ideal surface quality, so that a high aspect ratio etching structure with a horn-shaped side wall morphology with a smaller inclination angle can be manufactured, thereby improving the shortcomings of the traditional single etching process in manufacturing high aspect ratio etching structures with inclined side walls (such as large side wall roughness and top morphology defects), providing higher flexibility and precision, and thus meeting the requirements of the inclination angle of the side wall in different applications, thereby meeting the requirements of high-performance devices for electrical connection and heat dissipation.

[0028] (2) The present application provides a complete set of manufacturing process of high aspect ratio etching structure with inclined angle side wall morphology, which solves the challenges of depth, morphology, inclination angle and other aspects, so that the high aspect ratio etching structure with improved side wall inclination angle can better control the filling effect during the subsequent metal filling process, avoid the defect of incomplete filling (such as voids), and significantly improve the performance and reliability of the high aspect ratio etching structure after filling.

[0029] (3) The present application not only overcomes the limitation of the traditional single etching process that cannot realize high-precision control, but also provides a more precise and controllable high aspect ratio etching structure etching scheme for the manufacturing of high-performance devices.

[0030] Other advantages of the present application will be described in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 A flowchart of a method for improving the filling performance of a high aspect ratio etching structure according to a preferred embodiment of the present application.

[0032] Figure 2 A structure schematic diagram after forming a mask pattern on a substrate according to a preferred embodiment of the present application.

[0033] Figure 3 A structure schematic diagram after forming a via with a first inclination angle of the side wall on a substrate according to a preferred embodiment of the present application.

[0034] Figure 4 A structure schematic diagram after removing the mask pattern provided for a preferred embodiment of the present application.

[0035] Figure 5 A structure schematic diagram after forming a chamfer on the top of the side wall of the via provided for a preferred embodiment of the present application.

[0036] Figure 6 A structure schematic diagram after smoothing the top of the chamfer and the side wall of the via provided for a preferred embodiment of the present application.

[0037] Figure 7 A structure schematic diagram after forming a via with a second inclined angle on the side wall on the substrate provided for a preferred embodiment of the present application.

[0038] Figure 8 A TEM schematic diagram of a traditional via A provided for Comparative Example 1.

[0039] Figure 9 A TEM schematic diagram of a traditional via B provided for Comparative Example 2.

[0040] Figure 10 A TEM schematic diagram of a via with a second inclined angle on the side wall provided for a preferred embodiment of the present application.

[0041] In the figure, 10. substrate; 11. mask pattern; 12. opening; 13. via; 14. scallop; 15. chamfer. DETAILED DESCRIPTION

[0042] In order to solve the problems of incomplete filling, poor heat dissipation performance, and unstable electrical connection of the vertical via manufactured by the traditional process in the prior art, the embodiments of the present application provide a method for improving the filling performance of high aspect ratio etching structure, which comprises the following steps in sequence:

[0043] (a) providing a substrate with a high aspect ratio etching structure on a side surface; the side wall of the high aspect ratio etching structure has a first inclined angle of 88 degrees to 90 degrees;

[0044] (b) using a first process gas and a first pressure to perform a first treatment on the top of the side wall to form a chamfer, so that the top width of the high aspect ratio etching structure is expanded from a first width to a second width;

[0045] (c) using a second process gas and a second pressure to perform a second treatment on the side wall to smooth the top of the chamfer and the side wall;

[0046] (d) Using a third process gas and a third pressure, the sidewall is subjected to a third treatment, causing the sidewall to tilt in the same direction to a second tilt angle of 84 to 87 degrees, and increasing the top width of the high aspect ratio etched structure from the second width to the third width;

[0047] The first process gas includes an oxidizing gas, the second process gas includes an oxidizing gas and a fluorocarbon gas, and the third process gas includes a sulfur-fluorine gas and a fluorocarbon gas. The first pressure, the second pressure, and the third pressure increase sequentially so that the processed sidewall has a trumpet-shaped morphology that bends inward from top to bottom.

[0048] The high aspect ratio etched structure processed according to the embodiments of this application has a specific tilt angle on the sidewalls, providing greater flexibility and precision. Furthermore, the improved processing technology controls the smoothness of the top and the roughness of the sidewalls, enabling it to meet the electrical connection and thermal management requirements of high-performance electronic devices. The embodiments of this application not only overcome the limitations of traditional single etching processes, solving challenges related to depth, morphology, and tilt angle, but also provide a more refined and controllable processing solution for the manufacture of high-performance devices, significantly improving the filling performance and reliability of high aspect ratio etched structures.

[0049] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0050] refer to Figure 1 This application provides a method for improving the filling performance of high aspect ratio etched structures, which includes the following steps:

[0051] Step S11: Provide a substrate.

[0052] refer to Figure 2 In some embodiments, the material of substrate 10 includes silicon, i.e., substrate 10 is a silicon substrate.

[0053] In some embodiments, a silicon wafer may be used as substrate 10 to further form the desired high aspect ratio etched structure on substrate 10.

[0054] In some embodiments, the silicon wafer may be doped to provide a substrate 10 that meets the required electrical properties.

[0055] In some embodiments, an integrated circuit, such as a transistor structure, may be fabricated on the substrate 10 to achieve the desired vertical interconnect by filling metal after forming a high aspect ratio etched structure and processing it.

[0056] Step S12: Form multiple mask patterns on the surface of the substrate.

[0057] Reference Figure 2 In some embodiments, a photoresist layer is formed on the upper surface of the substrate 10 as a mask pattern layer. A photolithography process is performed on the photoresist layer to form a plurality of photoresist patterns on the upper surface of the substrate 10, and the photoresist patterns are used as the mask patterns 11. Any two adjacent mask patterns 11 have an opening 12 therebetween as an etching window.

[0058] It should be noted that, Figure 2 In the embodiment, only the case where three mask patterns 11 are formed on the upper surface of the substrate 10 is shown. However, it should be understood that other different numbers of mask patterns can be formed on the upper surface of the substrate 10, such as two mask patterns, four mask patterns, five mask patterns, ten mask patterns, and the like, and the application is not limited thereto.

[0059] Step S13: performing a first etching process and periodically and cyclically etching the exposed surface of the substrate through the mask patterns to form a high-aspect-ratio etching structure with a first inclination angle of 88 degrees to 90 degrees of the side wall on one side surface of the substrate.

[0060] In some embodiments, the high-aspect-ratio etching structure includes a trench or a via, and the like. The following will take the case of forming a via as the high-aspect-ratio etching structure on the substrate 10 as an example to describe the embodiments of the application in detail.

[0061] Reference Figure 3 In some embodiments, the first etching process is performed, and the upper surface of the substrate 10 exposed in the opening 12 is periodically and cyclically etched downward through the mask patterns 11 formed in the previous step to form a via 13 in the substrate 10 on the upper surface of the substrate 10 exposed in the opening 12.

[0062] In some embodiments, before the first etching process is performed, the substrate 10 is pre-etched to open the upper surface of the substrate 10. That is, the bottom of the opening 12 is pre-etched downward through the mask patterns 11 formed in the previous step to expose the upper surface of the substrate 10 on the bottom of the opening 12, so that the upper surface of the substrate 10 exposed in the opening 12 can be periodically and cyclically etched downward in the subsequent first etching process.

[0063] In some embodiments, the first etching process comprises periodic cycle steps of deposition steps and etching steps in sequence. That is, each cycle step comprises a deposition step and an etching step, and the cycle is repeated to form a periodic cycle etching. In the deposition step, a passivation layer (polymer) is formed to protect the sidewall and the mask pattern 11. In the etching step, the passivation layer on the inner wall of the via 13 being formed and the surface of the mask pattern 11 is etched open first, and then the etching continues downward by one unit depth of the substrate 10. In the etching step, the passivation layer on the sidewall of the via 13 being formed and the surface of the mask pattern 11 is also etched and consumed. In the deposition step of the next cycle, the passivation layer is deposited again on the inner wall of the via 13 being formed and the surface of the mask pattern 11, so as to continuously protect the sidewall and the mask pattern 11. In the etching step of the cycle, the new passivation layer on the bottom of the via 13 being formed is etched open again, and then the etching continues downward by one unit depth of the substrate 10. Through the above process, the periodic cycle etching is performed on the substrate 10, and the via 13 with a preset depth and a sidewall with a first inclination angle of 88 degrees to 90 degrees is formed in the substrate 10. In other words, the first inclination angle can be a perpendicular angle (90 degrees) or can have a certain slope (88 degrees to less than 90 degrees). When the first inclination angle is 90 degrees, the slope is 0 degrees.

[0064] It should be noted that in the first etching process, the etching step in each cycle is isotropically performed on the substrate 10, and due to the repeated deposition and passivation, a periodic wave pattern like a scallop (Scallop) is inevitably formed on the sidewall, that is, a scallop pattern 14, so as to increase the roughness of the sidewall and affect the via filling quality. Therefore, the subsequent steps can be used to improve the via filling quality.

[0065] The via 13 formed by the first etching process has a first roughness on the sidewall.

[0066] The via 13 formed by the first etching process has a first width L of the top width and a sidewall with a first inclination angle. The first inclination angle is a first included angle a between the sidewall of the via 13 and the cross-sectional direction (horizontal direction) of the via 13.

[0067] In some embodiments, in the first etching process, the deposition step uses a process gas comprising C4F8, and the etching step uses a process gas comprising SF6. By alternately using C4F8 to deposit the passivation layer and using SF6 to etch, the via 13 with the first width L, the first inclination angle and the first roughness is formed.

[0068] In some embodiments, the flow rate of C4F8 used in the deposition step when performing the first etching process is between 10 sccm and 1000 sccm. For example, the flow rate can be 10 sccm, 50 sccm, 100 sccm, 500 sccm, 800 sccm, 1000 sccm, or any value between any two of the aforementioned values. The flow rate range is not limited to this.

[0069] In some embodiments, the flow rate of SF6 used in the etching step when performing the first etching process is between 10 sccm and 1000 sccm. For example, the flow rate can be 10 sccm, 20 sccm, 60 sccm, 100 sccm, 500 sccm, 1000 sccm, or any value between any two of the aforementioned values. The flow rate range is not limited to this.

[0070] In some embodiments, an inert gas can also be used as a carrier gas when performing the first etching process. For example, argon (Ar) can be used as the carrier gas, and the flow rate is between 10 sccm and 500 sccm. For example, the flow rate can be 10 sccm, 40 sccm, 90 sccm, 200 sccm, 500 sccm, or any value between any two of the aforementioned values. The flow rate range is not limited to this.

[0071] In some embodiments, the temperature when performing the first etching process is between 10 °C and 60 °C. For example, the temperature can be 10 °C, 20 °C, 30 °C, 35 °C, 40 °C, 45 °C, 50 °C, 60 °C, or any value between any two of the aforementioned values. The temperature range is not limited to this.

[0072] In some embodiments, the pressure when performing the first etching process is between 1 mtorr and 100 mtorr. For example, the pressure can be 1 mtorr, 1.2 mtorr, 5 mtorr, 10 mtorr, 20 mtorr, 25 mtorr, 30 mtorr, 50 mtorr, 80 mtorr, 100 mtorr, or any value between any two of the aforementioned values. The pressure range is not limited to this.

[0073] In some embodiments, the source power when performing the first etching process is between 100 W and 3000 W. For example, the source power can be 100 W, 200 W, 500 W, 800 W, 1000 W, 1500 W, 2000 W, 2500 W, 3000 W, or any value between any two of the aforementioned values. The source power range is not limited to this.

[0074] In some embodiments, the bias power is 10W-200W when performing the first etching process. For example, the bias power can be 10W, 20W, 30W, 50W, 80W, 100W, 130W, 150W, 190W or 200W, or any value between any two of the foregoing bias power values. The bias power range can not be limited to this.

[0075] In some embodiments, when performing the first etching process, the lateral etching amount of the substrate 10 in each cycle step is gradually reduced to ensure balance between the deposition step and the etching step process, so that the first inclination angle is 88-89 degrees, and the overall etching morphology presents a certain conical hole shape. This etching method can also reduce the protruding degree of the sidewall scallop 14 to some extent, so that the sidewall surface is relatively smooth, thereby reducing the first roughness. The amount of lateral etching can be controlled by adjusting the etching step time in each cycle.

[0076] In some embodiments, the first roughness of the sidewall of the via hole 13 is about 30-50nm. However, it can not be limited to this.

[0077] In some embodiments, the aspect ratio of the via hole 13 is greater than 3:1, or greater than 5:1, or greater than 10:1. However, it can not be limited to this.

[0078] Step S14: removing the mask pattern.

[0079] Reference Figure 4 In some embodiments, a dry ashing and delamination process (an asher process) is used to remove the photoresist, i.e., the photoresist pattern is completely removed as the mask pattern 11. After removing the photoresist pattern (mask pattern 11), the entire upper surface of the substrate 10 is completely exposed, i.e., the upper surface of the substrate 10 on both sides of the via hole 13 is no longer protected by the mask pattern 11.

[0080] In some embodiments, when using a dry ashing and delamination process to remove the photoresist pattern 11 as the mask pattern 11, at least one of the process gases used includes a mixture of O2, H2 and N2, N2, etc., but can not be limited to this.

[0081] Step S15: performing a second etching process to perform a first treatment on the top of the high aspect ratio etching structure to form a chamfer, so that the top width of the high aspect ratio etching structure is expanded from a first width to a second width.

[0082] Reference Figure 5In some embodiments, a second etching process different from the periodic cycle etching of the first etching process is performed to etch the top of the sidewall of the via 13 as the first treatment to form a chamfer 15 on the top of the sidewall of the via 13, so as to expand the top width of the via 13 from the first width L to the second width M. Different from the periodic cycle etching of the first etching process, the second etching process only includes the corresponding etching step itself, and does not contain the deposition step as in the first etching process.

[0083] Since the mask pattern 11 in the previous step has been completely removed, the second etching process in the present step is performed to etch the upper surface of the substrate 10 without the mask pattern 11 on the upper surface of the substrate 10, that is, a maskless etching process is performed.

[0084] In some embodiments, the second etching process uses the first process gas and the first pressure to etch the top of the sidewall of the via 13 to form the chamfer 15 on the top of the sidewall of the via 13. Figure 5 The chamfer 15 is formed on the top of the sidewall of the via 13.

[0085] Reference is made to Figure 5 In some embodiments, when the second etching process is performed, the first process gas used includes an oxidizing gas. For example, the first process gas includes O2, and an inert gas such as Ar or the like can be used as a dilution and dissociation gas to etch the via 13 without any mask pattern, and to form the chamfer 15 on the top of the sidewall of the via 13.

[0086] In some embodiments, when the second etching process is performed, the flow rate of O2 as the first process gas is 10sccm-180sccm. For example, the flow rate can be 10sccm, 20sccm, 50sccm, 100sccm, 110sccm, 130sccm, 150sccm, or 180sccm, or any value between any two of the foregoing values. The flow rate range can not be limited to this.

[0087] In some embodiments, when the second etching process is performed, the temperature is 10°C-60°C. For example, the temperature can be 10°C, 11°C, 15°C, 20°C, 25°C, 30°C, 40°C, 45°C, 50°C, or 60°C, or any value between any two of the foregoing values. The temperature range can not be limited to this.

[0088] In some embodiments, when the second etching process is performed, the first pressure is 10mtorr-50mtorr. For example, the first pressure can be 10mtorr, 15mtorr, 20mtorr, 25mtorr, 30mtorr, 40mtorr, or 50mtorr, or any value between any two of the foregoing values. The first pressure range can not be limited to this.

[0089] In some embodiments, the source power is 100W-3000W when performing the second etching process. For example, the source power can be 100W, 200W, 500W, 800W, 1000W, 1500W, 2000W, 2500W or 3000W, or any value between any two of the foregoing source power values. The source power range can not be limited to this.

[0090] In some embodiments, the bias power is 10W-100W when performing the second etching process. For example, the bias power can be 10W, 20W, 30W, 40W, 50W, 60W, 70W, 80W, 90W or 100W, or any value between any two of the foregoing bias power values. The bias power range can not be limited to this.

[0091] In some embodiments, the time is 4s-15s when performing the second etching process. For example, the time can be 4s, 5s, 6s, 7s, 8s, 9s, 10s, 11s, 12s, 13s, 14s or 15s, or any value between any two of the foregoing time values. The time range can not be limited to this.

[0092] After performing the second etching process, a structure of the via hole 13 with a chamfer 15 at the top of the side wall is formed, that is, a first transition via hole structure is formed, as shown in Figure 5 .

[0093] In some embodiments, the angle of the chamfer 15 is a third inclination angle, which is a third included angle θ between the surface of the chamfer and the horizontal direction of the cross section of the via hole 13 in the outward direction. The third included angle θ is an acute angle, and the third included angle θ is smaller than the first included angle α.

[0094] In some embodiments, the third inclination angle (the third included angle θ) is 5-30 degrees. However, it can not be limited to this.

[0095] In some embodiments, when performing the second etching process, the size of the third inclination angle can be controlled by adjusting the size of the bias power on the basis of using the first pressure. Moreover, the size of the bias power is directly proportional to the size of the third inclination angle.

[0096] The purpose of forming the chamfer 15 on the top of the sidewall of the via 13 is to provide a transitional basic structure (first transitional via structure) for the subsequent formation of the first via 13 with a smaller sidewall inclination angle. That is, a chamfer 15 with a certain inclination angle is formed in advance on the top of the via 13, so that the aperture width dimension of the top of the via 13 is enlarged, an etching guide structure is formed, and the pattern transfer can be performed downward using the chamfer 15 as the guide structure for subsequent etching, so that the overall sidewall morphology with a certain inclination angle can be further obtained.

[0097] Since the chamfer 15 formed in this step has a relatively sharp chamfer step morphology, in order to avoid the step morphology from being transferred downward and affecting the smoothness of the sidewall, it is necessary to perform smoothing treatment on the top morphology of the via 13 at the chamfer 15. Moreover, since the first etching process is used to form the periodic scallop 14 on the sidewall of the via 13, resulting in a relatively high sidewall roughness, it is also necessary to perform smoothing treatment to ensure that the via 13 finally has a smooth sidewall and improve the filling quality.

[0098] Step S16: performing a third etching process to perform a second treatment on the sidewall of the high aspect ratio etching structure to smooth the morphology of the chamfer and smooth the sidewall.

[0099] Reference Figure 6 In some embodiments, a third etching process different from the periodic cycle etching of the first etching process is performed to perform etching treatment on the entire sidewall of the via 13 including the surface of the chamfer 15 as the second treatment, and a second process gas and a second pressure are used to smooth the top morphology at the chamfer 15 and modify the sidewall of the via 13 to smooth the sidewall of the via 13. The third etching process only includes its own corresponding etching step, and does not contain the deposition step as in the first etching process.

[0100] In some embodiments, when the third etching process is performed, the second process gas used includes an oxidizing gas and a fluorocarbon gas. For example, the second process gas includes O2 and CF4, and an inert gas such as Ar can be used as a dilution and dissociation gas. In the absence of a mask, the via 13 with the formed chamfer 15 is further etched to eliminate the relatively sharp step morphology of the chamfer 15, smooth the top morphology at the chamfer 15, and at the same time, the etching also has a modification effect on the sidewall of the via 13, which can eliminate the scallop 14 on the sidewall and smooth the original rough sidewall of the via 13 (smoothing).

[0101] Compared with the second etching process, when the third etching process is performed, CF4 is further added to O2 as the second process gas, and the second pressure is increased to some extent to improve the isotropic etching ability of the reaction, and at the same time, the sidewall damage can be reduced by correspondingly reducing the bias power.

[0102] In some embodiments, the flow rate of O2 is 10 sccm to 150 sccm and the flow rate of CF4 is 10 sccm to 150 sccm when performing the third etching process. For example, the flow rate of O2 can be 10 sccm, 20 sccm, 50 sccm, 100 sccm, 120 sccm, 130 sccm, 140 sccm, or 150 sccm, or any value between any two of the foregoing flow rates of O2. The flow rate of CF4 can be 10 sccm, 20 sccm, 40 sccm, 80 sccm, 100 sccm, 120 sccm, 130 sccm, 140 sccm, or 150 sccm, or any value between any two of the foregoing flow rates of CF4. The flow rates of O2 and CF4 are not limited to the foregoing ranges.

[0103] In some embodiments, the temperature is 10 °C to 60 °C when performing the third etching process. For example, the temperature can be 10 °C, 11 °C, 15 °C, 20 °C, 25 °C, 30 °C, 40 °C, 45 °C, 50 °C, or 60 °C, or any value between any two of the foregoing temperatures. The temperature is not limited to the foregoing range.

[0104] In some embodiments, the second pressure is 15 mtorr to 90 mtorr when performing the third etching process. For example, the second pressure can be 15 mtorr, 20 mtorr, 30 mtorr, 35 mtorr, 50 mtorr, 70 mtorr, 80 mtorr, or 90 mtorr, or any value between any two of the foregoing pressures. The second pressure is not limited to the foregoing range.

[0105] In some embodiments, the source power is 100 W to 3000 W when performing the third etching process. For example, the source power can be 100 W, 200 W, 500 W, 800 W, 1000 W, 1500 W, 2000 W, 2500 W, or 3000 W, or any value between any two of the foregoing source powers. The source power is not limited to the foregoing range.

[0106] In some embodiments, the bias power is 0 W to 90 W when performing the third etching process. For example, the bias power can be 0 W, 10 W, 20 W, 30 W, 40 W, 50 W, 60 W, 70 W, 80 W, or 90 W, or any value between any two of the foregoing bias powers. The bias power is not limited to the foregoing range.

[0107] In some embodiments, the third etching process is performed for 4s to 15s. For example, the time can be 4s, 5s, 6s, 7s, 8s, 9s, 10s, 11s, 12s, 13s, 14s, or 15s, or any value between any two of the aforementioned time values. The time range is not limited to this.

[0108] After the third etching process is performed, the surface of the chamfer 15 at the top of the via 13 is smoothed, so that the entire top profile at the chamfer 15 is also smoothed. At the same time, the etching in the third etching process acts on the sidewall surface of the via 13, which can eliminate (or substantially eliminate) the original periodic scallop pattern 14 on the sidewall of the via 13, so that the sidewall of the via 13 is smoothed, thereby reducing the sidewall roughness and improving the smoothness of the sidewall. After the etching in the third etching process, the sidewall roughness of the via 13 can be reduced to about 10nm to 25nm based on the first roughness. Moreover, the top aperture width of the via 13 can be further enlarged due to the smoothing of the top profile.

[0109] After the third etching process is performed, the structure of the via 13 after the top profile at the chamfer 15 is smoothed and the sidewall is smoothed, i.e., the second transition via structure, is formed, as shown in Figure 6 .

[0110] By performing the third etching process, the top profile at the chamfer 15 is smoothed, the sidewall of the via 13 is smoothed, and the top aperture width of the via 13 is further enlarged, thereby laying a foundation for performing the fourth etching process to form the via 13 with a specific inclined sidewall profile.

[0111] Step S17: performing a fourth etching process to perform a third treatment on the sidewall of the high aspect ratio etching structure, so that the sidewall has a second inclination angle of 84 degrees to 87 degrees, and the top width of the high aspect ratio etching structure is enlarged from the second width to a third width.

[0112] Reference Figure 7 In some embodiments, the fourth etching process different from the periodic cycle etching of the first etching process is performed to perform an etching treatment on the sidewall of the via 13 as the third treatment, and a third process gas and a third pressure are used to form the via 13 with the third width N at the top and the second inclination angle at the sidewall, so that the processed via 13 has a horn-shaped sidewall profile that is inclined and curved inward from the top to the bottom. That is, the top aperture width (the third width N) of the via 13 is greater than the bottom aperture width, the aperture gradually decreases from the top to the bottom, forming a nearly horn-shaped via 13 with a large top and a small bottom. The fourth etching process only includes its own corresponding etching step, and does not contain a deposition step like the first etching process.

[0113] In some embodiments, the through hole 13 has an open top and a side wall curved outwardly in the lateral direction, as shown in FIG. 1. Figure 7

[0114] In some embodiments, the second inclined angle is a second included angle β between the side wall of the through hole 13 and the cross-sectional direction (horizontal direction) of the through hole 13 in the outward direction. The second included angle β is an acute angle, and the second included angle β is smaller than the first included angle α, and the third included angle θ is smaller than the second included angle β.

[0115] In some embodiments, the second inclined angle (second included angle β) is 84-87 degrees. However, it can not be limited thereto.

[0116] In some embodiments, the side wall segment of the top open part of the through hole 13 has a smaller curved inclined angle than the side wall segment of the lower part, which is less than 84-87 degrees.

[0117] In some embodiments, when performing the fourth etching process, the third process gas used includes sulfur fluoride gas and fluorocarbon gas. For example, the third process gas includes SF6 and C4F8, and an inert gas such as Ar can be used as a dilution and dissociation gas. In the same way, the etching process is performed on the through hole 13 (second transition through hole structure) after the top profile of the chamfer 15 is smoothed and the side wall is smoothed without a mask, to further expand the top aperture width and form a more inclined side wall, i.e., to further reduce the side wall inclined angle.

[0118] In some embodiments, when performing the fourth etching process, the third process gas includes SF6, C4F8 and O2. By adding an appropriate amount of O2, the polymer forming ability of C4F8 can be controlled to avoid excessive polymerization affecting the etching effect.

[0119] Compared with the third etching process, in order to expand the top aperture width and form a more inclined side wall, the third pressure needs to be kept at a high level when performing the etching of the fourth etching process, so as to intensify the isotropic etching during the reaction to form an open curved profile. At the same time, by using the third process gas, the etching rate can be reduced to avoid excessive etching. In addition, the bottom width of the through hole 13 can be ensured by adjusting the bias power (relatively increasing the bias power can reduce the tendency of the bottom width to expand).

[0120] ​In some embodiments, the flow rate of SF6 is 10 sccm to 200 sccm and the flow rate of C4F8 is 10 sccm to 200 sccm when performing the etching of the fourth etching process. For example, the flow rate of SF6 can be 10 sccm, 20 sccm, 50 sccm, 100 sccm, 130 sccm, 150 sccm, 180 sccm, or 200 sccm, or any value between any two of the foregoing flow rates of SF6. The flow rate of C4F8 can be 10 sccm, 20 sccm, 50 sccm, 100 sccm, 130 sccm, 150 sccm, 180 sccm, or 200 sccm, or any value between any two of the foregoing flow rates of C4F8. The flow rates of SF6 and C4F8 are not limited to the foregoing ranges.

[0121] In some embodiments, the temperature is 10 °C to 60 °C when performing the etching of the fourth etching process. For example, the temperature can be 10 °C, 11 °C, 15 °C, 20 °C, 25 °C, 30 °C, 40 °C, 45 °C, 50 °C, or 60 °C, or any value between any two of the foregoing temperatures. The temperature is not limited to the foregoing ranges.

[0122] In some embodiments, the third pressure is 110 mtorr to 180 mtorr when performing the etching of the fourth etching process. For example, the third pressure can be 110 mtorr, 120 mtorr, 130 mtorr, 135 mtorr, 150 mtorr, 160 mtorr, 170 mtorr, or 180 mtorr, or any value between any two of the foregoing pressures. The third pressure is not limited to the foregoing ranges.

[0123] In some embodiments, the source power is 100 W to 3000 W when performing the etching of the fourth etching process. For example, the source power can be 100 W, 200 W, 500 W, 800 W, 1000 W, 1500 W, 2000 W, 2500 W, or 3000 W, or any value between any two of the foregoing source powers. The source power is not limited to the foregoing ranges.

[0124] In some embodiments, the bias power is 0 W to 100 W when performing the etching of the fourth etching process. For example, the bias power can be 0 W, 10 W, 20 W, 30 W, 40 W, 50 W, 60 W, 70 W, 80 W, 90 W, or 100 W, or any value between any two of the foregoing bias powers. The bias power is not limited to the foregoing ranges.

[0125] In some embodiments, the etching of the fourth etching process is performed for 10-80 seconds. For example, the etching can be performed for 10 seconds, 15 seconds, 20 seconds, 30 seconds, 40 seconds, 50 seconds, 65 seconds, 70 seconds, or 80 seconds, or any value between any two of the aforementioned values. The time range is not limited to the above.

[0126] In some embodiments, the sidewall of the via hole 13 has a second roughness. By performing the third etching process to smooth the top profile at the chamfer 15 and to smooth the sidewall of the via hole 13, the original first roughness of the via hole 13 is reduced, so that after the etching of the fourth etching process, the second roughness of the sidewall of the via hole 13 is also reduced accordingly, so that the second roughness is smaller than the original first roughness.

[0127] After the etching of the fourth etching process, the structure of the via hole 13 formed is as shown in FIG. 6. Figure 7 As compared with Figure 4 or Figure 3 It can be seen that after the etching of the fourth etching process, the top aperture width (third width N) of the via hole 13 is further enlarged. The third width N of the final via hole 13 is significantly larger than the initial first width L and the second width M. Moreover, the sidewall of the via hole 13 has a more inclined sidewall, and the second inclination angle is smaller than the first inclination angle (the second included angle β is smaller than the first included angle α). Moreover, the smooth profile of the sidewall formed after the etching of the third etching process is well transferred in the etching of the fourth etching process, so that the final sidewall of the via hole 13 after processing also has a smooth profile, and thus the quality of subsequent via hole filling can be improved, and the generation of filling voids can be effectively prevented.

[0128] In some embodiments, the second etching process, the third etching process, and the fourth etching process are non-periodic cyclic dry etching processes, which are different from the periodic cyclic dry etching process of the first etching process.

[0129] In some embodiments, the first pressure in the second etching process, the second pressure in the third etching process, and the third pressure in the fourth etching process are sequentially increased, so that the sidewall after processing has a horn-shaped profile that is curved inwardly from the top to the bottom.

[0130] In some embodiments, the first etching gas, the second etching gas, and the third etching gas are different from each other and different from the process gas in the first etching process.

[0131] In some embodiments, after the mask pattern 11 is removed to completely expose one side surface of the substrate 10, the first treatment, the second treatment, and the third treatment are sequentially performed.

[0132] Subsequently, a metal deposition process can be used to fill the via 13 with metal, and a planarization process (e.g., a chemical mechanical polishing process) can be used to remove excess metal material on the top surface of the substrate 10 to form a metal via with a flat top (not shown). Other process steps required for chip manufacturing can be performed subsequently, and will not be described herein.

[0133] In the metal filling process, the via 13 with the improved sidewall inclination angle can better control the filling effect, avoid incomplete filling defects, and make the obtained metal via meet the requirements of high-performance devices in electrical connection and heat dissipation, thereby improving the stability and performance of the device.

[0134] Figure 8 A conventional via A structure formed in a substrate using a conventional periodic cyclic dry etching process is shown. The conventional via A is a vertical via with a sidewall inclination angle of about 89 degrees. Figure 8 The mark 1 indicates a top width of 36.215 microns in the X direction, the mark 2 indicates a bottom width of 30.758 microns in the X direction, and the mark 3 indicates a depth of 102.20 microns in the Y direction. Figure 9 A conventional via B structure formed in a substrate using a conventional non-periodic cyclic dry etching process is shown. The conventional via B is an inclined via with a sidewall inclination angle of about 87 degrees. The conventional periodic cyclic dry etching process has advantages in etching rate and etching selectivity, but is limited in manufacturing complex hole shapes and high-performance devices due to challenges in inclination angle control, top smoothness, and sidewall roughness. The conventional non-periodic cyclic dry etching process can manufacture inclined vias with a certain inclination angle, but its low etching rate and poor selectivity characteristics limit its application in high-performance devices.

[0135] Figure 10 An electron microscope diagram of a via with a sidewall having a second inclination angle processed using the method for improving the filling performance of a high aspect ratio etching structure is shown. The second inclination angle of the via is about 85 degrees. Figure 10 The mark 1 indicates a depth of 86.568 microns in the Y direction, the mark 2 indicates a top width of 58.415 microns in the X direction, and the mark 3 indicates a bottom width of 35.843 microns in the X direction. Compared with the conventional via A and the conventional via B shown above, Figure 8 Compared with the conventional via A and the conventional via B shown above, Figure 9 Compared with the conventional via A and the conventional via B shown above, Figure 10 The via with a sidewall having a second inclination angle shown has a more inclined sidewall, a larger overall opening, a more inclined and smoother top angle, and a smooth sidewall, thereby facilitating the filling of a high-quality metal via.

[0136] The present application forms the via hole 13 with a smaller inclination angle (second inclination angle) of the sidewall by sequentially performing the first treatment, the second treatment and the third treatment on the sidewall of the via hole 13 on the surface of the substrate 10 with a certain inclination angle (first inclination angle), can realize the required depth by using the pre-formed via hole 13, and ensure the stability of the depth and the uniformity of the size, while ensuring the reasonable balance of the etching rate and the selection ratio, avoiding the problem of uneven depth and width, providing a stable reference for the subsequent processing technology; on this basis, by sequentially performing the first treatment, the second treatment and the third treatment, the top width can be expanded, the smoothness of the top of the via hole 13 can be effectively improved, the top can be ensured to be free of sharp corners, and the roughness of the sidewall can be repaired to achieve an ideal surface quality, so that the via hole 13 with a trumpet-shaped sidewall morphology with a smaller inclination angle can be manufactured, thereby improving the shortcomings of the traditional single etching process in manufacturing the via hole with an inclined sidewall (such as the problems of large sidewall roughness and top morphology defects), providing higher flexibility and precision, and thus meeting the requirements of the sidewall inclination angle in different applications, thereby meeting the requirements of high-performance devices in electrical connection and heat dissipation.

[0137] The embodiment of the present application also provides a semiconductor structure, which contains a high aspect ratio etching structure processed by the method for improving the filling performance of the high aspect ratio etching structure.

[0138] Reference Figure 7 In some embodiments, the semiconductor structure includes a substrate 10, and the substrate 10 is provided with a via hole 13 as a high aspect ratio etching structure, and the via hole 13 is processed by the method for improving the filling performance of the high aspect ratio etching structure, so that the sidewall of the processed via hole 13 has a second inclination angle of 84 degrees to 87 degrees, and the top width of the via hole 13 is expanded from the original first width L to a third width N. The processed sidewall has a trumpet-shaped morphology that is inclined and curved inward from the top to the bottom, and the sidewall surface is smooth, so that the roughness is effectively reduced.

[0139] In some embodiments, the semiconductor structure is applied to the field of three-dimensional advanced packaging, and the filled high aspect ratio etching structure formed on the substrate is used as a vertical interconnection structure on a 3D integrated circuit chip.

[0140] In a third aspect, the embodiment of the present application also provides a plasma processing device, which is used to perform the first etching process to the fourth etching process corresponding to the above-mentioned embodiments to manufacture (process) the high aspect ratio etching structure with the sidewall having the second inclination angle corresponding to the above-mentioned embodiments. The plasma processing device can be, for example, an inductively coupled plasma (ICP) etching device or a capacitively coupled plasma (CCP) etching device.

[0141] In other aspects, the embodiments of the present application also provide an electronic device comprising a semiconductor structure obtained by using the method for improving the filling performance of high aspect ratio etching structure of the above embodiments. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0142] In summary, the embodiments of the present application combine the high aspect ratio etching structure forming process (first etching process) and the processing process (second to fourth etching processes), not only overcoming the limitations of traditional single etching process that cannot achieve high precision control, but also providing a more precise and controllable process scheme for the manufacturing of high-performance devices. Moreover, the embodiments of the present application provide a complete set of efficient manufacturing processing technology for high aspect ratio etching structure with inclined angle sidewall, solving the challenges in depth, morphology, inclination angle, etc. In the filling process, through the improved high aspect ratio etching structure, the filling effect can be better controlled, avoiding the defect of incomplete filling, and significantly improving the device performance and reliability. The present application can be widely applied in the manufacturing of high-performance devices, including but not limited to integrated circuits, power electronic devices, image sensors (CIS), MEMS devices and optoelectronic devices, etc.

[0143] The above is only the preferred embodiments of the present application, and the embodiments are not intended to limit the protection scope of the present application, therefore, any equivalent changes made according to the content of the specification and drawings of the present application shall be included in the protection scope of the present application.

Claims

1. A method for improving the fill performance of high aspect ratio etched structures, comprising: The method comprises the following steps in sequence: (a) providing a substrate with high aspect ratio etching structures on one side surface; the sidewall of the high aspect ratio etching structure has a first inclination angle of 88 degrees to 90 degrees; (b) performing a first treatment on the top of the sidewall using a first process gas and a first pressure to form a chamfer, so that the top width of the high aspect ratio etching structure is expanded from a first width to a second width; (c) performing a second treatment on the sidewall using a second process gas and a second pressure to smooth the morphology of the chamfer and smooth the sidewall; (d) performing a third treatment on the sidewall using a third process gas and a third pressure to make the sidewall incline in the same direction to have a second inclination angle of 84 degrees to 87 degrees, and to expand the top width of the high aspect ratio etching structure from the second width to a third width; wherein the first process gas comprises an oxidizing gas, the second process gas comprises an oxidizing gas and a fluorocarbon gas, the third process gas comprises a sulfur-fluorine gas and a fluorocarbon gas, and the first pressure, the second pressure and the third pressure increase in sequence, so that the processed sidewall has a horn-shaped morphology that inclines and curves inward from top to bottom.

2. The method of claim 1, wherein, The angle of the chamfer is 5 degrees to 30 degrees.

3. The method for improving the filling performance of high aspect ratio etched structures according to claim 1, characterized in that, The method of providing a substrate with high aspect ratio etching structures on one side surface specifically comprises: providing a substrate, and the substrate material comprises silicon; forming a plurality of mask patterns on one side surface of the substrate; performing a first etching process and periodically and cyclically etching the exposed surface of the substrate through the mask patterns to form high aspect ratio etching structures on one side surface of the substrate.

4. The method of claim 3, wherein the method is performed by adding a surfactant to the etching solution. After completely exposing one side surface of the substrate by removing the mask patterns, the first treatment, the second treatment and the third treatment are performed in sequence.

5. The method of claim 4, wherein, The first treatment is performed by executing a second etching process and using the first process gas and the first pressure; The second treatment is performed by executing a third etching process and using the second process gas and the second pressure; The third treatment is performed by executing a fourth etching process and using the third process gas and the third pressure.

6. The method of claim 5, wherein the method is performed by adding a surfactant to the etching solution. The first process gas comprises O2, the flow rate is 10-180sccm, the first pressure is 10-50mtorr, the temperature is 10-60℃, and the time is 4-15s; and / or, the second process gas comprises O2 and CF4, the flow rate of O2 is 10-150sccm, the flow rate of CF4 is 10-150sccm, the second pressure is 15-90mtorr, the temperature is 10-60℃, and the time is 4-15s; and / or, the third process gas comprises SF6 and C4F8, the flow rate of SF6 is 10-200sccm, the flow rate of C4F8 is 10-200sccm, the third pressure is 110-180mtorr, the temperature is 10-60℃, and the time is 10-80s.

7. The method of claim 3, wherein the method is performed by adding a surfactant to the etching solution. The first etching process comprises periodic cycle steps formed by deposition steps and etching steps in sequence, the fourth process gas used in the deposition steps comprises C4F8, and the fifth process gas used in the etching steps comprises SF6, so that the high aspect ratio etching structure is formed by alternately depositing a passivation layer using C4F8 and etching using SF6.

8. The method for improving the filling performance of high aspect ratio etched structures according to claim 7, characterized in that, In the first etching process, the lateral etching amount of the substrate in each of the periodic cycle steps is gradually reduced, so that the first inclination angle is 88-89 degrees and the sidewall roughness is reduced.

9. The method for improving the filling performance of high aspect ratio etched structures according to claim 7, characterized in that, In the first etching process, the flow rate of C4F8 is 10-1000sccm, the flow rate of SF6 is 10-1000sccm, the temperature is 10-60℃, the pressure is 1-100mtorr, the source power is 100-3000W, and the bias power is 10-200W.

10. A semiconductor structure, characterized by A high aspect ratio etching structure processed by the method for improving the filling performance of a high aspect ratio etching structure according to any one of claims 1-9. A high aspect ratio etching structure processed by the method for improving the filling performance of a high aspect ratio etching structure according to any one of claims 1-9.

Images