A dynamic bias circuit to boost DEVM

Abstract

This invention relates to the field of wireless communication technology, specifically to a dynamic bias circuit for improving the DEVM (Digital Source Bipolar Transmission). Utilizing the high density of BiCMOS, a reference voltage VREF that varies with the junction temperature of the high-voltage transformer (HBT) is provided to the output stage dynamic bias circuit. When the amplifier operates in long data packet transmission mode, the HBT junction temperature increases, and the amplifier's power gain begins to decrease. The voltage source bias circuit PTAT detects the temperature rise, and the reference voltage VREF increases to compensate for the gain decrease. The gain remains stable throughout the long data packet transmission, thereby optimizing the DEVM's performance.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more specifically, to a dynamic bias circuit for improving DEVM. Background Technology

[0002] With a growing number of wireless internet users demanding high-speed data access, new wireless communication standards must also ensure stability and continuity in densely populated environments (hotels, cafes, stadiums, airports, train stations, restaurants, etc.). To achieve more efficient communication and increase channel capacity, some RF systems now use 1024-state quadrature amplitude modulation (QAM). The transmitted information includes both amplitude and phase; when the PA output power approaches the compression point, nonlinear distortion occurs, generating in-band interference. These nonlinearities primarily stem from AM-to-AM and AM-to-PM distortions. PA linearity is evaluated using EVM to measure the deviation of the actual transmitted data position from its ideal position within the I / Q constellation. The electrothermal transient response of the power amplifier (especially the power gain) varies depending on the PA's operating environment, including the duty cycle (PA on...). The EVM varies depending on factors such as the temperature of the device, data packet length, and power supply voltage. Therefore, the concept of a dynamic EVM (DEVM) is more reasonable, especially in applications with a wide temperature range, where it must be used to replace the static EVM.

[0003] Traditionally, EVM calculations are based on AM-to-AM distortion (δGp) and AM-to-PM distortion (δθ), both introduced as functions of the output power range. These nonlinearities are strongly dependent on output power, load impedance, and quiescent current. However, this static approach fails to capture dynamic behaviors, such as thermal variations, which severely impact DEVM performance. As the PA junction temperature increases, transistor self-heating intensifies, and the electrical characteristics of HBT transistors (such as β, gm, fT, and fMAX) degrade significantly. Therefore, power gain is strongly temperature-dependent. Since EVM is highly sensitive to changes in power gain, as the junction temperature increases, the power gain decreases, and the dynamic error vector magnitude (DEVM) deteriorates significantly, leading to detection errors on the receiver side. Summary of the Invention

[0004] This invention addresses the problem that as junction temperature increases, power gain decreases, leading to a significant deterioration in DEVM (Distribution-to-Voltage Variable) and resulting in detection errors on the receiver side. It proposes a dynamic bias circuit to improve DEVM. Utilizing the high density of BiCMOS, a reference voltage VREF that varies with the HBT junction temperature is provided to the output stage dynamic bias circuit. When the amplifier operates in long packet transmission mode (packet transmission time greater than 4ms), the HBT junction temperature increases, and the amplifier's power gain begins to decrease. The voltage source bias circuit (PTAT) detects the temperature rise, and the reference voltage VREF increases, compensating for the gain decrease. The gain remains stable throughout the long packet transmission period, thereby optimizing DEVM performance.

[0005] The specific implementation details of this invention are as follows:

[0006] A dynamic bias circuit for improving DEVM is connected to the output stage dynamic bias circuit; it includes a power-on startup unit, a bandgap reference voltage unit, and a high-temperature compensation unit.

[0007] The input terminal of the power-on start-up unit is connected to the power supply, and the output terminal is connected to the input terminal of the bandgap reference voltage unit.

[0008] The input terminal of the high temperature compensation unit is connected to the output terminal of the bandgap reference voltage unit, and the output terminal of the high temperature compensation unit is connected to the output stage dynamic bias circuit.

[0009] The power-on startup unit is used to generate an excitation signal based on the constructed self-biased current source, and generate a first voltage based on the excitation signal to complete the power-on startup.

[0010] The bandgap reference voltage unit is used to generate a second voltage that is linearly related to temperature based on the first voltage;

[0011] The high-temperature compensation unit is used to generate a reference voltage that increases with increasing temperature based on the second voltage.

[0012] To better realize the present invention, the power-on startup unit further includes transistor Qs1, transistor Qs2, MOS transistor J1, and transistor Qs3;

[0013] The gate and source of the MOS transistor J1 are connected, the source of the MOS transistor J1 is connected to the collector of the transistor Qs2, and the drain power supply VDD of the MOS transistor J1 is connected.

[0014] The base of transistor Qs2 is connected to the input terminal of the bandgap reference voltage unit and the collector of transistor Qs2, and the emitter of transistor Qs2 is connected to the collector of transistor Qs1.

[0015] The base of transistor Qs1 is connected to the collector of transistor Qs1, and the emitter of transistor Qs1 is connected to the power supply VSS.

[0016] The base of transistor Qs3 is connected between the source of MOS transistor J1 and the collector of transistor Qs2. The collector of transistor Qs3 is connected to the power supply VDD. The emitter of transistor Qs3 is connected to the input terminal of the bandgap reference voltage unit.

[0017] To better realize the present invention, the bandgap reference voltage unit further includes a bandgap reference structure and a current mirror unit;

[0018] The bandgap reference structure includes transistor Q1, transistor Q2, resistor R8, and resistor R9;

[0019] The collector of transistor Q1 is connected to the current mirror unit, the emitter of transistor Q1 is connected to resistor R8, and the base of transistor Q1 is connected to the emitter of transistor Qs3 and the base of transistor Q2.

[0020] The collector of transistor Q2 is connected to the current mirror unit, and the emitter of transistor Q2 is connected between resistor R8 and resistor R9.

[0021] The resistor R9 is connected to the power supply VSS.

[0022] To better realize the present invention, the current mirror unit further includes transistors Q3, Q4, Q5, Q7, Q8, Q9, Q10, Q11, Q12, resistors R5, R6, and R7.

[0023] One end of the resistor R5 is connected between the drain of the MOSFET J1 and the power supply VDD, and the other end is connected between the emitter of the transistor Q7 and the emitter of the transistor Q9.

[0024] One end of the resistor R6 is connected between the drain of the MOS transistor J1 and the power supply VDD, and the other end is connected between the emitter of the transistor Q8 and the emitter of the transistor Q10.

[0025] One end of the resistor R7 is connected between the drain of the MOSFET J1 and the power supply VDD, and the other end is connected to the emitter of the transistor Q11.

[0026] The drain of transistor Q7 is connected to the base of transistor Q7, the drain of transistor Q8, and the emitter of transistor Q12.

[0027] The drain of transistor Q8 is connected to the base of transistor Q8 and the emitter of transistor Q12.

[0028] The drain of transistor Q9 is connected to the emitter of transistor Q3, and the base of transistor Q9 is connected to the base of transistor Q10.

[0029] The collector of transistor Q10 is connected to the emitter of transistor Q4;

[0030] The collector of transistor Q11 is connected between the emitter of transistor Q5 and the base of transistor Q13.

[0031] The base of transistor Q12 is connected to the base of transistor Q4, and the collector of transistor Q12 is connected to the power supply VSS.

[0032] The collector of transistor Q3 is connected to the collector of transistor Q1, the base of transistor Q3, and the base of transistor Q4.

[0033] The collector of transistor Q4 is connected between the base of transistor Q5 and the collector of transistor Q2.

[0034] The collector of transistor Q5 is connected to power supply VSS.

[0035] To better realize the present invention, the bandgap reference voltage unit further includes a redundant transistor Qex and a capacitor C4;

[0036] The collector of the redundant transistor Qex is connected between the collector of transistor Q2 and the base of transistor Q5. The emitter of the redundant transistor Qex is connected to ground. The base of the redundant transistor Qex is connected between the emitter of the redundant transistor Qex and ground.

[0037] One end of the capacitor C4 is connected between the emitter of the transistor Qs3 and the input of the high-temperature compensation unit, and the other end is connected to the power supply VSS.

[0038] To better realize the present invention, the high temperature compensation unit further includes resistor R10, resistor R11, resistor R12, resistor R13, and transistor Q6;

[0039] One end of the resistor R12 is connected between the emitter of transistor Qs3 and capacitor C2, and the other end is connected to the input terminal of the output stage dynamic bias circuit.

[0040] One end of the resistor R13 is connected between the resistor R12 and the emitter of the transistor Q13, and the other end is connected between the base of the transistor Q6 and the resistor R11.

[0041] One end of the resistor R10 is connected to the emitter of the transistor Q6, and the other end is connected to the power supply VSS;

[0042] One end of the resistor R11 is connected to the base of transistor Q6 and resistor R13, and the other end is connected to the power supply VSS.

[0043] To better realize the present invention, the output stage dynamic bias circuit further includes an adaptive active bias circuit, an input matching network, and an output matching network;

[0044] The input terminal of the adaptive active bias circuit is connected to resistor R12, and the output terminal of the adaptive active bias circuit is connected between the input matching network and the output matching network.

[0045] The input terminal of the input matching network receives a radio frequency signal;

[0046] The output of the output matching network outputs a radio frequency signal.

[0047] To better realize the present invention, the adaptive active bias circuit further includes power transistors M1, M2, M3, M4, and M5, resistors R1, R2, R3, R4, and R15, capacitors C1, C2, and C3, and inductor L1.

[0048] One end of resistor R2 is connected to resistor R12, and the other end is connected between the emitter of power transistor M2 and the collector of power transistor M1.

[0049] One end of resistor R3 is connected to resistor R12, and the other end is connected to the collector of power transistor M2.

[0050] One end of capacitor C2 is connected between resistors R12 and R3, and the other end is connected to ground.

[0051] The base and collector of the power transistor M2 are connected;

[0052] The base of the power transistor M3 is connected to the base of the power transistor M2, the emitter of the power transistor M3 is connected to the base of the power transistor M1 through resistor R1, and the collector of the power transistor M3 is connected to ground through resistor R4 and capacitor C3.

[0053] The emitter of the power transistor M1 is connected to ground.

[0054] The collector of the power transistor M4 is connected to the power supply VCC1, the base of the power transistor M4 is connected to the base of the power transistor M2, and the emitter of the power transistor M4 is connected to the resistor R15.

[0055] The base of the power transistor M5 is connected between the resistor R15 and the output terminal of the input matching network, the collector of the power transistor M5 is connected between the input terminal of the output matching network and the output terminal of the inductor L1, and the emitter of the power transistor M5 is connected to ground.

[0056] The input terminal of the inductor L1 is connected to the power supply VCC1.

[0057] The present invention has the following beneficial effects:

[0058] (1) This invention utilizes the high density of BiCMOS to provide a reference voltage VREF for the output stage dynamic bias circuit that varies with the junction temperature of the HBT. When the amplifier operates in long data packet transmission mode, the junction temperature of the HBT increases and the power gain of the amplifier begins to decrease. The voltage source bias circuit detects the temperature rise and the reference voltage VREF will increase, compensating for the decrease in gain. The gain will remain stable throughout the long data packet transmission, thus optimizing the performance of the DEVM.

[0059] (2) The present invention solves the problem of unstable power gain in long data packet transmission mode by introducing a bandgap reference voltage source bias circuit.

[0060] (3) The present invention solves the problem of large gain fluctuation at high and low power temperatures by introducing a bandgap reference voltage source bias circuit. Attached Figure Description

[0061] Figure 1 The schematic diagram of the dynamic bias circuit for improving DEVM provided by the present invention. Detailed Implementation

[0062] To more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments, and therefore should not be regarded as a limitation on the scope of protection. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0064] Example 1:

[0065] This embodiment proposes a dynamic bias circuit to enhance DEVM, which is connected to the output stage dynamic bias circuit; it includes a power-on startup unit, a bandgap reference voltage unit, and a high-temperature compensation unit;

[0066] The input terminal of the power-on start-up unit is connected to the power supply, and the output terminal is connected to the input terminal of the bandgap reference voltage unit.

[0067] The input terminal of the high temperature compensation unit is connected to the output terminal of the bandgap reference voltage unit, and the output terminal of the high temperature compensation unit is connected to the output stage dynamic bias circuit.

[0068] The power-on startup unit is used to generate an excitation signal based on the constructed self-biased current source, and generate a first voltage based on the excitation signal to complete the power-on startup.

[0069] The bandgap reference voltage unit is used to generate a second voltage that is linearly related to temperature based on the first voltage;

[0070] The high-temperature compensation unit is used to generate a reference voltage that increases with increasing temperature based on the second voltage.

[0071] Working principle: This embodiment utilizes the high density of BiCMOS to provide a reference voltage VREF for the output stage dynamic bias circuit that varies with the junction temperature of the HBT. When the amplifier operates in long data packet transmission mode, the junction temperature of the HBT increases, and the power gain of the amplifier begins to decrease. The voltage source bias circuit detects the temperature rise, and the reference voltage VREF will increase to compensate for the decrease in gain. The gain will remain stable throughout the long data packet transmission, thus optimizing the performance of the DEVM.

[0072] Example 2:

[0073] This embodiment is based on the above embodiment 1, such as... Figure 1 As shown, the specific structure of the power-on start-up unit is described using a specific embodiment.

[0074] The power-on startup unit includes transistor Qs1, transistor Qs2, MOS transistor J1, and transistor Qs3;

[0075] The gate and source of the MOS transistor J1 are connected, the source of the MOS transistor J1 is connected to the collector of the transistor Qs2, and the drain power supply VDD of the MOS transistor J1 is connected.

[0076] The base of transistor Qs2 is connected to the input terminal of the bandgap reference voltage unit and the collector of transistor Qs2, and the emitter of transistor Qs2 is connected to the collector of transistor Qs1.

[0077] The base of transistor Qs1 is connected to the collector of transistor Qs1, and the emitter of transistor Qs1 is connected to the power supply VSS.

[0078] The base of transistor Qs3 is connected between the source of MOS transistor J1 and the collector of transistor Qs2. The collector of transistor Qs3 is connected to the power supply VDD. The emitter of transistor Qs3 is connected to the input terminal of the bandgap reference voltage unit.

[0079] Working principle: The startup circuit consists of NPN transistors Qs1 and Qs2 and MOSFET J1. The gate and source of J1 are connected, forming a self-biased current source that drives Qs1 and Qs2, generating a base-emitter voltage twice that of Qs3. When the circuit is first powered on, the voltage at point X is 0. At this time, the startup circuit turns on transistor Qs3, driving the voltage at point X away from zero and continuously increasing the voltage at that point. After the circuit is operating normally, the voltage at point X is high enough that the base-emitter voltage of Qs3 is insufficient to turn it on, thus turning it off and completing the power-on startup.

[0080] The other parts of this embodiment are the same as those in Embodiment 1 above, so they will not be described again.

[0081] Example 3:

[0082] This embodiment is based on any one of Embodiments 1-2 above, such as Figure 1 As shown, a specific embodiment of the bandgap reference voltage unit is illustrated.

[0083] The bandgap reference voltage unit includes a bandgap reference structure and a current mirror unit;

[0084] The bandgap reference structure includes transistor Q1, transistor Q2, resistor R8, and resistor R9;

[0085] The collector of transistor Q1 is connected to the current mirror unit, the emitter of transistor Q1 is connected to resistor R8, and the base of transistor Q1 is connected to the emitter of transistor Qs3 and the base of transistor Q2.

[0086] The collector of transistor Q2 is connected to the current mirror unit, and the emitter of transistor Q2 is connected between resistor R8 and resistor R9.

[0087] The resistor R9 is connected to the power supply VSS.

[0088] The current mirror unit includes transistors Q3, Q4, Q5, Q7, Q8, Q9, Q10, Q11, Q12, resistors R5, R6, and R7.

[0089] One end of the resistor R5 is connected between the drain of the MOSFET J1 and the power supply VDD, and the other end is connected between the emitter of the transistor Q7 and the emitter of the transistor Q9.

[0090] One end of the resistor R6 is connected between the drain of the MOS transistor J1 and the power supply VDD, and the other end is connected between the emitter of the transistor Q8 and the emitter of the transistor Q10.

[0091] One end of the resistor R7 is connected between the drain of the MOSFET J1 and the power supply VDD, and the other end is connected to the emitter of the transistor Q11.

[0092] The drain of transistor Q7 is connected to the base of transistor Q7, the drain of transistor Q8, and the emitter of transistor Q12.

[0093] The drain of transistor Q8 is connected to the base of transistor Q8 and the emitter of transistor Q12.

[0094] The drain of transistor Q9 is connected to the emitter of transistor Q3, and the base of transistor Q9 is connected to the base of transistor Q10.

[0095] The collector of transistor Q10 is connected to the emitter of transistor Q4;

[0096] The collector of transistor Q11 is connected between the emitter of transistor Q5 and the base of transistor Q13.

[0097] The base of transistor Q12 is connected to the base of transistor Q4, and the collector of transistor Q12 is connected to the power supply VSS.

[0098] The collector of transistor Q3 is connected to the collector of transistor Q1, the base of transistor Q3, and the base of transistor Q4.

[0099] The collector of transistor Q4 is connected between the base of transistor Q5 and the collector of transistor Q2.

[0100] The collector of transistor Q5 is connected to power supply VSS.

[0101] The bandgap reference voltage unit also includes a redundant transistor Qex and a capacitor C4;

[0102] The collector of the redundant transistor Qex is connected between the collector of transistor Q2 and the base of transistor Q5. The emitter of the redundant transistor Qex is connected to ground. The base of the redundant transistor Qex is connected between the emitter of the redundant transistor Qex and ground.

[0103] One end of the capacitor C4 is connected between the emitter of the transistor Qs3 and the input of the high-temperature compensation unit, and the other end is connected to the power supply VSS.

[0104] Working principle: The core circuit of the bandgap reference voltage source consists of transistors Q1-Q5, Q7-Q12 and resistors R8, R9, R5, R6, and R7. Among them, Q1, Q2, R8, and R9 form the Brokaw bandgap reference structure, while Q3-Q5, Q7-Q12, and resistors R5-R7 form a current mirror, providing equal current input to the collectors of Q1 and Q2.

[0105] The collector currents of transistors Q1 and Q2 are equal. The current IR9 flowing through resistor R9 is twice the current IR8 flowing through resistor R8. Therefore, the voltage across R9 is (2*ΔVBE*R9) / R8.

[0106] The voltage at the base of transistor Q2, i.e., point X, is equal to the sum of the voltage across R9 and the base-emitter voltage of Q2. Its calculation expression is: VX = Vbe2 + (2*R9 / R8)*ΔVBE;

[0107] Among them, VBE2 is negatively correlated with temperature, and ΔVBE is positively correlated with temperature. By reasonably adjusting the ratio of R9 to R8, a VX that is linearly correlated with temperature can be obtained.

[0108] Under normal operating conditions, the parasitic diodes of Q1 and Q2 are reverse-biased, and their reverse saturation current increases sharply with rising temperature. When the temperature reaches a certain value, this current will leak into the substrate. Since the number of transistors Q1 is N times that of Q2, the current leaking from the collector of Q1 is also N times that leaking from Q2, resulting in a current mismatch between the collectors of Q1 and Q2. To compensate for the current leakage from the collectors of Q1 and Q2, a redundant transistor Qex is added at the collector of Q2, with its base and emitter short-circuited to keep it in the off state, thus not affecting the normal operation of the circuit. When the number of Qex transistors is set to (N-1) times that of Q1, the current leaking from the collectors of Q1 and Q2 through the reverse-biased parasitic diodes is equal, thus ensuring that the collector currents of Q1 and Q2 are also equal at high temperatures.

[0109] The other parts of this embodiment are the same as any one of the above embodiments 1-2, so they will not be described again.

[0110] Example 4:

[0111] This embodiment is based on any one of embodiments 1-3 above, such as Figure 1 As shown, the structure of the high-temperature compensation unit is illustrated with a specific embodiment.

[0112] The high-temperature compensation unit includes resistors R10, R11, R12, and R13, and transistor Q6;

[0113] One end of the resistor R12 is connected between the emitter of transistor Qs3 and capacitor C2, and the other end is connected to the input terminal of the output stage dynamic bias circuit.

[0114] One end of the resistor R13 is connected between the resistor R12 and the emitter of the transistor Q13, and the other end is connected between the base of the transistor Q6 and the resistor R11.

[0115] One end of the resistor R10 is connected to the emitter of the transistor Q6, and the other end is connected to the power supply VSS;

[0116] One end of the resistor R11 is connected to the base of transistor Q6 and resistor R13, and the other end is connected to the power supply VSS.

[0117] Working Principle: The high-temperature compensation circuit works by using resistors R13 and R11 to divide VREF, resulting in a voltage bias at the base of Q6. At lower temperatures, the base-emitter voltage required to turn on Q6 is higher, resulting in a relatively lower base bias. Q6 is in the off state and cannot be turned on, the current flowing through resistor R13 is approximately zero, and the reference output voltage VREF equals VX. As the temperature increases, the required turn-on voltage for Q6 gradually decreases, eventually turning on at a certain temperature. At this point, a current, denoted as IC6, flows through the collector of Q6. This current flows entirely through resistor R12, creating a voltage drop across R12, which in turn increases the VREF voltage.

[0118] The other parts of this embodiment are the same as any one of the embodiments 1-3 above, so they will not be described again.

[0119] Example 5:

[0120] This embodiment is based on any one of embodiments 1-4 above, such as Figure 1 As shown, the structure of the output stage dynamic bias circuit is illustrated with a specific embodiment.

[0121] The output stage dynamic bias circuit includes an adaptive active bias circuit, an input matching network, and an output matching network;

[0122] The input terminal of the adaptive active bias circuit is connected to resistor R12, and the output terminal of the adaptive active bias circuit is connected between the input matching network and the output matching network.

[0123] The input terminal of the input matching network receives a radio frequency signal;

[0124] The output of the output matching network outputs a radio frequency signal.

[0125] The adaptive active bias circuit includes power transistors M1, M2, M3, M4, and M5, resistors R1, R2, R3, R4, and R15, capacitors C1, C2, and C3, and inductor L1.

[0126] One end of resistor R2 is connected to resistor R12, and the other end is connected between the emitter of power transistor M2 and the collector of power transistor M1.

[0127] One end of resistor R3 is connected to resistor R12, and the other end is connected to the collector of power transistor M2.

[0128] One end of capacitor C2 is connected between resistors R12 and R3, and the other end is connected to ground.

[0129] The base and collector of the power transistor M2 are connected;

[0130] The base of the power transistor M3 is connected to the base of the power transistor M2, the emitter of the power transistor M3 is connected to the base of the power transistor M1 through resistor R1, and the collector of the power transistor M3 is connected to ground through resistor R4 and capacitor C3.

[0131] The emitter of the power transistor M1 is connected to ground.

[0132] The collector of the power transistor M4 is connected to the power supply VCC1, the base of the power transistor M4 is connected to the base of the power transistor M2, and the emitter of the power transistor M4 is connected to the resistor R15.

[0133] The base of the power transistor M5 is connected between the resistor R15 and the output terminal of the input matching network, the collector of the power transistor M5 is connected between the input terminal of the output matching network and the output terminal of the inductor L1, and the emitter of the power transistor M5 is connected to ground.

[0134] The input terminal of the inductor L1 is connected to the power supply VCC1.

[0135] Working principle: The adaptive active bias circuit is a current mirror bias structure. M2 and M4 form a current mirror to provide current to the power transistor M5. M1 is close to M5 in the layout, so as to transfer the heat from the junction temperature rise of M5 to M1, so that the Vbe turn-on voltage of M1 changes with the Vbe turn-on voltage of M5. When the temperature of M5 increases, due to heat transfer, the turn-on voltages Vbe of both M1 and M3 decrease, and the voltage drop across R1 increases, thus compensating for the decrease in the base potential of M3. The Vbe of M4 also decreases. Since the bases of M4 and M3 are connected together, the emitter potential of M4 increases, resulting in a larger current through R5 and a larger current flowing into the base of M5. Due to the rectification effect of the base-emitter junction of M5, the Vbe voltage of M5 is increased, compensating for the decrease in Vbe caused by the increase in junction temperature of M5. When the input power increases, due to the self-heating effect of M5 and the rectification characteristics of the diode, the base potential Vb of M5 decreases. At the same time, radio frequency signals leak into the emitter of M4. The radio frequency signal bypasses to ground through capacitor C1, thus keeping the base potential of M4 constant. Due to the rectification effect of the diode in M4, the base-emitter potential of M4 decreases. Since its base potential remains constant, the emitter potential increases, thus compensating for the decrease in the base potential of M5. To ensure that M5 is in a reasonable quiescent current range during initial power-up, the resistance values ​​of R1, R2, R3, R4, and R5 need to be adjusted appropriately. The base-emitter voltages of M1 and M3, along with R1 and R3, form a complete current loop. The resistance values ​​of R1 and R3 reflect the degree to which the bias circuit compensates for the drop in Vbe of M5. C2 and C3 act as filters, ensuring that the voltages VCC1 and VREF are relatively independent and clean.

[0136] When the junction temperature of power transistor M5 rises rapidly, the compensation of the emitter potential of M4 to the base potential of M5 will be delayed, resulting in a decrease in Vb of M5, a reduction in power gain, and a deterioration in DEVM. At this time, the VREF voltage needs to be increased to compensate for the decrease in the gain of power transistor M5.

[0137] The other parts of this embodiment are the same as any one of the embodiments 1-4 above, so they will not be described again.

[0138] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the present invention.

Claims

1. A dynamic bias circuit for boosting DEVM, connected to an output stage dynamic bias circuit; characterized in that, Includes a power-on startup unit, a bandgap reference voltage unit, and a high-temperature compensation unit; The input terminal of the power-on start-up unit is connected to the power supply, and the output terminal is connected to the input terminal of the bandgap reference voltage unit. The input terminal of the high temperature compensation unit is connected to the output terminal of the bandgap reference voltage unit, and the output terminal of the high temperature compensation unit is connected to the output stage dynamic bias circuit. The power-on startup unit is used to generate an excitation signal based on the constructed self-biased current source, and generate a first voltage based on the excitation signal to complete the power-on startup. The bandgap reference voltage unit is used to generate a second voltage that is linearly related to temperature based on the first voltage; The high-temperature compensation unit is used to generate a reference voltage that increases with increasing temperature based on the second voltage. The power-on startup unit includes transistor Qs1, transistor Qs2, MOS transistor J1, and transistor Qs3; The gate and source of the MOS transistor J1 are connected, the source of the MOS transistor J1 is connected to the collector of the transistor Qs2, and the drain power supply VDD of the MOS transistor J1 is connected. The base of transistor Qs2 is connected to the input terminal of the bandgap reference voltage unit and the collector of transistor Qs2, and the emitter of transistor Qs2 is connected to the collector of transistor Qs1. The base of transistor Qs1 is connected to the collector of transistor Qs1, and the emitter of transistor Qs1 is connected to the power supply VSS. The base of transistor Qs3 is connected between the source of MOS transistor J1 and the collector of transistor Qs2. The collector of transistor Qs3 is connected to power supply VDD. The emitter of transistor Qs3 is connected to the input terminal of the bandgap reference voltage unit. The bandgap reference voltage unit includes a bandgap reference structure and a current mirror unit; The bandgap reference structure includes transistor Q1, transistor Q2, resistor R8, and resistor R9; The collector of transistor Q1 is connected to the current mirror unit, the emitter of transistor Q1 is connected to resistor R8, and the base of transistor Q1 is connected to the emitter of transistor Qs3 and the base of transistor Q2. The collector of transistor Q2 is connected to the current mirror unit, and the emitter of transistor Q2 is connected between resistor R8 and resistor R9. The resistor R9 is connected to the power supply VSS.

2. The dynamic bias circuit for boosting DEVM according to claim 1, characterized in that, The current mirror unit includes transistors Q3, Q4, Q5, Q7, Q8, Q9, Q10, Q11, Q12, resistors R5, R6, and R7. One end of the resistor R5 is connected between the drain of the MOSFET J1 and the power supply VDD, and the other end is connected between the emitter of the transistor Q7 and the emitter of the transistor Q9. One end of the resistor R6 is connected between the drain of the MOS transistor J1 and the power supply VDD, and the other end is connected between the emitter of the transistor Q8 and the emitter of the transistor Q10. One end of the resistor R7 is connected between the drain of the MOSFET J1 and the power supply VDD, and the other end is connected to the emitter of the transistor Q11. The drain of transistor Q7 is connected to the base of transistor Q7, the drain of transistor Q8, and the emitter of transistor Q12. The drain of transistor Q8 is connected to the base of transistor Q8 and the emitter of transistor Q12. The drain of transistor Q9 is connected to the emitter of transistor Q3, and the base of transistor Q9 is connected to the base of transistor Q10. The collector of transistor Q10 is connected to the emitter of transistor Q4; The collector of transistor Q11 is connected between the emitter of transistor Q5 and the base of transistor Q13. The base of transistor Q12 is connected to the base of transistor Q4, and the collector of transistor Q12 is connected to the power supply VSS. The collector of transistor Q3 is connected to the collector of transistor Q1, the base of transistor Q3, and the base of transistor Q4. The collector of transistor Q4 is connected between the base of transistor Q5 and the collector of transistor Q2. The collector of transistor Q5 is connected to power supply VSS.

3. The dynamic bias circuit for boosting DEVM according to claim 2, characterized in that, The bandgap reference voltage unit also includes a redundant transistor Qex and a capacitor C4; The collector of the redundant transistor Qex is connected between the collector of transistor Q2 and the base of transistor Q5. The emitter of the redundant transistor Qex is connected to ground. The base of the redundant transistor Qex is connected between the emitter of the redundant transistor Qex and ground. One end of the capacitor C4 is connected between the emitter of the transistor Qs3 and the input of the high-temperature compensation unit, and the other end is connected to the power supply VSS.

4. The dynamic bias circuit for boosting DEVM according to claim 3, characterized in that, The high-temperature compensation unit includes resistors R10, R11, R12, and R13, and transistor Q6; One end of the resistor R12 is connected between the emitter of transistor Qs3 and capacitor C2, and the other end is connected to the input terminal of the output stage dynamic bias circuit. One end of the resistor R13 is connected between the resistor R12 and the emitter of the transistor Q13, and the other end is connected between the base of the transistor Q6 and the resistor R11. One end of the resistor R10 is connected to the emitter of the transistor Q6, and the other end is connected to the power supply VSS; One end of the resistor R11 is connected to the base of transistor Q6 and resistor R13, and the other end is connected to the power supply VSS.

5. The dynamic bias circuit for boosting DEVM according to claim 4, characterized in that, The output stage dynamic bias circuit includes an adaptive active bias circuit, an input matching network, and an output matching network; The input terminal of the adaptive active bias circuit is connected to resistor R12, and the output terminal of the adaptive active bias circuit is connected between the input matching network and the output matching network. The input terminal of the input matching network receives a radio frequency signal; The output of the output matching network outputs a radio frequency signal.

6. The dynamic bias circuit for boosting DEVM according to claim 5, characterized in that, The adaptive active bias circuit includes power transistors M1, M2, M3, M4, and M5, resistors R1, R2, R3, R4, and R15, capacitors C1, C2, and C3, and inductor L1. One end of resistor R2 is connected to resistor R12, and the other end is connected between the emitter of power transistor M2 and the collector of power transistor M1. One end of resistor R3 is connected to resistor R12, and the other end is connected to the collector of power transistor M2. One end of capacitor C2 is connected between resistors R12 and R3, and the other end is connected to ground. The base and collector of the power transistor M2 are connected; The base of the power transistor M3 is connected to the base of the power transistor M2, the emitter of the power transistor M3 is connected to the base of the power transistor M1 through resistor R1, and the collector of the power transistor M3 is connected to ground through resistor R4 and capacitor C3. The emitter of the power transistor M1 is connected to ground. The collector of the power transistor M4 is connected to the power supply VCC1, the base of the power transistor M4 is connected to the base of the power transistor M2, and the emitter of the power transistor M4 is connected to the resistor R15. The base of the power transistor M5 is connected between the resistor R15 and the output terminal of the input matching network, the collector of the power transistor M5 is connected between the input terminal of the output matching network and the output terminal of the inductor L1, and the emitter of the power transistor M5 is connected to ground. The input terminal of the inductor L1 is connected to the power supply VCC1.

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