A differential phase self-calibrating single-supply variable gain distributed balun circuit

Abstract

This invention relates to the field of radio frequency technology and discloses a differential phase self-calibrating single-supply variable gain distributed balun circuit, comprising: a differential phase calibration module, an ultra-wideband matching gain adjustment module, and a distributed balun amplifier core module connecting the differential phase calibration module and the ultra-wideband matching gain adjustment module. Based on the traditional differential-to-single-ended distributed balun circuit, this invention requires only one power supply voltage, overcoming the drawback of traditional distributed baluns requiring multiple power supply voltages. Furthermore, the distributed balun circuit proposed in this invention also has a digital gain calibration function, providing greater flexibility in balun usage. In addition, this invention uses a differential signal self-calibration circuit to ensure that the phase error of the differential input of the balun is minimized.

Description

Technical Field

[0001] This invention relates to the field of radio frequency technology, and in particular to a differential phase self-calibrating single-supply variable gain distributed balun circuit. Background Technology

[0002] Distributed baluns are widely used in ultra-wideband communication and radar systems. Especially in transmitting circuits, since the antenna is single-ended, differential-to-single-ended baluns ensure that the vast majority of circuit modules within the transmitting system are single-ended, giving the system sufficient linearity and image rejection characteristics. However, traditional distributed differential-to-single-ended baluns often require multiple power supply voltages and are difficult to implement with digital variable gain. Furthermore, the 180° phase difference at the differential ports of these baluns often results in phase errors due to manufacturing process or component mismatches, thus hindering their performance in practical applications.

[0003] Figure 1 This is the schematic diagram of an existing differential-to-single-ended distributed balun circuit. The differential positive signal enters from the positive input port, the differential negative signal enters from the negative input port, and the final output signal exits from the output port to the outside of the circuit. To ensure the balun operates normally, this circuit requires a total of three power supply voltages: VDD, VDD1, and VDD2, making the power supply voltage relatively complex. Furthermore, current technology cannot guarantee that the positive and negative input signals maintain a 180° angle after entering the balun, thus degrading the balun's performance.

[0004] The shortcomings of existing technologies are clear. First, they require three sets of power supply voltages, which increases design complexity. Second, if the model used in the design has errors, the balun cannot achieve gain calibration, nor can the gain be adjusted according to actual usage requirements, and its performance will fluctuate due to process or temperature variations. Finally, existing baluns also struggle to achieve 180° phase calibration; process deviations or device deviations during actual chip manufacturing will also lead to performance degradation. Summary of the Invention

[0005] This invention provides a differential phase self-calibrating single-supply variable gain distributed balun circuit, which aims to solve at least one of the above-mentioned technical problems.

[0006] To achieve the above objectives, the present invention provides a differential phase self-calibrating single-supply variable gain distributed balun circuit, comprising: a differential phase calibration module, an ultra-wideband matching gain adjustment module, and a distributed balun amplifier core module connecting the differential phase calibration module and the ultra-wideband matching gain adjustment module;

[0007] The differential phase calibration module is connected to the positive input terminal and the negative input terminal of the differential signal. It is configured to perform phase error elimination on the differential positive input signal and the differential negative input signal, which have errors, and then transmit the differential positive input signal and differential negative input signal after phase error elimination to the first input terminal and the second input terminal of the distributed balun amplifier core module, respectively.

[0008] The ultra-wideband matching gain adjustment module is connected to the digital signal input terminal and is configured to convert the digital input signal into an analog DC voltage signal and transmit the analog DC voltage signal to the third input terminal of the distributed balun amplifier core module.

[0009] The core module of the distributed balun amplifier includes a distributed amplifier architecture connecting a first input terminal, a second input terminal, and a third input terminal. The first and second input terminals are configured to transmit differential positive and differential negative signals to the distributed amplifier architecture, driving the distributed amplifier architecture to convert the differential signal into a single-ended signal. The third input terminal is configured to transmit an analog DC voltage signal to the distributed amplifier architecture and is configured to adjust the DC voltage of several transistors in the distributed amplifier architecture.

[0010] Optionally, the differential phase calibration module includes:

[0011] The first distributed amplifier unit, connected to the negative input terminal of the differential signal, includes inductors Li0 and Li1 and transistor Mc1, and is configured to invert the differential negative input signal and transmit the inverted differential negative input signal to transistor Mc3.

[0012] The second distributed amplifier unit, connected to the positive input terminal of the differential signal, includes inductors Lm0 and Lm1 and transistor Mc2, and is configured to maintain the phase of the differential positive input signal.

[0013] The transistors Mc2 and Mc3 are connected to form an analog multiplier, which is configured to perform phase error self-calibration on the negative and positive differential signals in the differential signal.

[0014] Optionally, the source of transistor Mc2 is connected to the drain of transistor Mc3. In the analog multiplier formed by connecting transistors Mc2 and Mc3, the expressions for the gate voltage of transistor Mc2, the gate voltage of transistor Mc3, and the drain voltage of transistor Mc2 are:

[0015] ;

[0016] ;

[0017] ;

[0018] In the formula, This is the gate voltage of transistor Mc2. This is the gate voltage of transistor Mc3. This is the drain voltage of transistor Mc2. This represents the amplification factor of transistor Mc2. ω is the amplification factor of transistor Mc3, Δ is the phase error between the differential negative terminal signal and the differential positive terminal signal, ω is the angular frequency, and t is time.

[0019] Optionally, the drain of transistor Mc2 is connected to the VDD input terminal and is equipped with a low-pass filter. The low-pass filter filters out high-frequency signals in the drain voltage of transistor Mc2, and the expression of the filtered signal is:

[0020] ;

[0021] In the formula, Let the proportionality coefficient be 1. , deduced , where k is the proportionality coefficient.

[0022] Optionally, the differential phase calibration module further includes a voltage-controlled capacitor connecting the drain of the transistor Mc2 to the positive input terminal. The voltage-controlled capacitor The expression is:

[0023] ;

[0024] In the formula, m is the proportionality coefficient, set to 1, and V is the DC voltage of the substrate. The phase error Δ between the differential negative terminal signal and the differential positive terminal signal and the voltage-controlled capacitor are derived. The relationship is .

[0025] Optionally, the distributed amplifier architecture includes:

[0026] The first distributed amplifier group, including transistors M10, M20 and M30 whose gates are connected to the second input terminal, is configured to invert the differential negative terminal signal input to the second input terminal;

[0027] The second distributed amplifier group includes transistors M11, M12, and M13, whose gates are respectively connected to the drains of transistors M10, M20, and M30, so that transistors M10 and M11, M20 and M12, and M30 and M13 each constitute an independent amplifier unit.

[0028] Optionally, the core module of the distributed balun amplifier further includes an input negative terminal signal gain adjustment circuit. The input negative terminal signal gain adjustment circuit is connected to the gates of transistors M10, M20, and M30. The input negative terminal signal gain adjustment circuit includes resistors R4 and R5 connecting the VDD input terminal and ground. The gates of transistors M10, M20, and M30 are connected between resistors R4 and R5.

[0029] Optionally, the ratio of resistor R4 to resistor R5 is configured such that the gain of the amplifier formed by transistors M10, M20 and M30 is 1.

[0030] Optionally, the gates of transistors M11, M12, and M13 are connected to the first input terminal and the third input terminal, and are configured to control the gain of the distributed amplifier architecture according to the analog DC voltage signal input at the third input terminal.

[0031] Optionally, the ultra-wideband matching gain adjustment module includes: an operational amplifier EA with differential input and single-ended output, a digital-to-analog converter DAC1 connected to the positive input terminal of the operational amplifier EA, a power transistor MP connected to the output terminal of the operational amplifier EA, and a voltage divider resistor unit connecting the source of the power transistor MP to the negative input terminal of the operational amplifier EA.

[0032] The operational amplifier EA has a filter capacitor Cf at its positive input terminal, the drain of the power transistor MP is connected to the VDD input terminal through a high-frequency resonant capacitor Lr, and the voltage divider resistor unit includes a resistor R1 connecting the source of the power transistor MP to the negative input terminal of the operational amplifier EA, and resistors R2 and R3 connecting the source of the power transistor MP to ground.

[0033] The source of the power transistor MP and the voltage divider resistor unit serve as the output of the ultra-wideband matching gain adjustment module, which is connected to the third input terminal of the core module of the distributed balun amplifier.

[0034] The beneficial effects of this invention are as follows: It proposes a differential phase self-calibrating single-supply variable gain distributed balun circuit. Based on the traditional differential-to-single-ended distributed balun circuit, this invention's balun circuit requires only one power supply voltage, overcoming the drawback of traditional distributed baluns requiring multiple power supply voltages. Furthermore, the distributed balun circuit proposed in this invention also has a digital gain calibration function, allowing for greater flexibility in balun usage. In addition, this invention uses a differential signal self-calibration circuit to ensure that the phase error of the differential input of the balun is minimized. Attached Figure Description

[0035] Figure 1This is a schematic diagram of a differential-to-single-ended distributed balun circuit in the prior art.

[0036] Figure 2 This is a schematic diagram of the differential phase self-calibrating single-supply variable gain distributed balun circuit of the present invention.

[0037] Figure 3 This is a schematic diagram of the equivalent circuit of the power transistor in this invention under different conditions;

[0038] Figure 4 This is an example diagram of the ultra-wideband matching gain adjustment module in the differential phase self-calibrating single-supply variable gain distributed balun circuit of the present invention.

[0039] Figure 5 The simulation results of C1, C2 and C3 under different control words in this invention are shown.

[0040] Figure 6 The simulation results are for the positive and negative port differential signals of this invention with and without self-calibration. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0042] like Figure 2 As shown, this embodiment of the invention provides a differential phase self-calibrating single-supply variable gain distributed balun circuit, including: a differential phase calibration module, an ultra-wideband matching gain adjustment module, and a distributed balun amplifier core module connecting the differential phase calibration module and the ultra-wideband matching gain adjustment module.

[0043] (1) For the differential phase calibration module:

[0044] The differential positive input signal enters from the left plate of the positive input port Cp2, and the differential negative input signal enters from the left plate of the negative input port Cp1. The negative input signal, after being amplified by a distributed amplifier consisting of Li0, Li1, and transistor Mc1, is inverted by 180° and enters the gate of the calibration transistor Mc3. The positive input signal, after being amplified by a distributed amplifier consisting of Lm0, Lm1, and Mc2, remains in phase at the gate of Mc2. Ideally, the gate signals of Mc3 and Mc2 are in phase at this point.

[0045] At this point, as mentioned earlier, due to device or process deviations, there will be phase errors in Mc2 and Mc3. If the phase error is Δ, and considering that the angular frequencies of the two signals are the same at this time, let's call it ω. Then the gate voltages of Mc2 and Mc3 can be written as: ;

[0046] ;

[0047] At this point, Mc2 and Mc3 form an analog multiplier, so the voltage at the drain of Mc2 can be written as:

[0048] ;

[0049] In the formula, ω is the angular frequency and t is time;

[0050] At this point, Cp4 is a low-pass filter, and the signal with frequency 2ω will be filtered out.

[0051] ;

[0052] if If k is constant and the phase difference is small, then the voltage at this time is:

[0053] ;

[0054] Therefore, a DC voltage with a phase error signal can be used to voltage-controlle a capacitor. To regulate The capacitance value. Voltage-controlled variable capacitor. The relationship between the voltage of the substrate and the DC voltage is as follows:

[0055] ;

[0056] Both m and k are proportionality coefficients. We can simply assume that m is 1 to obtain the relationship between the phase errors of Mc2 and Mc3 and the capacitance of the voltage-controlled capacitor:

[0057] ;

[0058] The phase of the positive input terminal is affected by The capacitance is adjusted by changing... The value of can change the phase of the positive input signal, so if Δ exists, it can be adjusted by Δ. The value of Δ is changed to 0, thus achieving phase error self-calibration of the differential signal. Therefore, after differential phase self-calibration, the positive and negative signals maintain a precise 180° phase difference.

[0059] (2) For the core module of the distributed balun amplifier:

[0060] Both the positive and negative inputs use a distributed amplifier architecture, ensuring a sufficiently high operating bandwidth. The signal input at the negative terminal, after being inverted by M10, M20, and M30, has the same phase as the signal input at the positive terminal. At the same time, by adjusting the ratio of R4 and R5, the amplifier formed by M10, M20, and M30 has a gain of 1. This ensures that the positive and negative input signals of the balun have the same gain and a phase difference of exactly 180° from the output signal, realizing the function of differential to single-ended conversion.

[0061] The gain of the input negative signal can be adjusted by the ratio of R4 and R5. In addition, by selecting the values ​​of R4 and R5, the load looking to the right of Li4 ​​is the characteristic impedance of the system. This ensures that the port impedance of the distributed amplifier for the input negative signal is the characteristic impedance of the system, and at the same time, no new power supply voltage is required.

[0062] (3) For the ultra-wideband matching gain adjustment module:

[0063] The DC voltage of the transistor at the positive input terminal is guaranteed by a negative feedback loop consisting of the digital-to-analog converter DAC1, the differential input single-ended output operational amplifier EA, the filter capacitor Cf, the power transistor MP, the voltage divider resistors R1, R2, R3, and the high-frequency resonant capacitor Lr, as shown in this invention. The digital input signal is converted into the required analog DC voltage signal by DAC1 to control the gate voltage of the positive input transistor and the drain voltage of the negative input transistor. MP is a power transistor with a source follower structure, and Lr is the resonant inductor at high frequencies. Figure 3 In diagram (a), the small-signal equivalent circuit of the impedance seen from the source of the power transistor MP is shown. To ensure that the impedance seen at the balun port is the characteristic impedance of the distributed balun system, this impedance needs to be 50Ω over an extremely wide bandwidth. In this case, as long as the values ​​of R1, R2, and R3 are set much higher than 50Ω, the impedance seen from the balun port will be entirely determined by the impedance seen from the source of MP.

[0064] At low frequencies, the small-signal equivalent circuit viewed from the source of the MP is as follows: Figure 3 As shown in (b), Cgs, Cgd, and Cf are essentially open circuits at this point, so they are not drawn further. Point X is the port node of the MP source, therefore Vx / Ix is the port impedance seen outwards by the distributed balun at this time. Furthermore, at low frequencies, the gate of the MP is equivalent to being connected to a DC voltage, so AC signals can treat this port as signal ground. Figure 3 As shown in (b), the impedance at point X can be written as 1 / gmmp, where gmmp is the transconductance of the power transistor MP. By selecting the size of the transistor MP, 1 / gmmp can achieve 50Ω, which ensures the port impedance requirement at low frequencies. At high frequencies, the small-signal equivalent circuit seen from the source of MP is as follows... Figure 3As shown in (c). At this point, Cgs, Cgd, and Cf are equivalent to a short circuit. The short circuit of Cgs makes the current generated by gmmp zero, thus it is equivalent to an open circuit. In addition, due to the presence of Lr, the path from Cgd in series with Lr to the small-signal ground is also equivalent to an open circuit. Therefore, the impedance seen from the source of MP is Ro2, because the short circuit of Cf is equivalent to grounding the right side of Ro2. In summary, by setting 1 / gmmp to 50Ω and Ro2 to 50Ω, the impedance seen from the balun port can be equal to the characteristic impedance of the system, which is 50Ω.

[0065] Furthermore, by adjusting the digital input of the DAC, under the normal voltage clamping effect of EA, the output DC potential of the source of the MP transistor can be adjusted, thereby adjusting the gate voltages of M11, M12 and M13 to change their gain and achieve the effect of digitally controlled variable gain.

[0066] It should be noted that in this embodiment, the port impedance of the positive or negative input transmission line must use, for example... Figure 2 As shown, the negative feedback loop, including MP, Lr, Ro2, R1, R2, R3, Cf, EA, and DAC, is the ultra-wideband matching gain adjustment module. This ensures that the impedance seen from the balun port remains at 50Ω. MP is a source follower structure, and its size guarantees that its gm value is 0.02S, or 1 / gm, which is 50Ω. Ro2 is also 50Ω. Furthermore, the balun uses a differential phase self-calibration circuit for the input signal to ensure the lowest possible differential phase error between the positive and negative terminals. The characteristic impedance of the artificial transmission line formed by the gate capacitances of Li0, Li1, and Mc1 is 50Ω, and the characteristic impedance of the artificial transmission line formed by the gate capacitances of Lm0, Lm1, and Mc2 is also 50Ω. This ensures that the characteristics of the distributed balun itself are not affected.

[0067] To explain the invention more clearly, a circuit example of a differential phase self-calibrating single-supply variable gain distributed balun circuit is provided below.

[0068] like Figure 4 As shown, C1, C2, and C3 are digital input ports. These ports control the switching on and off of transistors MSW1-MSW3, thus adjusting the DC voltage input to the gate of transistor M2. M1-M6 form the EA circuit. Through the negative feedback of the EA circuit, the value of the MP output DC voltage can be controlled by the digital ports of C1, C2, and C3. All modules share a single power supply VDD, and the gain of the balun can be changed through the digital inputs of C1, C2, and C3.

[0069] Figure 5The simulation results for the balun gain of C1, C2, and C3 under different control words are shown, using only one power supply voltage. It can be seen that the balun gain can achieve different values ​​under different CNC states, while traditional distributed baluns require multiple power supply voltages and can only achieve a fixed gain.

[0070] Figure 6 Simulation results are presented for the input positive and negative port differential signals with and without self-calibration. The differential phase error is optimized under the effect of self-calibration.

[0071] The following is a set of possible size parameters for a circuit example of a differential phase self-calibrating single-supply variable gain distributed balun circuit:

[0072] MS4 is 40nm / 6um, MS5 is 40nm / 12um, and MS6 is 40nm / 24um;

[0073] Rs1 and Rs2 are 500Ω;

[0074] MSW1~MSW3 are 40nm / 48um;

[0075] M1~M6 are 40nm / 12um;

[0076] MP is 40nm / 52um;

[0077] Cf is 1pF;

[0078] R1 is 1KΩ, R2 is 1KΩ, and R3 is 1.5KΩ;

[0079] M10, M20, M30, M11, M12, M13 are 40nm / 48um;

[0080] Li2, Li3: 50pH, Li4: 25pH, Li1: 35pH, Li0: 15pH;

[0081] Ld2, Ld3: 60pH, Ld1, Ld4: 30pH;

[0082] Lm2, Lm3: 70pH, Lm4: 35pH, Lm1: 50pH, Lm0: 20pH;

[0083] Ro1, Ro2: 50Ω;

[0084] Cp1: 50pF, Lr5nH, Cp2: 50pF;

[0085] R4: 150Ω, R5: 75Ω;

[0086] Mc1: 40nm / 12um;

[0087] Mc2 and Mc3: 40nm / 6um;

[0088] Cp4: 50 pF, Cp3: 25 pF;

[0089] The initial value is 85fF;

[0090] Rb1: 75Ω;

[0091] Rb3: 50Ω.

[0092] Therefore, this embodiment addresses the problems of existing differential-to-single-ended distributed balun circuits requiring multiple power supply voltages and being difficult to calibrate by proposing a solution that requires only one power supply voltage and allows for digitally controlled gain adjustment. This simplifies the use of the balun circuit and ensures that the balun can operate normally under different processes and temperatures. Furthermore, this invention employs differential phase self-calibration technology, enabling the positive and negative input signals of the balun to adaptively maintain a 180° angle, thus improving the balun's performance.

[0093] It is understood that in the description of this specification, references to terms such as "one embodiment," "another embodiment," "other embodiments," or "first embodiment to Nth embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0094] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0095] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A differential phase self-calibrating single-supply variable gain distributed balun circuit, characterized in that, include: The differential phase calibration module, the ultra-wideband matching gain adjustment module, and the core module of the distributed balun amplifier connecting the differential phase calibration module and the ultra-wideband matching gain adjustment module; The differential phase calibration module is connected to the positive input terminal and the negative input terminal of the differential signal. It is configured to perform phase error elimination on the differential positive input signal and the differential negative input signal, which have errors, and then transmit the differential positive input signal and differential negative input signal after phase error elimination to the first input terminal and the second input terminal of the distributed balun amplifier core module, respectively. The ultra-wideband matching gain adjustment module is connected to the digital signal input terminal and is configured to convert the digital input signal into an analog DC voltage signal and transmit the analog DC voltage signal to the third input terminal of the distributed balun amplifier core module. The core module of the distributed balun amplifier includes a distributed amplifier architecture connecting a first input terminal, a second input terminal, and a third input terminal. The first and second input terminals are configured to transmit differential positive and differential negative signals to the distributed amplifier architecture, driving the distributed amplifier architecture to convert the differential signal into a single-ended signal. The third input terminal is configured to transmit an analog DC voltage signal to the distributed amplifier architecture and is configured to adjust the DC voltage of several transistors in the distributed amplifier architecture.

2. The differential phase self-calibrating single-supply variable gain distributed balun circuit as described in claim 1, characterized in that, The differential phase calibration module includes: The first distributed amplifier unit, connected to the negative input terminal of the differential signal, includes inductors Li0 and Li1 and transistor Mc1, and is configured to invert the differential negative input signal and transmit the inverted differential negative input signal to transistor Mc3. The second distributed amplifier unit, connected to the positive input terminal of the differential signal, includes inductors Lm0 and Lm1 and transistor Mc2, and is configured to maintain the phase of the differential positive input signal. The transistors Mc2 and Mc3 are connected to form an analog multiplier, which is configured to perform phase error self-calibration on the negative and positive differential signals in the differential signal.

3. The differential phase self-calibrating single-supply variable gain distributed balun circuit as described in claim 2, characterized in that, The source of transistor Mc2 is connected to the drain of transistor Mc3. In the analog multiplier formed by the connection of transistors Mc2 and Mc3, the expressions for the gate voltage of transistor Mc2, the gate voltage of transistor Mc3, and the drain voltage of transistor Mc2 are: ; ; In the formula, This is the gate voltage of transistor Mc2. This is the gate voltage of transistor Mc3. This is the drain voltage of transistor Mc2. This represents the amplification factor of transistor Mc2. ω is the amplification factor of transistor Mc3, Δ is the phase error between the differential negative terminal signal and the differential positive terminal signal, ω is the angular frequency, and t is time.

4. The differential phase self-calibrating single-supply variable gain distributed balun circuit as described in claim 3, characterized in that, The drain of transistor Mc2 is connected to the VDD input terminal and is equipped with a low-pass filter. The low-pass filter filters out high-frequency signals in the drain voltage of transistor Mc2. The expression of the filtered signal is as follows: In the formula, Let the proportionality coefficient be 1. , deduced , where k is the proportionality coefficient.

5. The differential phase self-calibrating single-supply variable gain distributed balun circuit as described in claim 4, characterized in that, The differential phase calibration module also includes a voltage-controlled capacitor connected between the drain of the transistor Mc2 and the positive input terminal. The voltage-controlled capacitor The expression is: ； In the formula, m is the proportionality coefficient, set to 1, and V is the DC voltage of the substrate. The phase error Δ between the differential negative terminal signal and the differential positive terminal signal and the voltage-controlled capacitor are derived. The relationship is .

6. The differential phase self-calibrating single-supply variable gain distributed balun circuit as described in claim 1, characterized in that, The distributed amplifier architecture includes: The first distributed amplifier group, including transistors M10, M20 and M30 whose gates are connected to the second input terminal, is configured to invert the differential negative terminal signal input to the second input terminal; The second distributed amplifier group includes transistors M11, M12, and M13, whose gates are respectively connected to the drains of transistors M10, M20, and M30, so that transistors M10 and M11, M20 and M12, and M30 and M13 each constitute an independent amplifier unit.

7. The differential phase self-calibrating single-supply variable gain distributed balun circuit as described in claim 6, characterized in that, The core module of the distributed balun amplifier also includes an input negative terminal signal gain adjustment circuit. The input negative terminal signal gain adjustment circuit is connected to the gates of transistors M10, M20 and M30. The input negative terminal signal gain adjustment circuit includes resistors R4 and R5 connecting the VDD input terminal and ground. The gates of transistors M10, M20 and M30 are connected between resistors R4 and R5.

8. The differential phase self-calibrating single-supply variable gain distributed balun circuit as described in claim 7, characterized in that, The ratio of resistor R4 to resistor R5 is configured such that the gain of the amplifier composed of transistors M10, M20 and M30 is 1.

9. The differential phase self-calibrating single-supply variable gain distributed balun circuit as described in claim 6, characterized in that, The gates of transistors M11, M12, and M13 are connected to the first input terminal and the third input terminal, and are configured to control the gain of the distributed amplifier architecture according to the analog DC voltage signal input at the third input terminal.

10. The differential phase self-calibrating single-supply variable gain distributed balun circuit as described in claim 1, characterized in that, The ultra-wideband matching gain adjustment module includes: an operational amplifier EA with differential input and single-ended output, a digital-to-analog converter DAC1 connected to the positive input terminal of the operational amplifier EA, a power transistor MP connected to the output terminal of the operational amplifier EA, and a voltage divider resistor unit connecting the source of the power transistor MP to the negative input terminal of the operational amplifier EA. The operational amplifier EA has a filter capacitor Cf at its positive input terminal, the drain of the power transistor MP is connected to the VDD input terminal through a high-frequency resonant capacitor Lr, and the voltage divider resistor unit includes a resistor R1 connecting the source of the power transistor MP to the negative input terminal of the operational amplifier EA, and resistors R2 and R3 connecting the source of the power transistor MP to ground. The source of the power transistor MP and the voltage divider resistor unit serve as the output of the ultra-wideband matching gain adjustment module, which is connected to the third input terminal of the core module of the distributed balun amplifier.

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