Implementation method and equipment of digital fixed-frequency three-phase phase-locked loop and medium

Abstract

The invention discloses an implementation method and device of a digital fixed-frequency three-phase phase-locked loop and a medium, and is applied to a digital controller, and the method comprises the steps: carrying out the multiplication of a three-phase sine input signal obtained through sampling with two paths of orthogonal signals outputted by a fixed-frequency signal generator, and obtaining a three-phase sine input signal; obtaining two paths of output signals respectively corresponding to each phase of sine input signal; respectively carrying out sliding average filtering on the two paths of output signals corresponding to each phase of sine input signal to obtain two paths of corresponding filtering signals; for each phase of sine input signal, performing complex number synthesis on two paths of filtering signals corresponding to the sine input signal to obtain a synthesized complex number signal, and performing complex number calculation on three complex number signals corresponding to the three-phase sine input signal to obtain a positive sequence complex number signal and a negative sequence complex number signal; according to the positive sequence complex signal and the negative sequence complex signal, a positive sequence phase and a negative sequence phase are obtained, and phase locking of the three-phase sine input signal is achieved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of phase-locked loops, in particular to an implementation method, equipment and medium of a digital fixed-frequency three-phase phase-locked loop. BACKGROUND

[0002] In grid-connected power electronic products, a phase-locked loop is a key component, and its core function is to lock the phase angle of the grid voltage and realize accurate tracking of the phase of the grid voltage. In many power electronic projects such as energy storage converters, wind power converters, static var compensators and active filters, phase-locked loops are widely used.

[0003] With the continuous expansion of new energy power generation systems, efficient and accurate tracking of the phase of the grid voltage has become an important task. However, the traditional phase-locked loop technology can only track the positive sequence signal, and when there is a negative sequence component in the grid voltage, the tracking effect of the conventional phase-locked loop is poor, which is difficult to meet the requirements of phase accuracy in actual applications. SUMMARY

[0004] In order to solve the above problems, the application provides an implementation method of a digital fixed-frequency three-phase phase-locked loop, which is applied to a digital controller and includes the following steps.

[0005] The three-phase sinusoidal input signals obtained by sampling are multiplied by two orthogonal signals output by a fixed-frequency signal generator to obtain two output signals corresponding to each phase sinusoidal input signal.

[0006] The two output signals corresponding to each phase sinusoidal input signal are respectively subjected to sliding average filtering to obtain two filtered signals.

[0007] For each phase sinusoidal input signal, the two filtered signals corresponding to the phase sinusoidal input signal are combined to obtain a combined complex signal, and complex calculation is performed on the three complex signals corresponding to the three-phase sinusoidal input signals to obtain a positive sequence complex signal and a negative sequence complex signal.

[0008] According to the positive sequence complex signal and the negative sequence complex signal, a positive sequence phase and a negative sequence phase are obtained to realize phase locking of the three-phase sinusoidal input signal.

[0009] In an implementation manner of the application, before the three-phase sinusoidal input signals obtained by sampling are multiplied by two orthogonal signals output by a fixed-frequency signal generator, the method further includes the following steps.

[0010] The phase change amount in each sampling period is determined by a fixed-frequency signal generator, and the phase at the previous moment and the change amount are superimposed and subjected to a modulo operation to generate the phase at the current moment.

[0011] Perform sine and cosine operations on the current phase to output two orthogonal signals.

[0012] In one implementation of the present application, obtaining a positive-sequence phase and a negative-sequence phase according to the positive-sequence complex signal and the negative-sequence complex signal specifically includes:

[0013] Calculating a positive-sequence phase angle corresponding to the positive-sequence complex signal and a negative-sequence phase angle corresponding to the negative-sequence complex signal;

[0014] The positive-sequence phase angle and the negative-sequence phase angle are respectively added to the phase value generated by the fixed-frequency signal generator to obtain the corresponding positive-sequence phase and negative-sequence phase.

[0015] In one implementation of the present application, sliding average filtering is performed on the two output signals corresponding to each phase of the sinusoidal input signal to obtain the corresponding two filtered signals, specifically including:

[0016] Determine the preset sampling window length;

[0017] For each output signal, the average value of the output signal corresponding to each sampling moment in the sampling window length is determined to obtain the corresponding filtered signal.

[0018] In one implementation of the present application, complex calculation is performed on three complex signals corresponding to the three-phase sinusoidal input signal to obtain a positive-sequence complex signal and a negative-sequence complex signal, specifically including:

[0019] The three complex signals corresponding to the three-phase sinusoidal input signal are calculated using the following formula:

[0020]

[0021] Where ComA(n), ComB(n) and ComC(n) represent the complex signals corresponding to the three-phase sinusoidal input signal at time n, ComPos(n) represents the positive sequence complex signal, ComNeg(n) represents the negative sequence complex signal, and e j2π / 3 and e -j2π / 3 is a constant complex expression.

[0022] In one implementation of the present application, the corresponding two filtered signals are complex-synthesized to obtain a synthesized complex signal, specifically including:

[0023] The corresponding two-way filter signals are complex synthesized using the following formula:

[0024] Com(n)=Re(n)+j*Im(n)

[0025] Wherein, Com(n) represents a complex signal at n time, Re(n) and Im(n) are real and imaginary parts, corresponding to two filtered signals respectively, and j is an imaginary symbol.

[0026] In an implementation manner of the present application, after obtaining the positive sequence complex signal and the negative sequence complex signal, the method further comprises:

[0027] Performing complex modulus operation on the positive sequence complex signal and the negative sequence complex signal to obtain a positive sequence modulus value corresponding to the positive sequence complex signal and a negative sequence modulus value corresponding to the negative sequence complex signal.

[0028] In an implementation manner of the present application, the preset sampling window length is determined, specifically comprising:

[0029] Determining a sampling frequency and a power grid frequency;

[0030] Determining the preset sampling window length according to a ratio between the sampling frequency and the power grid frequency.

[0031] The embodiment of the present application provides an implementation device of a digital fixed-frequency three-phase phase-locked loop, and the device comprises:

[0032] At least one processor;

[0033] and a memory in communication connection with the at least one processor;

[0034] Wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to:

[0035] Performing multiplication operation on the sampled three-phase sinusoidal input signal and two orthogonal signals output by a fixed frequency signal generator respectively to obtain two output signals corresponding to each phase sinusoidal input signal respectively;

[0036] Performing sliding average value filtering on the two output signals corresponding to each phase sinusoidal input signal respectively to obtain two filtered signals corresponding thereto;

[0037] For each phase sinusoidal input signal, performing complex synthesis on the two filtered signals corresponding thereto to obtain a synthesized complex signal, and performing complex calculation on three complex signals corresponding to the three-phase sinusoidal input signal to obtain a positive sequence complex signal and a negative sequence complex signal;

[0038] According to the positive sequence complex signal and the negative sequence complex signal, obtaining a positive sequence phase and a negative sequence phase to realize phase locking of the three-phase sinusoidal input signal.

[0039] The embodiment of the present application provides a nonvolatile computer storage medium, which stores computer executable instructions, and the computer executable instructions are configured as follows:

[0040] The sampled three-phase sinusoidal input signals are respectively multiplied with two-way orthogonal signals output by a fixed frequency signal generator to obtain two-way output signals corresponding to each-phase sinusoidal input signal respectively;

[0041] The two-way output signals corresponding to each-phase sinusoidal input signal are respectively subjected to sliding average value filtering to obtain corresponding two-way filtered signals;

[0042] For each-phase sinusoidal input signal, the corresponding two-way filtered signals are subjected to complex synthesis to obtain synthesized complex signals, and three complex signals corresponding to the three-phase sinusoidal input signals are subjected to complex calculation to obtain positive sequence complex signals and negative sequence complex signals;

[0043] According to the positive sequence complex signals and the negative sequence complex signals, positive sequence phases and negative sequence phases are obtained, and phase locking of the three-phase sinusoidal input signals is realized.

[0044] The implementation method of the digital fixed-frequency three-phase phase-locked loop provided in the present application can bring the following advantages

[0045] Advantages:

[0046] Through multiplication operation of the three-phase sinusoidal input signals and two-way orthogonal signals, and through sliding average value filtering, complex synthesis and complex calculation, the positive sequence and negative sequence complex signals can be effectively separated, so that the positive sequence phases and the negative sequence phases are obtained, the phase-locked loop is no longer limited to tracking of the positive sequence signals, the negative sequence components in the power grid voltage can be effectively coped with, the phase locking of the three-phase sinusoidal input signals is realized, and the adaptability of the system in the complex power grid environment is enhanced, thereby providing strong support for stable connection and efficient operation of the power electronic equipment and the power grid. BRIEF DESCRIPTION OF DRAWINGS

[0047] The drawings described herein are used to provide further understanding of the present application, constitute a part of the present application, and the illustrative embodiments of the present application and the description thereof are used to explain the present application, and do not constitute improper limitation on the present application. In the drawings:

[0048] Figure 1 A flowchart of the implementation method of the digital fixed-frequency three-phase phase-locked loop provided in the embodiment of the present application is shown in the figure;

[0049] Figure 2 A flowchart of another implementation method of the digital fixed-frequency three-phase phase-locked loop provided in the embodiment of the present application is shown in the figure;

[0050] Figure 3A phase locking and amplitude output schematic diagram for a three-phase positive sequence input signal provided by an embodiment of the present application;

[0051] Figure 4 A phase locking and amplitude output schematic diagram for a sudden negative sequence input signal provided by an embodiment of the present application;

[0052] Figure 5 A structure schematic diagram of an implementation device of a digital fixed-frequency three-phase phase-locked loop provided by an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely below in combination with specific embodiments of the present application and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0054] When the power grid appears short circuit, sudden starting of large motors and the like, the power grid voltage can no longer be symmetrical. At this time, in addition to the normal positive sequence component, the power grid voltage will also generate a negative sequence component. The traditional phase-locked loop can only lock the positive sequence component, and has no means to deal with the negative sequence component, and even can be disturbed by the negative sequence to cause locking error or instability. In order to solve this problem, the embodiments of the present application can make the digital controller accurately separate and output the amplitude and phase of the positive sequence and negative sequence components through complex operation on the signal obtained after sampling the power grid voltage, so as to lock the positive sequence component and the negative sequence component at the same time.

[0055] The digital controller refers to the core computing unit for realizing the control algorithm by digital hardware. In the embodiments of the present application, the whole phase-locked loop process is realized by program code or hardware logic in the digital controller. After sampling the power transmission and distribution grid, the digital controller will finally output the corresponding positive sequence phase and negative sequence phase through the phase-locked loop for the three-phase sinusoidal input signal obtained by sampling.

[0056] The technical solutions provided by the embodiments of the present application will be described in detail below in combination with the drawings.

[0057] As shown in Figure 1 The implementation method of the digital fixed-frequency three-phase phase-locked loop provided by the embodiments of the present application is applied to a digital controller, and includes the following steps:

[0058] S101: Perform multiplication operation on the three-phase sinusoidal input signal obtained by sampling and two paths of quadrature signals output by a fixed frequency signal generator respectively to obtain two paths of output signals corresponding to each phase sinusoidal input signal respectively.

[0059] As Figure 2 shown, the digital controller will sample the three-phase sinusoidal input signal (input A, input B, input C) and the two-way orthogonal signal (2sin(θ), 2cos(θ)) output by the fixed frequency signal generator to perform multiplication operation, and obtain two-way output signals corresponding to each phase sinusoidal input signal.

[0060] Before multiplication operation, the digital controller needs to obtain the orthogonal signal generated by the fixed frequency signal generator at the current sampling time. The angular frequency of the fixed frequency signal generator is a fixed value ω, and according to the ratio between the fixed angular frequency and the sampling period, the phase change amount of the digital controller in each sampling period can be determined. The phase of the last time and the change amount are superimposed and then subjected to modulo operation to generate the current time phase. The phase is a periodic quantity, and the modulo operation ensures that the phase value always circulates within the range of [0, 2π), simulating the behavior of a real rotating electric angle. The current time phase is subjected to sine operation and cosine operation to generate two-way orthogonal signals with a phase difference of 90°, i.e. 2sin(θ(n)) and 2cos(θ(n)), as the local reference of the phase-locked loop. The above process can be represented by the following formula:

[0061]

[0062] wherein θ(n) represents the current time phase, θ(n-1) represents the last time phase, n represents the time, and T represents the sampling period.

[0063] Through phase accumulation and modulo operation, a digital phase signal rotating at a preset angular frequency ω is generated, and then through sine and cosine calculation, two-way reference signals with standardized amplitude and orthogonal phase are output, providing a fixed frequency reference for the phase-locked loop that is not affected by power grid disturbance.

[0064] After generating two-way orthogonal signals by the fixed frequency signal generator, multiplication operation is performed on each phase signal with 2sin(θ(n)) and 2cos(θ(n)) generated by the fixed frequency signal generator.

[0065] 2×sin(θ(n))×InA(n)

[0066] 2×cos(θ(n))×InA(n)

[0067] 2×sin(θ(n))×InB(n)

[0068] 2×cos(θ(n))×InB(n)

[0069] 2×sin(θ(n))×InC(n)

[0070] 2 * cos(0(n)) * InC(n)

[0071] wherein InA(n), InB(n) and InC(n) represent the sampling values of the three-phase input sinusoidal signals at time n, respectively.

[0072] If the input signal frequency is exactly equal to the frequency of the signal generator ω, and the phase also matches, after multiplication and filtering, a direct current signal is obtained, which represents a phase difference of zero. If the frequencies are equal but the phases differ, a low-frequency signal is obtained after multiplication and filtering, and its value reflects the phase difference. If the input signal contains positive and negative sequences, they can be separated into different frequency positions through this multiplication operation, which facilitates subsequent separation. After the above multiplication operation, as shown in FIG. 2, two output signals InX*2sin(0) and InX*2cos(0) (X represents A, B, and C) are obtained after multiplication of each-phase input signal, and thus, a total of six output signals are finally obtained. Figure 2

[0073] S102: The two output signals corresponding to each-phase sinusoidal input signal are respectively subjected to sliding average filtering to obtain two corresponding filtered signals.

[0074] After obtaining the two output signals corresponding to each-phase sinusoidal input signal, the input signal is subjected to sliding average filtering to filter out noise and interference of other frequencies, and finally two filtered signals are obtained. As shown in FIG. 3, the sliding average filter is used for sliding average filtering calculation, and the number thereof corresponds to the number of output signals, which is six, and the finally output filtered signals are also six. Figure 2

[0075] In an embodiment, when performing sliding average filtering, the fundamental frequency of the digital controller and the grid frequency need to be determined first, and then according to the ratio between the sampling frequency and the grid frequency, the preset sampling window length is determined, which is specifically represented as: wherein N represents the sampling window length, and f represents the sampling frequency. The sampling window length represents the number of samplings in one grid cycle, and an integer operation needs to be performed on the calculation result. By setting the sampling window length, it can be ensured that the window time of the sliding average is exactly equal to one grid cycle, so that the alternating component with the same frequency as the grid fundamental frequency can be completely filtered out, and only the direct current component is retained.

[0076] After the sampling window length is determined, for each output signal, the average value of the output signal corresponding to the sampling value at each sampling time in the sampling window length is determined to obtain the corresponding filtered signal. It is specifically represented as:

[0077] Out(n) = [In(n) + In(n-1) + In(n-2) +... + In(n-N+1)] / N ​​

[0078] Wherein, Out(n) represents the filtering signal at n time, In(n), In(n-1)…In(n-N+1) represents the value corresponding to the output signal at n time.

[0079] After the output signal passes through the sliding average filter, for the positive sequence component which is in phase with the frequency of the signal generator, a direct current value reflecting the amplitude and phase of the positive sequence component in this phase will be obtained after averaging for a complete cycle. For the negative sequence component which is in the same frequency but opposite direction as the signal generator, a direct current value reflecting the amplitude and phase of the negative sequence component in this phase will also be obtained after averaging for a complete cycle. For noise or interference of other frequencies, it will be effectively filtered out.

[0080] S103: For each phase sinusoidal input signal, the corresponding two filtering signals are complexly synthesized to obtain a synthesized complex signal, and the three complex signals corresponding to the three-phase sinusoidal input signals are complexly calculated to obtain a positive sequence complex signal and a negative sequence complex signal.

[0081] The two filtering signals obtained after filtering each phase sinusoidal input signal are complexly synthesized, and the complex obtained after combination represents the complex representation of the locked frequency component in the reference system of the signal generator phase θ(n) in the phase voltage signal, and the modulus value represents the amplitude of the component and the angle represents the phase difference of the component relative to θ(n). After complex synthesis of the sinusoidal input signals of each phase, three complex signals will be obtained, and complex calculation of the three complex signals will realize the positive sequence separation and negative sequence separation of the signals and obtain the corresponding positive sequence complex signal and negative sequence complex signal.

[0082] Wherein, when complex synthesis is performed, the following formula can be used:

[0083] Com(n) = Re(n) + j*Im(n)

[0084] Wherein, Com(n) represents the complex signal at n time, Re(n) and Im(n) are the real part and the imaginary part, corresponding to the two filtering signals, and j is the imaginary symbol. The real part represents the voltage amplitude information, and the imaginary part represents the phase difference information. The real part corresponds to the filtering signal of the InX*2cos(θ) channel, and the imaginary part corresponds to the filtering signal of the InX*2sin(θ) channel.

[0085] In one embodiment, the three complex signals corresponding to the three-phase sinusoidal input signals are complexly calculated by the following formula:

[0086]

[0087] wherein, ComA(n), ComB(n) and ComC(n) represent the complex signals corresponding to the three-phase sinusoidal input signal at n time, ComPos(n) represents the positive sequence complex signal, and ComNeg(n) represents the negative sequence complex signal, e j2π / 3 and e -j2π / 3 are constant complex expressions.

[0088] The formula is actually a linear transformation based on complex number operation, which uses the characteristics of complex phasor representing signal amplitude and phase and the characteristics of complex multiplication realizing phase rotation to construct a transformation matrix. By multiplying the three-phase original signal (ComA, ComB, ComC) with the matrix, two basic rotating components in the signal, i.e., the positive sequence complex signal and the negative sequence complex signal, can be effectively separated. The output result is a complex phasor, whose modulus quantifies the strength of the signal, and whose argument gives the instantaneous phase information of the signal.

[0089] S104: According to the positive sequence complex signal and the negative sequence complex signal, the positive sequence phase and the negative sequence phase are obtained, and the phase locking of the three-phase sinusoidal input signal is realized.

[0090] According to the separated positive sequence complex signal and the negative sequence complex signal, complex modulus and phase angle calculation are performed on the positive sequence complex signal and the negative sequence complex signal, so that the positive sequence phase, the positive sequence amplitude, the negative sequence phase and the negative sequence amplitude can be calculated. By estimating and tracking the positive sequence phase and the negative sequence phase, the output phase of the system is adjusted to keep consistent with the phase of the input signal or to satisfy a specific phase relationship, thereby realizing the phase locking of the entire three-phase sinusoidal input signal.

[0091] Specifically, the positive sequence phase angle corresponding to the positive sequence complex signal and the negative sequence phase angle corresponding to the negative sequence complex signal are calculated through the arctangent function. The fixed frequency signal generator provides a phase reference of the reference frequency, i.e., θ(n), and the signal phase angle is superimposed with the phase reference, so that the result phase is locked to the system reference frequency and the frequency drift influence is eliminated. Therefore, by adding the positive sequence phase angle and the negative sequence phase angle to the phase value θ(n) generated by the fixed frequency signal generator, the corresponding positive sequence phase and negative sequence phase can be obtained, wherein the positive sequence phase corresponds to the actual phase in the inverse rotation direction, and the negative sequence phase corresponds to the actual phase in the forward rotation direction. By independently calculating the compensation phases of the two, the components in different rotation directions can be accurately tracked.

[0092] Figure 2 Another flowchart of the implementation method of the digital fixed-frequency three-phase phase-locked loop provided by the embodiment of the application is shown. As shown in Figure 2As shown, the fixed frequency signal generator generates two orthogonal signals 2sin(θ) and 2cos(θ) according to the angular frequency ω, and then the three-phase sinusoidal input signals A, B and C are respectively connected to the two output signals of the signal generator through the multiplier, and each phase signal obtains two corresponding output signals after passing through the multiplier; the output signals passing through the multiplier are respectively connected to the moving average filter, the moving average filter performs moving average filtering on the output signals, and outputs the filtered signals, and the filtered signals are connected to the complex synthesis module to obtain three complex signals. The three complex signals pass through the complex calculation module to obtain the positive sequence complex signal and the negative sequence complex signal, the amplitude and phase angle of the positive sequence complex are calculated, the amplitude and phase angle of the negative sequence complex are calculated, and finally the modulus and phase of the positive sequence signal and the negative sequence signal are obtained.

[0093] The implementation method of the digital fixed-frequency three-phase phase-locked loop proposed in the embodiment of the application is simulated and verified in MATLAB / Simulink. In the embodiment, the controller sampling frequency is 16 kHz, and the known power grid frequency is 50 Hz. The input signal is a three-phase 380V 50Hz power grid voltage signal (single-phase amplitude 311V). Figure 3 The phase locking and amplitude output of the three-phase positive sequence input signal in the embodiment of the application can be seen, and it can be seen that the output amplitude is correct, and the phase almost coincides with the phase of the input signal. Figure 4 A 20% negative sequence signal is suddenly increased at 0.5s, and it can be seen that the negative sequence output amplitude and phase reach stability in 20ms, and the negative sequence phase almost coincides with the negative sequence input phase. The simulation verifies that the phase-locked loop proposed in the embodiment of the application can correctly and quickly lock the amplitude and phase of the positive sequence and negative sequence signals of the three-phase sinusoidal signal.

[0094] The above is the method embodiment proposed in the application. Based on the same idea, some embodiments of the application also provide a device and a non-volatile computer storage medium corresponding to the above method.

[0095] Figure 5 The structure schematic diagram of the implementation device of the digital fixed-frequency three-phase phase-locked loop provided in the embodiment of the application is shown in FIG. 1. Figure 5 As shown in FIG. 1, it comprises:

[0096] at least one processor; and

[0097] a memory in communication connection with the at least one processor; wherein

[0098] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to:

[0099] The sampled three-phase sinusoidal input signals are multiplied with two orthogonal signals output by a fixed frequency signal generator respectively to obtain two output signals corresponding to each phase sinusoidal input signal respectively;

[0100] The two output signals corresponding to each phase sinusoidal input signal are respectively subjected to sliding average filtering to obtain two filtered signals respectively;

[0101] The two filtered signals corresponding to each phase sinusoidal input signal are subjected to complex synthesis to obtain a synthesized complex signal, and three complex signals corresponding to the three-phase sinusoidal input signals are subjected to complex calculation to obtain a positive sequence complex signal and a negative sequence complex signal;

[0102] The positive sequence phase and the negative sequence phase are obtained according to the positive sequence complex signal and the negative sequence complex signal, and phase locking of the three-phase sinusoidal input signals is realized.

[0103] The non-volatile computer storage medium provided by the embodiment of the application stores computer executable instructions, and the computer executable instructions are configured to:

[0104] The sampled three-phase sinusoidal input signals are multiplied with two orthogonal signals output by a fixed frequency signal generator respectively to obtain two output signals corresponding to each phase sinusoidal input signal respectively;

[0105] The two output signals corresponding to each phase sinusoidal input signal are respectively subjected to sliding average filtering to obtain two filtered signals respectively;

[0106] The two filtered signals corresponding to each phase sinusoidal input signal are subjected to complex synthesis to obtain a synthesized complex signal, and three complex signals corresponding to the three-phase sinusoidal input signals are subjected to complex calculation to obtain a positive sequence complex signal and a negative sequence complex signal;

[0107] The positive sequence phase and the negative sequence phase are obtained according to the positive sequence complex signal and the negative sequence complex signal, and phase locking of the three-phase sinusoidal input signals is realized.

[0108] Each of the embodiments in the application is described in a progressive manner, and the same or similar parts of each of the embodiments can be referred to each other, and each of the embodiments mainly describes the difference from other embodiments. In particular, the device and medium embodiments are basically similar to the method embodiments, so the description is relatively simple, and the related parts can be referred to the part of the method embodiment.

[0109] The device and medium provided by the embodiments of the present application are one-to-one corresponding, and therefore, the device and medium also have similar beneficial technical effects to the corresponding method. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the device and medium will not be described here again.

[0110] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. In addition, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0111] The present application is described with reference to flowcharts and / or block diagrams of the method, device (system), and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus generate a means for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that implements the functions specified in one or more flows and / or blocks.

[0112] These computer program instructions can also be stored in a computer-readable memory that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction apparatus, which implements the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that implements the functions specified in one or more flows and / or blocks.

[0113] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable data processing apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide a means for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that implements the functions specified in one or more flows and / or blocks.

[0114] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memories.

[0115] Memory can include non-persistent memory, Random Access Memory (RAM), and / or non-volatile memory, such as Read Only Memory (ROM) or flash memory, in computer readable media. Memory is an example of computer readable media.

[0116] Computer readable media includes permanent and non-permanent, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital versatile disc (DVD), or other optical storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to a computing device. According to the definition herein, computer readable media does not include transitory media, such as modulated data signals and carrier waves.

[0117] It should also be noted that the terms "comprising", "containing", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not include only those elements in the list, but can also include other elements not expressly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0118] The above description is only some embodiments of the present application, and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. A method for implementing a digital fixed-frequency three-phase phase-locked loop, characterized in that: Applied to a digital controller, the method comprises: The sampled three-phase sinusoidal input signal is multiplied by two orthogonal signals output by a fixed-frequency signal generator to obtain two output signals corresponding to each phase of the sinusoidal input signal; Perform sliding average filtering on the two output signals corresponding to each phase of the sinusoidal input signal to obtain the corresponding two filtered signals; For each phase of the sinusoidal input signal, the corresponding two filtered signals are complex synthesized to obtain a synthesized complex signal, and the three complex signals corresponding to the three-phase sinusoidal input signals are complex calculated to obtain a positive sequence complex signal and a negative sequence complex signal; A positive-sequence phase and a negative-sequence phase are obtained according to the positive-sequence complex signal and the negative-sequence complex signal, thereby achieving phase locking of the three-phase sinusoidal input signal.

2. The method for realizing a digital fixed-frequency three-phase phase-locked loop according to claim 1, characterized in that: Before multiplying the sampled three-phase sinusoidal input signal with the two orthogonal signals output by the fixed-frequency signal generator, the method further includes: The fixed frequency signal generator is used to determine the phase change within each sampling period, and the phase at the previous moment and the change are superimposed and then modulo operation is performed to generate the phase at the current moment; Perform sine and cosine operations on the current phase to output two orthogonal signals.

3. The method for realizing a digital fixed-frequency three-phase phase-locked loop according to claim 1, characterized in that: Obtaining a positive-sequence phase and a negative-sequence phase according to the positive-sequence complex signal and the negative-sequence complex signal specifically includes: Calculating a positive-sequence phase angle corresponding to the positive-sequence complex signal and a negative-sequence phase angle corresponding to the negative-sequence complex signal; The positive-sequence phase angle and the negative-sequence phase angle are respectively added to the phase value generated by the fixed-frequency signal generator to obtain the corresponding positive-sequence phase and negative-sequence phase.

4. The method for realizing a digital fixed-frequency three-phase phase-locked loop according to claim 1, characterized in that: The two output signals corresponding to each phase of the sinusoidal input signal are respectively subjected to sliding average filtering to obtain the corresponding two filtered signals, specifically including: Determine the preset sampling window length; For each output signal, the average value of the output signal corresponding to each sampling moment in the sampling window length is determined to obtain the corresponding filtered signal.

5. The method for realizing a digital fixed-frequency three-phase phase-locked loop according to claim 1, characterized in that: Perform complex calculations on the three complex signals corresponding to the three-phase sinusoidal input signal to obtain positive sequence complex signals and negative sequence complex signals, specifically including: The three complex signals corresponding to the three-phase sinusoidal input signal are calculated using the following formula: Where ComA(n), ComB(n) and ComC(n) represent the complex signals corresponding to the three-phase sinusoidal input signal at time n, ComPos(n) represents the positive sequence complex signal, ComNeg(n) represents the negative sequence complex signal, and e j2π / 3 and e -j2π / 3 is a constant complex expression.

6. The method for realizing a digital fixed-frequency three-phase phase-locked loop according to claim 1, characterized in that: The corresponding two-way filtered signals are complex-synthesized to obtain a synthesized complex signal, specifically including: The corresponding two-way filter signals are complex synthesized using the following formula: Com(n)=Re(n)+j*Im(n) Where Com(n) represents the complex signal at time n, Re(n) and Im(n) are the real and imaginary parts, corresponding to the two filtered signals respectively, and j is the imaginary number sign.

7. The method for realizing a digital fixed-frequency three-phase phase-locked loop according to claim 1, characterized in that: After obtaining the positive sequence complex signal and the negative sequence complex signal, the method further includes: Complex modulo is performed on the positive-sequence complex signal and the negative-sequence complex signal to obtain a positive-sequence modulus value corresponding to the positive-sequence complex signal and a negative-sequence modulus value corresponding to the negative-sequence complex signal.

8. The method for realizing a digital fixed-frequency three-phase phase-locked loop according to claim 4, characterized in that: Determine the preset sampling window length, including: Determine the sampling frequency and grid frequency; A preset sampling window length is determined according to a ratio between the sampling frequency and the grid frequency.

9. A device for implementing a digital fixed-frequency three-phase phase-locked loop, characterized in that: The device comprises: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the implementation method of a digital fixed-frequency three-phase phase-locked loop as described in any one of claims 1-8.

10. A non-volatile computer storage medium storing computer executable instructions, characterized in that: The computer executable instructions are configured to: A method for implementing a digital fixed-frequency three-phase phase-locked loop as claimed in any one of claims 1 to 8.

Images