Compensation method and device applied to clock data restorer

Abstract

The embodiment of the invention provides a compensation method and device applied to a clock data restorer, and relates to the field of communication. The method comprises the following steps: obtaining a jitter domain value based on a phase interpolator control code and a frequency offset value; obtaining a periodic jitter total compensation value based on a phase discrimination result and the jitter domain value; and sending the total compensation value of the periodic jitter to a clock data restorer, so that the clock data restorer adjusts the phase interpolator control code based on the total compensation value of the periodic jitter. According to the invention, the problem that the resistance of the clock data restorer to the periodic jitter of the link needs to be ensured at the additional cost of increasing resource overhead or performance loss in the prior art is at least solved; and thus, the effect of improving the resistance of the clock data restorer to the link periodic jitter on the premise of not sacrificing performance and relatively small resource overhead is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communications, and in particular to a compensation method and device applied to a clock data restorer. Background Art

[0002] With the rapid development of fields such as artificial intelligence and cloud computing, data centers are increasingly demanding higher stability for high-speed data transmission. This requires high-speed data transmission interface SerDes (Serializer-Deserializer) receivers to have higher robustness when dealing with complex link environments. However, interference factors such as periodic jitter in the link can directly affect the control code output from the receiver's clock data recovery (CDR) to the phase interpolator (PI), causing periodic jumps in the sampling phase and ultimately worsening the SerDes receiver's bit error rate.

[0003] Currently, the majority of operations in related jitter compensation solutions are implemented entirely in hardware circuits, which identify different types of jitter and implement adaptive compensation based on their classification. However, as the number of identifiable jitter types increases and the recognition resolution improves, the circuit size will increase accordingly.

[0004] Obviously, the related technology has the defect that it requires additional costs such as increased resource overhead or performance degradation to ensure the clock data recovery device's resistance to link period jitter. Summary of the Invention

[0005] The embodiments of the present invention provide a compensation method and device for a clock data recovery device, which at least solves the problem that related technologies require additional costs such as increased resource overhead or performance degradation to ensure the clock data recovery device's resistance to link period jitter.

[0006] According to one embodiment of the present invention, a compensation method for a clock data recoverer is provided, comprising: obtaining a jitter domain value based on a phase interpolator control code and a frequency offset value; obtaining a total period jitter compensation value based on a phase detection result and the jitter domain value; and sending the total period jitter compensation value to the clock data recoverer so that the clock data recoverer adjusts the phase interpolator control code based on the total period jitter compensation value.

[0007] According to another embodiment of the present invention, a compensation device for a clock data recoverer is provided, comprising: a firmware operation module for obtaining a jitter domain value based on a phase interpolator control code and a frequency deviation value; a hardware real-time tracking module for obtaining a total period jitter compensation value based on a phase detection result and the jitter domain value; and sending the total period jitter compensation value to the clock data recoverer so that the clock data recoverer adjusts the phase interpolator control code based on the total period jitter compensation value; wherein the phase interpolator control code, the frequency deviation value, and the phase detection result are sent by the clock data recoverer.

[0008] Through one of the above-mentioned embodiments of the present invention, a method of obtaining a jitter domain value based on a phase interpolator control code and a frequency deviation value is adopted. The phase interpolator control code reflects the current state of the phase interpolator, and the frequency deviation value reflects the deviation in frequency. The two are combined to determine the jitter domain value. This jitter domain value can more accurately measure the degree of influence of periodic jitter in the current link environment, and the process can be implemented using software, avoiding the problem of increased resource overhead such as circuit scale expansion caused by relying solely on hardware circuits to identify multiple jitter types in related technologies. Then, a total compensation value for periodic jitter is obtained based on the phase detection result and the jitter domain value. The phase detection result can reflect the phase difference between the clock signal and the data signal. The compensation value is determined in combination with the jitter domain value, which can compensate for periodic jitter in a more targeted manner, without the need to increase a large amount of hardware resources to improve the recognition and compensation capabilities of multiple types of jitter as in related technologies. Finally, the total period jitter compensation value is sent to the clock data recovery device, which adjusts the phase interpolator control code based on the compensation value, thereby achieving effective adjustment of the sampling phase, reducing sampling phase jumps caused by period jitter, and lowering the bit error rate, thereby improving the clock data recovery device's resistance to link period jitter. Furthermore, the device can optimize the allocation of computing tasks based on computational real-time performance and computing resources, maintaining system stability. Therefore, this method at least solves the problem of related technologies requiring additional costs such as increased resource overhead or performance degradation to ensure the clock data recovery device's resistance to link period jitter. This method achieves the effect of improving the clock data recovery device's resistance to link period jitter without sacrificing performance and with minimal resource overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a flow chart of a compensation method applied to a clock data restorer according to an embodiment of the present invention;

[0010] Figure 2 is a flow chart of a method for obtaining a jitter threshold value based on a phase interpolator control code and a frequency offset value according to an embodiment of the present invention;

[0011] Figure 3is a flow chart of an exemplary method for obtaining a jitter threshold value based on a phase interpolator control code and a frequency offset value according to an embodiment of the present invention;

[0012] Figure 4 is a flow chart of a method for obtaining a total period jitter compensation value based on a phase detection result, a period jitter frequency compensation value, and a period jitter amplitude compensation value according to an embodiment of the present invention;

[0013] Figure 5 is a flow chart of a method for obtaining a total period jitter compensation value based on tracking phase values ​​and period jitter amplitude compensation values ​​according to an embodiment of the present invention;

[0014] Figure 6 is a flowchart of a method for obtaining a total period jitter compensation value based on a period jitter amplitude compensation value, a sine iteration final value, or a cosine iteration final value according to an embodiment of the present invention;

[0015] Figure 7 Flowchart of a method for iterating in parallel step by step a sine iteration initial value, a cosine iteration initial value, and a radian iteration initial value to obtain a sine iteration final value and a cosine iteration final value according to an embodiment of the present invention;

[0016] Figure 8 is a schematic structural diagram of a compensation device applied to a clock data restorer according to an embodiment of the present invention;

[0017] Figure 9 is a schematic structural diagram of a hardware real-time tracking module according to an embodiment of the present invention;

[0018] Figure 10 is a schematic structural diagram of a phase tracking submodule according to an embodiment of the present invention;

[0019] Figure 11 This is a schematic diagram of the structure of the sine and cosine value calculation submodule according to an embodiment of the present invention. Figure 1 ;

[0020] Figure 12 This is a schematic diagram of the structure of the sine and cosine value calculation submodule according to an embodiment of the present invention. Figure 2 ;

[0021] Figure 13 This is a schematic diagram of the structure of the sine and cosine value calculation submodule according to an embodiment of the present invention. Figure 3 .

[0022] Explanation of reference signs: 81, firmware operation module; 82, hardware real-time tracking module; 821, phase tracking submodule; 8211, phase range adjustment unit; 8212, proportional path unit; 8213, integral path unit; 8214, first compensation quantization unit; 822, sine and cosine value calculation submodule; 8221, phase normalization unit; 8222, concatenated lookup table unit; 82221, radian iterative lookup table subunit; 82222, sine and cosine iterative lookup table subunit; 8223, second compensation quantization unit. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0024] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence.

[0025] In an embodiment of the present application, a compensation method applied to a clock data recovery device is provided, Figure 1 is a flowchart of a compensation method applied to a clock data recovery device according to an embodiment of the present application, as Figure 1 shown, the flow includes the following steps:

[0026] Step S101, obtaining a jitter domain value based on a phase interpolator control code and a frequency offset value;

[0027] In an exemplary embodiment, for example, a firmware operation module can be designed, which includes a register. A processor reads a phase interpolator sequence and a frequency offset value register of a clock data recovery device, and completes the calculation of frequency compensation and amplitude compensation value in the processor to obtain a jitter domain value, and writes the jitter domain value back to the register of the firmware operation module through the write register.

[0028] Step S102, obtaining a total period jitter compensation value based on a phase discrimination result and the jitter domain value;

[0029] In an exemplary embodiment, for example, a hardware real-time tracking module can be designed. The hardware real-time tracking module is directly physically connected to the register of the firmware operation module on the circuit, so as to read the jitter domain value from the register of the firmware operation module in real time. The phase discrimination result is obtained from the clock data recovery device through the circuit, so as to obtain a total period jitter compensation value based on the phase discrimination result and the jitter domain value.

[0030] Step S103, sending the total period jitter compensation value to the clock data recovery device, so that the clock data recovery device adjusts the phase interpolator control code based on the total period jitter compensation value.

[0031] In an example embodiment, the hardware real-time tracking module can transmit the total cycle jitter compensation value to the clock data recovery device via a circuit, so that the clock data recovery device adjusts the phase interpolator control code based on the total cycle jitter compensation value.

[0032] Through the above steps S101 to S103, since the jitter domain value is obtained based on the phase interpolator control code and the frequency offset value. The phase interpolator control code reflects the current state of the phase interpolator, and the frequency offset value reflects the deviation of the frequency. The two are combined to determine the jitter domain value, which can more accurately measure the influence of the cycle jitter in the current link environment. The process can be implemented by software, avoiding the problem of increased resource overhead caused by the expansion of the circuit size due to the pure dependence on hardware circuit to identify multiple jitter types in the related art. Then, the total cycle jitter compensation value is obtained based on the phase discrimination result and the jitter domain value. The phase discrimination result can reflect the phase difference between the clock signal and the data signal. Combined with the jitter domain value, the compensation value can be determined to more specifically compensate for the cycle jitter. Unlike the related art, it does not need to increase a large amount of hardware resources to improve the identification and compensation ability of multiple types of jitter. Finally, the total cycle jitter compensation value is sent to the clock data recovery device, so that it adjusts the phase interpolator control code based on the compensation value, thereby effectively adjusting the sampling phase, reducing the sampling phase jump caused by the cycle jitter, and reducing the bit error rate. Thus, the resistance of the clock data recovery device to the link cycle jitter is improved, and the calculation task can be optimized and distributed according to the operation real-time performance and operation resources. Therefore, at least the problem of the related art that needs to increase resource overhead or performance loss to ensure the resistance of the clock data recovery device to the link cycle jitter is solved, thereby achieving the effect of improving the resistance of the clock data recovery device to the link cycle jitter without sacrificing performance and with small resource overhead.

[0033] Figure 2 is a flowchart of the method for obtaining a jitter domain value based on a phase interpolator control code and a frequency offset value according to an embodiment of the application, as shown in Figure 2 In an embodiment, the method for obtaining a jitter domain value based on a phase interpolator control code and a frequency offset value comprises:

[0034] Step S201, eliminating the frequency offset for the interpolator control code based on the frequency offset value to obtain a phase interpolator control code sequence without frequency offset;

[0035] Figure 3 is a flowchart of an example method for obtaining a jitter domain value based on a phase interpolator control code and a frequency offset value according to an embodiment of the application, in combination with Figure 3As shown, in an exemplary embodiment, the phase interpolator control code sequence (PI code sequence) without frequency deviation and the frequency deviation value are monitored in real time, the captured PI code sequence is checked, and it is determined whether there is a frequency deviation. If there is a frequency deviation, the frequency deviation is eliminated for the interpolator control code based on the frequency deviation value to obtain a phase interpolator control code sequence without frequency deviation (PI code sequence without frequency deviation) after the frequency deviation is eliminated. For example, a pre-trained compensation model is loaded or the influence of the frequency deviation value on the phase interpolator control code is calculated according to a known formula to eliminate the frequency deviation. If there is no frequency deviation: directly proceed to the subsequent processing steps.

[0036] Step S202 : performing fast Fourier transform and statistical distribution swing processing on the phase interpolator control code sequence without frequency offset to obtain a jitter threshold value.

[0037] In an exemplary embodiment, when a frequency-bias-free phase interpolator control code sequence (frequency-bias-free PI code sequence) is obtained after frequency offset elimination, a fast Fourier transform is performed on the frequency-bias-free phase interpolator control code sequence (frequency-bias-free PI code sequence) after frequency offset elimination, and the peak value in the frequency domain is scanned to extract the jitter frequency. For example, the FFT function in the mathematical library can be called to implement this operation. For example, the FFT function in the NumPy library can be used in Python language. The distribution of the frequency-bias-free phase interpolator control code sequence (frequency-bias-free PI code sequence) after frequency offset elimination is statistically analyzed, the frequency of occurrence of different amplitude values ​​is calculated, and the range and distribution pattern of the amplitude value are determined. Based on these statistical results, the jitter swing is calculated in combination with specific rules or models (such as assuming that the data conforms to a normal distribution, etc.). According to the jitter frequency obtained by FFT processing and the jitter swing obtained by statistical distribution swing processing, the jitter frequency and amplitude compensation parameters are configured to obtain the jitter domain value.

[0038] In one embodiment, after obtaining the jitter domain value based on the phase interpolator control code and the frequency offset value, the method further includes: decomposing the jitter domain value into a periodic jitter frequency compensation value and a periodic jitter amplitude compensation value, so as to obtain a total periodic jitter compensation value based on the phase detection result, the periodic jitter frequency compensation value, and the periodic jitter amplitude compensation value.

[0039] In an exemplary embodiment, the jitter domain value is analyzed, for example, using a mathematical model or a signal processing algorithm. The jitter domain value is regarded as a composite signal, which contains two main components: frequency and amplitude. Through frequency domain analysis methods such as Fourier transform, the frequency component in the jitter can be extracted and used as the periodic jitter frequency compensation value. At the same time, the jitter domain value is subjected to time domain or statistical analysis to calculate the characteristics of its amplitude change, such as the standard deviation or peak value, to determine the periodic jitter amplitude compensation value. For example, the data can be processed with the help of functions in the digital signal processing library, such as the fast Fourier transform (FFT) function, and then the frequency and amplitude components are extracted respectively by a specific algorithm or formula to obtain the periodic jitter frequency compensation value and the periodic jitter amplitude compensation value, so as to obtain the periodic jitter total compensation value based on the phase detection result, the periodic jitter frequency compensation value, and the periodic jitter amplitude compensation value.

[0040] Figure 4 FIG. 1 is a flow chart of a method for obtaining a total period jitter compensation value based on a phase detection result, a period jitter frequency compensation value, and a period jitter amplitude compensation value according to an embodiment of the present invention. Figure 4 As shown, in one embodiment, the total period jitter compensation value is obtained based on the phase detection result, the period jitter frequency compensation value, and the period jitter amplitude compensation value, including:

[0041] Step S401, obtaining a tracking phase value based on the periodic jitter frequency compensation value and the phase detection result;

[0042] In an exemplary embodiment, for example, after the phase detection result is feedback-adjusted using the tracking phase value, a new tracking phase value is obtained in combination with the periodic jitter frequency compensation value, and feedback adjustment is continued based on the new tracking phase value and used to execute step S402.

[0043] Step S402 : Obtaining a total period jitter compensation value based on the tracking phase value and the period jitter amplitude compensation value.

[0044] In one exemplary embodiment, the tracking phase value is combined with the period jitter amplitude compensation value, comprehensively considering both phase and amplitude jitter factors to obtain a comprehensive total period jitter compensation value. This effectively compensates for period jitter in the clock data recovery, improving the accuracy and stability of data recovery, and enhancing the system's adaptability in complex signal environments, thereby ensuring reliable data transmission.

[0045] Figure 5 FIG. 1 is a flow chart of a method for obtaining a total period jitter compensation value based on tracking phase value and period jitter amplitude compensation value according to an embodiment of the present invention. Figure 5 As shown, in one embodiment, obtaining a total period jitter compensation value based on the tracking phase value and the period jitter amplitude compensation value includes:

[0046] Step S501, obtaining a phase detection result adjustment value based on the phase detection result and the tracking phase value;

[0047] In an exemplary embodiment, for example, the tracking phase value is utilized to perform feedback adjustment on the phase discrimination result using a feedback control algorithm (eg, a PID algorithm) to obtain a phase discrimination result adjustment value.

[0048] Step S502, tracking the phase deviation value of the phase detection result adjustment value;

[0049] In an exemplary embodiment, for example, a proportional path unit is designed to track the phase deviation value of the phase detection result adjustment value. Step S503: Track the frequency deviation value of the phase detection result adjustment value;

[0050] In an exemplary embodiment, for example, an integral path unit is designed to track a frequency deviation value of the phase detection result adjustment value.

[0051] Step S504 : obtaining a tracking phase value based on the phase deviation value, the frequency deviation value, and the period jitter frequency compensation value, and obtaining a period jitter total compensation value based on the tracking phase value and the period jitter amplitude compensation value.

[0052] In one exemplary embodiment, the aforementioned technical solution implements a closed-loop feedback mechanism, allowing real-time adjustment of the tracking phase value, comprehensively considering both phase and frequency deviations, and achieving precise compensation for period jitter. This not only enhances the clock data recovery's adaptability in complex signal environments, but also significantly improves the accuracy and stability of data recovery, ensuring reliable data transmission.

[0053] Figure 6 1 is a flow chart of a method for obtaining a total period jitter compensation value based on a period jitter amplitude compensation value, a sine iteration final value, or a cosine iteration final value according to an embodiment of the present invention. Figure 6 As shown, in one embodiment, after obtaining the tracking phase value based on the phase deviation value, the frequency deviation value, and the periodic jitter frequency compensation value, the method further includes:

[0054] Step S601, performing phase normalization based on the tracking phase value to obtain an initial value for radian iteration;

[0055] In one exemplary embodiment, the tracking phase value can be normalized to limit its range to a standard interval, such as -π to π. This can be achieved by calculating the tracking phase value modulo 2π. The result of the modulo operation is the normalized phase value, ensuring that it is between -π and π. The normalized phase value is then used as the initial value for the radian iteration and is used in subsequent radian iteration calculations. For example, if the tracking phase value is 3π / 2, the modulo operation is -π / 2, which can be used as the initial value for the radian iteration.

[0056] Step S602, iterating the sine iteration initial value, the cosine iteration initial value, and the radian iteration initial value in parallel step by step to obtain the sine iteration final value and the cosine iteration final value;

[0057] Figure 7 This is a flowchart of a method for iterating the sine iteration initial value, the cosine iteration initial value, and the radian iteration initial value in parallel step by step according to an embodiment of the present invention to obtain the sine iteration final value and the cosine iteration final value. Figure 7 As shown, in one embodiment, the sine iteration initial value, the cosine iteration initial value, and the radian iteration initial value are iterated in parallel step by step to obtain the sine iteration final value and the cosine iteration final value, including:

[0058] Step S701, performing fitting iteration on the initial value of the arc iteration to obtain the arc fitting result;

[0059] In step S702, the sine iteration initial value and the cosine iteration initial value are iterated in parallel step by step in combination with the radian iteration initial value to obtain the sine iteration final value and the cosine iteration final value; wherein, the sine iteration value and cosine iteration value obtained at each level of iteration are based on the radian iteration value, sine iteration value, and cosine iteration value of the previous level.

[0060] In an exemplary embodiment, for example, the number of parallel iterations can be set based on actual needs to implement multiple fitting of the initial value of the radian iteration to obtain a final radian fitting result close to 0, and to implement multiple parallel fitting of the initial value of the sine iteration, the initial value of the cosine iteration, and the initial value of the radian iteration to obtain a sine iteration final value close to the initial value of the radian iteration, and a cosine iteration final value close to the cosine value of the initial value of the radian iteration. For example, for the third-level fitting process, the input is the radian iteration value, the sine iteration value, and the cosine iteration value output by the second-level fitting process, and fitting iterations are performed. The output is the sine iteration value and cosine iteration value obtained by the third-level fitting process, and the radian iteration value, the sine iteration value, and the cosine iteration value obtained by the third-level fitting process are used as inputs to the fourth-level fitting process, ..., until the final sine iteration value and the final cosine iteration value are obtained.

[0061] Step S603 : Obtain a total period jitter compensation value based on the period jitter amplitude compensation value, the sine iteration final value, or the cosine iteration final value.

[0062] In an exemplary embodiment, for example, the final value of the sine iteration or the final value of the cosine iteration may be used as a reference for the phase adjustment amount and multiplied by the period jitter amplitude compensation value to obtain the total period jitter compensation value.

[0063] In one embodiment, the method further includes: when a total period jitter compensation value is obtained based on the period jitter amplitude compensation value and the final value of the sine iteration, determining the convergence of the iterative process based on the final value of the cosine iteration; or, when a total period jitter compensation value is obtained based on the period jitter amplitude compensation value and the final value of the cosine iteration, determining the convergence of the iterative process based on the final value of the sine iteration; or, determining the convergence of the iterative process based on the radian fitting result.

[0064] In an exemplary embodiment, for example, if the error between the cosine value of the final value of the cosine iteration and the cosine value of the initial value of the radian iteration is within a preset range, the iterative process is determined to have converged. Alternatively, if the error between the sine value of the final value of the sine iteration and the sine value of the initial value of the radian iteration is within a preset range, the iterative process is determined to have converged. Alternatively, if the error between the radian fitting result and zero is within a preset range, the iterative process is determined to have converged. The preset range is 0 ± the error value, or 0.

[0065] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention is essentially or part of the contribution to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of various embodiments of the present invention.

[0066] It should be noted that the sequence numbers of the above steps do not limit the order of the steps. For example, step S502 and step S503 can be executed at the same time.

[0067] In an embodiment of the present invention, a compensation device for a clock data restorer is also provided. The device is used to implement the above-mentioned embodiments and preferred embodiments. Details already described are omitted. As used below, the term "module" may include a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0068] Figure 8 FIG. 1 is a schematic structural diagram of a compensation device applied to a clock data recovery device according to an embodiment of the present invention. Figure 8 As shown, the device includes:

[0069] A firmware operation module 81 is configured to obtain a jitter threshold value based on a phase interpolator control code and a frequency offset value;

[0070] In an exemplary embodiment, the firmware operation module 81 includes registers. A processor reads the phase interpolator sequence and frequency offset value register of the clock data recovery device, calculates frequency compensation and amplitude compensation values ​​within the processor to obtain a jitter threshold value, and writes the jitter threshold value back to the register of the firmware operation module 81 via a write register. The hardware real-time tracking module 82 is configured to obtain a total period jitter compensation value based on the phase detection result and the jitter threshold value; and transmit the total period jitter compensation value to the clock data recovery device, so that the clock data recovery device adjusts the phase interpolator control code based on the total period jitter compensation value.

[0071] Among them, the phase interpolator control code, frequency deviation value, and phase detection result are sent by the clock data recovery device.

[0072] In an exemplary embodiment, the hardware real-time tracking module 82 is directly physically connected to the registers of the firmware operation module 81 in a circuit, so that the jitter threshold value can be read from the registers of the firmware operation module 81 in real time. The circuit obtains the phase detection result from the clock data recovery device, and the total period jitter compensation value is obtained based on the phase detection result and the jitter threshold value.

[0073] By adopting the above technical solution, a jitter domain value is obtained based on the phase interpolator control code and the frequency deviation value. The phase interpolator control code reflects the current state of the phase interpolator, and the frequency deviation value reflects the deviation in frequency. The two are combined to determine the jitter domain value. This jitter domain value can more accurately measure the impact of periodic jitter in the current link environment, and the process can be implemented using software such as the firmware operation module 81, avoiding the problem of increased resource overhead such as circuit scale expansion caused by relying solely on hardware circuits to identify multiple jitter types in related technologies. Then, the total compensation value of periodic jitter is obtained based on the phase detection result and the jitter domain value. The phase detection result can reflect the phase difference between the clock signal and the data signal. Combined with the jitter domain value to determine the compensation value, periodic jitter can be compensated more specifically, without the need to increase a large amount of hardware resources to improve the recognition and compensation capabilities of multiple types of jitter as in related technologies. Finally, the total period jitter compensation value is sent to the clock data recovery device, which adjusts the phase interpolator control code based on the compensation value, thereby achieving effective adjustment of the sampling phase, reducing sampling phase jumps caused by period jitter, and lowering the bit error rate, thereby improving the clock data recovery device's resistance to link period jitter and optimizing the allocation of computing tasks based on the real-time nature of the operation and computing resources. Therefore, at least the problem of related technologies requiring additional costs such as increased resource overhead or performance degradation to ensure the clock data recovery device's resistance to link period jitter is solved, thereby achieving the effect of improving the clock data recovery device's resistance to link period jitter without sacrificing performance and with less resource overhead.

[0074] In one embodiment, the firmware operation module 81 is further used to: eliminate the frequency deviation for the interpolator control code based on the frequency deviation value to obtain a phase interpolator control code sequence without frequency deviation; and perform fast Fourier transform and statistical distribution swing processing on the phase interpolator control code sequence without frequency deviation to obtain a jitter domain value.

[0075] In an exemplary embodiment, after the firmware operation module 81 receives the phase interpolator control code sequence without frequency deviation, the controller performs a fast Fourier transform (FFT) on the phase interpolator control code sequence without frequency deviation. The phase interpolator control code sequence without frequency deviation in the time domain can be converted to the frequency domain through FFT, so as to analyze the jitter frequency therein. The converted frequency domain data is subjected to statistical distribution swing processing. Statistical distribution swing processing is to analyze the statistical characteristics such as the amplitude of the frequency domain signal to determine the jitter swing of the signal. According to the jitter frequency obtained by FFT processing and the jitter swing obtained by statistical distribution swing processing, the jitter frequency and amplitude compensation parameters are configured to obtain the jitter domain value.

[0076] In one embodiment, the firmware operation module 81 is further configured to decompose the jitter domain value into a period jitter frequency compensation value and a period jitter amplitude compensation value, so that the hardware real-time tracking module 82 can obtain a total period jitter compensation value based on the phase detection result, the period jitter frequency compensation value, and the period jitter amplitude compensation value.

[0077] In an exemplary embodiment, the firmware operation module 81 analyzes the jitter domain value based on the controller using a mathematical model or a signal processing algorithm. The jitter domain value is regarded as a composite signal, which contains two main components: frequency and amplitude. Through frequency domain analysis methods such as Fourier transform, the frequency component in the jitter can be extracted and used as the period jitter frequency compensation value. At the same time, the jitter domain value is subjected to time domain or statistical analysis to calculate the characteristics of its amplitude change, such as the standard deviation or peak value, to determine the period jitter amplitude compensation value. For example, the data can be processed with the help of functions in the digital signal processing library, such as the fast Fourier transform (FFT) function, and then the frequency and amplitude components are extracted respectively through a specific algorithm or formula to finally obtain the required period jitter frequency compensation value and period jitter amplitude compensation value, so that the hardware real-time tracking module 82 can obtain the total period jitter compensation value based on the phase detection result, the period jitter frequency compensation value, and the period jitter amplitude compensation value.

[0078] Figure 9 FIG. 1 is a schematic diagram of the structure of a hardware real-time tracking module according to an embodiment of the present invention. Figure 9 As shown, in one embodiment, the hardware real-time tracking module 82 includes:

[0079] The phase tracking submodule 821 is used to obtain a tracking phase value based on the periodic jitter frequency compensation value and the phase detection result;

[0080] The sine and cosine value calculation submodule 822 is configured to obtain a total period jitter compensation value based on the tracking phase value and the period jitter amplitude compensation value.

[0081] In an exemplary embodiment, the phase tracking submodule 821 obtains a period jitter frequency compensation value from the firmware operation module 81 and a phase detection result from the clock data recovery device. The phase detection result and the period jitter frequency compensation value are processed to obtain a tracking phase value, which is then sent to the sine and cosine value calculation submodule 822. The sine and cosine value calculation submodule 822 obtains a period jitter amplitude compensation value from the firmware operation module 81, processes the period jitter amplitude compensation value and the tracking phase value to obtain a total period jitter compensation value, and sends the total period jitter compensation value to the clock data recovery device, which adjusts the phase interpolator control code based on the total period jitter compensation value.

[0082] Figure 10 FIG. 1 is a structural diagram of a phase tracking submodule according to an embodiment of the present invention. Figure 10 As shown, in one embodiment, the phase tracking submodule 821 includes:

[0083] The phase range adjustment unit 8211 is used to obtain a phase detection result adjustment value based on the phase detection result and the tracking phase value;

[0084] In an exemplary embodiment, for example, the phase range adjustment unit 8211 uses a feedback control algorithm (such as a PID algorithm) to perform feedback adjustment on the phase detection result by utilizing the tracking phase value to obtain a phase detection result adjustment value.

[0085] The proportional path unit 8212 is used to track the phase deviation value of the phase detection result adjustment value;

[0086] The integral path unit 8213 is used to track the frequency deviation value of the phase detection result adjustment value;

[0087] The first compensation quantization unit 8214 is used to obtain a tracking phase value based on the phase deviation value, the frequency deviation value, and the periodic jitter frequency compensation value, and send the tracking phase value to the phase range adjustment unit 8211 and the sine and cosine value calculation submodule 822.

[0088] In an exemplary embodiment, the phase range adjustment unit 8211 obtains a phase detection result from a clock data recovery device and a tracking phase value from the first compensation quantization unit 8214. The phase detection result is feedback-adjusted using a feedback control algorithm (e.g., a PID algorithm) using the tracking phase value to obtain a phase detection result adjustment value. The phase detection result adjustment value is then sent to the proportional path unit 8212 and the integral path unit 8213. The proportional path unit 8212 tracks the phase deviation of the phase detection result adjustment value and sends the phase deviation value to the first compensation quantization unit 8214. The integral path unit 8213 tracks the frequency deviation of the phase detection result adjustment value and sends the frequency deviation value to the first compensation quantization unit 8214. The first compensation quantization unit 8214 receives the period jitter frequency compensation value sent by the firmware operation module 81, processes the phase deviation value, frequency deviation value, and period jitter frequency compensation value to obtain a tracking phase value, and sends the tracking phase value to the phase range adjustment unit 8211 and the sine and cosine value calculation submodule 822.

[0089] Figure 11 This is a schematic diagram of the structure of the sine and cosine value calculation submodule according to an embodiment of the present invention. Figure 1 ,like Figure 11 As shown, in one embodiment, the sine and cosine value calculation submodule 822 includes:

[0090] A phase normalization unit 8221 is configured to perform phase normalization based on the tracking phase value to obtain an initial value for radian iteration;

[0091] The cascade lookup table unit 8222 is used to iterate the sine iteration initial value, the cosine iteration initial value, and the radian iteration initial value in parallel step by step to obtain the sine iteration final value and the cosine iteration final value;

[0092] The second compensation quantization unit 8223 is configured to obtain a total period jitter compensation value based on the period jitter amplitude compensation value, the sine iteration final value, or the cosine iteration final value.

[0093] In an exemplary embodiment, the phase normalization unit 8221 receives the tracking phase value sent by the phase tracking submodule 821, performs phase normalization processing on the tracking phase value to obtain a radian iteration initial value, and sends the radian iteration initial value to the cascade lookup table unit 8222. The cascade lookup table unit 8222 obtains the sine iteration initial value and the cosine iteration initial value, and iterates the sine iteration initial value, the cosine iteration initial value, and the radian iteration initial value in parallel step by step to obtain a sine iteration final value and a cosine iteration final value, and sends the sine iteration final value or the cosine iteration final value to the second compensation quantization unit 8223. The second compensation quantization unit 8223 receives the periodic jitter amplitude compensation value sent by the firmware operation module 81, and processes the final value of the sine iteration and the periodic jitter amplitude compensation value, or processes the final value of the cosine iteration and the periodic jitter amplitude compensation value to obtain a total periodic jitter compensation value, and sends the total periodic jitter compensation value to the clock data recoverer so that the clock data recoverer adjusts the phase interpolator control code based on the total periodic jitter compensation value.

[0094] Figure 12 This is a schematic diagram of the structure of the sine and cosine value calculation submodule according to an embodiment of the present invention. Figure 2 ,like Figure 12 As shown, in one embodiment, the cascade lookup table unit 8222 includes:

[0095] The radian iteration lookup table subunit 82221 is used to perform fitting iteration on the radian iteration initial value to obtain a radian fitting result;

[0096] The sine-cosine iteration lookup table sub-unit 82222 is used to perform parallel iteration of the sine iteration initial value and the cosine iteration initial value step by step in combination with the radian iteration initial value to obtain the sine iteration final value and the cosine iteration final value; wherein, the sine iteration value and cosine iteration value obtained at each iteration level are based on the radian iteration value, sine iteration value, and cosine iteration value of the previous level.

[0097] In an exemplary embodiment, the radian iteration lookup table subunit 82221 receives the radian iteration initial value sent by the phase normalization unit 8221 and performs fitting iteration on the radian iteration initial value to obtain a radian fitting result. The sine-cosine iteration lookup table subunit 82222 receives the sine iteration initial value and the cosine iteration initial value, and performs parallel iterations on the sine iteration initial value, the cosine iteration initial value, and the radian iteration initial value sent by the phase normalization unit 8221. During each fitting iteration, the output result of the radian iteration lookup table subunit 82221 of the previous level is fitted with the output result of the sine-cosine iteration lookup table subunit 82222 of the previous level to perform parallel iterations on a step-by-step basis. For example, for the third-level fitting process, the input is the radian iteration value, sine iteration value, and cosine iteration value output by the second-level fitting process. Fitting iterations are performed, and the output is the sine iteration value and cosine iteration value obtained by the third-level fitting process. The radian iteration value, sine iteration value, and cosine iteration value obtained by the third-level fitting process are used as the input of the fourth-level fitting process, and so on, until the final sine iteration value and the final cosine iteration value are obtained. The final sine iteration value or the final cosine iteration value is sent to the second compensation quantization unit 8223. The second compensation quantization unit 8223 receives the period jitter amplitude compensation value sent by the firmware operation module 81 and processes the final sine iteration value and the period jitter amplitude compensation value, or processes the final cosine iteration value and the period jitter amplitude compensation value to obtain a total period jitter compensation value. The total period jitter compensation value is sent to the clock data recovery device, so that the clock data recovery device adjusts the phase interpolator control code based on the total period jitter compensation value.

[0098] In one embodiment, the sine and cosine value calculation submodule 822 is further used to: determine the convergence of the iterative process based on the final value of the cosine iteration when the total periodic jitter compensation value is obtained based on the periodic jitter amplitude compensation value and the final value of the sine iteration; or, determine the convergence of the iterative process based on the final value of the sine iteration when the total periodic jitter compensation value is obtained based on the periodic jitter amplitude compensation value and the final value of the cosine iteration; or, determine the convergence of the iterative process based on the radian fitting result.

[0099] In an exemplary embodiment, for example, if the error between the cosine value of the final value of the cosine iteration and the cosine value of the initial value of the radian iteration is within a preset range, the iterative process is determined to have converged. Alternatively, if the error between the sine value of the final value of the sine iteration and the sine value of the initial value of the radian iteration is within a preset range, the iterative process is determined to have converged. Alternatively, if the error between the radian fitting result and zero is within a preset range, the iterative process is determined to have converged. The preset range is 0 ± the error value, or 0.

[0100] Figure 13 This is a schematic diagram of the structure of the sine and cosine value calculation submodule according to an embodiment of the present invention.Figure 3 ,like Figure 13 As shown, in an exemplary embodiment, the radian iterative lookup table subunit 82221 includes multiple cascaded radian iterative lookup tables, such as radian iterative lookup table 0, radian iterative lookup table 1, radian iterative lookup table 2, and radian iterative lookup table 3. The sin-cosine iterative lookup table subunit 82222 includes multiple cascaded sin-cosine iterative lookup tables, such as sin-cosine iterative lookup table 0, sin-cosine iterative lookup table 1, sin-cosine iterative lookup table 2, and sin-cosine iterative lookup table 3. It should be noted that the radian iterative lookup table and the sin-cosine iterative lookup table at each level are used in pairs. The output result of radian iterative lookup table 0 is sent to radian iterative lookup table 1 and sin-cosine iterative lookup table 1. The output result of radian iterative lookup table 1 is sent to radian iterative lookup table 2 and sin-cosine iterative lookup table 2. The output result of radian iterative lookup table 2 is sent to radian iterative lookup table 3 and sin-cosine iterative lookup table 3, to perform multiple parallel iterative calculations. Ultimately, radian iteration lookup table 3 obtains a radian iteration final value based on the result sent by radian iteration lookup table 2. Sin-cosine iteration lookup table 3 obtains a sine iteration final value and a cosine iteration final value based on the result sent by radian iteration lookup table 2 and the result sent by sin-cosine iteration lookup table 2, and sends the sine iteration final value or the cosine iteration final value to the second compensation quantization unit 8223, so that the second compensation quantization unit 8223 obtains a total period jitter compensation value based on the sine iteration final value and the period jitter amplitude compensation value sent by the firmware operation module 81, or obtains a total period jitter compensation value based on the cosine iteration final value and the period jitter amplitude compensation value sent by the firmware operation module 81, and sends the total period jitter compensation value to the clock data recovery unit, so that the clock data recovery unit adjusts the phase interpolator control code based on the total period jitter compensation value.

[0101] It should be noted that some of the above modules are implemented through software, and some modules are implemented through hardware.

[0102] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned method embodiments involving software when running.

[0103] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0104] An embodiment of the present invention further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps of any of the above method embodiments involving software.

[0105] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0106] For specific examples in the embodiments of the present invention, reference may be made to the examples described in the above embodiments and exemplary implementations, and the embodiments of the present invention will not be described in detail here.

[0107] An embodiment of the present invention further provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned method embodiments involving software when executed by a processor.

[0108] Obviously, those skilled in the art will appreciate that the various modules or steps of the present invention described above can be implemented using a general-purpose computing device, can be centralized on a single computing device, or can be distributed across a network of multiple computing devices. They can be implemented using program code executable by the computing device, and thus, can be stored in a storage device and executed by the computing device. In some cases, the steps shown or described herein can be performed in a different order than that shown, or can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0109] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A compensation method for a clock data recovery device, characterized in that: include: A jitter threshold value is obtained based on a phase interpolator control code and a frequency offset value; Obtaining a total period jitter compensation value based on the phase detection result and the jitter domain value; The total period jitter compensation value is sent to a clock data recovery device, so that the clock data recovery device adjusts the phase interpolator control code based on the total period jitter compensation value.

2. The method according to claim 1, characterized in that After obtaining the jitter threshold value based on the phase interpolator control code and the frequency offset value, the following is also included: The jitter domain value is decomposed into a period jitter frequency compensation value and a period jitter amplitude compensation value, so as to obtain the period jitter total compensation value based on the phase detection result, the period jitter frequency compensation value and the period jitter amplitude compensation value.

3. The method according to claim 2, characterized in that Obtaining the total period jitter compensation value based on the phase detection result, the period jitter frequency compensation value, and the period jitter amplitude compensation value, including: Obtaining a tracking phase value based on the periodic jitter frequency compensation value and the phase detection result; The total period jitter compensation value is obtained based on the tracking phase value and the period jitter amplitude compensation value.

4. The method according to claim 1, wherein The jitter threshold is obtained based on the phase interpolator control code and the frequency offset value, including: Eliminating the frequency offset for the interpolator control code based on the frequency offset value to obtain a phase interpolator control code sequence without frequency offset; Fast Fourier transform and statistical distribution swing processing are performed on the frequency-bias-free phase interpolator control code sequence to obtain the jitter threshold value.

5. The method according to claim 3, characterized in that Obtaining the total period jitter compensation value based on the tracking phase value and the period jitter amplitude compensation value includes: Obtaining a phase detection result adjustment value based on the phase detection result and the tracking phase value; Tracking the phase deviation value of the phase detection result adjustment value; Tracking the frequency deviation value of the phase detection result adjustment value; The tracking phase value is obtained based on the phase deviation value, the frequency deviation value, and the period jitter frequency compensation value, and the period jitter total compensation value is obtained based on the tracking phase value and the period jitter amplitude compensation value.

6. The method according to claim 5, characterized in that After obtaining the tracking phase value based on the phase deviation value, the frequency deviation value, and the periodic jitter frequency compensation value, the method further includes: Performing phase normalization based on the tracking phase value to obtain an initial value for radian iteration; Iterating the sine iteration initial value, the cosine iteration initial value, and the radian iteration initial value in parallel step by step to obtain the sine iteration final value and the cosine iteration final value; The total period jitter compensation value is obtained based on the period jitter amplitude compensation value, the sine iteration final value, or the cosine iteration final value.

7. The method according to claim 6, characterized in that Iterating the sine iteration initial value, the cosine iteration initial value, and the radian iteration initial value in parallel step by step to obtain the sine iteration final value and the cosine iteration final value, including: Performing fitting iteration on the radian iteration initial value to obtain a radian fitting result; The sine iteration initial value and the cosine iteration initial value are iterated in parallel step by step in combination with the radian iteration initial value to obtain the sine iteration final value and the cosine iteration final value; wherein the sine iteration value and cosine iteration value obtained at each level of iteration are based on the radian iteration value, sine iteration value, and cosine iteration value of the previous level.

8. The method according to claim 7, characterized in that Also includes: When the period jitter total compensation value is obtained based on the period jitter amplitude compensation value and the sine iteration final value, determining whether the iterative process has converged based on the cosine iteration final value; Alternatively, when the total period jitter compensation value is obtained based on the period jitter amplitude compensation value and the cosine iteration final value, convergence of the iterative process is determined based on the sine iteration final value; Alternatively, the convergence of the iterative process is determined based on the arc fitting result.

9. A compensation device for a clock data recovery device, characterized in that: include: A firmware calculation module, used for obtaining a jitter threshold value based on a phase interpolator control code and a frequency offset value; A hardware real-time tracking module is used to obtain a total period jitter compensation value based on a phase detection result and the jitter domain value; and, sending the total period jitter compensation value to a clock data recovery device, so that the clock data recovery device adjusts the phase interpolator control code based on the total period jitter compensation value; The phase interpolator control code, the frequency deviation value, and the phase detection result are sent by the clock data recovery device.

10. The device according to claim 9, characterized in that The firmware operation module is further configured to decompose the jitter domain value into a period jitter frequency compensation value and a period jitter amplitude compensation value, so that the hardware real-time tracking module obtains the total period jitter compensation value based on the phase detection result, the period jitter frequency compensation value, and the period jitter amplitude compensation value.

11. The device according to claim 10, characterized in that The hardware real-time tracking module includes: A phase tracking submodule, configured to obtain a tracking phase value based on the periodic jitter frequency compensation value and the phase detection result; The sine and cosine value calculation submodule is used to obtain the total period jitter compensation value based on the tracking phase value and the period jitter amplitude compensation value.

12. The device according to claim 9, characterized in that The firmware operation module is further used to: eliminate the frequency deviation for the interpolator control code based on the frequency deviation value to obtain a phase interpolator control code sequence without frequency deviation; and perform fast Fourier transform and statistical distribution swing processing on the phase interpolator control code sequence without frequency deviation to obtain the jitter domain value.

13. The device according to claim 11, characterized in that The phase tracking submodule includes: A phase range adjustment unit, configured to obtain a phase detection result adjustment value based on the phase detection result and the tracking phase value; A proportional path unit, configured to track a phase deviation value of the phase detection result adjustment value; An integral path unit, configured to track a frequency deviation value of the phase detection result adjustment value; The first compensation quantization unit is used to obtain the tracking phase value based on the phase deviation value, the frequency deviation value, and the periodic jitter frequency compensation value, and send the tracking phase value to the phase range adjustment unit and the sine and cosine value calculation submodule.

14. The device according to claim 11, characterized in that The sine and cosine value calculation submodule includes: A phase normalization unit, configured to perform phase normalization based on the tracking phase value to obtain an initial value for radian iteration; A cascade lookup table unit is used to iterate the sine iteration initial value, the cosine iteration initial value, and the radian iteration initial value in parallel step by step to obtain the sine iteration final value and the cosine iteration final value; The second compensation quantization unit is configured to obtain the total period jitter compensation value based on the period jitter amplitude compensation value, the sine iteration final value, or the cosine iteration final value.

15. The device according to claim 14, characterized in that The cascade lookup table unit includes: The radian iteration lookup table subunit is used to perform fitting iteration on the radian iteration initial value to obtain a radian fitting result; The sine and cosine iteration lookup table sub-unit is used to perform parallel iteration on the sine iteration initial value and the cosine iteration initial value in combination with the radian iteration initial value to obtain the sine iteration final value and the cosine iteration final value; wherein the sine iteration value and cosine iteration value obtained at each iteration level are based on the radian iteration value, sine iteration value, and cosine iteration value of the previous level.

16. The device according to claim 15, characterized in that The sine and cosine value calculation submodule is also used for: When the period jitter total compensation value is obtained based on the period jitter amplitude compensation value and the sine iteration final value, determining whether the iterative process has converged based on the cosine iteration final value; Alternatively, when the total period jitter compensation value is obtained based on the period jitter amplitude compensation value and the cosine iteration final value, convergence of the iterative process is determined based on the sine iteration final value; Alternatively, the convergence of the iterative process is determined based on the arc fitting result.

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