ADC circuitry

Abstract

The invention discloses an ADC circuit system, and belongs to the field of electronic circuits. In order to solve the current efficiency problem and the nonlinear deviation calibration problem during wide-range driving, the ADC circuit system is composed of a first multiplexer, a second multiplexer, a first comparator, a second comparator, an input buffer, an ADC and an adder. The first multiplexer selects one path of input signal, and after processing, the input of the input buffer is a differential signal. And the ADC original code value and the output of the second multiplexer pass through an adder to obtain a final effective output code. The output of the first multiplexer is used as the input of the two comparators, the threshold value of the first comparator is higher than the threshold value of the NMOS tube by a first margin, the threshold value of the second comparator is lower than the threshold value of the VDD minus the threshold value of the PMOS tube by a second margin, and control signals are respectively output. And according to the input signal interval of the input buffer and the control signal logic operation, the three working states of the input buffer are controlled, and the second multiplexer selects one of the three deviation calibration codes for output. The method is applied to the ADC field and has higher quantization precision.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to an ADC circuit system. Background Art

[0002] The analog-to-digital converter (ADC) is the core interface circuit connecting analog signals and digital systems. Its core function is to convert continuously changing analog signals into discrete digital signals, thereby enabling the digital system to process, store and transmit analog signals.

[0003] In complex electronic systems such as systems-on-chip (SoCs), power management systems, the Industrial Internet of Things (IIoT), and wireless sensor networks, ADCs typically use time-division multiplexing (TD-SDM) to cyclically sample voltage signals from multiple input channels. However, switching noise generated during the ADC quantization process can interfere with the input signal, causing signal instability at the sampling moment. To ensure input signal stability at the sampling moment, the front-end input signal must have sufficient drive capability. Failure to do so will not only introduce quantization errors that affect ADC output accuracy, but may also cause reverse interference to the preceding signal generation circuitry.

[0004] Therefore, configuring an ADC buffer at the front end of the ADC has become a mainstream design solution. The typical ADC circuit system architecture in the prior art is as follows: Figure 1 As shown in the figure, it includes a multiplexer (MUX), an ADC buffer, an ADC, and an adder. The input of the ADC is ADC_IN, the input of the ADC buffer is BUFFERIN, and the input of the MUX is multiple input signals TEST. <1> 、TEST <2> 、......、TEST <n>, N is a positive integer.

[0005] In addition, due to the influence of process deviation and circuit noise, the raw code value ADC_RAWDATA output by the ADC needs to be corrected by the deviation calibration code ADC_OS to obtain the final valid output code ADC_OUTDATA.

[0006] In measurement ADC applications, the input channel voltage range typically spans a wide dynamic range, from near the common ground voltage (Voltage Source-to-Source, VSS) to the device operating voltage (Voltage Drain-to-Drain, VDD). This requires the input buffer to not only be able to drive an ultra-wide input voltage range but also maintain high linearity across the full range. Traditional Class AB input buffers are a common choice in this scenario due to their combination of low quiescent power consumption and wide output swing. Figure 2 Shows the circuit diagram of a traditional Class AB input buffer.

[0007] However, the existing Class AB input buffer architecture has the following drawbacks:

[0008] (1) Problem of limited signal dynamic range: When the input signal is close to VSS, the N-channel Metal Oxide Semiconductor (NMOS) input pair MN1 and MN2 cannot be turned on due to insufficient gate-source voltage. At this time, the PMOS transistors MP3 and MP4 in the pull-up current branch do not undergo dynamic bias adjustment, resulting in a sudden drop in branch current and a dramatic change in input impedance, which increases the design difficulty of the sampling and holding circuit of the subsequent ADC. When the input signal is close to VDD, the P-channel Metal Oxide Semiconductor (PMOS) input pair MP1 and MP2 are also cut off due to insufficient gate-source voltage, and the NMOS transistors MN3 and MN4 in the pull-down current branch do not undergo adaptive adjustment, resulting in the inability to effectively recover the static current, causing unnecessary power consumption.

[0009] (2) Deviation calibration accuracy defects: Due to the difference in threshold voltage between NMOS and PMOS transistors, the deviation introduced by different input voltage ranges has significant nonlinear characteristics. The existing calibration scheme uses a unified deviation calibration code ADC_OS to calibrate the full-scale signal. When the input signal is near VSS, mid-level, and near VDD, the calibration residual will accumulate with the input signal changes, eventually leading to systematic deviations in the output results of the ADC circuit system, affecting the accuracy indicators of the measurement ADC circuit system.

[0010] The above-mentioned problems have led to increasingly prominent performance bottlenecks in traditional Class AB input buffers in wide dynamic range and high-precision measurement scenarios. It is urgent to solve the current efficiency problems and nonlinear deviation calibration problems during wide-range driving through circuit architecture innovation and calibration optimization to meet the design requirements of the next generation of high-precision ADC circuit systems. Summary of the Invention

[0011] In order to alleviate or partially alleviate the above technical problems, the solutions of the present invention are as follows:

[0012] An ADC circuit system, the ADC circuit system comprising a first multiplexer, a second multiplexer, a first comparator, a second comparator, an input buffer, an ADC, and an adder;

[0013] Selecting one input signal from a plurality of input signals as an output signal of the first multiplexer through a first multiplexer, obtaining an input signal of an input buffer according to the output signal of the first multiplexer, wherein the input signal of the input buffer is a differential signal;

[0014] The original code value output by the ADC and the output signal of the second multiplexer are added together by an adder to obtain the final effective output code of the ADC circuit system; and

[0015] The output signal of the first multiplexer serves as an input signal of the first comparator and the second comparator at the same time, wherein the comparison threshold voltage of the first comparator is higher than the threshold voltage of the NMOS transistor by a first margin, and the comparison threshold voltage of the second comparator is lower than the threshold voltage of the PMOS transistor by a second margin compared to VDD minus the threshold voltage of the PMOS transistor. The first comparator outputs a first control signal, and the second comparator outputs a second control signal.

[0016] When the size of the input signal of the input buffer is within three different ranges, the input buffer is controlled to operate in three different states according to the results of the logical operations performed by the first control signal and the second control signal, and the second multiplexer is controlled to select one of the three different deviation calibration codes as the output signal of the second multiplexer.

[0017] Furthermore, the three different ranges are specifically:

[0018] (a) First interval: less than VCOMP1;

[0019] (b) Second interval: less than VCOMP2 and greater than VCOMP1;

[0020] (c) The third interval: greater than VCOMP2; wherein,

[0021] The VCOMP1 is higher than the threshold voltage of the NMOS transistor by a first margin, and the VCOMP2 is lower than VDD minus the threshold voltage of the PMOS transistor by a second margin.

[0022] Furthermore, the first margin and the second margin are equal and range from 50mV to 200mV.

[0023] Furthermore, the circuit of the input buffer is composed of elements having the following connection relationship:

[0024] PMOS transistor MP0: The gate is connected to the control voltage VG_MP0, the source is connected to VDD, and the drain is connected to the source of PMOS transistor MP1 and the source of PMOS transistor MP2;

[0025] PMOS transistor MP1: The gate is connected to the input signal INP, the source is connected to the drain of the PMOS transistor MP0, and the drain is connected to the drain of the NMOS transistor MN1;

[0026] PMOS transistor MP2: The gate is connected to the input signal INN, the source is connected to the drain of the PMOS transistor MP0, and the drain is connected to the source of the NMOS transistor MN5;

[0027] PMOS transistors MP30 and MP31: their sources are connected to VDD, their drains are connected to the source of PMOS transistor MP5, the gate of PMOS transistor MP31 is connected to the control voltage VG_MP31, and the gate of PMOS transistor MP30 is connected to the control voltage VBP0 derived from the drain of PMOS transistor MP5;

[0028] PMOS transistors MP40 and MP41: their sources are both connected to VDD, their drains are both connected to the drain of NMOS transistor MN1, the gate of PMOS transistor MP40 is connected to the control voltage VBP0, and the gate of PMOS transistor MP41 is connected to the gate of PMOS transistor MP31;

[0029] PMOS transistor MP5: the source is connected to the drain of the PMOS transistor MP30, the drain is connected to the drain of the NMOS transistor MN5, and the gate is connected to the first bias voltage;

[0030] PMOS transistor MP6: the source is connected to the drain of PMOS transistor MP40, the drain is connected to the source of PMOS transistor MP10, and the gate is connected to the first bias voltage;

[0031] PMOS tube MP7: the source is connected to VDD, and the drain and gate are connected to the source of PMOS tube MP8;

[0032] PMOS transistor MP8: the source is connected to the drain of the PMOS transistor MP7, the gate and drain are commonly connected to the positive terminal of the second current source CS2, and the positive terminal of the second current source CS2 outputs the control voltage VBPC;

[0033] PMOS tube MP9: The source is connected to VDD, the gate is connected to the drain of PMOS tube MP6, and the drain is directly connected to the output terminal OUT;

[0034] PMOS transistor MP10: The gate is connected to the control voltage VBPC, the source is connected to the drain of the PMOS transistor MP6, and the drain is connected to the source of the NMOS transistor MN10;

[0035] NMOS transistor MN0: The gate is connected to the control voltage VG_MN0, the source is connected to VSS, and the drain is connected to the source of NMOS transistor MN1;

[0036] NMOS transistor MN1: The gate is connected to the input signal INP, the source is connected to the source of NMOS transistor MN2, and the drain is connected to the drain of PMOS transistor MP40;

[0037] NMOS transistor MN2: The gate is connected to the input signal INN, the source is connected to the source of the NMOS transistor MN1, and the drain is connected to the source of the PMOS transistor MP5;

[0038] NMOS transistors MN31 and MN30: their sources are both connected to VSS, their drains are both connected to the source of NMOS transistor MN5, the gate of NMOS transistor MN30 is connected to the control voltage VBN1, and the gate of NMOS transistor MN31 is connected to the control voltage VG_MN31;

[0039] NMOS transistors MN41 and MN40: their sources are both connected to VSS, their drains are both connected to the source of NMOS transistor MN6, the gate of NMOS transistor MN40 is connected to the control voltage VBN1, and the gate of NMOS transistor MN40 is connected to NMOS transistor MN31;

[0040] NMOS transistor MN5: the source is connected to the drain of NMOS transistor MN30, the drain is connected to the drain of PMOS transistor MP5, and the gate is connected to the second bias voltage;

[0041] NMOS transistor MN6: the source is connected to the drain of MN40, the drain is connected to the drain of PMOS transistor MN10, and the gate is connected to the second bias voltage;

[0042] NMOS transistor MN7: the gate and drain are commonly connected to the negative electrode of the first current source CS1, and the source is connected to the drain of the NMOS transistor MN8;

[0043] NMOS transistor MN8: The source is connected to VSS, and the gate and drain are connected to the source of NMOS transistor MN7;

[0044] NMOS transistor MN9: The source is connected to VSS, the gate is connected to the source of NMOS transistor MN10, and the drain is directly connected to the output terminal OUT;

[0045] NMOS transistor MN10: the gate is connected to the control voltage VBNC, the source is connected to the drain of the NMOS transistor MN6, and the drain is connected to the drain of the PMOS transistor MP6;

[0046] The first current source CS1 has its positive electrode connected to VDD and its negative electrode connected to the drain of the NMOS transistor MN7 and outputs a control voltage VBNC.

[0047] The second current source CS2 has a negative electrode connected to VSS, an anode connected to the drain of the PMOS transistor MP8 and draws out a control voltage VBPC.

[0048] Furthermore, the first bias voltage is VDD minus 2 times the threshold voltage of the PMOS transistor.

[0049] Furthermore, the second bias voltage is twice the threshold voltage of the NMOS transistor.

[0050] Furthermore, when the magnitude of the input signal of the input buffer is within the first interval:

[0051] The control voltage VG_MN0 is equal to VSS;

[0052] The control voltage VG_MP0 is equal to VBP0;

[0053] The control voltage VG_MP31 is equal to VDD;

[0054] The control voltage VG_MN31 is equal to VBN1 .

[0055] Furthermore, when the magnitude of the input signal of the input buffer is within the second interval:

[0056] The control voltage VG_MN0 is equal to VBN1;

[0057] The control voltage VG_MP0 is equal to VBP0.

[0058] Furthermore, when the magnitude of the input signal of the input buffer is within the third interval:

[0059] The control voltage VG_MN0 is equal to VBN1;

[0060] The control voltage VG_MP0 is equal to VDD;

[0061] The control voltage VG_MP31 is equal to VBP0;

[0062] The control voltage VG_MN31 is equal to VSS.

[0063] Furthermore, the control voltage VBN1 is equal to the threshold voltage of the PMOS transistor plus a value ranging from 50 mV to 200 mV.

[0064] The technical solution of the present invention has one or more of the following beneficial technical effects:

[0065] (1) The present invention divides the input signal of the input buffer in the ADC circuit system into three segments. Each segment corresponds to a different input buffer circuit structure and three deviation calibration codes. This scheme performs targeted calibration based on the different characteristics of the three stages of the input signal, thereby improving the ADC quantization accuracy.

[0066] (2) It avoids unnecessary energy waste in the existing technology and improves current or energy efficiency.

[0067] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1 This is a typical ADC circuit system architecture diagram in the prior art;

[0069] Figure 2 This is the circuit diagram of a traditional Class AB input buffer;

[0070] Figure 3 is a diagram of the ADC circuit system architecture of the present invention;

[0071] Figure 4 1 is a circuit diagram of an input buffer of the present invention. DETAILED DESCRIPTION

[0072] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0073] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish between identical or similar items having substantially the same functions and effects. Those skilled in the art will appreciate that the terms "first" and "second" do not limit the quantity or order of execution.

[0074] Figure 3 The first multiplexer MUX1 receives the multi-channel input signal TEST. <1> 、TEST <2> 、......、TEST <n>, where N is a positive integer. The input signal is the signal to be quantized by the ADC in the subsequent stage. The first multiplexer MUX1 can select which input signal to quantize. The input signal BUFFER_IN of the input buffer is obtained based on the output signal of the first multiplexer MUX1.

[0075] On the other hand, the input signal BUFFER_IN of the input buffer also serves as the input signal of the first comparator COMP1 and the input signal of the second comparator COMP2.

[0076] The first control signal CTL1 output by the first comparator COMP1 and the second control signal CLT2 output by the second comparator COMP2 are both used as inputs of the input buffer and as channel selection signals of the second multiplexer MUX2.

[0077] In the present invention, the first control signal CTL1 and the second control signal CLT2 can be used to control three different stages of the input buffer described below after undergoing logic operations.

[0078] The input buffer's output signal ADC_IN serves as the ADC input signal. The original code value output by the ADC serves as the first input signal of the adder, and the output signal of the second multiplexer serves as the second input signal of the adder. After the adder adds the first and second input signals, it outputs the final valid output code ADC_OUTDATA of the ADC circuit system. The inputs to the second multiplexer MUX2 are the first, second, and third offset calibration codes OS1, OS2, and OS3, which can be stored in different memory spaces of the ADC circuit system's offset calibration register.

[0079] The comparison threshold voltage VCOMP1 connected to the first comparator COMP1 is higher than the threshold voltage of the NMOS transistor by a first margin. The comparison threshold voltage VCOMP2 connected to the second comparator COMP2 is lower than VDD minus the threshold voltage of the PMOS transistor by a second margin. Both the first margin and the second margin are any reasonable positive integers close to 0, such as 100mV. In other words, VCOMP1 is slightly higher than the threshold voltage of the NMOS transistor, and VCOMP2 is slightly lower than VDD minus the threshold voltage of the PMOS transistor.

[0080] Optionally, the first margin and the second margin are equal, and are between 50 mV and 200 mV, and are illustratively both 100 mV.

[0081] Furthermore, both the first comparator COMP1 and the second comparator COMP2 are hysteresis comparators.

[0082] Through the above design, the input signal BUFFER_IN of the input buffer of the present invention is divided into three sections:

[0083] (a) First interval: less than VCOMP1; (b) Second interval: less than VCOMP2 and greater than VCOMP1; (c) Third interval: greater than VCOMP2.

[0084] In the present invention, the input signal BUFFER_IN of the input buffer within the three ranges will turn on different MOS tubes in the input buffer, and correspondingly, the deviation calibration code input to the second multiplexer MUX2 is also different, which can be selected by the first control signal CTL1 and the second control signal CTL2 output by the first comparator COMP1 and the second comparator COMP2 respectively.

[0085] The input buffer in the present invention is applied to an ADC circuit system and can be regarded as an ADC buffer.

[0086] Figure 4 Next, the specific operation of how the input signals BUFFER_IN of three different input buffers trigger different MOS transistors in the output buffer circuit will be described.

[0087] The input buffer circuit of the present invention includes the following circuit components and their connection relationships:

[0088] For PMOS type MOS tubes in the circuit:

[0089] PMOS transistor MP0: the gate is connected to the control voltage VG_MP0, the source is connected to VDD, and the drain is connected to the source of the PMOS transistor MP1 and the source of the PMOS transistor MP2.

[0090] PMOS transistor MP1: the gate is connected to the input signal INP, the source is connected to the drain of the PMOS transistor MP0, and the drain is connected to the drain of the NMOS transistor MN1.

[0091] PMOS transistor MP2: the gate is connected to the input signal INN, the source is connected to the drain of the PMOS transistor MP0, and the drain is connected to the source of the NMOS transistor MN5.

[0092] PMOS transistors MP30 and MP31: their sources are both connected to VDD, their drains are both connected to the source of PMOS transistor MP5, the gate of PMOS transistor MP31 is connected to the control voltage VG_MP31, and the gate of PMOS transistor MP30 is connected to the control voltage VBP0 derived from the drain of PMOS transistor MP5.

[0093] PMOS transistor MP40 and PMOS transistor MP41: the source is connected to VDD, the drain is connected to the drain of NMOS transistor MN1, the gate of PMOS transistor MP40 is connected to control voltage VBP0, and the gate of PMOS transistor MP41 is connected to the gate of PMOS transistor MP31.

[0094] PMOS transistor MP5: the source is connected to the drain of PMOS transistor MP30, the drain is connected to the drain of NMOS transistor MN5, and the gate is connected to a first bias voltage, for example, VDD minus twice the threshold voltage of the PMOS transistor.

[0095] PMOS transistor MP6: the source is connected to the drain of PMOS transistor MP40, the drain is connected to the source of PMOS transistor MP10, and the gate is connected to a first bias voltage, for example, VDD minus twice the threshold voltage of the PMOS transistor.

[0096] PMOS transistor MP7: the source is connected to VDD, and the drain and the gate are connected to the source of PMOS transistor MP8.

[0097] PMOS transistor MP8: the source is connected to the drain of PMOS transistor MP7, and the gate and the drain are connected to the positive terminal of second current source CS2, and the positive terminal of second current source CS2 outputs control voltage VBPC.

[0098] PMOS transistor MP9: the source is connected to VDD, the gate is connected to the drain of PMOS transistor MP6, and the drain is directly connected to the output terminal OUT.

[0099] PMOS transistor MP10: the gate is connected to control voltage VBPC, the source is connected to the drain of PMOS transistor MP6, and the drain is connected to the source of NMOS transistor MN10.

[0100] For NMOS type MOS transistors in the circuit:

[0101] NMOS transistor MN0: the gate is connected to control voltage VG_MN0, the source is connected to VSS, and the drain is connected to the source of NMOS transistor MN1.

[0102] NMOS transistor MN1: the gate is connected to input signal INP, the source is connected to the source of NMOS transistor MN2, and the drain is connected to the drain of PMOS transistor MP40.

[0103] NMOS transistor MN2: the gate is connected to input signal INN, the source is connected to the source of NMOS transistor MN1, and the drain is connected to the source of PMOS transistor MP5.

[0104] NMOS transistors MN31 and MN30: sources are both connected to VSS, drains are both connected to the source of NMOS transistor MN5, the gate of NMOS transistor MN30 is connected to control voltage VBN1, and the gate of NMOS transistor MN31 is connected to control voltage VG_MN31.

[0105] NMOS transistors MN41 and MN40: their sources are both connected to VSS, their drains are both connected to the source of NMOS transistor MN6, their gate is connected to control voltage VBN1, and their gate is connected to NMOS transistor MN31.

[0106] NMOS transistor MN5: the source is connected to the drain of NMOS transistor MN30, the drain is connected to the drain of PMOS transistor MP5, and the gate is connected to the second bias voltage. For example, the second bias voltage is twice the threshold voltage of the NMOS transistor.

[0107] NMOS transistor MN6: the source is connected to the drain of MN40, the drain is connected to the drain of PMOS transistor MN10, and the gate is connected to the second bias voltage. For example, the second bias voltage is twice the threshold voltage of the NMOS transistor.

[0108] NMOS transistor MN7: the gate and drain are commonly connected to the negative electrode of the first current source CS1, and the source is connected to the drain of the NMOS transistor MN8.

[0109] NMOS transistor MN8: the source is connected to VSS, and the gate and drain are commonly connected to the source of NMOS transistor MN7.

[0110] NMOS transistor MN9: the source is connected to VSS, the gate is connected to the source of NMOS transistor MN10, and the drain is directly connected to the output terminal OUT.

[0111] NMOS transistor MN10: the gate is connected to the control voltage VBNC, the source is connected to the drain of the NMOS transistor MN6, and the drain is connected to the drain of the PMOS transistor MP6.

[0112] The first current source CS1 has a positive electrode connected to VDD, a negative electrode connected to the drain of the NMOS transistor MN7 and draws out a control voltage VBNC.

[0113] The second current source CS2 has a negative electrode connected to VSS, an anode connected to the drain of the PMOS transistor MP8 and draws out a control voltage VBPC.

[0114] The output terminal OUT of the input buffer of the present invention is connected to the drain of the PMOS transistor MP9 and the drain of the NMOS transistor MN9.

[0115] In the present invention, the input signal INN and the input signal INP are differential signals of the input signal BUFFER_IN of the input buffer.

[0116] Optionally, the signal output from the first multiplexer may be subjected to differential conversion (such as a differential driver) to obtain a differential input signal BUFFER_IN of the input buffer.

[0117] When the magnitude of the input signal of the input buffer (or the output signal of the first multiplexer) is within three different ranges, the input buffer is controlled to operate in three different states according to the results of the logic operation performed by the first control signal and the second control signal. In the three different states or stages, the input buffer performs the following actions:

[0118] (a) When the input signal BUFFER_IN of the input buffer is in the first interval: NMOS transistors MN1 and MN2 cannot be turned on, and the control voltage VG_MN0 of the gate of NMOS transistor MN0 is VSS. PMOS transistors MP1 and MP2 are turned on normally, and the control voltage VG_MP0 of the gate of PMOS transistor MP0 is VBP0.

[0119] Compared with the PMOS transistor MP3 and PMOS transistor MP4 in the prior art, the present invention is divided into two parts: one part (PMOS transistor MP30 and PMOS transistor MP40) is connected in the same way as the traditional method, and the control voltage VG_MP31 of the gate of the other part (PMOS transistor MP31 and PMOS transistor MP41) is VDD at this time.

[0120] Compared with the NMOS transistor MN3 and NMOS transistor MN4 in the prior art, the present invention also splits them into two parts: one part (NMOS transistor MN30 and NMOS transistor MN40) is connected in the same way as the traditional method, and the control voltage VG_MN31 of the gate of the other part (NMOS transistor MN31 and NMOS transistor MN41) is now VBN1.

[0121] (b) When the input signal BUFFER_IN of the input buffer is in the second interval: the NMOS transistors MN1 and MN2 and the PMOS transistors MP1 and MP2 can all be turned on, the control voltage VG_MN0 of the gate of the NMOS transistor MN0 is VBN1, and the control voltage VG_MP0 of the gate of the PMOS transistor MP0 is VBP0.

[0122] Compared with the PMOS transistor MP3 and the PMOS transistor MP4 in the prior art, the above two parts of the present invention are consistent with the traditional connection method.

[0123] Compared with the NMOS transistor MN3 and the NMOS transistor MN4 in the prior art, the above two parts of the present invention are consistent with the traditional connection method.

[0124] (c) When the input signal BUFFER_IN of the input buffer is in the third interval: the NMOS transistors MN1 and MN2 are turned on, and the control voltage VG_MN0 of the gate of the NMOS transistor MN0 is connected to VBN1; the PMOS transistors MP1 and MP2 cannot be turned on, and the control voltage VG_MP0 of the gate of the PMOS transistor MP0 is VDD.

[0125] Compared with the PMOS transistor MP3 and PMOS transistor MP4 in the prior art, the present invention is divided into two parts: one part (PMOS transistor MP30 and PMOS transistor MP40) is connected in accordance with the traditional method, and the control voltage VG_MP31 of the gate of the other part (PMOS transistor MP31 and PMOS transistor MP41) is VBP0 at this time.

[0126] Compared with the NMOS transistor MN3 and NMOS transistor MN4 in the prior art, the present invention is divided into two parts: one part (NMOS transistor MN30 and NMOS transistor MN40) is connected in the same way as the traditional method, and the control voltage VG_MN31 of the gate of the other part (NMOS transistor MN31 and NMOS transistor MN41) is VSS at this time.

[0127] In the present invention, the NMOS transistor MN1 and the NMOS transistor MN2, as well as the PMOS transistor MP1 and the PMOS transistor MP2 are all input pair transistors.

[0128] In the present invention, the control voltage VBPC and the control voltage VBNC are both generated within the circuit of the input buffer, rather than being externally applied voltages.

[0129] Table 1: Input buffer internal state relationship table of the present invention

[0130] First stage Second stage Third stage MN1, MN2 Off On On VG_MN0 VSS VBN1 VBN1 MP1, MP2 On On Off VG_MP0 VBP0 VBP0 VDD MP30+MP40 Conventional connection Conventional connection Conventional connection MP31+MP41 VG_MP31=VDD Conventional connection VG_MP31=VBP0 MN30+MN40 Conventional connection Conventional connection Conventional connection MN31+MN41 VG_MN31=VBN1 Conventional connection VG_MN31=VSS

[0131] Among them, the first control signal CTL1 and the second control signal CLT2 output by the first comparator COMP1 and the second comparator COMP2 respectively can control the gate voltage VG_MP0, VG_MN0 and the PMOS transistor according to the combination shown in Table 1 after logical operation.

[0132] The gate voltage of transistors MP31, MP41, and NMOS transistors MN31, MN41.

[0133] In the present invention, the control voltage VBP0 is input from the internal node of the buffer.

[0134] It is generated by the drain of the PMOS transistor MP5. For example, the value of VPB0 used as the bias voltage may be equal to VDD-the threshold voltage of the PMOS transistor-100 mV.

[0135] Furthermore, the control voltage VBN1 is a bias voltage, which may be equal to the threshold voltage of the PMOS transistor plus a value in the range of 50 mV to 200 mV. As an example, it may be equal to the threshold voltage of the PMOS transistor + 100 mV.

[0136] To better illustrate the present invention, numerous specific details are provided in the detailed description above. Those skilled in the art will appreciate that the present invention can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main purpose of the present invention.

[0137] 340 The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited to

[0138] Without being limited thereto, any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention.

[0139] Therefore, the protection scope of the present invention should be based on the protection scope of the claims.< / n> < / n>

Claims

1. An ADC circuit system, characterized in that: The ADC circuit system includes a first multiplexer, a second multiplexer, a first comparator, a second comparator, an input buffer, an ADC, and an adder; Selecting one input signal from a plurality of input signals as an output signal of the first multiplexer through a first multiplexer, obtaining an input signal of an input buffer according to the output signal of the first multiplexer, wherein the input signal of the input buffer is a differential signal; The original code value output by the ADC and the output signal of the second multiplexer are added together by an adder to obtain the final effective output code of the ADC circuit system; and The output signal of the first multiplexer serves as an input signal of the first comparator and the second comparator at the same time, wherein the comparison threshold voltage of the first comparator is higher than the threshold voltage of the NMOS transistor by a first margin, and the comparison threshold voltage of the second comparator is lower than the threshold voltage of the PMOS transistor by a second margin compared to VDD minus the threshold voltage of the PMOS transistor. The first comparator outputs a first control signal, and the second comparator outputs a second control signal. When the size of the input signal of the input buffer is within three different ranges, the input buffer is controlled to operate in three different states according to the results of the logical operations performed by the first control signal and the second control signal, and the second multiplexer is controlled to select one of the three different deviation calibration codes as the output signal of the second multiplexer.

2. The ADC circuit system according to claim 1, wherein: The three different ranges are specifically: (a) First interval: less than VCOMP1; (b) Second interval: less than VCOMP2 and greater than VCOMP1; (c) The third interval: greater than VCOMP2; wherein, The VCOMP1 is higher than the threshold voltage of the NMOS transistor by a first margin, and the VCOMP2 is lower than VDD minus the threshold voltage of the PMOS transistor by a second margin.

3. The ADC circuit system according to claim 2, wherein: The first margin and the second margin are equal and range from 50mV to 200mV.

4. The ADC circuit system according to claim 3, wherein: The circuit of the input buffer is composed of elements with the following connection relationship: PMOS transistor MP0: The gate is connected to the control voltage VG_MP0, the source is connected to VDD, and the drain is connected to the source of PMOS transistor MP1 and the source of PMOS transistor MP2; PMOS transistor MP1: The gate is connected to the input signal INP, the source is connected to the drain of the PMOS transistor MP0, and the drain is connected to the drain of the NMOS transistor MN1; PMOS transistor MP2: The gate is connected to the input signal INN, the source is connected to the drain of the PMOS transistor MP0, and the drain is connected to the source of the NMOS transistor MN5; PMOS transistors MP30 and MP31: their sources are connected to VDD, their drains are connected to the source of PMOS transistor MP5, the gate of PMOS transistor MP31 is connected to the control voltage VG_MP31, and the gate of PMOS transistor MP30 is connected to the control voltage VBP0 derived from the drain of PMOS transistor MP5; PMOS transistors MP40 and MP41: their sources are both connected to VDD, their drains are both connected to the drain of NMOS transistor MN1, the gate of PMOS transistor MP40 is connected to the control voltage VBP0, and the gate of PMOS transistor MP41 is connected to the gate of PMOS transistor MP31; PMOS transistor MP5: the source is connected to the drain of the PMOS transistor MP30, the drain is connected to the drain of the NMOS transistor MN5, and the gate is connected to the first bias voltage; PMOS transistor MP6: the source is connected to the drain of PMOS transistor MP40, the drain is connected to the source of PMOS transistor MP10, and the gate is connected to the first bias voltage; PMOS tube MP7: the source is connected to VDD, and the drain and gate are connected to the source of PMOS tube MP8; PMOS transistor MP8: the source is connected to the drain of the PMOS transistor MP7, the gate and drain are commonly connected to the positive terminal of the second current source CS2, and the positive terminal of the second current source CS2 outputs the control voltage VBPC; PMOS tube MP9: The source is connected to VDD, the gate is connected to the drain of PMOS tube MP6, and the drain is directly connected to the output terminal OUT; PMOS transistor MP10: The gate is connected to the control voltage VBPC, the source is connected to the drain of the PMOS transistor MP6, and the drain is connected to the source of the NMOS transistor MN10; NMOS transistor MN0: The gate is connected to the control voltage VG_MN0, the source is connected to VSS, and the drain is connected to the source of NMOS transistor MN1; NMOS transistor MN1: The gate is connected to the input signal INP, the source is connected to the source of NMOS transistor MN2, and the drain is connected to the drain of PMOS transistor MP40; NMOS transistor MN2: The gate is connected to the input signal INN, the source is connected to the source of the NMOS transistor MN1, and the drain is connected to the source of the PMOS transistor MP5; NMOS transistors MN31 and MN30: their sources are both connected to VSS, their drains are both connected to the source of NMOS transistor MN5, the gate of NMOS transistor MN30 is connected to the control voltage VBN1, and the gate of NMOS transistor MN31 is connected to the control voltage VG_MN31; NMOS transistors MN41 and MN40: their sources are both connected to VSS, their drains are both connected to the source of NMOS transistor MN6, the gate of NMOS transistor MN40 is connected to the control voltage VBN1, and the gate of NMOS transistor MN40 is connected to NMOS transistor MN31; NMOS transistor MN5: the source is connected to the drain of NMOS transistor MN30, the drain is connected to the drain of PMOS transistor MP5, and the gate is connected to the second bias voltage; NMOS transistor MN6: the source is connected to the drain of MN40, the drain is connected to the drain of PMOS transistor MN10, and the gate is connected to the second bias voltage; NMOS transistor MN7: the gate and drain are commonly connected to the negative electrode of the first current source CS1, and the source is connected to the drain of the NMOS transistor MN8; NMOS transistor MN8: The source is connected to VSS, and the gate and drain are connected to the source of NMOS transistor MN7; NMOS transistor MN9: The source is connected to VSS, the gate is connected to the source of NMOS transistor MN10, and the drain is directly connected to the output terminal OUT; NMOS transistor MN10: the gate is connected to the control voltage VBNC, the source is connected to the drain of the NMOS transistor MN6, and the drain is connected to the drain of the PMOS transistor MP6; The first current source CS1 has its positive electrode connected to VDD and its negative electrode connected to the drain of the NMOS transistor MN7 and outputs a control voltage VBNC. The second current source CS2 has a negative electrode connected to VSS, an anode connected to the drain of the PMOS transistor MP8 and draws out a control voltage VBPC.

5. The ADC circuit system according to claim 4, wherein: The first bias voltage is VDD minus 2 times the threshold voltage of the PMOS tube.

6. The ADC circuit system according to claim 5, wherein: The second bias voltage is twice the threshold voltage of the NMOS transistor.

7. The ADC circuit system according to claim 2, 4 or 6, wherein: When the magnitude of the input signal of the input buffer is within the first interval: The control voltage VG_MN0 is equal to VSS; The control voltage VG_MP0 is equal to VBP0; The control voltage VG_MP31 is equal to VDD; The control voltage VG_MN31 is equal to VBN1 .

8. The ADC circuit system according to claim 7, wherein: When the magnitude of the input signal of the input buffer is within the second interval: The control voltage VG_MN0 is equal to VBN1; The control voltage VG_MP0 is equal to VBP0.

9. The ADC circuit system according to claim 8, wherein: When the magnitude of the input signal of the input buffer is within the third interval: The control voltage VG_MN0 is equal to VBN1; The control voltage VG_MP0 is equal to VDD; The control voltage VG_MP31 is equal to VBP0; The control voltage VG_MN31 is equal to VSS.

10. The ADC circuit system according to claim 9, wherein: The control voltage VBN1 is equal to the threshold voltage of the PMOS tube plus a value in the range of 50mV to 200mV.

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