A phased array readout electronics platform and method

Abstract

The application relates to the technical field of readout electronics, and discloses a phased array system readout electronics platform and method, wherein the platform comprises: a radio frequency acquisition module configured to convert spatial electromagnetic waves into radio frequency acquisition signals; a digital receiving module comprising a time-frequency management unit and at least one signal processing unit, the time-frequency management unit is configured to send a clock output signal and a timing control pulse signal to each signal processing unit respectively, so that each signal processing unit synchronously analyzes the timing control pulse signal according to the clock output signal and performs coarse channel processing on the radio frequency acquisition signals to obtain multiple channel signals; and a backend readout module configured to generate astronomical observation data according to the channel signals. The application precisely controls the clock output signal and the timing control pulse signal to ensure the consistency and synchronization of the processing processes of the signal processing units, and simultaneously reduces the data processing pressure by means of coarse channelization processing, thereby effectively reducing the system power consumption.

Description

Technical Field

[0001] This application relates to the field of readout electronics technology, and in particular to a phased array-based readout electronics platform and method. Background Technology

[0002] A phased array system is a system that precisely controls the phase and amplitude of multiple antenna elements in an array. These antenna elements are arranged according to a specific pattern to form an array. By changing the phase and amplitude of the signals transmitted or received by each antenna element, the signals interfere with each other in space, achieving flexible beam pointing and precise focusing. Therefore, it plays an important role in readout electronics systems in the field of radio astronomy.

[0003] In related technologies, readout electronics systems obtain astronomical detection data by analyzing signals received by devices such as phased arrays. This process involves a large amount of signal and data processing work, resulting in low analysis efficiency and low readout accuracy. Summary of the Invention

[0004] This application provides a phased array readout electronics platform and method, which solves the technical problems of low resolution efficiency and low readout accuracy in phased array readout electronics systems. By precisely controlling the clock output signal and timing control pulse signal, the consistency and synchronization of the processing process of each signal processing unit are ensured. At the same time, coarse channelization processing is used to reduce the data processing pressure of the back-end readout module and facilitates further refined analysis of the specified sub-channel signals, effectively reducing system power consumption.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, embodiments of this application provide a phased array readout electronics platform, the platform comprising:

[0007] A radio frequency acquisition module, configured to acquire spatial electromagnetic waves and convert the spatial electromagnetic waves into radio frequency acquisition signals;

[0008] A digital receiving module is provided, which is adapted to receive the radio frequency acquisition signal. The digital receiving module includes a time-frequency management unit and at least one signal processing unit. The time-frequency management unit is configured to generate a clock output signal and a timing control pulse signal, and send the clock output signal and the timing control pulse signal to each of the signal processing units respectively, so that each of the signal processing units performs synchronous analysis on the timing control pulse signal according to the clock output signal, and performs coarse channel processing and framing on the radio frequency acquisition signal according to the analysis result to obtain multiple channel signals.

[0009] A back-end readout module is configured to generate astronomical observation data based on the channel signal.

[0010] The phased array readout electronics platform proposed in this application achieves effective acquisition and signal front-end processing of space electromagnetic waves through a radio frequency acquisition module, providing a foundation for subsequent processing. The collaborative operation of the time-frequency management unit and signal processing unit in the digital receiving module enables each signal processing unit to synchronously analyze the timing control pulse signal based on a unified clock output signal. Compared with related technologies, this not only improves the integration of the digital receiving module but also ensures the synchronization of coarse-channel processing of the radio frequency acquisition signal by each signal processing unit, allowing the back-end readout module to function normally and significantly improving the accuracy of astronomical observation data. Furthermore, this application utilizes coarse-channel processing of the radio frequency acquisition signal to reduce the data processing pressure on the back-end readout module and facilitates further refined analysis of specified sub-channel signals. This not only significantly improves the working efficiency of the phased array readout electronics platform but also effectively reduces system power consumption and lowers system operating costs.

[0011] Optionally, in some embodiments of this application, the time-frequency management unit includes a clock source and a frequency synthesis subunit;

[0012] The clock source is used to generate a reference clock signal;

[0013] The frequency synthesis subunit is used to generate multiple clock output signals based on the reference clock signal, wherein the number of clock output signals is greater than the number of signal processing units, and the multiple clock output signals are in phase and have the same frequency as the reference clock signal.

[0014] The frequency synthesis subunit generates multiple clock output signals with the same frequency and phase based on the reference clock signal, and the number of these signals is greater than that of the signal processing unit. This provides each signal processing unit with a sufficient and unified clock signal source, ensuring that each signal processing unit works under the same clock rhythm. This further improves the synchronization of coarse channel processing of RF acquisition signals and effectively avoids the problem of multi-channel signal delay or phase inconsistency caused by clock asynchrony.

[0015] Optionally, in some embodiments of this application, the frequency synthesis subunit includes a first frequency signal distributor and a second frequency signal distributor, the input terminals of the first frequency signal distributor and the second frequency signal distributor are respectively connected to the clock source, and the output terminals of the first frequency signal distributor and the second frequency signal distributor are connected to the clock input terminal of the corresponding signal processing unit;

[0016] The first frequency signal distributor and the second frequency signal distributor are used to generate a plurality of clock output signals according to the reference clock signal.

[0017] The first and second frequency signal distributors can generate multiple clock output signals with the same frequency and phase from a single reference clock signal, reserving space for system expansion and enhancing the system's scalability. This eliminates the need to redesign the clock generation module when additional signal processing units are required, reducing system upgrade costs and complexity, and greatly improving the reusability and applicability of the phased array readout electronics platform.

[0018] Optionally, in some embodiments of this application, the clock source is further used to generate a trigger signal, and the time-frequency management unit further includes a timing control subunit;

[0019] The timing control subunit is adapted to receive the trigger signal and the clock output signal, and in response to the trigger signal and the clock output signal, generate the timing control pulse signal according to the system preset control parameters, wherein the pulse width of the timing control pulse signal is matched with the system preset control parameters.

[0020] The timing control subunit generates timing control pulse signals by combining trigger signals and clock output signals. This enables the timing control pulse signals to accurately carry the relevant control information of the system's preset control parameters. According to different system requirements and application scenarios, the pulse width of the timing control pulse signals can be precisely adjusted. While ensuring the synchronization of the acquisition channels between signal processing units, it also realizes the multiplexing control of other functions such as inter-channel synchronization state triggering and logic reset, and phase signal acquisition. This better adapts to different observation tasks and data processing requirements, improves the flexibility and adaptability of the phased array readout electronics platform, and saves a lot of hardware circuit design costs.

[0021] Optionally, in some embodiments of this application, the timing control subunit includes a programmable logic processor;

[0022] The first input terminal of the programmable logic processor is adapted to receive the clock output signal, the second input terminal of the programmable logic processor is adapted to receive the trigger signal, and the output terminal of the programmable logic processor is connected to the corresponding signal processing unit to output the timing control pulse signal, wherein the output terminal of the programmable logic processor corresponds one-to-one with the signal processing unit.

[0023] Optionally, in some embodiments of this application, the signal processing unit is configured to parse the pulse width of the timing control pulse signal according to the clock output signal, and perform synchronous coarse channel processing on the radio frequency acquisition signal when the pulse width meets preset conditions.

[0024] By analyzing the pulse width of the timing control pulse signal, it is ensured that each signal processing unit performs signal acquisition and coarse channel processing under the same time reference, which greatly improves the synchronization between signal processing units, effectively improves the accuracy and reliability of signal processing, and enables the back-end readout module to accurately generate astronomical observation data.

[0025] Optionally, in some embodiments of this application, the signal processing unit is an integrated chip based on a Radio Frequency System on Chip (RFSoC). The integrated chip includes an analog-to-digital conversion subunit, which is configured to perform analog-to-digital conversion on the radio frequency acquisition signal in response to the clock output signal and the timing control pulse signal, and obtain the converted digital acquisition signal, so as to perform the coarse channel processing on the digital acquisition signal.

[0026] By employing an integrated chip based on RFSoC as the signal processing unit, its high integration reduces the complexity of connecting multiple independent chips, thereby lowering the difficulty and cost of hardware design. Furthermore, by performing coarse-channel processing on the digitally acquired signal, the signal data rate is significantly reduced, thus saving substantial hardware logic resources and improving processing efficiency.

[0027] Optionally, in some embodiments of this application, the integrated chip further includes a demodulation subunit, a filtering subunit, and a framing subunit;

[0028] The demodulation subunit is configured to perform quadrature demodulation on the digital acquisition signal and obtain the demodulated initial baseband signal;

[0029] The filtering subunit is configured to perform a decimation-by-two filter on the initial baseband signal to obtain the target baseband signal, and to perform synchronous coarse channel processing on the target baseband signal through polyphase filtering and fast Fourier transform to obtain multiple sub-channel signals.

[0030] The framing subunit is configured to frame the subchannel signals according to the computing power of the backend readout module to obtain the channel signals, and transmit the channel signals to the backend readout module via the UDP protocol.

[0031] Optionally, in some embodiments of this application, the radio frequency acquisition module includes an antenna array unit and a radio frequency front-end unit;

[0032] The antenna array unit includes multiple independent antennas, and the multiple antennas are arranged in a planar array to collect the spatial electromagnetic waves;

[0033] The radio frequency front-end unit is configured to sequentially perform low-noise amplification, analog filtering, and gain amplification on the spatial electromagnetic wave, so that the amplitude of the obtained radio frequency acquisition signal after processing is within a preset range.

[0034] Secondly, embodiments of this application provide a phased array readout electronics method, applied to the platform described in any of the above embodiments. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 This is one of the structural schematic diagrams of the phased array readout electronics platform proposed in the embodiments of this application;

[0037] Figure 2 This is the second schematic diagram of the phased array readout electronics platform proposed in the embodiments of this application;

[0038] Figure 3 This is a schematic diagram of the structure of the frequency synthesis subunit proposed in the embodiments of this application;

[0039] Figure 4 This is a schematic diagram of the signal timing of the digital receiving module proposed in the embodiments of this application;

[0040] Figure 5 This is a schematic diagram of the timing control subunit proposed in the embodiments of this application;

[0041] Figure 6 This is a schematic diagram of the signal flow of the timing control subunit proposed in the embodiments of this application;

[0042] Figure 7 This is a schematic diagram of the signal processing unit proposed in the embodiments of this application;

[0043] Figure 8 This is a schematic diagram of the integrated chip structure proposed in the embodiments of this application;

[0044] Figure 9 This is a schematic diagram of the structure of a computer device proposed in an embodiment of this application. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] A phased array system is a technology that precisely controls the phase and amplitude of multiple antenna elements arranged in a specific pattern. By altering the phase and amplitude of the transmitted or received signals from each antenna element, the signals interfere with each other in space, achieving flexible beam pointing and precise focusing. Compared to traditional mechanically scanned antenna elements, phased array systems can rapidly change beam pointing through electronic scanning, enabling observation of different sky regions in a short time. They can also simultaneously form multiple beams to observe multiple targets in parallel, offering extremely high observation flexibility. Furthermore, the field of view can be expanded using phased array feeds, and digital beamforming technology can achieve a wider observation field and faster observation speed. In terms of resolution, by precisely controlling the phase and amplitude of antenna elements and combining interferometry, higher resolution than single-aperture telescopes can be obtained, which is beneficial for studying the fine structure of celestial objects. In addition, phased array systems consist of multiple independent antenna elements, resulting in relatively low equipment construction and maintenance costs. The failure of a single antenna element does not affect the overall basic observation function. Therefore, phased array systems play a crucial role in readout electronics systems in radio astronomy.

[0047] The readout electronics system obtains astronomical detection data by analyzing signals received by devices such as phased arrays. In some application scenarios, a system architecture combining an independent analog-to-digital converter (ADC) with a field-programmable gate array (FPGA) on the acquisition board is typically adopted. Data transmission between the various acquisition channels of the acquisition board is realized through high-speed serial interface protocols such as J204B.

[0048] As the demands for sensitivity and resolution in radio astronomy observations continue to increase, the number of acquisition channels required for readout electronics systems based on phased array architectures is rising dramatically. However, in related technologies, on the one hand, limitations in semiconductor process technology mean that the synchronization between acquisition channels in the aforementioned data transmission schemes is determined by the quality of external clock and trigger signals. With the increase in the number of channels, the synchronization between acquisition channels becomes more susceptible to transmission delays and signal jitter, leading to decreased synchronization. On the other hand, the separate architecture of independent ADCs and FPGAs lengthens the signal transmission path, increasing the time delay differences between channels and making it difficult to guarantee high-precision signal synchronization. Therefore, related technologies suffer from low resolution and low readout accuracy, failing to meet the needs of high-precision astronomical observations.

[0049] To address the aforementioned issues, this specification provides a phased array readout electronics platform applicable to phased array systems. Phased array systems can be used in various fields, including radio astronomy, radar, ultrasonic imaging, and meteorological observation. In radio astronomy, phased array systems can be used to construct phased array radio telescopes, enabling high-speed, real-time, and synchronous acquisition and preprocessing of large-scale, wide-band radio frequency signals. It is understood that, with adaptive modifications, this application can also be used in other systems or devices for multi-channel signal acquisition, such as multi-channel data acquisition systems, high-frequency trading systems, or automated testing systems.

[0050] Figure 1 This is a schematic diagram of the phased array readout electronics platform according to an embodiment of this application, as shown below. Figure 1 As shown, the platform includes an RF acquisition module 100, a digital receiving module 200, and a back-end readout module 300.

[0051] The radio frequency (RF) acquisition module 100 is configured to acquire spatial electromagnetic waves and convert them into RF acquisition signals. Specifically, the RF acquisition module 100 needs to process the received spatial electromagnetic waves through a series of signal processing steps, such as signal amplification and filtering, to convert these weak spatial electromagnetic waves into RF acquisition signals with specific frequency ranges, amplitudes, and other parameters. This allows the subsequent digital receiving module 200 to effectively process the RF acquisition signals, thereby providing suitable input signals for the normal operation of the entire phased array readout electronics platform.

[0052] The digital receiving module 200 is suitable for receiving radio frequency acquisition signals, and includes a time and frequency management unit 210 and at least one signal processing unit 220. The time and frequency management unit 210 is configured to generate a clock output signal and a timing control pulse signal, and send the clock output signal and the timing control pulse signal to each signal processing unit 220 respectively, so that each signal processing unit 220 performs synchronous analysis on the timing control pulse signal according to the clock output signal, and performs coarse channel processing and framing on the radio frequency acquisition signal according to the analysis result to obtain multiple channel signals.

[0053] Specifically, the digital receiving module 200 generates a clock output signal Ex_Refclk through the time-frequency management unit 210 to provide a unified operating clock source for each signal processing unit 220. Furthermore, the time-frequency management unit 210 sends timing control pulse signals to the signal processing units 220. Each signal processing unit 220 performs synchronous analysis on the timing control pulse signals based on the clock output signals of the same frequency and phase. Each signal processing unit 220 includes multiple acquisition channels, enabling each signal processing unit 220 to perform one of the following operations based on the analysis results: inter-channel synchronization state triggering operation, logic reset operation, or phase acquisition operation. Specifically, when the analysis result triggers a channel acquisition operation, each signal processing unit 220 begins multi-channel acquisition and coarse-channel processing of the RF acquisition signal to obtain multiple sub-channel signals, and then frames these multiple sub-channel signals to obtain multiple channel signals.

[0054] The back-end readout module 300 is configured to generate astronomical observation data based on the channel signal. Specifically, the back-end readout module 300 receives the channel signal processed by the digital receiving module 200, performs subsequent digital beamforming, radio frequency interference cancellation, channel narrowing, and neutral hydrogen / fast radio burst (FRB) search, and finally outputs scientific astronomical observation data. This data includes important information such as the position, velocity, and radiation intensity of celestial objects, providing crucial data support for astronomical research.

[0055] Therefore, the phased array readout electronics platform provided in this embodiment achieves effective acquisition and signal front-end processing of space electromagnetic waves through the radio frequency acquisition module 100, providing a foundation for subsequent processing. The collaborative operation of the time-frequency management unit 210 and the signal processing unit 220 in the digital receiving module 200 enables each signal processing unit 220 to synchronously analyze the timing control pulse signal based on a unified clock output signal. Compared with related technologies, this not only improves the integration of the digital receiving module 200 but also ensures the synchronization of coarse-channel processing of the radio frequency acquisition signal by each signal processing unit 220, enabling the back-end readout module 300 to operate normally and greatly improving the accuracy of astronomical observation data. Furthermore, this application utilizes coarse-channel processing of the radio frequency acquisition signal to reduce the data processing pressure on the back-end readout module and facilitates further refined analysis of designated sub-channel signals. This not only significantly improves the working efficiency of the phased array readout electronics platform but also effectively reduces power consumption and lowers system operating costs.

[0056] In some embodiments of this application, such as Figure 2 As shown, the radio frequency acquisition module 100 includes an antenna array unit 110 and a radio frequency front end (AFE) 120;

[0057] The antenna array unit 110 includes multiple independent antennas, and the multiple antennas are arranged in a planar array to collect spatial electromagnetic waves.

[0058] The radio frequency front-end unit 120 is configured to sequentially perform low-noise amplification, analog filtering, and gain amplification on the spatial electromagnetic wave so that the amplitude of the processed radio frequency acquisition signal is within a preset range.

[0059] Specifically, the antenna array unit 110 consists of a large number of independent antennas. These antennas adopt a planar array layout, which can cover radio signals in a specific frequency band, and are responsible for the efficient reception of space electromagnetic waves, providing raw signal input to the platform.

[0060] The RF front-end unit 120 integrates a low-noise amplifier, a bandpass filter, a gain amplifier, and a distribution network. Since the electromagnetic waves transmitted from the antenna array typically have extremely low signal power, they are highly susceptible to interference from various noise sources during subsequent processing, leading to signal quality degradation. The low-noise amplifier amplifies the power of these weak signals while minimizing its own noise introduction. The bandpass filter receives the signal processed by the low-noise amplifier and can precisely set a specific frequency range. Only signals within this range can pass through smoothly, while signals at other frequencies are effectively suppressed, thereby further improving the signal-to-noise ratio. The gain amplifier receives the signal processed by the bandpass filter and amplifies it to obtain an analog RF signal. This analog RF signal is then sent to the corresponding signal processing unit 220 in the digital receiver module 200, thereby amplifying the weak electromagnetic waves received by the antenna array to a range that can be processed by the various signal processing units 220 in the digital receiver module 200, while maintaining a high signal-to-noise ratio.

[0061] In some embodiments of this application, such as Figure 2 As shown, the time and frequency management unit 210 includes a clock source 211 and a frequency synthesis subunit 212. The clock source 211 is used to generate a reference clock signal, and the frequency synthesis subunit 212 is used to generate multiple clock output signals based on the reference clock signal. The number of clock output signals is greater than the number of signal processing units 220, and the multiple clock output signals are in phase and have the same frequency as the reference clock signal.

[0062] Specifically, in this embodiment, the clock source 211 is a rubidium atomic clock standard source. The rubidium atomic clock standard source has GPS / BeiDou satellite discipline capabilities, receiving GPS / BeiDou satellite signals to synchronize the output frequency of the rubidium oscillator with the GPS / BeiDou satellite signals, thereby providing a 10MHz high-precision reference clock signal. Furthermore, the clock source 211 is also used to generate a trigger signal; in this embodiment, the trigger signal is a 1pps (pulse per second) second pulse.

[0063] The frequency synthesis subunit 212 is adapted to receive the 10MHz reference clock signal generated by the clock source 211 and split the reference clock signal into multiple clock output signals Ex_Refclk that are of the same source, frequency, and phase, thereby providing a stable external clock for the digital receiving module 200 and ensuring that the input clock of each signal processing unit 220 is synchronized.

[0064] Therefore, in this embodiment, the frequency synthesis subunit 212 generates multiple clock output signals Ex_Refclk with the same frequency and phase based on the reference clock signal, and the number of these signals is greater than the number of signal processing units 220. This provides each signal processing unit 220 with a sufficient and uniform clock signal source, ensuring that each signal processing unit 220 works under the same clock rhythm. This further improves the synchronization of coarse channel processing of RF acquisition signals and effectively avoids the problem of multi-channel signal delay or phase inconsistency caused by clock asynchrony.

[0065] Furthermore, in some embodiments of this application, such as Figure 3 As shown, the frequency synthesis subunit 212 includes a first frequency signal distributor 2121 and a second frequency signal distributor 2122. The input terminals of the first frequency signal distributor 2121 and the second frequency signal distributor 2122 are respectively connected to the clock source 211, and the output terminals of the first frequency signal distributor 2121 and the second frequency signal distributor 2122 are respectively connected to the clock input terminal of the corresponding signal processing unit 220. The first frequency signal distributor 2121 and the second frequency signal distributor 2122 are used to generate multiple clock output signals Ex_Refclk based on the reference clock signal.

[0066] Specifically, a frequency signal distributor is a radio frequency signal distribution and amplification device that distributes a single frequency standard signal into multiple output signals of the same frequency. In one embodiment of this application, a 10MHz reference clock signal output from clock source 211 is input to the input terminals of a first frequency signal distributor 2121 and a second frequency signal distributor 2122, respectively. The first frequency signal distributor 2121 and the second frequency signal distributor 2122 are respectively used to distribute a single 10MHz reference clock signal into 16 clock output signals Ex_Refclk. That is, the frequency synthesis subunit 212 can split a single reference clock signal into 32 clock output signals Ex_Refclk1 to Ex_Refclk32 that are of the same source, frequency, and phase, and connect 28 of these clock output signals Ex_Refclk to the corresponding 28 signal processing units 220.

[0067] It should be noted that, Figure 3 The example of generating 32 clock output signals Ex_Refclk1 to Ex_Refclk32 using only two frequency signal distributors is just one example of an embodiment of this application. Similarly, the inclusion of 28 signal processing units 220 in the digital receiving module 200 is also just one example of an embodiment of this application and is not intended to limit this application.

[0068] Therefore, this embodiment utilizes a frequency signal distributor to generate multiple clock output signals Ex_Refclk with the same frequency and phase. The number of clock output signals Ex_Refclk is redundant relative to the signal processing unit 220. This provides space for system expansion, enhancing system scalability and eliminating the need to redesign the clock generation module when additional signal processing units 220 are required, thus reducing system upgrade costs and complexity. Furthermore, during actual operation, if a clock output signal Ex_Refclk malfunctions or is interfered with, other redundant clock output signals Ex_Refclk can immediately replace it, ensuring that the signal processing unit 220 still receives a stable clock signal, maintaining normal system operation and improving system reliability and fault tolerance. Therefore, it significantly improves the reusability and applicability of the phased array readout electronics platform.

[0069] In some embodiments of this application, such as Figure 2 As shown, the time and frequency management unit 210 further includes a timing control subunit 213, wherein the timing control subunit 213 is adapted to receive a trigger signal and a clock output signal Ex_Refclk, and generate a timing control pulse signal SYNC_OUT according to the system preset control parameters in response to the trigger signal and the clock output signal Ex_Refclk, wherein the pulse width of the timing control pulse signal SYNC_OUT matches the system preset control parameters.

[0070] Specifically, the timing control subunit 213 has the aforementioned system preset control parameters built in. These system preset control parameters are determined during the entire readout electronics platform debugging phase. By using the system preset control parameters, the generation timing of the rising and falling edges of the timing control pulse signal SYNC_OUT can be determined, thereby realizing the pulse width control of the timing control pulse signal SYNC_OUT.

[0071] Furthermore, upon receiving a 1pps trigger signal, the timing control subunit 213 begins generating a timing control pulse signal SYNC_OUT based on the system's preset control parameters. The timing control subunit 213 utilizes different pulse widths of the SYNC_OUT timing control pulse signal to characterize the control information contained in the system's preset control parameters. For example, as... Figure 4As shown, when the pulse width of the timing control pulse signal SYNC_OUT corresponds to the period of 3 clock output signals Ex_Refclk, the timing control pulse signal SYNC_OUT represents the synchronization state trigger control function of the acquisition channel. When the pulse width of the timing control pulse signal SYNC_OUT corresponds to the period of 2 clock output signals Ex_Refclk, the timing control pulse signal SYNC_OUT represents the logic reset control function of the acquisition channel. When the pulse width of the timing control pulse signal SYNC_OUT corresponds to the period of 1 clock output signal Ex_Refclk, the timing control pulse signal SYNC_OUT represents the phase signal acquisition function of the acquisition channel.

[0072] The timing control subunit 213 then sends the timing control pulse signal SYNC_OUT to each signal processing unit 220. The signal processing unit 220 uses the counting signal count to count the pulse width of the timing control pulse signal SYNC_OUT in order to parse out the specific function represented by the timing control pulse signal SYNC_OUT.

[0073] Therefore, the timing control subunit 213 generates a timing control pulse signal SYNC_OUT by combining the trigger signal, the system preset control parameters, and the clock output signal Ex_Refclk. This allows the timing control pulse signal SYNC_OUT to accurately carry the relevant control information of the system preset control parameters. According to different system requirements and application scenarios, the pulse width of the timing control pulse signal SYNC_OUT can be precisely adjusted. While ensuring the channel synchronization between signal processing units 220, it also realizes the multiplexing control of other functions such as synchronous state triggering and logic reset of the acquisition channel of the signal processing unit and phase signal acquisition. This better adapts to different observation tasks and data processing requirements, improves the flexibility and adaptability of the phased array readout electronics platform, and saves a lot of hardware circuit design costs.

[0074] Furthermore, in some embodiments of this application, Figure 5 The hardware structure of the timing control subunit 213 is shown, as follows: Figure 5 As shown, the timing control subunit 213 includes a programmable logic processor 2131. The first input terminal of the programmable logic processor 2131 is adapted to receive a clock output signal Ex_Refclk, and the second input terminal of the programmable logic processor 2131 is adapted to receive a trigger signal. The output terminal of the programmable logic processor 2131 is connected to the corresponding signal processing unit 220 to output a timing control pulse signal SYNC_OUT. The output terminals of the programmable logic processor 2131 and the signal processing unit 220 correspond one-to-one.

[0075] Specifically, the timing control subunit 213 includes a programmable logic processor 2131 on the programmable logic (PL) side and a state manager 2132 on the processing system (PS) side. In one example of this embodiment, the state manager 2132 is a Zynq7Z020 SoC series FPGA module and the programmable logic processor 2131 is an XCKU35 series FPGA module.

[0076] also, Figure 6 The signal flow of the timing control subunit 213 is shown, such as Figure 6 As shown, in some embodiments of this application, system operating parameters are also sent out by the host computer 400 for system configuration. Specifically, the state manager 2132 is connected to the switch 500 via the PS-side gigabit Ethernet port GE, thereby communicating with the host computer 400, receiving and parsing the system operating parameters sent by the host computer 400, and then distributing the system operating parameters to each signal processing unit 220 to achieve the initialization configuration of system operating parameters such as the operating mode and start frequency of the signal processing unit 220.

[0077] The state manager 2132 also interacts with the programmable logic processor 2131 through a GPIO interface. Specifically, the third input terminal of the programmable logic processor 2131 is a GPIO interface, which is connected to the state manager 2132 to receive synchronization instructions sent by the host computer 400. When the programmable logic processor 2131 receives the above synchronization instructions, it responds to the 1pps trigger signal and starts to generate timing control pulse signals SYNC_OUT with different pulse widths at different times.

[0078] Furthermore, the clock output signal Ex_Refclk generated by the frequency synthesis subunit 212 is processed by the buffer to obtain the Ex_Refclk_in signal, which is then input to the first input terminal of the programmable logic processor 2131. Simultaneously, a 1pps trigger signal generated by the clock source 211 is input to the second input terminal of the programmable logic processor 2131. Upon receiving the 1pps trigger signal, the programmable logic processor 2131 begins to parse the built-in system preset control parameters and generates a timing control pulse signal SYNC_OUT based on the parsing results. For details of the generation process, please refer to the relevant descriptions in the above embodiments.

[0079] Taking the digital receiving module 200, which includes 28 signal processing units 220, as an example, the programmable logic processor 2131 generates 28 timing control pulse signals SYNC_OUT1 to SYNC_OUT28 through 28 output terminals and sends them to the corresponding signal processing units 220 respectively.

[0080] In addition, the status manager 2132 is also configured to periodically acquire the unit status information of each signal processing unit 220 and upload it to the host computer 400 for display. At the same time, the status manager 2132 collects the channel phase information of each signal processing unit 220, calculates the channel phase information to obtain the channel phase adjustment information between each signal processing unit 220, and distributes the channel phase adjustment information to each signal processing unit 220 to achieve synchronization.

[0081] For example, the status manager 2132 polls the status information of each signal processing unit 220 through the switch 500. Specifically, it collects unit status information such as clock lock status, UDP transmission link status, and channel status information uploaded by 28 signal processing units 220 and reports it to the host computer 400 for system status display. In addition, the status manager 2132 collects the acquisition channel status information of each signal processing unit 220, such as phase information, and then uses the phase information to calculate and determine the phase difference between all acquisition channels. The phase adjustment value is then distributed to each signal processing unit 220 as channel adjustment information, enabling each signal processing unit 220 to configure the phase of its digitally controlled oscillator (NCO) based on the channel adjustment information, thereby realizing phase calibration and synchronous acquisition functions between all acquisition channels.

[0082] In some embodiments of this application, the signal processing unit 220 is configured to parse the pulse width of the timing control pulse signal SYNC_OUT according to the clock output signal Ex_Refclk, and perform synchronous coarse channel processing on the radio frequency acquisition signal when the pulse width meets preset conditions.

[0083] Specifically, the signal processing unit 220 receives the timing control pulse signal SYNC_OUT and performs internal parsing, such as... Figure 4 As shown, the signal processing unit 220 internally counts the pulse width of the timing control pulse signal SYNC_OUT based on the clock output signal Ex_Refclk, and generates a corresponding count signal count. Specifically, when the pulse width of the timing control pulse signal SYNC_OUT is equal to three cycles of the clock output signal Ex_Refclk (i.e., after three cycles, the rising edge of the timing control pulse signal SYNC_OUT is detected), the count signal counts to 3 after a certain delay, and at the moment it counts to 3, a pulse SYNC is generated to trigger the inter-channel synchronous acquisition operation of the signal processing unit 220.

[0084] Therefore, this embodiment utilizes different pulse widths of the timing control pulse signal SYNC_OUT to achieve time-division multiplexing of inter-channel synchronization state triggering operations, logic reset operations, or phase acquisition operations within the signal processing unit 220. For example, when the pulse width of the timing control pulse signal SYNC_OUT is equal to two cycles of the clock output signal Ex_Refclk, i.e., after two cycles, the rising edge of the timing control pulse signal SYNC_OUT is detected. The counting signal counts to 2 after a certain delay, and a pulse Reset is generated at the moment the count reaches 2. The signal processing unit 220 responds to this pulse Reset to trigger the logic reset operation of the signal processing unit 220, thereby resetting the state of each acquisition channel of the signal processing unit 220. For example, when the pulse width of the timing control pulse signal SYNC_OUT is equal to one cycle of the clock output signal Ex_Refclk, that is, after one cycle, the rising edge of the timing control pulse signal SYNC_OUT is detected, the counting signal count counts to 1 after a certain delay, and generates a pulse Catch at the moment the count reaches 1. The signal processing unit 220 responds to the pulse Catch to trigger the phase acquisition operation of the signal processing unit 220, thereby sending the phase information of each acquisition channel of the signal processing unit 220 to the state manager 2132.

[0085] Therefore, by analyzing the pulse width of the timing control pulse signal SYNC_OUT, this embodiment of the application ensures that each signal processing unit 220 performs signal acquisition and coarse channel processing under the same time reference, which greatly improves the synchronization between signal processing units 220, effectively improves the accuracy and reliability of signal processing, and enables the back-end readout module to accurately generate astronomical observation data.

[0086] Furthermore, the signal processing unit 220 is an integrated chip based on RFSoC, specifically, Figure 7 The hardware structure of the signal processing unit 220 is shown, such as... Figure 7 As shown, the integrated chip includes an RFdc IP core and its peripheral circuits. The integrated chip includes eight acquisition channels, Ch1 to Ch8, for high-speed, parallel, real-time, and synchronous acquisition and processing of radio frequency acquisition signals.

[0087] Each integrated chip's peripheral circuitry includes a phase-locked loop (PLL) to keep the output signal in phase synchronized with the input reference signal. In one example of an embodiment of this application, the peripheral circuitry includes a first PLL unit and a second PLL unit. The input of the first PLL unit is connected to a time-frequency management unit, the output of the first PLL unit is connected to the input of the second PLL unit, and the output of the second PLL unit is connected to the input of an analog-to-digital converter subunit.

[0088] The peripheral circuitry also includes a memory module (DDR) for buffering and reassembling signals from multiple acquisition channels at multiple times during signal framing.

[0089] The peripheral circuitry also includes a power supply module, which provides the various voltages required for the integrated chip to operate.

[0090] The peripheral circuit also includes four QSFP28 optical ports with a single-port communication rate of 100Gbps, used for high-speed real-time data transmission between the signal processing unit 220 and the back-end readout module.

[0091] Figure 8 The architecture of the RFdc IP core in the above-mentioned integrated chip is shown. The integrated chip includes an analog-to-digital conversion subunit 221, which is configured to perform analog-to-digital conversion on the radio frequency acquisition signal in response to the clock output signal Ex_Refclk and the timing control pulse signal SYNC_OUT, and obtain the converted digital acquisition signal for coarse channel processing of the digital acquisition signal.

[0092] Specifically, the first PLL unit is configured to generate an internal clock signal Clk based on the clock output signal Ex_Refclk and the timing control pulse signal SYNC_OUT. The second PLL unit is an RF PLL, which is configured to perform frequency multiplication sampling based on the internal reference clock Refclk output by the first PLL unit to obtain a high-frequency sampling clock Sampling clk, and distribute the high-frequency sampling clock Sampling clk to each analog-to-digital conversion subunit in the integrated chip to convert the RF acquisition signal into a digital acquisition signal based on the high-frequency sampling clock Samplingclk.

[0093] Furthermore, such as Figure 8 As shown, the integrated chip also includes a demodulation subunit 222, a filtering subunit 223, and a framing subunit 224. The demodulation subunit 222 is configured to perform quadrature demodulation on the digitally acquired signal to obtain the demodulated initial baseband signal. The filtering subunit 223 is configured to perform decimation-by-two filtering on the initial baseband signal to obtain the target baseband signal, and then perform synchronous coarse channel processing on the target baseband signal through polyphase filtering and fast Fourier transform to obtain multiple sub-channel signals. The framing subunit 224 is configured to frame the sub-channel signals according to the computing power of the back-end readout module to obtain the channel signal, and then transmit the channel signal to the back-end readout module via the UDP protocol.

[0094] Specifically, the digital acquisition signal output by the analog-to-digital converter subunit 221 is quadrature demodulated to remove the high-frequency NCO carrier / local oscillator frequency components, resulting in an initial baseband signal carrying phase information. Furthermore, the effective bandwidth of the initial baseband signal is less than the bandwidth of the radio signal entering the antenna array. Subsequently, the initial baseband signal undergoes a decimation-by-two (D2) filter. Specifically, after filtering with a low-pass filter (LPF), for every two input sampling points of the initial baseband signal, only one valid sampling point is retained. This reduces the data rate of the target baseband signal to half that of the initial baseband signal, effectively alleviating the data processing pressure on the back-end readout module.

[0095] The target baseband signal is then processed by polyphase filtering of polyphase filter banks (PFB) or over-sampled polyphase filter banks (OPFB) through the filtering subunit 223, and then coarse digital channelization is achieved by fast Fourier transform (FFT). The target baseband signal can be divided into M coarse-grained sub-channel signals, where the number of sub-channel signals is determined by the number of branches of PFB or OPFB and the number of FFT points.

[0096] The framing subunit 224 performs variable length data exchange format (VLBI) framing and user datagram protocol (UDP) encapsulation on the subchannel signal according to the GPU processing requirements and capabilities of the back-end readout module. Finally, it distributes the signal to each GPU processing board of the back-end readout module via a 100Gbps UDP QSFP28 optical port for processing such as digital beamforming (DBF), radio frequency interference (RFI) cancellation, and fine channelization.

[0097] Therefore, this embodiment uses an RFSoC-based integrated chip as the signal processing unit. Leveraging its high integration, it reduces the complexity of connecting multiple independent chips, lowering hardware design difficulty and cost. Furthermore, by performing coarse-channel processing on the digitally acquired signal, the signal data rate is significantly reduced, thereby saving substantial hardware logic resources and improving processing efficiency.

[0098] Therefore, the digital receiving module proposed in this application integrates ADC, FPGA and high-speed interconnect resources into a single chip using the RFSoC architecture. It also utilizes the RFdc IP core to achieve the entire process of radio frequency signal acquisition, analog-to-digital conversion and signal synchronization processing on-chip. Furthermore, the high integration of the RFSoC architecture not only ensures the synchronization and phase consistency of multi-channel signal acquisition through close hardware-level collaboration, reducing the delay and interference caused by inter-board transmission in traditional discrete architectures, but also achieves rapid conversion and preprocessing from radio frequency signals to coarse-channelized data through an efficient on-chip signal processing link, greatly improving signal processing efficiency. It can construct a highly integrated single-chip phased array unit, ultimately ensuring the accuracy and real-time performance of astronomical observation data.

[0099] Accordingly, this application provides a phased array readout electronics method, which is applied to the platform described in any of the above embodiments.

[0100] The detailed content of the method proposed in this application embodiment is the same as that of the corresponding embodiment described above, and will not be repeated here.

[0101] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application, such as... Figure 9 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 9 Take a processor 10 as an example.

[0102] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0103] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0104] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0105] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0106] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0107] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0108] This application provides a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method of any embodiment of this application.

[0109] Exemplary terms of the scope of protection of this disclosure are as follows:

[0110] Clause 1A. A phased array readout electronics platform, comprising a time-frequency management unit and at least one signal processing unit;

[0111] The time-frequency management unit is configured to generate a clock output signal and a timing control pulse signal, and send the clock output signal and the timing control pulse signal to each of the signal processing units respectively.

[0112] The multiple signal processing units are configured to synchronously analyze the timing control pulse signal according to the clock output signal, and perform coarse channel processing on the radio frequency acquisition signal according to the analysis result, so as to obtain astronomical observation data based on the processing result.

[0113] Clause 2A. The platform according to Clause 1A, wherein the timing control pulse signals received by each of the signal processing units have equal pulse widths and are in phase with each other.

[0114] Clause 3A. The platform according to Clause 1A, wherein each of the signal processing units includes multiple acquisition channels, and the signal processing unit is further configured to parse the pulse width of the timing control pulse signal according to the period of the clock output signal, so as to perform one of the following operations on the multiple acquisition channels: inter-channel synchronization state triggering operation, logic reset operation, or phase acquisition operation according to the pulse width.

[0115] Clause 4A. The platform according to Clause 3A, wherein the signal processing unit is further configured to parse the pulse width of the timing control pulse signal according to the clock output signal, and trigger the inter-channel synchronization state triggering operation when the pulse width meets a first preset condition, so as to perform synchronous coarse channel processing on the radio frequency acquisition signal according to the inter-channel synchronization state triggering operation.

[0116] Clause 5A. The platform according to Clause 3A, wherein the signal processing unit is further configured to parse the pulse width of the timing control pulse signal according to the clock output signal, and trigger the logic reset operation when the pulse width meets a second preset condition, so as to reset the acquisition channel according to the logic reset operation.

[0117] Clause 6A. The platform according to Clause 3A, wherein the signal processing unit is further configured to parse the pulse width of the timing control pulse signal according to the clock output signal, and trigger the phase acquisition operation when the pulse width satisfies a third preset condition, so as to acquire the phase information of the acquisition channel according to the phase acquisition operation, and adjust the phase difference between all acquisition channels according to the phase information.

[0118] Clause 7A. The platform as described in Clause 1A, wherein the time-frequency management unit includes a clock source and a frequency synthesis subunit;

[0119] The clock source is used to generate a reference clock signal;

[0120] The frequency synthesis subunit is used to generate multiple clock output signals based on the reference clock signal, wherein the number of clock output signals is greater than the number of signal processing units, and the multiple clock output signals are in phase and have the same frequency as the reference clock signal.

[0121] Clause 8A. The platform according to Clause 7A, wherein the frequency synthesis subunit includes a first frequency signal distributor and a second frequency signal distributor, the input terminals of the first frequency signal distributor and the second frequency signal distributor are respectively connected to the clock source, and the output terminals of the first frequency signal distributor and the second frequency signal distributor are connected to the clock input terminal of the corresponding signal processing unit;

[0122] The first frequency signal distributor and the second frequency signal distributor are used to generate a plurality of clock output signals according to the reference clock signal, and the plurality of clock output signals are in phase and have the same frequency.

[0123] Clause 9A. The platform as described in Clause 7A, wherein the clock source is further used to generate a trigger signal, and the time-frequency management unit further includes a timing control subunit;

[0124] The timing control subunit is adapted to receive the trigger signal and the clock output signal, and in response to the trigger signal and the clock output signal, generate the timing control pulse signal according to the system preset control parameters, wherein the pulse width of the timing control pulse signal is matched with the system preset control parameters.

[0125] Clause 10A. The platform described in Clause 9A, wherein the timing control subunit includes a programmable logic processor, the programmable logic processor having built-in system preset control parameters, and a first input terminal of the programmable logic processor being adapted to receive the clock output signal, a second input terminal of the programmable logic processor being adapted to receive the trigger signal, and an output terminal of the programmable logic processor being connected to the signal processing unit to output the control pulse signal, wherein the output terminal of the programmable logic processor corresponds one-to-one with the signal processing unit.

[0126] Clause 11A. According to the platform described in Clause 9A, the timing control subunit further includes a state manager, which is configured to periodically acquire the unit status information of each signal processing unit and upload it to the host computer for display. The state manager is also configured to collect the channel phase information of each signal processing unit, calculate the channel phase information to obtain the channel phase adjustment information between each signal processing unit, and distribute the channel phase adjustment information to each signal processing unit to achieve synchronization.

[0127] In the aforementioned clauses, the time-frequency management unit can trigger operations, logic reset operations, or phase acquisition operations through one of the following: time-division channel synchronization state triggering operation, logic reset operation, or phase acquisition operation through an IO port. This not only achieves port multiplexing, saving a significant amount of external cables and hardware circuit design, but also ensures that the states of multiple acquisition channels of multiple information processing units remain synchronized. This allows each signal processing unit to synchronously analyze the timing control pulse signal based on a unified clock output signal. Compared with related technologies, this not only improves the integration of the digital receiving module but also ensures the synchronization of coarse channel processing of the RF acquisition signal by each signal processing unit, enabling the back-end readout module to function normally and greatly improving the accuracy of astronomical observation data.

[0128] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

[0129] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0130] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the apparatus embodiments, so the description is relatively simple; relevant parts can be referred to the description of the method embodiments.

[0131] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application.

[0132] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A phased array readout electronics platform, characterized in that, The platform includes: A radio frequency acquisition module, configured to acquire spatial electromagnetic waves and convert the spatial electromagnetic waves into radio frequency acquisition signals; A digital receiving module is provided, which is adapted to receive the radio frequency acquisition signal. The digital receiving module includes a time-frequency management unit and at least one signal processing unit. The time-frequency management unit is configured to generate a clock output signal and a timing control pulse signal, and send the clock output signal and the timing control pulse signal to each of the signal processing units respectively, so that each of the signal processing units performs synchronous analysis on the timing control pulse signal according to the clock output signal, and performs coarse channel processing and framing on the radio frequency acquisition signal according to the analysis result to obtain multiple channel signals. A back-end readout module is configured to generate astronomical observation data based on the channel signal.

2. The phased array readout electronics platform according to claim 1, characterized in that, The time and frequency management unit includes a clock source and a frequency synthesis subunit; The clock source is used to generate a reference clock signal; The frequency synthesis subunit is used to generate multiple clock output signals based on the reference clock signal, wherein the number of clock output signals is greater than the number of signal processing units, and the multiple clock output signals are in phase and have the same frequency as the reference clock signal.

3. The phased array readout electronics platform according to claim 2, characterized in that, The frequency synthesis subunit includes a first frequency signal distributor and a second frequency signal distributor. The input terminals of the first frequency signal distributor and the second frequency signal distributor are respectively connected to the clock source, and the output terminals of the first frequency signal distributor and the second frequency signal distributor are connected to the clock input terminal of the corresponding signal processing unit. The first frequency signal distributor and the second frequency signal distributor are used to generate a plurality of clock output signals according to the reference clock signal.

4. The phased array readout electronics platform according to claim 2, characterized in that, The clock source is also used to generate a trigger signal, and the time and frequency management unit further includes a timing control subunit; The timing control subunit is adapted to receive the trigger signal and the clock output signal, and in response to the trigger signal and the clock output signal, generate the timing control pulse signal according to the system preset control parameters, wherein the pulse width of the timing control pulse signal is matched with the system preset control parameters.

5. The phased array readout electronics platform according to claim 4, characterized in that, The timing control subunit includes a programmable logic processor; The first input terminal of the programmable logic processor is adapted to receive the clock output signal, the second input terminal of the programmable logic processor is adapted to receive the trigger signal, and the output terminal of the programmable logic processor is connected to the corresponding signal processing unit to output the timing control pulse signal, wherein the output terminal of the programmable logic processor corresponds one-to-one with the signal processing unit.

6. The phased array readout electronics platform according to claim 1, characterized in that, The signal processing unit is configured to parse the pulse width of the timing control pulse signal according to the clock output signal, and to perform synchronous coarse channel processing on the radio frequency acquisition signal when the pulse width meets preset conditions.

7. The phased array readout electronics platform according to claim 6, characterized in that, The signal processing unit is an integrated chip based on RFSoC. The integrated chip includes an analog-to-digital conversion subunit, which is configured to perform analog-to-digital conversion on the radio frequency acquisition signal in response to the clock output signal and the timing control pulse signal, and obtain the converted digital acquisition signal, so as to perform the coarse channel processing on the digital acquisition signal.

8. The phased array readout electronics platform according to claim 7, characterized in that, The integrated chip also includes a demodulation subunit, a filtering subunit, and a framing subunit; The demodulation subunit is configured to perform quadrature demodulation on the digital acquisition signal and obtain the demodulated initial baseband signal; The filtering subunit is configured to perform a decimation-by-two filter on the initial baseband signal to obtain the target baseband signal, and to perform synchronous coarse channel processing on the target baseband signal through polyphase filtering and fast Fourier transform to obtain multiple sub-channel signals. The framing subunit is configured to frame the subchannel signals according to the computing power of the backend readout module to obtain the channel signals, and transmit the channel signals to the backend readout module via the UDP protocol.

9. The phased array readout electronics platform according to any one of claims 1 to 8, characterized in that, The radio frequency acquisition module includes an antenna array unit and a radio frequency front-end unit; The antenna array unit includes multiple independent antennas, and the multiple antennas are arranged in a planar array to collect the spatial electromagnetic waves; The radio frequency front-end unit is configured to sequentially perform low-noise amplification, analog filtering, and gain amplification on the spatial electromagnetic wave, so that the amplitude of the obtained radio frequency acquisition signal after processing is within a preset range.

10. A phased array readout electronics method, characterized in that, Applied to the platform according to any one of claims 1 to 9, the method comprises: Generate a clock output signal and a timing control pulse signal, and perform synchronous analysis on the timing control pulse signal based on the clock output signal; Based on the analysis results, coarse channel processing and framing are performed on the radio frequency acquisition signals to obtain multiple channel signals. The radio frequency acquisition signals are obtained by acquiring space electromagnetic waves and converting the space electromagnetic waves. The multiple channel signals are used to generate astronomical observation data.

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