Power device and method of manufacturing the same

Abstract

The application relates to a power device and a preparation method thereof. The device comprises a substrate, and a first epitaxial layer and a second epitaxial layer which are sequentially stacked on a first surface of the substrate. The second epitaxial layer comprises a plurality of split gates which extend along a first direction towards the substrate via a top surface of the second epitaxial layer and are spaced apart along a second direction parallel to the first surface, and ion columns which are in contact with the split gates. The split gates comprise sub-gates which are spaced apart along the second direction, and a dielectric layer which surrounds the outer surface of the sub-gates. The dielectric layer comprises an extension between adjacent sub-gates. The ion columns are located directly below the one-to-one arranged extensions and extend into the first epitaxial layer along the first direction. The ion columns have a conductive type opposite to that of the first epitaxial layer and the second epitaxial layer. The compromise between the breakdown voltage and the specific on-state voltage can be effectively improved, and the switching power consumption is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a power device and a preparation method thereof. BACKGROUND

[0002] Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a widely used and superior performance power device, among which silicon carbide (SiC) material has strong attraction in high power due to its excellent characteristics and becomes one of the ideal materials for high-performance power MOSFET. SiC MOSFET devices mainly have a planar gate structure and a trench gate structure.

[0003] Compared with the planar gate structure, the trench gate silicon carbide (SiC) MOSFET eliminates the junction field effect transistor (JFET) area effect due to the trench gate structure, so that the current can flow more vertically and directly from the source to the drift region, and the cell density can be made higher, thereby significantly reducing the on-resistance per unit area. Benefiting from higher cell density and shorter channel, its input capacitance is smaller, the switching speed is faster, the loss is lower, and more device units can be integrated on the same area wafer, effectively improving the utilization rate of the wafer and the chip density.

[0004] However, the device withstand voltage of the trench gate SiC MOSFET is limited by the thickness and doping concentration of the epitaxial layer, and there is a significant trade-off relationship between the on-resistance and the breakdown voltage, which restricts the breakthrough of the device switching speed, power density and reliability. SUMMARY

[0005] Therefore, it is necessary to provide a power device and a preparation method thereof, which can at least reduce the power consumption as much as possible while ensuring the device withstand voltage level in view of the technical problems in the prior art.

[0006] In a first aspect, the present application provides a power device, comprising: a substrate, and a first epitaxial layer, a second epitaxial layer which are sequentially stacked on a first surface of the substrate;

[0007] The second epitaxial layer comprises a plurality of split gates extending along a first direction towards the substrate via a top surface of the second epitaxial layer and spaced apart along a second direction parallel to the first surface, and ion columns in contact with the split gates;

[0008] The split gate comprises a plurality of sub-gates spaced apart along the second direction, and a dielectric layer surrounding an outer surface of the sub-gate; wherein the dielectric layer comprises an extension between adjacent sub-gates;

[0009] The ion column is located directly below the extension arranged in one-to-one and extends into the first epitaxial layer along the first direction; the ion column has a conductive type opposite to that of the first epitaxial layer and the second epitaxial layer.

[0010] In the power device in the above embodiment, the extension separates the sub-gates to form a split-gate structure, compared with a common trench-gate structure, the split-gate opposite to the drain has a reduced area, and a detailed gate-drain capacitance characteristic can be obtained; and the ion column opposite in conductive type to the epitaxial layer is arranged in one-to-one at the bottom of the split-gate structure, and is alternately arranged in the second direction to form a super-junction structure, which withstands high voltage by mutual depletion during voltage resistance, so that the voltage resistance of the device is relatively independent of the doping concentration. Therefore, the power device provided in the embodiment can effectively reduce its specific on-resistance under the same breakdown voltage, and reduce the switching time and switching loss by reducing the gate-drain capacitance.

[0011] In some embodiments, the second epitaxial layer includes a top surface of the second epitaxial layer, and the source region, the base region are arranged in sequence along the first direction;

[0012] The split-gate penetrates the source region and the base region along the first direction.

[0013] In some embodiments, the dielectric layer includes:

[0014] The gate oxide layer surrounds the contact interface between the split-gate and the second epitaxial layer.

[0015] The extension extends to the gate oxide layer along the first direction.

[0016] The top surface of the ion column is located within the bottom surface of the gate oxide layer.

[0017] In some embodiments, the power device further includes:

[0018] The interlayer dielectric layer is located on the top surface of the second epitaxial layer.

[0019] The extension and the interlayer dielectric layer are prepared synchronously in the same process step.

[0020] In some embodiments, the split-gate includes:

[0021] The metal source electrode extends into the extension through the top surface of the extension, and the width and the depth of the metal source electrode are related to the gate-source capacitance of the power device; wherein the depth is used to represent the size along the first direction, and the width is used to represent the size along the second direction.

[0022] In a second aspect, the application also provides a preparation method of a power device, for preparing the power device in any of the above embodiments, the preparation method of the power device includes:

[0023] A substrate is provided, which is configured with a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer which are sequentially stacked;

[0024] A plurality of split gates are formed in the second epitaxial layer, which extend along a first direction towards the substrate via a top surface of the second epitaxial layer, and are spaced apart along a second direction parallel to the first surface, and ion pillars in contact with the split gates;

[0025] The split gate comprises sub-gates spaced apart along the second direction, and a dielectric layer surrounding an outer surface of the sub-gates; wherein the dielectric layer comprises an extension between adjacent sub-gates;

[0026] The ion pillars are located directly below the extension arranged one-to-one, and extend into the first epitaxial layer along the first direction; the ion pillars have a conductive type opposite to that of the first epitaxial layer and the second epitaxial layer.

[0027] In the above embodiment, the ion pillars are formed at the bottom of the split gate, and the second epitaxial layer with a conductive type opposite to that of the first epitaxial layer forms a super-junction structure, which assists in depleting the voltage-resistance layer (i.e. the second epitaxial layer), decouples the doping concentration, thickness and breakdown voltage of the second epitaxial layer, and improves the trade-off relationship between specific on-resistance and breakdown voltage; at the same time, the sub-gates are inserted into the dielectric layer (extension), forming a split gate, which can weaken the coupling relationship between the gate and the drain, reduce the gate-drain capacitance of the device, and improve the switching characteristics of the device, thereby effectively optimizing the dynamic characteristics of the super-junction structure device.

[0028] In some embodiments, the ion pillars are formed by:

[0029] After forming the first trench in the second epitaxial layer, a sacrificial layer is formed to fill the first trench;

[0030] After removing part of the sacrificial layer, a mask layer is formed to be spaced apart along the second direction in the first trench, and a second trench is formed between adjacent mask layers;

[0031] Based on the mask layer, ion implantation is performed on the second epitaxial layer at the bottom of the second trench to form the ion pillars.

[0032] In some embodiments, the dielectric layer is formed by:

[0033] After removing the mask layer, a gate oxide layer and a conductive material layer are formed in the first trench, which are arranged away from the first direction;

[0034] A third trench is formed in the conductive material layer, which penetrates the conductive material layer along the first direction;

[0035] An interlayer dielectric layer is formed in the third trench and on the top surface of the second epitaxial layer by a deposition process, and the interlayer dielectric layer in the third trench is used to form the extension.

[0036] In some embodiments, the method for manufacturing the power device further comprises: forming a contact hole in the interlayer dielectric layer, the contact hole being arranged at intervals in the second direction and extending to the second epitaxial layer along the first direction;

[0037] forming a metal layer filling the contact hole and covering the top surface of the interlayer dielectric layer; the metal layer in the contact hole is used to form a metal source electrode.

[0038] In some embodiments, the method for manufacturing the power device further comprises: forming a metal source electrode in the split gate, the metal source electrode extending into the extension portion through the top surface of the extension portion, and the width and depth of the metal source electrode being related to the gate-source capacitance of the power device.

[0039] The power device and the method for manufacturing the same provided in the application have the following unexpected technical effects:

[0040] The power device provided in the application realizes decoupling of the doping concentration and the thickness of the second epitaxial layer and the breakdown voltage by adding the ion column in the first epitaxial layer and the second epitaxial layer, introduces the alternately arranged P-type and N-type regions in the second direction, each P-type region and the N-type region next to it together form a super-junction structure, optimizes the compromise between the specific on-resistance and the breakdown voltage, and improves the gate oxide reliability by surrounding the gate oxide at the bottom of the trench, effectively reduces the probability of device damage, and prolongs the service life.

[0041] Meanwhile, the split gate structure enables the super-junction power device to greatly reduce the on-resistance R on while obtaining a lower gate-drain capacitance C gd characteristic, and can flexibly design the depth and width of the extension portion of the metal source electrode inserted between the sub-gates according to the needs of the application scenario, flexibly adjust the gate-source capacitance C gs , and thus obtain excellent C gs / C gd performance. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0043] Figure 1 The power device provided in the related art has the trench gate structure;

[0044] Figure 2 One of the schematic diagrams of the power device provided in the trench gate structure in the embodiments of the application;

[0045] Figure 3This is a second schematic diagram of a power device with a trench gate structure provided in the embodiments of this application;

[0046] Figure 4 This is a flowchart of a preparation method provided in one embodiment;

[0047] Figure 5 This is a schematic cross-sectional view of the structure obtained after forming a buffer layer and an epitaxial layer in step S202 of the preparation method provided in one embodiment;

[0048] Figure 6 This is a schematic cross-sectional view of the structure obtained after forming the base region and the source region in step S204 of the preparation method provided in one embodiment;

[0049] Figure 7a This is a schematic cross-sectional view of the structure obtained after forming the first trench in step S206 of the preparation method provided in one embodiment;

[0050] Figure 7b for Figure 7a A schematic diagram of the cross-section of the structure after the sacrificial layer is formed;

[0051] Figure 8 This is a cross-sectional schematic diagram of the structure obtained by forming the second trench in step S208 of the preparation method provided in one embodiment;

[0052] Figure 9 This is a schematic cross-sectional view of the structure obtained after forming the shielding region in step S210 of the preparation method provided in one embodiment;

[0053] Figure 10 This is a schematic cross-sectional view of the structure obtained after removing the sacrificial layer in step S402 of the preparation method provided in one embodiment;

[0054] Figure 11 This is a schematic cross-sectional view of the structure obtained after forming the initial split gate in step S404 of the preparation method provided in one embodiment;

[0055] Figure 12 This is a schematic cross-sectional view of the structure obtained after forming the third trench in step S406 of the preparation method provided in one embodiment;

[0056] Figure 13 This is a schematic cross-sectional view of the structure obtained after forming the interlayer dielectric layer in step S408 of the preparation method provided in one embodiment;

[0057] Figure 14 This is one of the schematic cross-sectional views of the structure obtained after forming the metal source electrode in step S410 of the preparation method provided in one embodiment;

[0058] Figure 15 forFigure 14 A cross-sectional view of the structure after forming a back metal layer in the semiconductor structure.

[0059] Figure 16 A cross-sectional view of the structure after forming a metal source in step S410 of the preparation method provided in an embodiment.

[0060] BRIEF DESCRIPTION OF DRAWINGS

[0061] 1, initial substrate; 2, buffer layer; 10, substrate; 11, first epitaxial layer; 12, second epitaxial layer; 121, source region; 122, base region; 20, ion column; 30, split gate; 31, sub-gate; 311, conductive material layer; 32, dielectric layer; 321, gate oxide layer; 322, extension; 40, interlayer dielectric layer; 50, metal layer; 601, first trench; 611, sacrificial layer; 602, second trench; 603, third trench; DETAILED DESCRIPTION

[0062] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present application is more thorough and complete.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0064] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first dopant type could be termed a second dopant type, and, similarly, a second dopant type could be termed a first dopant type; a first dopant type and a second dopant type are different dopant types, for example, a first dopant type can be P-type and a second dopant type can be N-type, or a first dopant type can be N-type and a second dopant type can be P-type.

[0065] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that, when the term "comprising" is used in the present description and claims, it does not exclude the presence of other elements or steps than those listed. Likewise, the term "comprising" should not be interpreted as implying that the apparatus or method has to function only in the described way or that it has to function continuously. It should also be understood that the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0066] Embodiments of the application are described herein with reference to the drawings, which are idealized illustrations. Variations in the depicted shapes are expected due to, for example, manufacturing techniques and / or tolerances. Thus, embodiments of the application should not be limited to the specific shapes illustrated herein, but include deviations in shapes that result from, for example, manufacturing. For example, an implant region that is shown as rectangular will typically have rounded or curved features at its edges and / or an implant concentration gradient, rather than a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implant was performed. Thus, the regions shown in the figures are substantially schematic, their shapes are not intended to represent the actual shape of a region of a device, and do not limit the scope of the application.

[0067] To further reduce the specific on-resistance of the MOSFET and improve the performance of the device, in some related technologies, by adopting a single-channel asymmetric design concept, the characteristics of the <1120> surface high channel mobility are effectively utilized to reduce the channel resistance, and at the same time, a high-efficiency P-type emitter is formed to make the body diode work as a fast freewheeling diode. The deep P+ formed by high-energy ion implantation protects the gate oxide layer well and improves the short-circuit capability of the device. The specific structure is shown in (1) of Figure 1 However, when the single-trench structure optimizes the electric field through the asymmetric shielding area, about half of the channel quantity is sacrificed, so the on-resistance (R on ) is not at the optimal level.

[0068] The trench gate transistor shown in (2) of Figure 1 Although the super junction structure is introduced, R on is optimized, but the gate-drain capacitance C gd is not optimal, the gate-source capacitance C gs cannot be adjusted, and the source-drain capacitance C ds is significantly increased. If a high-speed switching scenario is encountered, it may cause increased oscillation, and the device performance adjustment space is small.

[0069] Based on this, the power device provided in the present application, for ease of understanding, in the embodiments of the present application, the epitaxial layer can include a first surface located on the front surface, and a back surface opposite to the front surface, i.e. a second surface. In the case of ignoring the flatness of the first surface and the second surface, the direction towards the substrate is defined as including a first direction perpendicular to the first surface of the substrate and a second direction parallel to the first surface. Wherein, the first direction and the second direction are perpendicular to each other. The first direction is defined as the Z-axis direction, and the second direction is defined as the Y-axis direction.

[0070] Next, the power device provided in the present application will be described in more detail in combination with the drawings.

[0071] Please refer to Figure 2 , Figure 2 Part of the cross-sectional view of the power device provided in the present application, as shown in Figure 2 , the power device includes a substrate 10, a first epitaxial layer 11, a second epitaxial layer 12 and an interlayer dielectric layer 40.

[0072] The second epitaxial layer 12 includes a plurality of split gates 30 extending along the OZ direction via the top surface of the second epitaxial layer 12 and spaced apart along the OY direction, and ion columns 20 in contact with the split gates 30;

[0073] The split gate 30 includes a sub-gate 31 spaced apart along the OY direction, and a dielectric layer 32 surrounding the outer surface of the sub-gate 31; wherein the dielectric layer 32 includes an extension 322 between adjacent sub-gates 31;

[0074] The ion column 20 is located directly below the extension 322 arranged in one-to-one, and extends into the first epitaxial layer 11 along the OZ direction; the conductive type of the ion column 20 is opposite to the conductive type of the first epitaxial layer 11 and the second epitaxial layer 12. The first epitaxial layer 11 serves as a carrier storage layer to reduce the resistance of the JFET region.

[0075] Specifically, the second epitaxial layer 12 further includes a source region 121 and a base region 122 arranged in sequence along the OZ direction; the split gate 30 penetrates the source region 121 and the base region 122 along the OZ direction; the dielectric layer 32 includes a gate oxide layer 321 surrounding the contact interface between the split gate 30 and the second epitaxial layer 12, and the extension 322 extends to the gate oxide layer 321 along the OZ direction to contact the gate oxide layer 321, thereby separating the sub-gate 31, forming the split gate 30, and reducing the gate leakage capacitance C gd .

[0076] Please continue to refer to Figure 2 , the top surface of the second epitaxial layer 12 further includes an interlayer dielectric layer 40 and a metal source electrode, and the extension 322 is prepared at the same time in the same process step as the interlayer dielectric layer 40; the metal source electrode extends into the base region 122 along the OZ direction through the top surface of the interlayer dielectric layer 40.

[0077] In the following embodiments, the conductive types of the source region 121, the substrate 10, the first epitaxial layer 11, and the second epitaxial layer 12 are all N-type, and the conductive types of the base region 122 and the ion column 20 are both P-type. It can be understood that when the substrate 10 is P-type, only the "P" and "N" in the above structure need to be exchanged.

[0078] In the above embodiments, the ion column 20 and the second epitaxial layer 12 form an alternating PN junction, when a voltage is applied, the depletion layer extends horizontally and merges quickly, forming a depletion layer equal to the trench depth, in the on state, the current can flow through a lower resistance path; at the same time in the off state, it can still withstand high voltage. So that under the condition of the same breakdown voltage, the voltage support layer doping concentration can be greatly improved, and the on resistance can be greatly reduced. This helps to reduce power loss and improve efficiency.

[0079] Please refer to Figure 3 In some embodiments, the split gate 30 further includes a metal source electrode extending into the split gate 30 through the top surface of the extension 322; the width (dimension along the OY direction) and the depth (dimension along the OZ direction) of the metal source electrode in the extension 322 are related to the gate-source capacitance C gs of the power device. From the perspective of the device, C gs / C gd is greatly increased, and has adjustment space, so that the device can optimize the switching speed, reduce oscillation, and optimize the switching loss when switching at high speed, and play the best dynamic performance of the device.

[0080] Referring to Figures 4-16 , in another aspect, the application provides a method for manufacturing a power device, for manufacturing a power device as shown in Figure 2 , the method comprising: step S20-step S40.

[0081] Step S20: a substrate 10, and a first epitaxial layer 11, a second epitaxial layer 12 which are sequentially stacked on the first surface 10a of the substrate 10.

[0082] Step S40: forming a plurality of split gates 30 extending along the OZ direction via the top surface of the second epitaxial layer 12 and spaced apart along the OY direction in the second epitaxial layer 12, and an ion column 20 in contact with the split gate 30;

[0083] Wherein, the split gate 30 includes a sub-gate 31 spaced apart along the OY direction, and a dielectric layer 32 surrounding the outer surface of the sub-gate 31; wherein the dielectric layer 32 includes an extension 322 between adjacent sub-gates 31;

[0084] The ion column 20 is located directly below the one-to-one arranged extension 322 and extends along the OY direction into the first epitaxial layer 11.

[0085] It should be understood that, although Figure 4 The flowchart in each step is sequentially displayed according to the direction of the arrow, but these steps are not necessarily sequentially executed according to the direction of the arrow. Unless otherwise stated herein, the execution of these steps has no strict order restriction, and these steps can be executed in other order. Moreover, Figure 4 At least part of the steps in The steps or stages can not necessarily be executed at the same time, but can be executed at different times, and the execution order of the steps or stages is not necessarily sequential, but can be alternately executed with at least part of other steps or steps or stages in other steps.

[0086] Next, the exemplary method of the power device according to the application is described in conjunction with Figures 5 to 16 , the exemplary method of the power device according to the application is described in conjunction with Figures 5 to 16 , the exemplary method of the power device according to the application is described in conjunction with

[0087] Referring to Figures 5-16 , step S20, further comprising:

[0088] Step S202: using epitaxial process, forming buffer layer 2, first epitaxial layer 11, second epitaxial layer 12 on the top surface of the initial substrate 1 in turn, buffer layer 2 and initial substrate 1 are used to constitute substrate 10, the specific structure is shown in Figure 5 .

[0089] As an example, the doping types of the second epitaxial layer 12, the first epitaxial layer 11, the buffer layer 2 and the initial substrate 1 are medium N-type doping, low N-type doping, medium-high N-type doping and high N-type doping, respectively, as described above.

[0090] Step S204: injecting a base region 122 of P-type and a source region 121 of high N-type doping on the second epitaxial layer 12 in sequence, and the specific structure is as shown in Figure 6 .

[0091] As an example, the depth of the source region 121 ranges from 0.15 μm to 0.25 μm, for example, 0.15 μm, 0.2 μm or 0.25 μm, etc.

[0092] As an example, the depth of the base region 122 ranges from 0.9 μm to 1.1 μm, for example, 0.9 μm, 1 μm or 1.1 μm, etc.

[0093] In this embodiment, the depth of the base region 122 is 1 μm, and the depth of the source region 121 is 0.2 μm.

[0094] Step S206: after etching a first trench 601 extending along the OZ direction in the second epitaxial layer 12, a sacrificial layer 611 is formed to fill the first trench 601, and is etched back to be flush with the top surface of the second epitaxial layer 12, and the specific structure is as shown in Figure 7a and Figure 7b .

[0095] As an example, the material of the sacrificial layer 611 includes but is not limited to polysilicon.

[0096] As an example, the depth of the first trench 601 ranges from 1.1 μm to 1.3 μm, for example, 1.1 μm, 1.2 μm or 1.3 μm, etc.; and the width thereof ranges from 2.5 μm to 3.5 μm, for example, 2.5 μm, 3 μm or 3.5 μm, etc.

[0097] In this embodiment, the depth of the primary trench structure (the first trench 601) is 1.2 μm.

[0098] Step S208: etching the sacrificial layer 611 to form a second trench 602 extending through the sacrificial layer 611 along the OZ direction and a mask layer located on both sides of the second trench 602, and the specific structure is as shown in Figure 8 .

[0099] As an example, the depth of the second trench 602 ranges from 1.1 μm to 1.3 μm, for example, 1.1 μm, 1.2 μm or 1.3 μm, etc.; and the width thereof ranges from 0.5 μm to 1.5 μm, for example, 0.5 μm, 1 μm or 1.5 μm, etc.

[0100] In the embodiment, the depth of the second trench 602 is 1.2 μm, which is ensured to be not more than the depth of the first trench.

[0101] Step S210: based on the mask layer, performing ion implantation process on the second epitaxial layer 12 at the bottom of the second trench 602 to form the ion column 20 of high-concentration P-type doping, and form the P-column structure for lateral depletion in the super-junction structure at the bottom of the second trench 602, and the specific structure is as shown in Figure 9

[0102] In the embodiment, the width of the ion column 20 is adjusted according to the actual requirement of the device.

[0103] Please refer to Figures 10-16 In some embodiments, the step S40 further includes:

[0104] Step S402: after removing the sacrifice layer 611 as the mask layer, performing high-temperature annealing on the second epitaxial layer 12 to activate the impurities, and the annealing temperature is 1650-1700 ℃, and the specific structure is as shown in Figure 10

[0105] Step S404: using the gate oxide process to form the gate oxide layer 321 in the first trench 601, and backfilling to form the conductive material layer 311, and the specific structure is as shown in Figure 11 The gate oxide layer 321 and the conductive material layer 311 are arranged in the first trench 601 along the direction away from the ZO direction. Of course, in some embodiments, the sacrifice oxidation can be performed in the first trench before the formal gate oxide growth, so as to smooth the bottom corner and remove the surface layer damaged by etching, and improve the interface characteristics of the gate oxide.

[0106] For example, the material of the conductive material layer 311 includes but is not limited to polysilicon.

[0107] For example, the thickness of the gate oxide layer 321 ranges from 45 nm to 55 nm, such as 45 nm, 47 nm, 50 nm, 53 nm or 55 nm. In the embodiment, the thickness of the gate oxide layer 321 is 50 nm.

[0108] Step S406: forming a third trench 603 penetrating the conductive material layer 311 along the OZ direction. Since the etching has the material selection characteristics, the etching will be automatically cut off on the gate oxide layer 321, and the specific structure is as shown in Figure 12

[0109] For example, in the embodiment, the same mask as that in the step S208 of etching the second trench can be used, and the etching amount of forming the third trench 603 is adjusted by adjusting the exposure amount, so as to reduce the cost; of course, other width of the layout can also be used, which is not limited in the application.

[0110] ​​​Step S408: using a deposition process, form an interlayer dielectric layer 40 in the third trench 603 and on the top surface of the second epitaxial layer 12, and using a reflow process or a chemical mechanical planarization process to make the top surface flat, the interlayer dielectric layer 40 in the third trench 603 is used to form the extension 322. The specific structure is as shown in Figure 13 .

[0111] For example, the material of the interlayer dielectric layer 40 includes but is not limited to high-k dielectric constant materials, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3), etc.

[0112] In this embodiment, the extension 322 and the gate oxide layer 321 jointly form the dielectric layer 32 surrounding the outer surface of the sub-gate 31. Compared with the typical trench gate structure, the sub-gate 31 is spaced apart, and the orthographic projection area on the top surface of the drain is significantly reduced, so that a lower gate-drain capacitance C gd is obtained.

[0113] Step S410: etch the interlayer dielectric layer 40 to form a contact hole which is spaced apart along the OY direction and extends to the base region 122 along the OZ direction; and using a deposition process, form a metal layer 50 covering the top surface of the interlayer dielectric layer 40 and filling the contact hole, the metal layer 50 in the contact hole is used as the source electrode, and the specific structure is as shown in Figure 14 .

[0114] It should be understood that, Figure 14 the related drawings of forming an ohmic contact P-type heavily doped region with the second epitaxial layer 12 are omitted, which should not affect the normal understanding of those skilled in the art. In addition, after step S40, a back thinning process and back metallization are performed on the semiconductor structure prepared through step S410, and the specific structure of the power device is as shown in Figure 15 . Since it is not the focus of the scheme of the present application, it will not be described in detail here.

[0115] In some embodiments, step S410 can be changed to: etch the interlayer dielectric layer 40 to form contact holes which are alternately arranged along the OY direction and have different depths; wherein one contact hole extends to the base region 122 along the OZ direction, and the other contact hole extends into the extension 322 along the OZ direction, and the specific structure is as shown in Figure 16 .

[0116] In the above embodiment, the width and depth of the metal source electrode extending into the extension 322 are related to the gate-source capacitance size of the power device. By reasonably setting the size, the gate-source capacitance C gs can be further increased according to the application requirements, and greater C gs / Cgd .

[0117] In the above embodiments, the unexpected technical effect of this application is:

[0118] The power device provided in this application has a superjunction structure in the first epitaxial layer and the second epitaxial layer, which protects the bottom of the trench, shields the high electric field, and optimizes the internal electric field distribution. Under the same breakdown voltage, the on-resistance is significantly reduced, effectively optimizing the breakdown voltage and specific on-resistance of the device.

[0119] Meanwhile, by designing a split gate with twin gates, the facing area between the gate and drain terminals is reduced, effectively lowering the gate-drain capacitance C of the superjunction device. gd A metal layer is inserted between the two gate conductive layers as a metal source. By adjusting the depth of the metal source inserted into the split gate and its thickness in the extension, an adjustable gate-source capacitance C can be obtained. gs Thus, a C++ code that meets application requirements can be obtained. gs / C gd It is better adapted to the needs of various application scenarios.

[0120] In addition, the preparation method provided in this application is highly compatible with existing mainstream process platforms, has excellent process feasibility, and has outstanding engineering practical value.

[0121] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0122] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A power device, characterized by, The power device comprises a substrate and a first epitaxial layer and a second epitaxial layer which are sequentially stacked on a first surface of the substrate; the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; The second epitaxial layer comprises a plurality of split gates which extend along a first direction towards the substrate and are spaced apart along a second direction parallel to the first surface via a top surface of the second epitaxial layer, and ion columns which are in contact with the split gates; the gate trenches of the split gates are formed by one-step etching, and the size along the second direction is first kept unchanged and then gradually reduced in the first direction, and the bottom surface is above the top surface of the first epitaxial layer; The split gate comprises sub-gates which are spaced apart along the second direction, and a dielectric layer which surrounds the outer surface of the sub-gates; the dielectric layer comprises an extension between adjacent sub-gates; the extension comprises a metal source which extends into the extension via the top surface of the extension; The ion column is located directly below the extension which is arranged one-to-one, and is formed by ion implantation process based on a mask layer, and extends into the first epitaxial layer along the first direction; the conductive type of the ion column is opposite to that of the first epitaxial layer and the second epitaxial layer; the mask required for etching the mask layer is the same as that required for forming the extension.

2. The power device of claim 1, wherein, The second epitaxial layer comprises a source region and a base region which are sequentially arranged along the first direction via the top surface of the second epitaxial layer; The split gate penetrates the source region and the base region via the first direction.

3. The power device of claim 2, wherein, The dielectric layer comprises: A gate oxide layer which surrounds the contact interface between the split gate and the second epitaxial layer; The extension extends to be in contact with the gate oxide layer along the first direction; The top surface of the ion column is located within the bottom surface of the gate oxide layer.

4. The power device of claim 3, wherein, Further comprising: An interlayer dielectric layer which is located on the top surface of the second epitaxial layer; The extension and the interlayer dielectric layer are simultaneously prepared in the same process step.

5. The power device of claim 1, wherein, The width and the depth of the metal source are related to the gate-source capacitance of the power device; The depth is used to represent the size along the first direction, and the width is used to represent the size along the second direction.

6. A method of manufacturing a power device, characterized by, The power device of any one of claims 1-5, and a method for manufacturing the power device, comprising: Providing a substrate which is provided with a first epitaxial layer and a second epitaxial layer which are sequentially stacked; Forming a plurality of split gates which extend along a first direction towards the substrate and are spaced apart along a second direction parallel to the first surface via a top surface of the second epitaxial layer, and ion columns which are in contact with the split gates in the second epitaxial layer; The split gate comprises sub-gates which are spaced apart along the second direction, and a dielectric layer which surrounds the outer surface of the sub-gates; the dielectric layer comprises an extension between adjacent sub-gates; The ion column is located directly below the extension which is arranged one-to-one, and extends into the first epitaxial layer along the first direction; the conductive type of the ion column is opposite to that of the first epitaxial layer and the second epitaxial layer.

7. The production method according to claim 6, characterized by, forming the ion columns, comprising: forming a first trench in the second epitaxial layer; forming a sacrificial layer filling the first trench after forming the first trench; forming a mask layer in the first trench along the second direction and a second trench between adjacent mask layers after removing part of the sacrificial layer; 8. The production method according to claim 7, characterized by, forming the ion columns by ion implantation on the second epitaxial layer at the bottom of the second trench based on the mask layer. forming the dielectric layer, comprising: forming a gate oxide layer and a conductive material layer in the first trench along a direction opposite to the first direction after removing the mask layer; forming a third trench in the conductive material layer along the first direction and penetrating the conductive material layer; 9. The production method according to claim 8, characterized by, forming an interlayer dielectric layer in the third trench and on the top surface of the second epitaxial layer by a deposition process, the interlayer dielectric layer in the third trench is used to form the extension. further comprising: forming a contact hole in the interlayer dielectric layer, the contact hole is spaced along the second direction and extends to the second epitaxial layer along the first direction; 10. The method of claim 6, wherein, forming a metal layer filling the contact hole and covering the top surface of the interlayer dielectric layer, the metal layer in the contact hole is used to form a metal source. further comprising: forming a metal source in the split gate, the metal source extends into the extension through the top surface of the extension, and the width and depth of the metal source are related to the gate-source capacitance of the power device.

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