Chip detection device and method
The chip detection device realizes the full process of automatic detection of chips, solves the problems of low efficiency and poor adaptability in the existing technology, and improves the detection efficiency and fault location accuracy.
Patent Information
- Application Number
- CN202510868355.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-26
- Publication Date
- 2025-10-14
AI Technical Summary
Existing chip detection methods are inefficient, have fragmented detection processes, poor adaptability, rely on manual recording of detection results, and lack real-time analysis capabilities.
The chip detection device consists of a detachable chip test socket, test module, serial debugging module and communication module. It realizes full-process automated detection through hardware testing, serial debugging protocol connection testing, burning testing and fault analysis.
The phased detection steps have been streamlined, detection efficiency has been improved, the adaptability of the device has been increased, the fault point has been dynamically located, manual intervention has been reduced, and overall detection efficiency has been improved.
Smart Images
Figure CN120779205A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip detection technology, and in particular to a chip detection device and a chip detection method. Background Art
[0002] With the continuous advancement of semiconductor technology, chip integration has increased, and system complexity has significantly increased. Modern chips often contain millions or even billions of transistors, with highly complex internal structures and numerous signal paths. This makes them extremely susceptible to various factors during manufacturing, packaging, transportation, or actual operation, resulting in functional failures.
[0003] At present, in the chip production and application maintenance stages, common fault detection methods have the following main problems: the detection process is fragmented and the detection efficiency is low. The traditional method requires the use of different equipment in stages to complete short-circuit detection, program debugging, etc., which is inefficient; the adaptability is poor, and different packaged chips require customized fixtures to adapt to different equipment, which has high replacement costs; the data is isolated, and the detection results rely on manual recording and lack real-time analysis capabilities. Summary of the Invention
[0004] In view of the above problems, the embodiments of the present application are proposed to provide a chip detection device and a corresponding chip detection method that overcome the above problems or at least partially solve the above problems.
[0005] In order to solve the above problems, the present invention discloses a chip detection device, including:
[0006] Removable chip test socket for connecting to the chip;
[0007] A test module, connected to the chip test socket, for performing a hardware test on the chip to obtain a hardware test result; the hardware test result is used to determine whether the hardware test has passed;
[0008] a serial debugging module connected to the chip test socket, and configured to perform a serial debugging protocol connection test on the chip after the hardware test passes, extract and save the original firmware program of the chip, capture the register state of the chip, and perform a burn test on the chip to obtain a burn test result; the burn test result is used to determine whether the burn test passes;
[0009] A communication module is connected to the test module, the serial debugging module and the host computer, and is used to transmit the hardware test result and the burning test result to the host computer, so that the host computer performs a fault analysis according to the hardware test result when the hardware test fails; and performs a fault analysis according to the hardware test result and the burning test result when the burning test fails.
[0010] Optionally, it also includes:
[0011] A serial port module is connected to the chip test socket and the communication module, and is used to receive the decryption code sent by the host computer and decrypt the chip when the serial debugging protocol connection test fails on the chip;
[0012] The serial debugging module is further configured to perform a serial debugging protocol connection test on the chip again after decrypting the chip.
[0013] Optionally, the test module includes:
[0014] a short-circuit test module, configured to perform a short-circuit test on the chip when the chip is not powered on, and obtain a short-circuit test result; the short-circuit test result is used to determine whether the short-circuit test has passed;
[0015] A voltage measurement module is used to detect the voltage value of the preset pin of the chip after the short circuit test is passed, and obtain a voltage test result; the voltage test result is used to determine whether the voltage test is passed;
[0016] The communication module is used to transmit the short-circuit test result and the voltage test result to the host computer, so that the host computer performs a fault analysis based on the short-circuit test result when the short-circuit test fails; and performs a fault analysis based on the short-circuit test result and the voltage test result when the voltage test fails; the hardware test result includes the short-circuit test result and the voltage test result.
[0017] Optionally, it also includes:
[0018] A signal processing module is connected to the chip test socket and the communication module, and is used to convert the hardware test results and the burning test results into digital signals; the communication module is used to transmit the hardware test results and the burning test results converted into digital signals to the host computer.
[0019] Optionally, it also includes:
[0020] A slot is connected to the chip test socket, the test module, the serial debugging module and the serial port module.
[0021] Optionally, it also includes:
[0022] A power supply module is used to provide power to the chip detection device.
[0023] In a second aspect, an embodiment of the present application discloses a chip detection method, which is applied to the chip detection device described above, and the method includes:
[0024] Place the chip into the detachable chip test socket;
[0025] Performing a hardware test on the chip through a test module to obtain a hardware test result; the hardware test result is used to determine whether the hardware test has passed;
[0026] After the hardware test passes, a serial debugging protocol connection test is performed on the chip through a serial debugging module. After the serial debugging protocol connection test passes, the original firmware program of the chip is extracted and saved through the serial debugging module, the register state of the chip is captured, and a burning test is performed on the chip to obtain a burning test result; the burning test result is used to determine whether the burning test passes;
[0027] The hardware test result and the burning test result are transmitted to the host computer through the communication module, so that the host computer performs fault analysis according to the hardware test result when the hardware test fails; and performs fault analysis according to the hardware test result and the burning test result when the burning test fails.
[0028] Optionally, it also includes:
[0029] When the serial debugging protocol connection test on the chip fails, the decryption code sent by the host computer is received through the serial port module to decrypt the chip;
[0030] The serial debugging protocol connection test is performed on the chip through the serial debugging module, including:
[0031] After the chip is decrypted by the serial port module, a serial debugging protocol connection test is performed on the chip again by the serial debugging module.
[0032] Optionally, performing hardware testing on the chip through a testing module includes:
[0033] When the chip is not powered on, a short circuit test is performed on the chip by a short circuit test module to obtain a short circuit test result; the short circuit test result is used to determine whether the short circuit test is passed;
[0034] When the short circuit test passes, the voltage value of the preset pin of the chip is detected by the voltage measurement module to obtain a voltage test result; the voltage test result is used to determine whether the voltage test passes;
[0035] The method of transmitting the hardware test result to the host computer through the communication module includes:
[0036] The short-circuit test result and the voltage test result are transmitted to the upper computer through the communication module, so that the upper computer performs fault analysis according to the short-circuit test result when the short-circuit test fails, and performs fault analysis according to the short-circuit test result and the voltage test result when the voltage test fails; and the hardware test result includes the short-circuit test result and the voltage test result.
[0037] Optionally, further comprising:
[0038] The hardware test result and the burning test result are converted into digital signals through a signal processing module;
[0039] The hardware test result and the burning test result are transmitted to the upper computer through the communication module, including:
[0040] The hardware test result and the burning test result converted into digital signals are transmitted to the upper computer through the communication module.
[0041] The embodiments of the application include the following advantages:
[0042] The application provides a chip detection device, which comprises a detachable chip test seat configured to be connected with a chip; a test module connected with the chip test seat and configured to perform hardware testing on the chip to obtain a hardware test result; the hardware test result is used to determine whether the hardware testing is passed; a serial debugging module connected with the chip test seat and configured to perform serial debugging protocol connection testing on the chip after the hardware testing is passed, extract and save an original firmware program of the chip, capture a register state of the chip, and perform burning testing on the chip to obtain a burning test result; the burning test result is used to determine whether the burning testing is passed; and a communication module connected with the test module, the serial debugging module and an upper computer and configured to transmit the hardware test result and the burning test result to the upper computer, so that the upper computer performs fault analysis according to the hardware test result when the hardware testing fails, and performs fault analysis according to the hardware test result and the burning test result when the burning testing fails. The detection steps of using different devices in different stages are simplified, the hardware detection time is shortened, and the fault chip detection efficiency is significantly improved; the device supports different models of chips by replacing the chip test seat, and the adaptability of the device is improved; the test program is dynamically burned, the chip fault point is accurately positioned, and the fault positioning accuracy is improved; the detection device is fully automated, and manual intervention is not required from hardware detection to fault diagnosis, and the overall detection efficiency is greatly improved. BRIEF DESCRIPTION OF DRAWINGS
[0043] Figure 1 is a structural block diagram of a chip detection device provided by the embodiments of the application;
[0044] Figure 2 is a structural block diagram of another chip detection device provided by an embodiment of the present application;
[0045] Figure 3 is an appearance schematic diagram of a chip detection device provided by an embodiment of the present application;
[0046] Figure 4 is a step flowchart of a chip detection method provided by an embodiment of the present application.
[0047] Figure 5 is a scheme flowchart of a chip detection method provided by an embodiment of the present application;
[0048] Figure 6 is a detection flowchart of a chip detection method provided by an embodiment of the present application; DETAILED DESCRIPTION
[0049] In order to make the above-mentioned purposes, characteristics and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below in combination with the drawings and specific embodiments.
[0050] The existing chip fault detection technology involves reading chip data through a debugging interface, but generally does not cover the automatic decryption process of encrypted chips, and the test program is mostly in a fixed mode, lacking dynamic programming and multi-scene coverage; or predicting faults based on data analysis and AI algorithms, the core lies in the fault identification strategy at the software level; or analyzing chip defects based on multi-dimensional data (temperature, running state), but not involving hardware parameter detection or dynamic program programming.
[0051] One of the core ideas of the embodiments of the present application is to connect "hardware detection (resistance / diode characteristics / voltage), firmware extraction, programming test, fault analysis" into a closed-loop system, covering the whole process of chip fault diagnosis, far beyond a single function patent. The modular chip test socket in the scheme can also make the device adapt to different models of chips.
[0052] Referring to Figure 1 , a structural schematic diagram of a chip detection device provided by an embodiment of the present application is shown, which can specifically include the following structure:
[0053] The detachable chip test socket 10 is used to connect with the chip;
[0054] The chip test socket (hereinafter referred to as Socket) is a special jig used in the semiconductor testing process, which allows the chip to be mounted on the test equipment without welding, and the integrated circuit is connected to the circuit board in a plug-in manner for various electrical and functional tests.
[0055] Chip test sockets are designed to be reusable and can be used repeatedly for different testing procedures without damaging the chip. When replacing or upgrading a chip, the new chip can be removed from the socket and inserted directly, which is much easier than desoldering and resoldering. This reduces the risk of damage to the circuit board or chip during the soldering process. During the development phase, using a socket allows for convenient insertion and removal, facilitating testing of different components or troubleshooting.
[0056] Sockets are widely used in computers, servers, communications equipment, and other electronic products requiring high-density integration and high-performance computing capabilities. While some high-performance applications tend to directly solder the main chip to improve signal integrity and stability as technology evolves, sockets remain a valuable design choice in many cases, especially where flexibility and ease of maintenance are crucial.
[0057] In some embodiments of the present application, the chip test socket 10 is modular and replaceable, consisting of a PCB, a socket, the electronic components required for a minimum system, and a gold-plated female header. The corresponding modular socket can be selected based on the type of faulty chip, increasing the adaptability of the device.
[0058] The test module 11 is connected to the chip test socket 10 and is used to perform hardware testing on the chip to obtain hardware test results; the hardware test results are used to determine whether the hardware test has passed;
[0059] The purpose of testing a faulty chip is to locate the root cause of the fault, assess the extent of damage, and determine the feasibility of repair or scrapping. Accurately locating the fault point means that chip failures may be caused by design defects, manufacturing defects, electrical overstress (EOS), electrostatic discharge (ESD), or aging. Hardware testing can clearly determine whether it is physical damage (such as burning, package cracks) or logical errors (such as firmware bugs). For example, infrared thermal imaging can detect local overheating of a power management chip and confirm that it is an internal short circuit. Distinguishing between repairable and unrepairable faults means that some faults (such as external circuit damage and poor welding) can be restored through repair, while internal damage to the silicon chip (such as transistor breakdown) usually requires scrapping. For example, a BGA packaged chip with a cold solder joint can be repaired through reflow soldering, but a core power short circuit requires chip replacement. Verifying the scope of the fault impact means confirming whether the fault has spread to the surrounding circuits (such as whether the short circuit has burned the PCB traces or adjacent components).
[0060] The main steps of hardware testing are: appearance inspection, generally using an optical microscope or electron microscope to check for package cracks, pin oxidation, burn marks, and welding defects (cold solder joints, bridging), etc.; using a multimeter, oscilloscope, LCR meter, or ATE (automatic test equipment) to perform a power short-circuit test and measure the impedance between VCC / VSS. The normal value should be >1kΩ (if close to 0Ω, it indicates an internal short circuit); signal pin leakage, check the leakage current of the IO pin to ground / power supply (if >1mA, it may be damaged).
[0061] In some embodiments of the present application, the principle of test module 11 is similar to that of a multimeter, comprising a constant current source, a voltage measurement unit, and a multi-way switch matrix for switching the pins of the chip under test. The hardening test performed by test module 11 primarily tests the resistance of all chip pins to ground, the resistance of each pin to all other pins, the diode characteristics of each pin to ground, the diode characteristics of each pin to the power supply, and key voltage values such as pins VCC, VDDCORE, XIN, and XOUT. The test results are used to determine whether the hardware test has passed. If so, the next test step is performed. If the test fails, the chip fault is detected in the hardware, resulting in a fault detection result.
[0062] A serial debugging module 12 is connected to the chip test socket 10 and is used to perform a serial debugging protocol connection test on the chip after the hardware test passes. After the serial debugging protocol connection test passes, the original firmware program of the chip is extracted and saved, the register state of the chip is captured, and a burn test is performed on the chip to obtain a burn test result; the burn test result is used to determine whether the burn test passes;
[0063] The SWD module is a highly efficient, low-pin count debug interface protocol designed for Cortex-M series microcontrollers (such as the STM32, GD32, and NXP LPC). It is used for development and debugging tasks such as program downloading, in-circuit debugging, and register / memory access. Compared to the traditional JTAG interface, SWD requires only two signal lines (SWDIO and SWCLK), making the hardware connection simpler and occupying fewer pin resources.
[0064] The main feature of SWD is that SWD uses two wires - SWDIO (bidirectional data I / O) and SWCLK (clock) for communication, which makes it more compact than the JTAG interface that requires five or more wires. Although SWD is designed for the ARM architecture, it can work with other non-ARM devices that support the protocol. Debugging functions include basic debugging operations such as breakpoint setting, single-step execution, memory reading and writing, as well as more advanced functions such as tracing and performance analysis. Programming capabilities In addition to debugging, SWD can also be used to download code or firmware updates to the target device.
[0065] The SWD interface is widely used in the field of embedded development, especially in development boards, evaluation kits and personal projects. Engineers use the SWD interface to debug their software and burn new programs into microcontrollers. Through a dedicated debugger (such as Segger J-Link, ST-LINK, etc.), developers can easily establish a connection with the target device and achieve an efficient development process. Using the SWD interface can reduce pin requirements: since only two wires are required, this reduces the demand for microcontroller pins, allowing more pins to be used for other functions, simplifying hardware design, reducing production costs, providing a simple and intuitive debugging experience, and improving development efficiency.
[0066] In some embodiments of the present application, when the hardware test passes and no fault is found, subsequent fault detection, i.e., functional verification, is performed. Generally, the chip ID register is read through JTAG / SWD to confirm whether communication is possible. In view of the above advantages of SWD, this application selects the SWD module for functional testing.
[0067] The serial debug module 12 (SWD module, hereinafter referred to as the SWD module) includes an SWD interface and is responsible for reading and burning the program of the faulty chip. It first attempts to connect to the SWD to perform a serial debug protocol connection test. If the connection is successful, it indicates that the serial debug protocol connection test has passed. Then, the firmware is extracted, the original program is saved, and the chip register status is captured. After the serial debug module 12 is connected to the chip test socket 10, it is equivalent to establishing a connection with the chip.
[0068] Extracting firmware reads the chip's flash memory via the SWD debug interface and transfers the firmware to a computer. Saving the original program saves the currently running program state to a file for later analysis or restoration. Capturing register state reads the target chip's register values and displays or saves them for program state analysis.
[0069] Then, the faulty chip is burned and tested. In some embodiments of the present application, the burn test is not a single test, but a burn test with multiple programs to eliminate and determine the fault point. The burn program will prioritize the dynamic loading of relevant modules based on the fault description, such as pre-stored programs for different modules such as SPI, I2C, SDRAM, etc., and these dynamic test program libraries support online updates and adapt to new chips. Finally, when the automatic burn test program is automatically burned, the running status is monitored in real time. Based on the program running results (such as the dead position), it is determined whether the burn test has passed. If it has not passed, the fault point can be determined based on the burn test results, which facilitates the subsequent generation of a fault analysis report.
[0070] The burn test process prioritizes high-priority modules: modules related to the fault are tested first to locate the problem as quickly as possible. Based on the test results, the selection and priority of subsequent test modules are dynamically adjusted, thus reducing ineffective testing time.
[0071] The communication module 13 is connected to the test module 11, the serial debugging module 12 and the host computer, and is used to transmit the hardware test results and the burning test results to the host computer, so that the host computer can perform a fault analysis based on the hardware test results when the hardware test fails; and perform a fault analysis based on the hardware test results and the burning test results when the burning test fails.
[0072] In some embodiments of the present application, the chip detection device is connected to a host computer, combining hardware and software to detect chip faults. At the same time, based on the test results and software analysis data, AI is used for analysis to obtain a fault analysis report. Among them, the communication module 13 takes on the important task of connecting the hardware detection module to the host computer. The communication module 13 includes a USB interface and is directly connected to the host computer. The host computer can be a desktop computer or a laptop computer, etc., which monitors data and performs fault analysis by installing software.
[0073] By connecting the communication module 13 to the test module 11, the hardware test results of the chip can be directly connected to the host computer. When the hardware test fails, the software and AI analysis of the host computer can perform fault analysis on the chip based on the hardware test results.
[0074] The communication module 13 is connected to the serial debugging module 12 (SWD module), so that the software on the host computer can be indirectly connected to the chip without any malicious intention, and the burned data of the chip is monitored to facilitate subsequent fault analysis.
[0075] In some embodiments of the present application, steps such as extracting firmware, saving the original program, and capturing register status are completed collaboratively through several modules or components such as debugging tools and corresponding software development kits (SDKs) (that is, the hardware aspect includes the SWD module 12, and the software aspect includes a debugging module). Among them, the debugging adapter (such as J-Link) provides a physical connection, communicates with the faulty chip through the SWD interface, is responsible for transmitting debugging commands from the computer to the faulty chip, and returns the chip status information to the computer. Burning tools (J-Link Commander, J-Mem, J-Flash) are specifically used for programming and debugging chips; debugging software (such as Keil uVision) provides a graphical user interface and a command line interface for sending debugging commands and displaying debugging information.
[0076] The present application provides a chip detection device, including a detachable chip test socket for connecting to the chip; a test module connected to the chip test socket for performing hardware testing on the chip to obtain hardware test results; the hardware test results are used to determine whether the hardware test passes; a serial debugging module connected to the chip test socket for performing a serial debugging protocol connection test on the chip after the hardware test passes, extracting and saving the original firmware program of the chip, capturing the register state of the chip, and performing a burn test on the chip to obtain a burn test result; the burn test result is used to determine whether the burn test passes; a communication module connected to the test module, the serial debugging module and the host computer, for transmitting the hardware test results and the burn test results to the host computer, so that the host computer can perform fault analysis based on the hardware test results when the hardware test fails; and when the burn test fails, performing fault analysis based on the hardware test results and the burn test results. The detection steps of using different equipment in stages have been streamlined, shortening the hardware detection time and significantly improving the efficiency of faulty chip detection; by replacing the chip test socket, the device can support different types of chips, increasing the adaptability of the device; the test program is dynamically burned to accurately locate the chip fault point and increase the accuracy of fault location; this detection device is fully automated, and no human intervention is required from hardware detection to fault diagnosis, greatly improving the overall detection efficiency.
[0077] Reference Figure 2 , shows a structural block diagram of another chip detection device provided by an embodiment of the present application. In addition to the structures mentioned in the above embodiments, the device may specifically include the following structures:
[0078] The serial port module 14 is connected to the chip test socket 10 and the communication module 13, and is used to receive the decryption code sent by the host computer and decrypt the chip when the serial debugging protocol connection test fails on the chip;
[0079] The serial port module, also known as the UART module, includes a UART interface and is responsible for decrypting and transmitting codes and coordinating fault detection. UART (Universal Asynchronous Receiver / Transmitter) is a serial communication protocol used to transmit data between devices. It uses asynchronous serial communication (without clock signal synchronization) to send and receive data and is widely used in embedded systems, sensors, Bluetooth / Wi-Fi modules, and debugging interfaces (such as serial printing). UART communication is accomplished through two signal lines: RX (receive data) and TX (transmit data). These two signal lines allow for bidirectional data exchange between two devices.
[0080] The characteristics of UART communication are: asynchronous communication, which does not require a synchronous clock signal, but relies on start and stop bits to achieve data frame synchronization; baud rate matching, both communicating parties need to set the same baud rate (that is, the number of bits transmitted per second), common baud rates are 9600, 19200, 38400, 57600, 115200, etc.; the data format usually contains a start bit, 5 to 9 data bits, an optional parity bit and one or two stop bits.
[0081] The main features are: The UART protocol is relatively simple, easy to implement, and suitable for short-distance communication; due to its simple hardware requirements, UART provides a cost-effective communication solution; it is often used for communication between microcontrollers and between microcontrollers and peripheral devices (such as GPS modules, Bluetooth modules, sensors, etc.).
[0082] UART application scenarios: Embedded system development, as a debug port, allowing developers to communicate directly with the device to monitor status or upload firmware updates; industrial automation, used to connect different control devices and sensors; consumer electronics, for example, for communication between devices in smart home devices; computer hardware, early PCs supported RS-232 standard serial ports through the UART interface.
[0083] UART functionality can be implemented in a variety of ways: dedicated hardware modules. Many microcontrollers have built-in UART hardware modules, which simplifies programming. Software simulation. In resource-constrained environments, UART functionality can also be simulated through software, but this will take up more CPU resources.
[0084] In some embodiments of the present application, the serial port module 14 is connected to the chip test socket 10, so that the serial port module (UART module) 14 can be connected to the chip. At the same time, the serial port module 14 is connected to the communication module 13, which can indirectly connect the chip to the host computer, so that the host computer can automatically process the encryption chip and send the password decryption through the UART module.
[0085] When the serial debugging protocol connection test fails on the chip, the serial debugging module 12 receives the decryption code sent by the host computer and decrypts the chip. Specifically, it connects to the host software via the UART module. After entering the password, the UART automatically sends the decryption code according to the set program, saving the time of converting the digital password into hexadecimal password.
[0086] In one embodiment, the serial debugging module 12 is further configured to perform a serial debugging protocol connection test on the chip again after decrypting the chip.
[0087] SWD is an interface technology used for embedded debugging, mainly used for ARM Cortex-M series controllers. It is an efficient debugging and programming interface, and its communication efficiency is usually higher than JTAG. This application uses the SWD interface and serial debugging module 12 for burning test, so whether SWD can be connected is related to decryption. When the encryption mechanism of the chip is ensured to be effective, reverse engineering through the SWD interface can be prevented. If the chip is encrypted, the chip cannot be connected for debugging and programming, so it is judged whether SWD can be connected. When the SWD interface is successfully connected, it means that the development tool chain (such as compiler, debugger) is configured correctly and can communicate with the chip; when the SWD interface fails to connect, either the chip has not been decrypted or the chip is damaged. After the decryption operation, if it still cannot be connected, the chip is damaged. If the connection is successful, continue with the next detection process.
[0088] After the UART module receives the host's password to decrypt the chip, it performs a serial debugging protocol connection test on the chip through the serial debugging module 12 to determine whether the failure of the serial debugging protocol connection test on the chip by the serial debugging module 12 is due to a chip failure. After eliminating the cause of non-decryption, a subsequent burning test is performed to confirm the chip failure point.
[0089] A signal processing module 15 is connected to the chip test socket 10 and the communication module 13 and is used to convert the hardware test results and the burning test results into digital signals;
[0090] Since the data obtained from each hardware structure test cannot be directly used by the host computer software, a signal processing module 15 is set up to convert the hardware test results and the burning test results into digital signals recognizable by the host computer by connecting with the chip test socket 10 and the communication module 13.
[0091] In one embodiment, the communication module 13 is used to transmit the hardware test results and the burning test results converted into digital signals to the host computer.
[0092] The hardware test results and burning test results converted into digital signals after being processed by the signal processing module 15 are then transmitted to the host computer through the communication module 13, and can be recognized by the software in the host computer and perform subsequent AI fault analysis.
[0093] The slot 16 is connected to the chip test socket 10 , the test module 11 , the serial debugging module 12 and the serial port module 14 .
[0094] Reference Figure 3 , shows a schematic diagram of the appearance of a chip detection device provided in an embodiment of the present application.
[0095] The slot 16 is connected to the test module 11, the serial debugging module 12 and the serial port module 14. Figure 3 The cube-like structure in the middle and lower part has a gold-plated pin header in slot 16. Figure 3 The gold-plated female header of the replaceable modular chip test socket 10 above is adapted to correspond. The gold-plated female header is used to ensure good contact between the pins of the chip and the gold-plated pins of the device, so that the detection device can adapt to chips of different models and different packages.
[0096] In one embodiment, the testing module 11 includes:
[0097] The short circuit test module 110 is used to perform a short circuit test on the chip when the chip is not powered on, and obtain a short circuit test result; the short circuit test result is used to determine whether the short circuit test is passed;
[0098] Performing a short-circuit test on a faulty chip is an important step in determining if there are any electrical connection anomalies, such as short circuits or low-impedance paths. This test helps identify potential problems within the chip's internal or external circuits, such as shorts in wires caused by manufacturing defects, physical damage, or aging.
[0099] In some embodiments of the present invention, the short circuit test is performed in a power-off state, that is, the device is powered on, but the chip is not powered on, and includes testing the resistance of all pins to ground, the resistance of each pin to all other pins, the diode characteristics of each pin to ground, and the diode characteristics of each pin to the power supply.
[0100] The ground diode characteristic refers to the diode characteristics between a chip pin and ground (GND), while the power diode characteristic refers to the diode characteristics between a chip pin and power (VCC). These characteristics describe the forward conduction and reverse blockage characteristics of the diode junction between the chip pin and ground or power. Testing these characteristics can help verify the normal operation of the chip pin and detect short circuits, open circuits, or abnormal leakage current. To test the ground diode characteristic with a multimeter, connect the black probe to ground and the red probe to the chip pin, and read the voltage displayed in the multimeter's diode test mode. To test the power diode characteristic with a multimeter, connect the red probe to power and the black probe to the chip pin, and read the voltage displayed in the multimeter's diode test mode.
[0101] In some embodiments provided herein, the short-circuit test module 110 employs the same testing principles as a multimeter, which can save time compared to manual testing. This is especially true when the number of chip pins is large, small, and densely packed. Manual multimeter testing can be difficult and time-consuming to accurately connect the chip pins. The pin testing method of the present application can accurately test all chip pins sequentially and efficiently.
[0102] The voltage measurement module 111 is used to detect the voltage value of the preset pin of the chip after the short circuit test is passed, and obtain a voltage test result; the voltage test result is used to determine whether the voltage test is passed;
[0103] When the short-circuit test passes and no fault points are determined, the next step of testing, namely voltage testing, is carried out. By measuring the voltage value on each pin and comparing it with the expected operating voltage, it can help identify whether the chip is working properly or has potential faults.
[0104] In some embodiments provided in the present application, after detecting the resistance value and diode characteristics of the faulty chip pin in the power-off state, when the short-circuit test passes, that is, when it is confirmed that there is no short circuit, the power supply is started, and after power-on, the voltage values of key pins such as VCC, VDDCORE, XIN, and XOUT (i.e., preset pins) are tested, and the voltage test results are used to determine whether the voltage test passes.
[0105] In one embodiment, the communication module 13 is used to transmit the short-circuit test result and the voltage test result to the host computer, so that the host computer performs a fault analysis based on the short-circuit test result when the short-circuit test fails; and performs a fault analysis based on the short-circuit test result and the voltage test result when the voltage test fails; the hardware test result includes the short-circuit test result and the voltage test result.
[0106] In some embodiments provided in the present application, the communication module 13 will send the short-circuit test result to the host computer. If the host computer detects that the short-circuit test result fails, that is, there is a fault point, the host computer will send it to the AI analysis software to generate a fault analysis report based on the short-circuit test result. If the short-circuit test result passes, the voltage test will continue. Then the communication module 13 will send the short-circuit test result and the voltage test result to the host computer. If the voltage test fails, the host computer will send it to the AI analysis software to generate a fault analysis report based on the short-circuit test result and the voltage test result. The short-circuit test result and the voltage test result here both belong to the hardware test results mentioned above.
[0107] The power supply module 17 is used to provide power to the chip detection device.
[0108] The power supply module 17 mainly provides appropriate power to the device and the faulty chip so that the circuit is powered on to complete subsequent detection.
[0109] The present application provides a chip detection device, including a detachable chip test socket for connecting to the chip; a test module connected to the chip test socket for performing hardware testing on the chip to obtain hardware test results; the hardware test results are used to determine whether the hardware test passes; a serial debugging module connected to the chip test socket for performing a serial debugging protocol connection test on the chip after the hardware test passes, extracting and saving the original firmware program of the chip, capturing the register state of the chip, and performing a burn test on the chip to obtain a burn test result; the burn test result is used to determine whether the burn test passes; a communication module connected to the test module, the serial debugging module and the host computer, for transmitting the hardware test results and the burn test results to the host computer, so that the host computer can perform fault analysis based on the hardware test results when the hardware test fails; and when the burn test fails, performing fault analysis based on the hardware test results and the burn test results. The system streamlines the detection steps of using different devices in different stages, shortens a lot of time for hardware detection (resistance / diode characteristics / voltage), and significantly improves the efficiency of fault chip detection. By replacing the modular socket, the device supports different types of chips, increasing the adaptability of the device. The host software is connected through the UART module. After entering the password, the UART automatically sends the code decryption through the set program, saving the time of converting the digital password into a hexadecimal password. The dual parameter cross-validation of resistance and diode avoids the misjudgment of a single indicator and reduces the misjudgment rate. The real-time data feedback of electrical parameters and the dynamic burning of the test program accurately locate the chip fault point and increase the accuracy of fault location. The entire process of this detection device is automated, and no manual intervention is required from hardware detection to fault diagnosis, which greatly improves the overall detection efficiency.
[0110] Reference Figure 4, a step flow chart of a chip detection method provided by an embodiment of the present application is shown, and the method can specifically include the following steps:
[0111] Step 401, placing a chip into a detachable chip test seat;
[0112] Step 402, performing hardware testing on the chip by a test module to obtain a hardware testing result; the hardware testing result is used to determine whether the hardware testing is passed;
[0113] In some embodiments of the application, the step 402 specifically includes the following sub-steps:
[0114] Sub-step S11, performing short circuit testing on the chip by a short circuit test module when the chip is not powered on to obtain a short circuit testing result; the short circuit testing result is used to determine whether the short circuit testing is passed;
[0115] Sub-step S12, detecting a voltage value of a preset pin of the chip by a voltage measurement module when the short circuit testing is passed to obtain a voltage testing result; the voltage testing result is used to determine whether the voltage testing is passed;
[0116] Sub-step S13, transmitting the hardware testing result to an upper computer by a communication module, including:
[0117] Sub-step S14, transmitting the short circuit testing result and the voltage testing result to the upper computer by the communication module, so that the upper computer performs fault analysis according to the short circuit testing result when the short circuit testing is not passed, and performs fault analysis according to the short circuit testing result and the voltage testing result when the voltage testing is not passed; the hardware testing result includes the short circuit testing result and the voltage testing result.
[0118] Step 403, after the hardware testing is passed, performing serial debugging protocol connection testing on the chip by a serial debugging module, after the serial debugging protocol connection testing is passed, extracting an original firmware program of the chip and saving by the serial debugging module, capturing a register state of the chip, and performing burning testing on the chip to obtain a burning testing result; the burning testing result is used to determine whether the burning testing is passed;
[0119] Step 404, transmitting the hardware testing result and the burning testing result to an upper computer by a communication module, so that the upper computer performs fault analysis according to the hardware testing result when the hardware testing is not passed, and performs fault analysis according to the hardware testing result and the burning testing result when the burning testing is not passed.
[0120] Reference Figure 5, showing a flow chart of a chip detection method provided by an embodiment of the present application. First, the replaceable modular socket ensures that the device is adaptable to faulty chips of different models and packages. Then, "hardware detection (resistance / diode characteristics / voltage) → decryption / firmware extraction → dynamic burn test → AI analysis" are connected in series into a closed-loop system, covering the entire process of chip fault diagnosis.
[0121] In some embodiments of the present application, the method further comprises:
[0122] When the serial debugging protocol connection test on the chip fails, the decryption code sent by the host computer is received through the serial port module to decrypt the chip;
[0123] The serial debugging protocol connection test of the chip is performed by the serial debugging module in step 403, which specifically includes the following sub-steps:
[0124] After the chip is decrypted by the serial port module, a serial debugging protocol connection test is performed on the chip again by the serial debugging module.
[0125] In some embodiments of the present application, the method further comprises:
[0126] Converting the hardware test result and the burning test result into digital signals through a signal processing module;
[0127] The step 403 of transmitting the hardware test result and the burning test result to the host computer through the communication module specifically includes the following sub-steps:
[0128] The hardware test result and the burning test result converted into digital signals are transmitted to the host computer through the communication module.
[0129] Reference Figure 6 , shows a detection flow chart of a chip detection method provided in an embodiment of the present application.
[0130] First, install the modular socket and put in the faulty chip; then perform short-circuit detection in the power-off state, including testing the resistance of all pins to ground, the resistance of each pin to all other pins, the diode characteristics of each pin to ground, and the diode characteristics of each pin to the power supply. After the test, the test results will be judged. If abnormal, they will be fed back to the host computer AI for analysis and an analysis report will be generated. If the test is normal, the power-on test will be started; after power-on, key voltage values such as VCC, VDDCORE, XIN, and XOUT will be tested. If abnormal, they will be fed back to the host computer AI for analysis and an analysis report will be generated. If normal, the decryption / firmware extraction link will be entered; after trying to connect to SWD, a judgment will be made. If the connection is successful, the firmware will be extracted, the original program will be saved, the register status will be captured, etc. If the connection fails, the decryption software will pop up on the host computer. After entering the digital password, the UART module will Receive the password of the host computer and send the code to decrypt the chip, then try to connect to SWD again. If it fails this time, it will feedback to the host computer AI analysis and generate an analysis report. If the connection is successful, it will extract the firmware, save the original program, capture the register status, etc.; then erase the original program and perform a dynamic burning test. The program will prioritize dynamic loading of related modules according to the fault description, such as pre-stored programs for different modules such as SPI, I2C, SDRAM, and these dynamic test program libraries support online updates and adapt to new chips; finally, when automatically burning the test program, the running status is monitored in real time, and the program running results (such as the dead position) or the test results fed back by the hardware detection module and the UART module (such as the program debugging GPIO pin output high level and other signals) will be fed back to the host computer AI analysis, and the AI analysis will locate the fault point and generate an analysis report.
[0131] Take the detection of QFP-48 packaged chips as an example: first, select a modular socket compatible with QFP-48, whose 48 gold-plated pins correspond one-to-one to the internal pins of the chip; after connecting the power cord, SWD interface, UART interface, and USB interface, the computer controls the test module through the USB interface to perform automated measurements. After the device is powered on (the faulty chip is not powered on), the multi-way switch matrix turns on pins 1 to 48 in a preset sequence; for each pin, first measure the resistance to ground (for example, apply a 1mA current and measure the voltage difference), then switch to diode mode (apply a 10mA constant current and detect a 0.6-0.7V voltage drop); the data is uploaded to the computer software via USB, and the software automatically compares it to the standard value. If the resistance value is lower than the threshold or the diode voltage drop is abnormal, it is marked as a faulty pin and fed back to the AI for analysis to generate an analysis report;
[0132] After testing the resistance and diode characteristics of the faulty chip pins in the power-off state, the power supply is turned on after confirming that there is no short circuit. After powering on, the voltage values of key pins such as VCC, VDDCORE, XIN, and XOUT are tested. If abnormal, the voltage values are fed back to the AI for analysis, and an analysis report is generated. If normal, the decryption / firmware extraction phase begins. Next, the chip program is read and backed up through the SWD interface or UART decryption interface. After attempting to connect to the SWD, a judgment is made. If the connection is successful, the firmware is extracted, the original program is saved, and the register status is captured. If the connection fails, the decryption software pops up. After entering the digital password, the UART module sends the code for decryption, and then attempts to connect to the SWD again. If this fails again, the code is fed back to the AI for analysis and an analysis report is generated. If the connection is successful, the firmware is extracted, the original program is saved, and the register status is captured. The debugger module integrates a J-LINK emulator and supports the SWD protocol of the ARM Cortex-M series chips. The UART communication module includes a level conversion circuit and is compatible with 3.3V / 5V chips. In terms of security mechanisms, the decryption password is transmitted through an encrypted channel to prevent interception.
[0133] Extract the firmware, save the original program, erase the original program, and burn the preset test program set. The backed-up original firmware is stored in an isolated security area to prevent accidental erasure. When dynamically burning the test program, the program will prioritize dynamic loading of related modules based on the fault description to reduce invalid testing time, such as pre-stored programs for different modules such as SPI, I2C, SDRAM, and these dynamic test program libraries support online updates and adapt to new chips. Finally, when automatically burning the test program, the program running status is monitored in real time. The program running results (such as the dead position) or the test results fed back by the hardware detection module and the UART module (such as the program debugging GPIO pin output high level and other signals) will be fed back to the AI analysis, and the AI analysis will locate the fault point and finally generate an analysis report.
[0134] The present application provides a chip detection method, which simplifies the detection steps of using different devices in stages, shortens a lot of time for hardware detection (resistance / diode characteristics / voltage), and significantly improves the efficiency of fault chip detection; by replacing the modular Socket seat, the device supports different types of chips, increasing the adaptability of the device; connects to the host software through the UART module, and after entering the password, the UART automatically sends the code decryption through the set program, saving the time of converting the digital password into a hexadecimal password; through the cross-validation of the resistance and diode dual parameters, avoids the misjudgment of a single indicator and reduces the misjudgment rate; real-time data feedback of electrical parameters and dynamic burning of test programs accurately locate the chip fault point and increase the accuracy of fault location; this detection device is fully automated, and no human intervention is required from hardware detection to fault diagnosis, greatly improving the overall detection efficiency.
[0135] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.
[0136] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0137] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0138] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.
[0139] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0140] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.
[0141] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.
[0142] The above is a detailed introduction to a chip detection device and a chip detection method provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A chip detection device, characterized in that: include: Removable chip test socket for connecting to the chip; A test module, connected to the chip test socket, for performing a hardware test on the chip to obtain a hardware test result; the hardware test result is used to determine whether the hardware test has passed; a serial debugging module connected to the chip test socket, and configured to perform a serial debugging protocol connection test on the chip after the hardware test passes, extract and save the original firmware program of the chip, capture the register state of the chip, and perform a burn test on the chip to obtain a burn test result; the burn test result is used to determine whether the burn test passes; A communication module is connected to the test module, the serial debugging module and the host computer, and is used to transmit the hardware test result and the burning test result to the host computer, so that the host computer performs a fault analysis according to the hardware test result when the hardware test fails; and performs a fault analysis according to the hardware test result and the burning test result when the burning test fails.
2. The chip detection device according to claim 1, characterized in that: Also includes: A serial port module is connected to the chip test socket and the communication module, and is used to receive the decryption code sent by the host computer and decrypt the chip when the serial debugging protocol connection test fails on the chip; The serial debugging module is further configured to perform a serial debugging protocol connection test on the chip again after decrypting the chip.
3. The chip detection device according to claim 1, characterized in that: The test module includes: a short-circuit test module, configured to perform a short-circuit test on the chip when the chip is not powered on, and obtain a short-circuit test result; the short-circuit test result is used to determine whether the short-circuit test has passed; A voltage measurement module is used to detect the voltage value of the preset pin of the chip after the short circuit test is passed, and obtain a voltage test result; the voltage test result is used to determine whether the voltage test is passed; The communication module is used to transmit the short-circuit test result and the voltage test result to the host computer, so that the host computer performs a fault analysis based on the short-circuit test result when the short-circuit test fails; and performs a fault analysis based on the short-circuit test result and the voltage test result when the voltage test fails; the hardware test result includes the short-circuit test result and the voltage test result.
4. The chip detection device according to claim 1, characterized in that: Also includes: A signal processing module, connected to the chip test socket and the communication module, for converting the hardware test results and the burning test results into digital signals; The communication module is used to transmit the hardware test results and the burning test results converted into digital signals to the host computer.
5. The chip detection device according to claim 2, characterized in that: Also includes: A slot is connected to the chip test socket, the test module, the serial debugging module and the serial port module.
6. The chip detection device according to claim 1, characterized in that: Also includes: A power supply module is used to provide power to the chip detection device.
7. A chip detection method, characterized in that: Applied to the chip detection device according to claims 1-6, the method comprises: Place the chip into the detachable chip test socket; Performing a hardware test on the chip through a test module to obtain a hardware test result; the hardware test result is used to determine whether the hardware test has passed; After the hardware test passes, a serial debugging protocol connection test is performed on the chip through a serial debugging module. After the serial debugging protocol connection test passes, the original firmware program of the chip is extracted and saved through the serial debugging module, the register state of the chip is captured, and a burning test is performed on the chip to obtain a burning test result; the burning test result is used to determine whether the burning test passes; The hardware test result and the burning test result are transmitted to the host computer through the communication module, so that the host computer performs fault analysis according to the hardware test result when the hardware test fails; and performs fault analysis according to the hardware test result and the burning test result when the burning test fails.
8. The chip detection method according to claim 7, characterized in that: Also includes: When the serial debugging protocol connection test on the chip fails, the decryption code sent by the host computer is received through the serial port module to decrypt the chip; The serial debugging protocol connection test is performed on the chip through the serial debugging module, including: After the chip is decrypted by the serial port module, a serial debugging protocol connection test is performed on the chip again by the serial debugging module.
9. The chip detection method according to claim 7, characterized in that: The hardware testing of the chip by the testing module includes: When the chip is not powered on, a short circuit test is performed on the chip by a short circuit test module to obtain a short circuit test result; the short circuit test result is used to determine whether the short circuit test is passed; When the short circuit test passes, the voltage value of the preset pin of the chip is detected by the voltage measurement module to obtain a voltage test result; the voltage test result is used to determine whether the voltage test passes; The method of transmitting the hardware test result to the host computer through the communication module includes: The short-circuit test result and the voltage test result are transmitted to the host computer through the communication module, so that when the short-circuit test fails, the host computer performs a fault analysis based on the short-circuit test result; and when the voltage test fails, the host computer performs a fault analysis based on the short-circuit test result and the voltage test result; the hardware test result includes the short-circuit test result and the voltage test result.
10. The chip detection method according to claim 7, characterized in that: Also includes: Converting the hardware test result and the burning test result into digital signals through a signal processing module; The method of transmitting the hardware test result and the burning test result to the host computer through the communication module includes: The hardware test result and the burning test result converted into digital signals are transmitted to the host computer through the communication module.