Floating point multiplication method and floating point multiplication circuit

Abstract

The application provides a floating-point multiplication method and a floating-point multiplication circuit, and relates to the technical field of processors. The method comprises the following steps: obtaining a shift result of the product of a first floating-point number and a second floating-point number; the shift result is the result of a shift operation on the decimal part of the product; performing a mantissa rounding operation on the shift result to obtain a mantissa rounding result of the shift result; obtaining a first judgment result of whether the mantissa satisfies a first preset rounding condition in the process of the mantissa rounding operation; if the first judgment result is that the mantissa satisfies the first preset rounding condition, obtaining a target mantissa of the multiplication result of the first floating-point number and the second floating-point number according to the mantissa rounding result. The floating-point multiplication method has the advantage of short operation period.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processors, and particularly relates to a floating-point multiplication method and a floating-point multiplication circuit. BACKGROUND

[0002] In the floating-point multiplication process, after the shift result of the floating-point product is obtained, the shift result needs to be subjected to a mantissa rounding processing.

[0003] In the related art, the shift result is first obtained, then the mantissa part of the shift result is subjected to rounding analysis, and an analysis result of whether the mantissa needs to be rounded is obtained. If rounding is needed, the mantissa part is subjected to rounding processing, and a rounding processing result is obtained.

[0004] However, this method needs to first obtain the rounding analysis result, and then perform the mantissa rounding processing in the case of needing rounding, which leads to a long processing period of the mantissa rounding and a long floating-point multiplication period. SUMMARY

[0005] Embodiments of the present application provide a floating-point multiplication method and a floating-point multiplication circuit to solve the problem of a long floating-point multiplication period in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a floating-point multiplication method, including: obtaining a shift result of a product of a first floating-point number and a second floating-point number; the shift result is a result of a shift operation on a decimal part of the product; performing a mantissa rounding operation on the shift result to obtain a mantissa rounding result of the shift result; in the process of performing the mantissa rounding operation, obtaining a first judgment result of whether the mantissa satisfies a first preset rounding condition; if the first judgment result is that the mantissa satisfies the first preset rounding condition, obtaining a target mantissa of a multiplication result of the first floating-point number and the second floating-point number according to the mantissa rounding result.

[0007] In a second aspect, an embodiment of the present application provides a floating-point multiplication circuit, which comprises a shift result obtaining unit, a mantissa rounding operation unit connected to the shift result obtaining unit, a rounding condition judging unit connected to the shift result obtaining unit, and a first multiplexer connected to the mantissa rounding operation unit and the rounding condition judging unit; the shift result obtaining unit is configured to obtain a shift result of a product of a first floating-point number and a second floating-point number; the shift result is a result of a shift operation on a decimal part of the product; the mantissa rounding operation unit is configured to perform a mantissa rounding operation on the shift result to obtain a mantissa rounding result of the shift result; the first judging result obtaining unit is configured to obtain a first judging result of whether the mantissa satisfies a first preset rounding condition during the mantissa rounding operation; and the first multiplexer is configured to obtain a target mantissa of a multiplication result of the first floating-point number and the second floating-point number according to the mantissa rounding result if the first judging result is that the mantissa satisfies the first preset rounding condition.

[0008] In a third aspect, an embodiment of the present application further provides a floating-point multiplication device, which comprises: a first obtaining module configured to obtain a shift result of a product of a first floating-point number and a second floating-point number; the shift result is a result of a shift operation on a decimal part of the product; a second obtaining module configured to perform a mantissa rounding operation on the shift result to obtain a mantissa rounding result of the shift result; a third obtaining module configured to obtain a first judging result of whether the mantissa satisfies a first preset rounding condition during the mantissa rounding operation; and a fourth obtaining module configured to obtain a target mantissa of a multiplication result of the first floating-point number and the second floating-point number according to the mantissa rounding result if the first judging result is that the mantissa satisfies the first preset rounding condition.

[0009] In a fourth aspect, an embodiment of the present application further provides an electronic device, which comprises a processor, and a memory configured to store instructions executable by the processor; and the processor is configured to execute the instructions to implement the method in the first aspect.

[0010] In a fifth aspect, an embodiment of the present application further provides a computer readable storage medium, when instructions in the computer readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method in the first aspect.

[0011] In the embodiment, a shift result of a product of the first floating-point number and the second floating-point number is obtained, a mantissa rounding operation is performed on the shift result to obtain a mantissa rounding result of the shift result, in the process of performing the mantissa rounding operation, a first judgment result of whether the mantissa satisfies a first preset rounding condition is obtained, and if the first judgment result is that the mantissa satisfies the first preset rounding condition, a multiplication result of the first floating-point number and the second floating-point number is obtained according to the mantissa rounding result. The embodiment can process the operations of obtaining the mantissa rounding result and obtaining the first judgment result in parallel, so that, in the case of determining that the mantissa satisfies the first preset rounding condition, the target mantissa of the multiplication result can be directly obtained according to the calculated mantissa rounding result. Compared with the method of analyzing whether the mantissa needs to be rounded in the related art, and then calculating the mantissa rounding result in the case of determining that the mantissa needs to be rounded, the embodiment shortens the time of obtaining the target mantissa of the multiplication result, and shortens the multiplication operation period.

[0012] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0014] Figure 1 is a floating-point multiplication method application scenario provided by an embodiment of the present application;

[0015] Figure 2 is a step flowchart of a floating-point multiplication method provided by an embodiment of the present application;

[0016] Figure 3 is a step flowchart of a floating-point multiplication method provided by an embodiment of the present application;

[0017] Figure 4 is a step flowchart of a floating-point multiplication method provided by an embodiment of the present application;

[0018] Figure 5 is a step flowchart of a floating-point multiplication method provided by an embodiment of the present application;

[0019] Figure 6 is a step flowchart of a floating-point multiplication method provided by an embodiment of the present application;

[0020] Figure 7 is a floating point multiplication circuit schematic diagram provided by an embodiment of the present application;

[0021] Figure 8 is a schematic diagram of a preset target mantissa acquisition circuit and a first stickiness bit value acquisition circuit of a right shift operation provided by an embodiment of the present application;

[0022] Figure 9 is a mantissa acquisition circuit schematic diagram in the case of no overflow provided by an embodiment of the present application;

[0023] Figure 10 is a floating point multiplication circuit schematic diagram provided by an embodiment of the present application;

[0024] Figure 11 is a flag bit acquisition circuit schematic diagram provided by an embodiment of the present application;

[0025] Figure 12 is an exponent overflow information acquisition circuit schematic diagram provided by an embodiment of the present application;

[0026] Figure 13 is a circuit schematic diagram for judging whether a mantissa meets a second preset rounding condition provided by an embodiment of the present application;

[0027] Figure 14 is a flag bit acquisition circuit schematic diagram provided by an embodiment of the present application;

[0028] Figure 15 is a flag bit acquisition circuit schematic diagram provided by an embodiment of the present application;

[0029] Figure 16 is a floating point multiplication device block diagram provided by an embodiment of the present application;

[0030] Figure 17 is a block diagram of an electronic device provided by an embodiment of the present application;

[0031] Figure 18 is a block diagram of another electronic device of another embodiment of the present application. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0033] The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class and do not limit the number of objects, for example, the first object can be one or more. In addition, the term "and / or" in this application is used to describe the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects. The term "multiple" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0034] Figure 1 is a schematic diagram of an application scenario of a floating-point multiplication method provided by an embodiment of the present application. The floating-point multiplication instruction is a commonly used instruction in a processor, which can be used to instruct a first floating-point number and a second floating-point number to perform multiplication, and then obtain the product between the first floating-point number and the second floating-point number.

[0035] In the multiplication process, the clock frequency is high, and correspondingly, the time of each operation period is very short. However, the floating-point multiplication operation process is relatively complex, which leads to the fact that usually multiple periods are needed to complete the floating-point multiplication operation. For example, in the related art, in some processor architectures, the multiplication between half-precision floating-point numbers, the multiplication between single-precision floating-point numbers, and the multiplication between double-precision floating-point numbers all need three periods.

[0036] Further, the floating-point number usually includes a sign part, an exponent part and a mantissa part, and the floating-point multiplication operation can be represented by the following formula:

[0037]

[0038] wherein, is a first floating-point number, is a second floating-point number, is the product between the first floating-point number and the second floating-point number. According to the above formula, the floating-point multiplication operation is to multiply the values of the first floating-point number and the second floating-point number.

[0039] Specifically, the sign values of the first floating point number and the second floating point number are multiplied, the exponent values of the first floating point number and the second floating point number are multiplied, and the decimal values of the first floating point number and the second floating point number are multiplied, thereby obtaining the product of the first floating point number and the second floating point number, and then the product is converted into a binary floating point number representation. Further, the multiplication of the sign values is an exclusive OR operation on the binary sign parts of the first floating point number and the second floating point number; the multiplication of the exponent values is an addition operation on the binary exponent parts of the first floating point number and the second floating point number; and the multiplication of the decimal values is a multiplication operation on the binary decimal parts of the first floating point number and the second floating point number.

[0040] Based on the above multiplication processing procedure, the value range of the result obtained by multiplying the decimal parts of the two floating point numbers should be [0, 4). Further, if both of the two floating point numbers are normalized numbers, the value range of the result obtained by multiplying the decimal parts of the two floating point numbers should be [1, 4). If the actual result obtained by multiplying the binary decimal parts of the two floating point numbers is between [2, 4), the mantissa part of the product of the two floating point numbers needs to be shifted to the right, and the exponent part of the product of the two floating point numbers needs to be increased by 1.

[0041] If both of the two floating point numbers are unnormalized numbers, the decimal part of the product is between [0, 1); if only one of the two floating point numbers is an unnormalized number, the decimal part of the product can also be between [1, 2).

[0042] Based on the above multiplication processing procedure, the value range of the result obtained by multiplying the two floating point numbers should be If the exponent part of the result obtained by multiplying the two floating point numbers is greater than the upper limit value of the floating point number exponent , overflow to infinity is needed; if the exponent part of the result obtained by multiplying the two floating point numbers is less than the lower limit value of the floating point number exponent , the decimal part of the result obtained by multiplying the exponent parts of the two floating point numbers needs to be shifted to the right, and the exponent part of the product of the two floating point numbers needs to be increased. That is, after obtaining the product of the two floating point numbers, the mantissa part of the product needs to be shifted according to the shift value.

[0043] Based on the above multiplication processing procedure, if the value of the exponent part of the result obtained by multiplying the exponent parts of the two floating point numbers is between , and the range of the result of the multiplication of the decimal parts is between , the decimal part of the multiplication result needs to be shifted to the left.

[0044] When the fractional part of the product is shifted left or right, the exponent part also needs to be adjusted accordingly. After the fractional part of the product is shifted left or right, the mantissa may need to be rounded.

[0045] In the related art, the product of two floating-point numbers is first obtained, and then the product is shifted to obtain a shift result. The mantissa part of the shift result is then rounded to obtain an analysis result of whether rounding is needed. If rounding is needed, the mantissa part is rounded to obtain a rounding result. However, this method has a long processing period.

[0046] To solve the problems in the related art, embodiments of the present application provide a floating-point multiplication method, which includes: obtaining a shift result of a product of a first floating-point number and a second floating-point number; the shift result is a result of a shift operation on a fractional part of the product; obtaining a mantissa of the shift result and a mantissa rounding result of the mantissa; obtaining a first judgment result of whether the mantissa satisfies a first preset rounding condition in a process of a mantissa rounding operation; if the first judgment result is that the mantissa satisfies the first preset rounding condition, obtaining a multiplication result of the first floating-point number and the second floating-point number according to the mantissa rounding result. Embodiments of the present application reduce the mantissa rounding processing time and the operation period of the floating-point multiplication operation.

[0047] The floating-point multiplication method provided by embodiments of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] Figure 2 is a step flowchart of a floating-point multiplication method provided by embodiments of the present application, as shown in Figure 2 The method can include:

[0049] Step 101: obtaining a shift result of a product of a first floating-point number and a second floating-point number.

[0050] The shift result is a result of a shift operation on a fractional part of the product.

[0051] For example, the shift number and the shift direction of the product can be obtained, and the product is shifted according to the shift number and the shift direction to obtain the shift result.

[0052] Step 102: performing a mantissa rounding operation on the shift result to obtain a mantissa rounding result of the shift result.

[0053] For example, a preset mantissa of the shift result is obtained, and a mantissa rounding operation is performed on the preset mantissa to obtain the mantissa rounding result of the shift result.

[0054] Step 103: During the rounding operation, obtain the first judgment result of whether the last digit meets the first preset rounding condition.

[0055] For example, the value of the first guard bit, the value of the first round bit, and the value of the first sticky bit of the mantissa are obtained. Based on the values ​​of the first guard bit, the first round bit, and the first sticky bit, the first judgment result of whether the mantissa meets the first preset rounding condition is obtained.

[0056] For example, obtain the preset rounding mode, and based on the first preset rounding condition corresponding to the preset rounding mode, as well as the value of the first retention bit, the value of the first rounding bit, and the value of the first sticky bit, obtain the first judgment result of whether the mantissa meets the first preset rounding condition.

[0057] For example, if the preset rounding mode is round Ties To Even (RNE), the corresponding first preset rounding conditions include: the value of the first retention bit is 1, and the value of at least one of the first rounding bit and the first sticky bit is 1.

[0058] If the default rounding mode is round to the negative (round Toward Negative) RDN If the first preset rounding condition is 1, then the first preset rounding condition includes at least one of the first reserved bit and the first sticky bit.

[0059] If the preset rounding mode is round to the positive (round Toward Positive) , If the first preset rounding condition is 1, then the first preset rounding condition includes at least one of the first reserved bit and the first sticky bit.

[0060] If the preset rounding mode is round Ties To Away (RMM), then the corresponding first preset rounding condition includes: the value of the first reserved digit is 1.

[0061] Step 104: If the first judgment result is that the mantissa meets the first preset rounding condition, then according to the mantissa rounding result, obtain the target mantissa of the multiplication result of the first floating-point number and the second floating-point number.

[0062] For example, if the first judgment result is that the mantissa does not meet the first preset rounding condition, then the result of the multiplication operation of the first floating-point number and the second floating-point number is obtained based on the mantissa.

[0063] For example, a second determination result is obtained regarding whether the exponent of the shifted result has overflowed. If the second determination result indicates that the exponent has not overflowed, and the first determination result indicates that the mantissa meets the first preset rounding condition, then the rounded mantissa result is determined as the target mantissa of the multiplication result. If the second determination result indicates that the exponent has not overflowed, and the first determination result indicates that the mantissa does not meet the first preset rounding condition, then the preset mantissa portion is determined as the target mantissa of the multiplication result. If the second determination result indicates that the exponent has overflowed, then the preset target mantissa is determined as the target mantissa of the multiplication result.

[0064] In this embodiment, the shift result of the product of a first floating-point number and a second floating-point number is obtained. A mantissa rounding operation is then performed on the shift result to obtain the mantissa rounding result. During the mantissa rounding operation, a first judgment result is obtained regarding whether the mantissa meets a first preset rounding condition. If the first judgment result indicates that the mantissa meets the first preset rounding condition, the multiplication result of the first floating-point number and the second floating-point number is obtained based on the mantissa rounding result. Based on the mantissa rounding result and the first judgment result obtained through parallel processing, the target mantissa of the multiplication result can be directly obtained from the calculated mantissa rounding result if the mantissa meets the first preset rounding condition. Compared to the related technologies that first analyze whether the mantissa needs rounding and then calculate the mantissa rounding result if rounding is required, this embodiment shortens the time for obtaining the target mantissa of the multiplication result and reduces the multiplication cycle.

[0065] Figure 3 This is a flowchart of another multiplication operation method provided in the embodiments of this application, referred to as follows: Figure 3 The methods may include:

[0066] Step 201: Obtain the shift result of the product of the first floating-point number and the second floating-point number.

[0067] The shift result is the result of shifting the fractional part of the product.

[0068] For example, the shifted result of the product of the first and second floating-point numbers can be obtained using the following method:

[0069]

[0070]

[0071]

[0072] Based on the above expression, and the shift result corresponding to a left shift. equal to product The decimal part is shifted to the left by a number of positions equal to... ; and the shift result corresponding to the right shift. equal to product The decimal part is shifted to the right by a number of places equal to... .

[0073] When the shift operation is a left shift operation ( ), shift result Equal to the shift result corresponding to a left shift Otherwise, it is equal to the shift result corresponding to a right shift. .

[0074] Step 202: Perform a rounding operation on the preset mantissa of the shift result to obtain the rounded mantissa result of the shift result.

[0075] For example, if the shift result meets the first condition, the preset mantissa includes the data from the third position to the least significant bit of the shift result. The total number of bits from the third position to the least significant bit of the shift result is equal to the sum of the mantissa bit width corresponding to the preset floating-point type and 1.

[0076] For example, if the shift result does not meet the first condition, the preset mantissa includes: the zero-padding result of padding the data from the fourth position to the least significant bit of the shift result with zeros at the lower bits. The total number of bits from the fourth position to the least significant bit of the shift result is equal to the mantissa bit width corresponding to the preset floating-point number type.

[0077] The first condition includes: the shift operation is a left shift operation, the fractional part of the product overflows, and the exponent of the product is not equal to 0.

[0078] After shifting the product, the mantissa of the shifted result needs to be selected, and subsequent rounding is performed based on the selected preset mantissa. For example, the result of whether the shifted result meets the first condition can be obtained using the following method. :

[0079]

[0080] According to this expression, the first condition Includes: needing to shift left ( ), and the decimal part of the product overflows ( ), and the exponent of the product Not equal to 0 (i.e., ).in,

[0081]

[0082]

[0083]

[0084] According to this expression, if the shift result satisfies the first condition... Then preset the last digit for , The shift result is from the third position ( The data from the least significant bit (0) to the least significant bit (0), The default mantissa width is set to the width of the floating-point number type; otherwise, the default mantissa width is 1. , For the fourth position of the shift result ( The result of padding the least significant bit (0) to the least significant bit (0) with zeros. ).

[0085] The first floating-point number, the second floating-point number, and the floating-point number of the product are of the same type, all of which are the preset floating-point number types in this embodiment.

[0086] The preset mantissa obtained according to the method in this step is the mantissa part used for rounding, which does not include integer digits, and its bit width is [missing information]. .

[0087] For example, data with a bit width equal to the bit width of the preset floating-point number type is truncated from the preset mantissa, and 1 is added to the truncated data to obtain the mantissa rounding result of the shift result.

[0088] Based on the method of this embodiment, the part of the mantissa of the shift result that needs to be rounded can be accurately obtained. This part is the preset mantissa in this embodiment. By performing a mantissa rounding operation on the preset mantissa, the mantissa rounding result can be obtained quickly and accurately.

[0089] For example, step 202 may include sub-step A1:

[0090] Sub-step A1: Increment 1 by the preset mantissa from the highest bit to the fifth bit to obtain the rounded mantissa result of the shifted result.

[0091] The total number of bits from the highest bit to the fifth bit of the preset mantissa is equal to the mantissa width of the preset floating-point number type.

[0092] For example, the rounding result is obtained using the following method:

[0093]

[0094] That is, preset the last digit. From the highest position ( ) to the fifth position ( The data is ,right Perform an increment operation to obtain the rounded result of the shifted result. for:

[0095]

[0096] In this embodiment, the initial value of the last digit is taken as a preset last digit ( (Higher median) The data is incremented by 1 to obtain the mantissa rounding result of the shifted result. Therefore, instead of performing the mantissa rounding operation after obtaining the result of whether rounding is needed, the mantissa rounding result with a bit width equal to the preset floating-point number type mantissa width is obtained in advance, shortening the calculation cycle.

[0097] Step 203: During the rounding operation, obtain the first parameter of the shift result.

[0098] The first parameter includes at least one of the following: the value of the first retained bit of the shift result, the value of the first rounded bit, and the value of the first sticky bit.

[0099] For example, the data in the preset last digit position from the highest digit to the fifth digit ( The value of the least significant bit in ) The value of the first retained bit of the shift result is determined. :

[0100]

[0101] For example, the preset last digit ( The value at the ninth position in the result is determined as the value of the first rounded bit of the shift result. :

[0102]

[0103] Among them, from the ninth position ( The total number of bits between the preset mantissa (0) and the preset least significant bit (0) is equal to the sum of the preset mantissa width and 1.

[0104] For example, the value of the first sticky bit of the preset mantissa is obtained according to the following method. :

[0105]

[0106] When the shift operation is a left shift, the value of the first sticky bit... It equals starting from the tenth position of the preset last digit ( The result of the OR reduction operation on the data from the tenth bit to the least significant bit (0); where the total number of bits from the tenth bit to the least significant bit is equal to the preset mantissa width of the floating-point number. In the case of a right shift operation, the first sticky bit The value of the first sticky bit is equal to the value of the shift operation to the right. .

[0107] For example, step 203 can include the following sub-steps:

[0108] Sub-step B1, obtaining a shift mask.

[0109] Wherein, the data from the first position of the shift mask to the lowest bit of the shift mask is 1, and the data of other bits of the shift mask is 0; the total number of bits from the first position to the lowest bit of the shift mask is equal to the right shift number of the decimal part of the product.

[0110] For example, the shift mask can be obtained according to the following method :

[0111]

[0112]

[0113] According to the above expression, an initial mask with a bit width equal to the total width corresponding to the preset floating-point type ( ) and each bit data being 1 can be obtained . For example, a plurality of 1s can be copied to be spliced to obtain the initial mask .

[0114] The initial mask is subjected to a left shift operation, and the shift number of the left shift operation is equal to the right shift number when the product is subjected to a right shift operation , and the high-bit zero padding operation is performed on the right shift result to obtain a high-bit zero padding result with a bit width of . Then, the data from (n-1) bits to (n-2) bits of the high-bit zero padding result is determined as the shift mask . In this embodiment, the shift mask is obtained by performing left shift and bit truncation on the initial mask

[0115] , then performing AND operation on the shift mask and the low-bit data of the decimal part of the product , and then performing or reduction to obtain the value of the first stick bit . Sub-step B2, obtaining the first data from the second position of the decimal part of the product to the lowest bit of the product.

[0116] Wherein, the total number of bits from the second position to the lowest bit of the product is equal to the difference between the total width corresponding to the preset floating-point type and 1.

[0117] The first data is:

[0118] ​​​According to the expression, the first data is data from the second position of the product decimal to the lowest bit (0), and the bit width of the part of data is equal to the total width corresponding to the preset floating-point number type minus one.

[0119] Sub-step B3, performing AND operation on the shift mask and the first data to obtain an AND operation result.

[0120] Sub-step B4, performing or reduction operation on the AND operation result to obtain the value of the first sticky bit corresponding to the right shift operation.

[0121] For example, according to the following method, the value of the first sticky bit in the case where the shift operation includes the right shift operation is obtained .

[0122]

[0123] In the shift operation, the left shift does not affect the calculation of the required in the subsequent rounding step, but the right shift operation may move a part of the number out of the mantissa part, and this part of the number also participates in the calculation of , so it is necessary to combine this part of the number to calculate the in the right shift process. In this embodiment, the AND operation result obtained by the shift mask can include the number that may be overflowed from the mantissa part in the right shift operation, and the value of the first sticky bit is obtained based on the AND operation result, which improves the accuracy of the value of the first sticky bit. Compared with the method of expanding the bit width in the right shift to retain all numbers and then performing or reduction on the low bits in the related art, the embodiment realizes a timing-optimized calculation method of the value of the first sticky bit in the right shift operation, which improves the efficiency and accuracy of obtaining the value of the first sticky bit in the right shift operation. Based on the value of the first sticky bit, the first determination result of whether the mantissa satisfies the first preset rounding condition can be accurately determined.

[0124] Step 204, obtaining the first determination result of whether the mantissa satisfies the first preset rounding condition according to the first parameter.

[0125] For example, according to the first parameter, the method of obtaining the first determination result of whether the mantissa satisfies the first preset rounding condition may be as follows:

[0126]

[0127]

[0128]

[0129] ​​

[0130] According to the expression, if the preset rounding mode is RNE (round to nearest even) , the value of the first rounding bit of the shift result is 1, and the value of at least one of the first reserved bit and the first sticky bit is 1, that is , the first determination result is that the mantissa satisfies the first preset rounding condition.

[0131] According to the expression, if the preset rounding mode is negative round down ( ) or positive round up ( ), the value of the first rounding bit or the first sticky bit of the shift result is 1 , the first determination result is that the mantissa satisfies the first preset rounding condition.

[0132] According to the expression, if the preset rounding mode is round to the larger absolute value number ( ), the value of the first rounding bit of the shift result is 1.

[0133] In this embodiment, the first parameter of the shift result is obtained; the first parameter includes at least one of the value of the first reserved bit, the value of the first rounding bit, and the value of the first sticky bit of the shift result; according to the first parameter, the first determination result of whether the mantissa satisfies the first preset rounding condition can be accurately obtained.

[0134] Step 205, if the first determination result is that the mantissa satisfies the first preset rounding condition, the target mantissa of the multiplication result of the first floating-point number and the second floating-point number is obtained according to the mantissa rounding result.

[0135] For example, if the exponent of the shift result is not overflowed, and the first determination result is that the mantissa satisfies the first preset rounding condition, the mantissa rounding result (for example, ) is determined as the target mantissa of the multiplication result of the first floating-point number and the second floating-point number.

[0136] Step 206, if the first determination result is that the mantissa does not satisfy the first preset rounding condition, the target mantissa of the multiplication result of the first floating-point number and the second floating-point number is obtained according to the preset mantissa.

[0137] For example, if the exponent of the shift result is not overflowed, and the first determination result is that the mantissa does not satisfy the first preset rounding condition, the data from the highest bit to the fifth bit of the preset mantissa ( ) is directly determined as the target bit number of the multiplication result of the first floating-point number and the second floating-point number.

[0138] ​​The method can further include:

[0139] In step 207, the overflow information of the exponent of the shift result is obtained.

[0140] The overflow information of the exponent of the shift result is obtained according to the following method :

[0141]

[0142] According to the expression, if the shift result exponent is 1 from the highest bit to the first bit of the data , and the first condition is met, it is determined that the exponent overflows, otherwise it is determined that the exponent does not overflow. The first condition includes that the value of the lowest bit of the shift result exponent is 1, or the exponent meets the first preset carry condition.

[0143] In step 208, if the overflow information is overflow, the preset target mantissa is determined as the target mantissa of the multiplication result.

[0144] If the preset rounding mode is other than the rounding mode to zero, the rounding down of positive numbers and the rounding up of negative numbers, the total number of bits of the preset target mantissa is equal to the mantissa bit width corresponding to the preset floating-point number type, and each bit value is 0; if the preset rounding mode is the rounding mode to zero, the rounding down of positive numbers or the rounding up of negative numbers, the total number of bits of the preset target mantissa is equal to the mantissa bit width corresponding to the preset floating-point number type, and each bit value is 1.

[0145] The preset target mantissa is obtained according to the following method :

[0146]

[0147] Wherein:

[0148]

[0149] According to the expression, if the preset rounding mode is the rounding mode to zero , the rounding down of positive numbers or the rounding up of negative numbers , the first parameter is equal to 1, and correspondingly, each bit value of the preset target mantissa is 1, and the total number of bits is equal to the mantissa bit width corresponding to the preset floating-point number type .

[0150] If the preset rounding mode is the rounding mode to zero , the rounding down of positive numbers or the rounding up of negative numbers​ If the rounding mode is other than the rounding mode of the first parameter equals 0, the corresponding preset target mantissa all bits are 0, and the total number of bits is equal to the mantissa bit width corresponding to the preset floating-point number type .

[0151] In this embodiment, if the mantissa is subjected to the rounding operation, the corresponding index may need to be incremented. In the case where the overflow information of the index is an overflow, the index cannot be incremented. Therefore, in this case, the mantissa is not subjected to the rounding operation, and the preset target mantissa is determined as the target mantissa of the multiplication result. In this way, the accuracy of the target mantissa of the multiplication result can be ensured.

[0152] If the overflow information is not an overflow, and the first determination result is that the mantissa satisfies the first preset rounding condition, the target mantissa of the multiplication result of the first floating-point number and the second floating-point number can be obtained according to the mantissa rounding result, which can include: directly determining the mantissa rounding result as the target mantissa of the multiplication result.

[0153] In this embodiment, if the overflow information is not an overflow, and the first determination result is that the mantissa satisfies the first preset rounding condition, the mantissa can be subjected to the rounding operation. Therefore, the mantissa rounding result is determined as the target mantissa of the multiplication result, and the accuracy of the target mantissa is improved.

[0154] Correspondingly, if the overflow information is not an overflow, and the first determination result is that the mantissa does not satisfy the first preset rounding condition, the target mantissa of the multiplication result of the first floating-point number and the second floating-point number can be obtained according to the preset mantissa, which can include: determining the data from the highest bit to the fifth bit of the preset mantissa of the shift result as the target mantissa of the multiplication result; wherein the total number of bits from the highest bit to the fifth bit of the preset mantissa is equal to the mantissa width of the preset floating-point number type.

[0155] For example, the target mantissa of the multiplication result can be obtained according to the following method :

[0156]

[0157] According to the expression, if the overflow information of the index of the shift result is an overflow , the preset target mantissa is determined as the target mantissa; otherwise, the target mantissa without overflow is determined as the target mantissa:

[0158]

[0159] According to the expression, if the first judging result is that the mantissa satisfies the first preset rounding condition , the target mantissa is equal to the mantissa rounding result ; otherwise, the target mantissa is equal to the data of the preset mantissa from the highest bit to the fifth bit . According to the foregoing embodiment, the mantissa rounding result is

[0160]

[0161]

[0162] The method for obtaining the overflow information of the exponent of the shift result can include the following sub-steps:

[0163] Sub-step C1: if the exponent from the highest bit to the first bit is all 1, and the exponent satisfies the third condition, it is determined that the overflow information is an up overflow.

[0164] The third condition includes that the value of the lowest bit of the exponent is 1, or the exponent satisfies the first preset carry condition.

[0165] In addition, if the exponent does not satisfy the third condition, it is determined that the overflow information of the exponent is not an up overflow; and the overflow information of the exponent is obtained according to the following method :

[0166]

[0167] According to the expression, the data of the exponent from the highest bit to the first bit is subjected to an AND reduction operation; the data of the lowest bit of the exponent and the second judging result of whether the exponent satisfies the first preset carry condition are subjected to an OR operation; the AND operation is performed on the AND reduction operation result and the OR operation result, and the overflow information is obtained according to the obtained AND operation result.

[0168] The method can further include the following steps:

[0169] Step 209: obtaining the exponent of the shift result, and performing an exponent carry operation on the exponent of the shift result to obtain an exponent carry result.

[0170] For example, if the third exponent of the product is all 1, or the decimal of the product is not overflowed, the third exponent of the product is determined as the exponent of the shift result; otherwise, the third exponent of the product is subjected to a plus 1 operation, and the obtained plus 1 operation result is determined as the exponent of the shift result.

[0171] The exponent of the shift result can be obtained according to the following method :

[0172]

[0173] According to this expression, for the third exponent of the product ( Perform AND and reduction operations, and ensure that the result of the AND and reduction operations and the decimal of the product do not overflow. If the result of the OR operation is 1, then the third exponent of the product () will be used. The result is determined by the exponent of the shifted product; otherwise, the exponent of the product is incremented by 1, and the result of the increment operation is ( ), which is determined as the exponent of the shift result.

[0174] For example, the carry-over result of the exponent can be obtained using the following method:

[0175]

[0176]

[0177] According to this expression, the exponent of the shift result ( Incrementing by 1 yields the result with carry-over from the exponent. ).

[0178] Step 210: During the exponent carry operation, obtain a second judgment result on whether the exponent of the shift result meets the first preset carry condition.

[0179] For example, step 210 may include the following sub-steps:

[0180] Sub-step D1: If the mantissa of the shift result satisfies the first preset rounding condition, and all the values ​​of the preset mantissa of the shift result from the highest bit to the fifth bit are 1, then the second judgment result is determined to be that the exponent of the shift result satisfies the first preset carry condition.

[0181] The total number of bits from the highest bit to the fifth bit of the preset mantissa is equal to the mantissa width of the preset floating-point number type.

[0182] Sub-step D2: If the mantissa of the shift result does not meet the first preset rounding condition, or if the value of any bit in the preset mantissa of the shift result from the highest bit to the fifth bit is 0, then the second judgment result is determined to be that the exponent of the shift result does not meet the first preset carry condition.

[0183] For example, the second judgment result is obtained according to the following method. :

[0184]

[0185] According to this expression, if the mantissa of the shifted result satisfies the first preset rounding condition ( ), and the preset mantissa of the shifted result has all 1s in its bits from the most significant bit to the fifth position. If the second judgment result is determined to be that the exponent of the shift result satisfies the first preset carry condition, then the second judgment result is determined to be that the exponent of the shift result does not satisfy the first preset carry condition.

[0186] Based on this embodiment, the judgment result of whether the exponent of the shift result meets the first preset carry condition can be accurately obtained.

[0187] Step 211: If the second judgment result is that the exponent satisfies the first preset carry condition, then according to the exponent carry result, obtain the target exponent of the multiplication operation result of the first floating-point number and the second floating-point number.

[0188] For example, if the exponent does not overflow and the second judgment result is that the exponent meets the first preset carry condition, then the carry result of the exponent is determined as the target exponent of the multiplication operation result.

[0189] Step 212: If the second judgment result is that the exponent does not meet the first preset carry condition, then obtain the target exponent of the multiplication result of the first floating-point number and the second floating-point number according to the exponent.

[0190] For example, if the exponent does not overflow and the second judgment result is that the exponent does not meet the first preset carry condition, then the exponent is determined as the target exponent of the multiplication operation result.

[0191] For example, the target index can be obtained using the following method. :

[0192]

[0193] According to this expression, if the exponent overflows, a target exponent will be preset. The target exponent is determined as the result of the multiplication of the first and second floating-point numbers; otherwise, the exponent in the non-overflow case is used. It was determined to be the target index.

[0194] Among them, the index under the non-overflow condition for:

[0195]

[0196] According to the above expression, if the exponent does not overflow, and the second judgment result is that the exponent satisfies the first preset carry condition ( ), then the result of the exponent will be carried over ( If the index is determined as the target index, and if the index does not overflow, and the second judgment result is that the index does not meet the first preset carry condition, then the index ( () was determined as the target index.

[0197] In this embodiment, it is not necessary to first analyze whether an exponential carry is needed after obtaining the shift result, and then calculate the exponential carry result if necessary. This embodiment improves the processing efficiency of exponential carry, shortens the time for obtaining the target exponent in the multiplication operation, and shortens the operation cycle of floating-point multiplication.

[0198] For example, the methods also include:

[0199] Step 213: Obtain the overflow information of the exponent of the shift result.

[0200] Overflow information can include whether it overflows or not.

[0201] Step 214: If the overflow information is overflow, then the preset target exponent is determined as the target exponent of the multiplication result.

[0202] For example, if the preset rounding mode is a rounding mode other than rounding to zero, rounding down for positive numbers, and rounding up for negative numbers, then the preset target exponent is an exponent with a total number of bits equal to the exponent width of the preset floating-point number, and each bit value equal to 1.

[0203] When the result overflows to infinity, both the exponent and the mantissa need to be adjusted according to the rounding mode. Rounding to zero, rounding down for positive numbers, and rounding up for negative numbers will round the result to the largest normalized number instead of infinity.

[0204] If the preset rounding mode is zero rounding mode, positive number rounding down or negative number rounding up mode, then the preset target exponent is an exponent with a total number of bits equal to the preset floating-point exponent width, the least significant bit being 0, and the other bits being 1.

[0205] For example, the preset target index can be obtained using the following method. :

[0206]

[0207]

[0208] According to the above expression, if the preset rounding mode is a rounding mode other than the zero rounding mode, positive number rounding down, or negative number rounding up mode ( ), then intermediate parameters Equal to 1, the total number of bits is equal to the preset exponent width of the floating-point number ( ), and each value is equal to the exponent of 1. If the total number of bits is equal to the preset floating-point number exponent bit width, and the value of the lowest bit is 0 and the values of other bits are all 1, the exponent is determined as the preset target exponent.

[0209] In the embodiment, if the exponent overflows, no more carry can be performed on the exponent, and therefore the preset target exponent is determined as the target exponent to prevent the exponent from overflowing due to the carry. If the preset rounding mode is a rounding mode other than the rounding to zero mode, rounding down for positive numbers and rounding up for negative numbers, the preset target exponent is an exponent whose total number of bits is equal to the preset floating-point number exponent bit width and the values of all bits are equal to 1. If the preset rounding mode is the rounding to zero mode, rounding down for positive numbers or rounding up for negative numbers, the preset target exponent is an exponent whose total number of bits is equal to the preset floating-point number exponent bit width, the value of the lowest bit is 0 and the values of other bits are all 1. Based on this, the correctness of the subsequent processing result can be ensured.

[0210] Further, if the overflow information is no overflow, and the second determination result is that the exponent satisfies the first preset carry condition, the target exponent of the multiplication result of the first floating-point number and the second floating-point number can be obtained according to the exponent carry result, which can include: determining the exponent carry result as the target exponent of the multiplication result.

[0211] Further, if the overflow information is no overflow, and the second determination result is that the exponent does not satisfy the first preset carry condition, the target exponent of the multiplication result of the first floating-point number and the second floating-point number can be obtained according to the exponent, which can include: determining the exponent of the shift result as the target exponent of the multiplication result.

[0212] In the embodiment, if the exponent does not overflow, it can be preliminarily determined that the exponent can be carried. Further, whether the exponent satisfies the first preset carry condition is determined, and when the condition is satisfied, the exponent carry result is determined as the target exponent, and when the condition is not satisfied, the exponent of the shift result is determined as the target exponent. In this way, it can be ensured that the exponent does not overflow after the carry, and the accuracy of the target exponent can be ensured.

[0213] For example, the method can further include the following steps:

[0214] In step 215, the overflow information of the exponent of the shift result is obtained.

[0215] The method of this step has been described in the foregoing embodiments, which will not be repeated here.

[0216] In step 216, if the overflow information of the exponent is overflow, the sign bit of the multiplication result is determined as overflow.

[0217] For example, the value of the identification bit used to identify overflow is obtained according to the following method :

[0218]

[0219] wherein, is the overflow information of the exponent.

[0220] If the shift result satisfies any one of the second conditions, the flag bit of the multiplication result is determined as being inaccurate in step 217.

[0221] The second conditions include: the overflow information is an overflow, the value of the first rounding bit of the shift result is 1, and the value of the first stick bit of the shift result is 1.

[0222] For example, the value of the flag bit used to identify the inaccuracy of the multiplication result is obtained according to the following method :

[0223]

[0224] According to the expression, the value of the first rounding bit of the shift result and the value of the first stick bit are obtained by an or operation, and the overflow information of whether the exponent of the shift result overflows is or operated with the or operation result to obtain the value of the flag bit used to identify the inaccuracy of the multiplication result .

[0225] If the exponent of the product is equal to 0, the exponent of the shift result does not satisfy the preset second carry condition, and the shift result satisfies any one of the second conditions, the flag bit of the multiplication result is determined as underflow in step 218.

[0226] For example, the value of the flag bit used to identify the underflow of the multiplication result is obtained according to the following method :

[0227]

[0228] According to the expression, if the exponent of the shift result is equal to 0, the exponent of the shift result does not satisfy the preset second carry condition , and the shift result satisfies any one of the second conditions, the flag bit is underflow of the multiplication result.

[0229] If the values of the exponent from the highest bit to the first bit are all 1, and the exponent satisfies the third condition, the overflow information is determined as overflow; the third condition includes that the value of the lowest bit of the exponent is 1, or the exponent satisfies the first preset carry condition.

[0230] If the shift result does not satisfy the third condition, it is determined that the exponent of the shift result does not satisfy the preset second carry condition, and the third condition includes that the data of the preset tail of the shift result decimal from the highest bit to the fifth bit are all 1, the value of the second reserved bit of the shift result is 1, and the tail of the shift result satisfies the second preset rounding condition.

[0231] That is, the second carry condition is:

[0232]

[0233] According to the expression, the data of the preset tail of the shift result decimal from the highest bit to the fifth bit are all 1 , and the values of the second reserved bits are all 1, and the tail of the shift result satisfies the second preset rounding condition , the exponent of the shift result satisfies the second preset carry condition; otherwise, it is determined that the exponent of the shift result does not satisfy the second preset carry condition.

[0234] For example, judging whether the tail satisfies the second preset rounding condition can include the following sub-steps:

[0235] Sub-step E1, obtaining the second parameter of the shift result.

[0236] The second parameter includes at least one of the following: the value of the second reserved bit of the shift result, the value of the second rounding bit, and the value of the second stick bit.

[0237] Sub-step E2, obtaining the third judgment result of whether the tail satisfies the second preset rounding condition according to the second parameter.

[0238] The value of the second reserved bit is the value of the preset tail at the sixth position; the position interval between the sixth position and the lowest position of the tail is equal to the sum of the tail bit width of the preset floating-point number type and 1.

[0239] The value of the second rounding bit is the value of the preset tail at the seventh position; the total number of bits from the seventh position to the lowest position of the preset tail is equal to the tail bit width of the preset floating-point number type.

[0240] In the case of left shift operation, the value of the second stick bit is the result of the or reduction operation of the data of the preset tail from the eighth position to the lowest position; the total number of bits from the eighth position to the lowest position of the preset tail is equal to the difference between the tail bit width of the preset floating-point number type and 1.

[0241] In the case of right shift operation, the value of the second stick bit is equal to the value of the first stick bit corresponding to the right shift operation.

[0242] For example, the value of the second reserved bit ; value of the second rounding bit ; value of the second sticky bit

[0243] In an example, the method for determining whether the mantissa satisfies the second preset carry condition is as follows :

[0244]

[0245]

[0246]

[0247]

[0248] According to the method of the embodiment, the results of the overflow flag bit, the inaccuracy flag bit and the underflow flag bit can be accurately and quickly obtained.

[0249] In an example, the value of the divide-by-zero flag bit can also be obtained according to the following method :

[0250]

[0251] In an example, the value of the invalid flag bit can also be obtained according to the following method .

[0252]

[0253]

[0254] The result of the flag bit is also divided into the result when the floating-point number belongs to a normal number and a special number (for example, including 0, infinity, non-number and infinity). If the floating-point number belongs to a normal number other than a special number, the flag bit will not be generated .

[0255] Further, the final result of the flag bit is :

[0256]

[0257]

[0258] Wherein, is the result of determining whether the first floating-point number or the second floating-point number is a non-number, zero and infinity.

[0259] The multiplication result of the first floating-point number and the second floating-point number obtained according to the method of the foregoing embodiment is :

[0260]

[0261] wherein, is a symbol; is a target exponent in a case where the first floating-point number and the second floating-point number belong to normal numbers; is a target mantissa in a case where the first floating-point number and the second floating-point number belong to normal numbers.

[0262] Figure 4 is a specific step flowchart of a floating-point number multiplication method provided by an embodiment of the present application, as shown in the figure, the method can include: Figure 4

[0263] Step S1, performing symbol processing on a first symbol of a first floating-point number and a second symbol of a second floating-point number to obtain a symbol result.

[0264] The symbol of the product is obtained according to the following formula.

[0265] Step S2, performing symbol processing on a first exponent of the first floating-point number and a second exponent of the second floating-point number to obtain an exponent of the product of the first floating-point number and the second floating-point number before a shift processing.

[0266] The exponent of the product before the shift processing.

[0267]

[0268] Step S3, calculating a to-be-shifted parameter of the product of the first floating-point number and the second floating-point number.

[0269] For example, the to-be-shifted parameter of the product of the first floating-point number and the second floating-point number is obtained according to the following formula:

[0270]

[0271]

[0272]

[0273] Optionally, the first exponent of the first floating-point number and the second exponent of the second floating-point number are obtained; in the process of calculating the product of the first floating-point number and the second floating-point number, according to the first exponent and the second exponent, a to-be-shifted parameter of a shift operation on a decimal part of the product is obtained; the to-be-shifted parameter includes a shift bit number and a shift direction; according to the shift bit number and the shift direction, the shift operation is performed on the decimal part of the product to obtain a multiplication result of the first floating-point number and the second floating-point number.

[0274] ​Optionally, the to-be-shifted parameter for the shifting operation on the decimal part of the product is obtained according to the first index and the second index, including: obtaining a third index of the product according to the first index of the first floating-point number and the second index of the second floating-point number; and obtaining the shift bit number corresponding to the decimal part of the product according to the third index.

[0275] Optionally, in the case that the shift bit number includes a left shift bit number, the shift bit number corresponding to the decimal part of the product is obtained according to the third index, including: obtaining a first number of leading zeros of the decimal part of the first floating-point number and a second number of leading zeros of the decimal part of the second floating-point number; performing an OR operation on the first number of leading zeros and the second number of leading zeros to obtain a third number of leading zeros; and obtaining the left shift bit number corresponding to the decimal part of the product according to the third index and the third number of leading zeros.

[0276] Optionally, the left shift bit number corresponding to the decimal part of the product is obtained according to the third index and the third number of leading zeros, including: if the third number of leading zeros is less than the third index, determining the third number of leading zeros as the left shift bit number; and if the third number of leading zeros is greater than or equal to the third index, determining a difference between the third index and a first preset index as the left shift bit number.

[0277] Optionally, the first number of leading zeros of the decimal part of the first floating-point number and the second number of leading zeros of the decimal part of the second floating-point number are obtained, including: if the first index of the first floating-point number is equal to zero, obtaining a first splicing result by splicing zero and a mantissa of the first floating-point number, and determining a number of leading zeros of the first splicing result as the first number of leading zeros of the decimal part of the first floating-point number; if the first index of the first floating-point number is not equal to zero, determining the first number of leading zeros of the decimal part of the first floating-point number as zero; if the second index of the second floating-point number is equal to zero, obtaining a second splicing result by splicing zero and a mantissa of the second floating-point number, and determining a number of leading zeros of the second splicing result as the second number of leading zeros of the decimal part of the second floating-point number; and if the second index of the second floating-point number is not equal to zero, determining the second number of leading zeros of the decimal part of the second floating-point number as zero.

[0278] Optionally, in the case that the shift bit number includes a right shift bit number, the shift bit number corresponding to the decimal part of the product is obtained according to the third index, including: determining a difference between a second preset index and the third index as the right shift bit number corresponding to the decimal part of the product.

[0279] Optionally, the to-be-shifted parameter for the shifting operation on the decimal part of the product is obtained according to the first index and the second index, including: obtaining a third index of the product according to the first index of the first floating-point number and the second index of the second floating-point number; and if the third index is greater than zero, determining that the shift direction is left shifting; and if the third index is less than or equal to zero, determining that the shift direction is right shifting.

[0280] Optionally, the first exponent of the first floating-point number and the second exponent of the second floating-point number are obtained by: if the first floating-point number and the second floating-point number both belong to a first digital type, obtaining the first exponent of the first floating-point number and the second exponent of the second floating-point number; wherein the first digital type includes other digital types except for a second digital type, and the second digital type includes: zero, non-number, and infinite number.

[0281] Optionally, the method further comprises: if the first floating-point number and / or the second floating-point number belongs to the second digital type, obtaining the multiplication result of the first floating-point number and the second floating-point number according to a multiplication operation strategy corresponding to the second digital type; the second digital type includes: zero, non-number, and infinite number; wherein the multiplication operation strategy includes: if the first floating-point number and / or the second floating-point number is non-number, determining that the multiplication result of the first floating-point number and the second floating-point number is equal to a preset value; if the first floating-point number and the second floating-point number are both zero, or one of the first floating-point number and the second floating-point number is zero and the other is a digital type other than non-number and infinite, determining that the multiplication result of the first floating-point number and the second floating-point number is equal to zero; if the first floating-point number and the second floating-point number are both infinite number, or one of the first floating-point number and the second floating-point number is infinite number and the other is a digital type other than non-number and zero, determining that the multiplication result of the first floating-point number and the second floating-point number is equal to infinite.

[0282] Optionally, the first exponent of the first floating-point number is obtained by: obtaining a first initial exponent of the first floating-point number; if the first initial exponent is equal to zero, determining that the first exponent of the first floating-point number is equal to 1; if the first initial exponent is not equal to zero, determining that the first exponent of the first floating-point number is equal to the first initial exponent; and the second exponent of the second floating-point number is obtained by: obtaining a second initial exponent of the second floating-point number; if the second initial exponent is equal to zero, determining that the second exponent of the second floating-point number is equal to 1; if the second initial exponent is not equal to zero, determining that the second exponent of the second floating-point number is equal to the first initial exponent.

[0283] Step S4: obtaining a decimal multiplication result of the product of the first floating-point number and the second floating-point number.

[0284] Step S5: obtaining a special result of the multiplication operation on the special number when the first floating-point number and / or the second floating-point number is a special number.

[0285] Wherein, steps S1 to S5 can be processed in parallel, thereby saving processing implementation and reducing the processing period of the floating-point number multiplication operation.

[0286] Step S6: performing carry detection according to the value to be shifted and the decimal multiplication result.

[0287] Step S7, according to the carry detection result and the exponent before the product is not shifted, the first exponent carry processing is performed.

[0288] Step S8, according to the value to be shifted and the decimal multiplication result, the decimal shift is performed.

[0289] The steps S6 to S8 can be processed in parallel, thereby the processing implementation can be saved and the processing period of the floating point multiplication operation is reduced.

[0290] Optionally, the first exponent of the first floating point number and the second exponent of the second floating point number are obtained; according to the first exponent and the second exponent, a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating point number and the second floating point number is obtained; the to-be-shifted parameter comprises a shift direction and a shift bit number; in the process of obtaining a shift result of the product according to the to-be-shifted parameter, according to the to-be-shifted parameter, overflow information of the shift result decimal part is obtained; the overflow information comprises overflow or no overflow; according to the overflow information, the exponent of the shift result is adjusted to obtain a multiplication result of the first floating point number and the second floating point number.

[0291] Optionally, in the case that the shift direction is left shift and the shift bit number comprises a left shift number, according to the to-be-shifted parameter, the overflow information of the shift result decimal part is obtained, comprising: obtaining an initial mask; the highest bit of the initial mask is 1, and the other bits are 0; according to the left shift number, the highest bit of the initial mask is shifted right to obtain a shift mask; the shift mask and the product are ANDed to obtain an AND result; according to the AND result, the overflow information of the shift result decimal part is obtained.

[0292] Optionally, according to the AND result, the overflow information of the shift result decimal part is obtained, comprising: the AND result is OR-reduced to obtain an OR-reduced result; according to the OR-reduced result, the overflow information of the shift result decimal part is obtained.

[0293] Optionally, according to the OR-reduced result, the overflow information of the shift result decimal part of the left shift is obtained, comprising: according to the first exponent and the second exponent, a third exponent of the product is obtained; according to the third exponent, first overflow information of the shift result is obtained; if the OR-reduced result is 1 and the first overflow information is overflow, it is determined that the overflow information of the shift result decimal part is overflow; if the OR-reduced result is 0 or the first overflow information is no overflow, it is determined that the overflow information of the shift result decimal part is no overflow.

[0294] Optionally, the first overflow information of the shift result is obtained according to the third index, including: obtaining a first number of leading zeros of the first floating-point number and a second number of leading zeros of the second floating-point number; obtaining a third number of leading zeros of the product according to the first number of leading zeros and the second number of leading zeros; and obtaining the first overflow information of the shift result according to a comparison result of the third index and the third number of leading zeros.

[0295] Optionally, the shift mask and the product are subjected to an AND operation to obtain an AND operation result, including:

[0296] The shift mask and the product are subjected to an AND operation to obtain an initial AND operation result; and data from a highest bit to a first bit of the initial AND operation result is intercepted to obtain the AND operation result; wherein a total number of bits from the highest bit to the first bit of the initial AND operation result is equal to a width of a mantissa of a preset floating-point number type.

[0297] Optionally, the value of the highest bit of the initial mask is right-shifted according to the left shift number to obtain the shift mask, including: obtaining a third index of the product according to the first index and the second index; if the third index is equal to zero, right-shifting the value of the highest bit of the initial mask according to a first shift value to obtain the shift mask; the first shift value is equal to a sum of the left shift number and 1; if the third index is not equal to zero, right-shifting the value of the highest bit of the initial mask according to the left shift number to obtain the shift mask.

[0298] Optionally, in a case where the shift direction includes right shifting and the shift bit number includes a right shift number, the overflow information of the decimal part of the shift result is obtained according to the to-be-shifted parameter, including:

[0299] If the value of the highest bit of the decimal part of the product is equal to 1 and the right shift number is equal to 1, it is determined that the decimal part of the shift result overflows; if the value of the highest bit of the decimal part of the product is equal to 0 or the right shift number is not equal to 1, it is determined that the decimal part of the shift result does not overflow.

[0300] Optionally, the index of the shift result is adjusted according to the overflow information to obtain a multiplication result of the first floating-point number and the second floating-point number, including: if the overflow information is non-overflow or the value of each bit of the third index of the product is 1, the index is kept unchanged; if the overflow information is overflow and the value of at least one bit of the third index of the product is equal to 0, the index is subjected to a carry operation.

[0301] Optionally, the method further comprises: obtaining a first mantissa of the first floating point number and a second mantissa of the second floating point number; obtaining a first partial product according to the first mantissa and the second mantissa; compressing the first partial product to obtain a first compression result, and obtaining a second partial product of the first implicit bit of the first floating point number and the second implicit bit of the second floating point number in the process of compressing the first partial product; and obtaining the product of the first floating point number and the second floating point number according to the first compression result and the second partial product.

[0302] Step S9, after decimal shifting, the mantissa is rounded to obtain the mantissa of the product.

[0303] Step S10, according to the first exponent carry processing and the decimal rounding result, the result after the mantissa rounding is subjected to a second exponent carry processing to obtain the exponent of the product after the shifting operation.

[0304] Step S11, according to the sign, the exponent and the mantissa of the product, the mantissa, the product of the first floating point number and the second floating point number is obtained, which is a normal result.

[0305] Step S12, according to the mantissa of the product, the mantissa rounding result and the special result, the identification bit is obtained.

[0306] Step S13, according to the normal result and the special result, the final product operation result of the first floating point number and the second floating point number is obtained.

[0307] In one embodiment, referring to Figure 5 For the multiplication operation of the double-precision floating point number (f64), it can be divided into three periods for processing, the first period is used for parallel execution of steps S1 to S5, and the processing result is stored in the corresponding register 1. The second period is used for obtaining the data of steps S6 to S8, and the data is stored in the corresponding register 2. Steps S9 to S13 are executed in the third period. Based on the method of the embodiment, the result is calculated in half of the third period, and the data can be bypassed to other functional units for fast wake-up.

[0308] Continuing to refer to Figure 5 The decimal multiplication is realized by using the fast Booth and setting compression method, the partial product is stored in the register 1, and the partial product is added to obtain the product, and then the decimal shifting operation of step S8 is performed on the product. The setting compression method is the carry-saved adder (CSA) method.

[0309] In one embodiment, referring to Figure 6For multiplication of half-precision floating-point numbers (f16) and single-precision floating-point numbers (f32), the operation period can be shortened to two periods. The first period is used to perform steps S1 to S5 in parallel and store the processing results in the corresponding registers Reg; and the second period is used to perform steps S6 to S13. Based on the method of the embodiment, the second period is completed in half a period, and the data can be bypassed to other functional units for fast wake-up.

[0310] In combination Figure 5 and Figure 6 , the difference between the two processing methods is that Figure 6 The embodiment can calculate the product of floating-point numbers by a multiplication sign. Figure 5 The embodiment shown in the figure obtains the product of floating-point numbers by a fast Booth and CSA compression method.

[0311] It should be noted that f64 can also be implemented by the two-period processing method shown in Figure 6 f32 and f16 can also be implemented by the three-period processing method shown in Figure 5 .

[0312] The embodiment reduces the floating-point multiplication calculation period of f32 and f16 in the processor to two periods, and the floating-point multiplication calculation period of f64 to three periods, and supports fast wake-up. The embodiment can shorten the floating-point multiplication calculation period, improve the performance of the processor in executing floating-point multiplication instructions, and is not limited to the processor, but can also improve the calculation performance in other calculation fields that require floating-point multiplication.

[0313] For example, based on the method of the embodiment, in the application scenario of half-precision floating-point multiplication and single-precision floating-point multiplication based on a CPU processor, the period of floating-point multiplication in the related art is reduced from 3 to 2, and the total period is reduced by 33.3%.

[0314] Referring to Figure 7 , the embodiment also provides a floating-point multiplication circuit, which includes a shift result acquisition unit 301, a mantissa rounding operation unit 302 connected to the shift result acquisition unit, a rounding condition judgment unit 303 connected to the shift result acquisition unit, and a first multiplexer (MUX) 304 connected to the mantissa rounding operation unit and the rounding condition judgment unit.

[0315] The shift result acquisition unit 301 is configured to acquire a shift result of the product of the first floating-point number and the second floating-point number; the shift result is a result of a shift operation on a decimal part of the product; the mantissa rounding operation unit 302 is configured to perform a mantissa rounding operation on the shift result to obtain a mantissa rounding result of the shift result; the first judgment result acquisition unit 303 is configured to acquire a first judgment result of whether the mantissa satisfies a first preset rounding condition in the process of performing the mantissa rounding operation; and the first multiplexer 304 is configured to acquire a target mantissa of the multiplication result of the first floating-point number and the second floating-point number according to the mantissa rounding result if the first judgment result is that the mantissa satisfies the first preset rounding condition.

[0316] In the embodiment, the mantissa rounding result and the first judgment result of whether the mantissa satisfies the first preset rounding condition can be acquired in parallel, and compared with the method of first judging whether the mantissa satisfies the first preset rounding condition and then performing the mantissa rounding operation according to the judgment result, the embodiment reduces the operation time of the mantissa rounding and shortens the operation period of the floating-point number multiplication operation.

[0317] For example, referring to Figure 8 The shift result acquisition unit 301 includes a second multiplexer configured to receive a left shift number, a right shift number, and a shift direction judgment result (d1, d0, and sel) of whether left shift is needed, and perform a shift operation on the product dMul according to the left shift number to obtain the shift result in the case of left shift, or perform a shift operation on the product dMul according to the right shift number to obtain the shift result in the case of right shift.

[0318] It should be noted that in the embodiments of the present application, when the input signal sel of the multiplexer is 1, the data output by the multiplexer is the data corresponding to the input d1; and when the input signal sel of the multiplexer is 0, the data output by the multiplexer is the data corresponding to the input d0.

[0319] For example, referring to Figure 9 The first judgment result acquisition unit 303 includes a first parameter acquisition subunit and a first judgment result acquisition subunit connected to the first parameter acquisition subunit; the first parameter acquisition subunit is configured to acquire a first parameter of the shift result; the first parameter includes at least one of the following: a value of a first reserved bit of the shift result, a value of a first rounding bit, and a value of a first sticky bit; and the first judgment result acquisition subunit is configured to acquire the first judgment result of whether the mantissa satisfies the first preset rounding condition according to the first parameter.

[0320] For example, referring to Figure 9 ​The first parameter acquisition subunit is used to obtain the value Fracinit(0) in the least significant bit of the data from the highest to the fifth position of the preset mantissa, and to determine it as the value of the first reserved bit guard; it is also used to obtain the preset mantissa in The value of the first rounding bit is determined as the value of the first rounding bit; it is also used to obtain the preset mantissa from ( The value from the least significant bit to the first significant bit is then processed by the OR operation unit to adjust the preset mantissa from ( The value of the least significant bit and the value of the first sticky bit when the shift operation on the product is performed in the rightward direction. Perform an OR operation to obtain the value of the first sticky bit of the shift result.

[0321] For example, the processing logic for obtaining the sub-unit as the first parameter is as follows:

[0322]

[0323]

[0324]

[0325] For example, refer to Figure 9 The first judgment result acquisition subunit is used to receive the first parameter from the first parameter acquisition unit, and to obtain the first operation result according to the preset rounding mode, guard, and sticky. The second operation result is obtained based on the preset rounding mode, round, and sticky. The third operation result is obtained based on the preset rounding mode, round, and sticky. The fourth judgment result is obtained based on the preset rounding mode and round. The four sets of operation results are input into the adder to obtain the first judgment result. .

[0326] For example, the first judgment result acquisition sub-unit obtains the first judgment result according to the following method. :

[0327]

[0328]

[0329]

[0330]

[0331] Reference Figure 8The first parameter acquisition unit further comprises a shift mask acquisition subunit, an AND operation subunit (not shown in the figure) connected to the shift mask acquisition subunit, and an OR reduction operation subunit (not shown in the figure) connected to the AND operation subunit.

[0332] The shift mask acquisition subunit is configured to acquire a shift mask. Data from a first position of the shift mask to a lowest bit of the shift mask is 1, and data of other bits of the shift mask is 0. A total number of bits from the first position to the lowest bit of the shift mask is equal to a right shift number of a right shift operation on a decimal part of the product.

[0333] The AND operation subunit is configured to perform an AND operation on the shift mask and first data to obtain an AND operation result. The first data is data from a second position of the decimal part to a lowest bit of the product, wherein a total number of bits from the second position to the lowest bit of the product is equal to a mantissa bit width corresponding to the preset floating-point number type.

[0334] The OR reduction operation subunit is configured to perform an OR reduction operation on the AND operation result to obtain a value of the first stick bit.

[0335] The first parameter acquisition unit acquires the value of the first stick bit in the case of the right shift operation by the following method :

[0336]

[0337]

[0338] represents that a plurality of 1s are concatenated.

[0339]

[0340] The mantissa rounding operation unit 302 comprises an adder, and the adder is configured to perform a mantissa rounding operation on a preset mantissa in the shift result decimal to obtain a mantissa rounding result of the shift result.

[0341] Specifically, the mantissa rounding operation unit 302 is configured to acquire the preset mantissa , and intercept data of high bits, that is, intercept data from the highest bit to the fifth position, and perform a plus 1 operation on the data by the adder to obtain the mantissa rounding result .

[0342] For example, the mantissa rounding operation unit 302 acquires the mantissa rounding result by the following method :

[0343]

[0344] ​

[0345] For example, the circuit also includes a preset mantissa acquisition unit connected to the mantissa rounding operation unit 302. The preset mantissa acquisition unit includes a first preset mantissa acquisition unit, a second preset mantissa acquisition unit, an operation unit, and a sixth multiplexer connected to the first preset mantissa acquisition unit, the second preset mantissa acquisition unit, and an adder.

[0346] The first preset last digit acquisition unit is used to acquire the first preset last digit. :

[0347]

[0348] That is, the shift result From the third position ( The data up to the least significant bit (0) is determined as the first preset mantissa. .

[0349] The second preset last digit acquisition unit is used to acquire the second preset last digit. :

[0350]

[0351] That is, the shift result Fourth position ( The result of padding the least significant bit (0) of the data is determined as the second preset mantissa. .

[0352] As shown in 8, Figure 8 The AND operation unit is used to perform an AND operation on shift information (whether the shift operation is a left shift), overflow information (whether the product decimal overflows), and the OR reduction operation result of the product exponent, to obtain a judgment result on whether the shift result satisfies the first condition. :

[0353]

[0354] As shown in 8, Figure 8 The third multiplexer is used when the judgment result is In the case of [condition], the preset last digit is determined to be the first preset last digit; otherwise, the preset last digit is determined to be the second preset last digit, that is:

[0355]

[0356] For example, refer to Figure 10The circuit further comprises an overflow information obtaining unit, a fourth multiplexer connected to the overflow information obtaining unit, a preset exponent obtaining unit connected to the fourth multiplexer, and an exponent obtaining unit for obtaining the exponent when no overflow occurs.

[0357] The overflow information obtaining unit is configured to obtain the overflow information expIsOverFlow of the exponent, the fourth multiplexer obtains the overflow information expIsOverFlow, the exponent when no overflow occurs, and the preset target exponent , and implements the following method:

[0358]

[0359] According to the foregoing analysis, the exponent when no overflow occurs is :

[0360]

[0361]

[0362]

[0363] For example, the exponent obtaining unit can be configured to, if the overflow information is no overflow (expIsOverFlow = 0) , and the first determination result is that the exponent does not satisfy the first preset rounding condition, determine the data from the highest bit to the fifth bit of the preset exponent as the target exponent of the multiplication result; the total number of bits from the highest bit to the fifth bit of the preset exponent is equal to the exponent width of the preset floating-point number type.

[0364] For example, the exponent obtaining unit can be configured to, if the overflow information is no overflow, and the first determination result is that the exponent satisfies the first preset rounding condition, determine the rounding result of the exponent as the target exponent of the multiplication result.

[0365] The fourth multiplexer can be configured to, if the overflow information is overflow, determine the preset target exponent as the target exponent of the multiplication result.

[0366] Wherein:

[0367]

[0368]

[0369] According to the above expression, if the preset rounding mode is a rounding mode other than the rounding to zero mode, rounding down for positive numbers and rounding up for negative numbers, the preset exponent is an exponent with total bits equal to the exponent bit width corresponding to the preset floating-point number type and all bit values being 0;

[0370] If the preset rounding mode is the rounding to zero mode, rounding down for positive numbers or rounding up for negative numbers, the preset exponent is an exponent with total bits equal to the exponent bit width corresponding to the preset floating-point number type and all bit values being 1.

[0371] In an example, the circuit includes an exponent carry unit, a target exponent obtaining unit connected to the exponent carry unit, and a second judgment result obtaining unit connected to the target exponent obtaining unit.

[0372] The exponent carry unit is configured to obtain an exponent of a shift result and perform an exponent carry operation on the exponent of the shift result to obtain an exponent carry result.

[0373] The second judgment result obtaining unit is configured to obtain a second judgment result of whether the exponent of the shift result satisfies a first preset carry condition in the process of performing the exponent carry operation.

[0374] The target exponent obtaining unit is configured to, if the second judgment result is that the exponent satisfies the first preset carry condition, obtain a target exponent of a multiplication result of the first floating-point number and the second floating-point number according to the exponent carry result.

[0375] The target exponent obtaining unit is further configured to, if the second judgment result is that the exponent does not satisfy the first preset carry condition, obtain the target exponent of the multiplication result of the first floating-point number and the second floating-point number according to the exponent.

[0376] The second judgment result obtaining unit includes an AND reduction operation unit and an AND operation unit connected to the AND reduction operation unit. The AND reduction operation unit is configured to perform an AND reduction operation on data fracinit of the preset exponent from the highest bit to the fifth bit to obtain an AND reduction operation result. The AND operation unit performs an AND operation on the AND reduction operation result and the first judgment result roundUp to obtain the second judgment result. :

[0377]

[0378] According to the expression, if the exponent of the shift result does not satisfy the first preset rounding condition or the data of any bit of the exponent of the shift result is 0, it is determined that the second judgment result is that the exponent of the shift result does not satisfy the first preset carry condition.

[0379] In an example, refer to Figure 10The target exponent acquisition unit further includes a fifth multiplexer, which acquires overflow information (expIsOverFlow) indicating whether the exponent has overflowed, a preset target exponent expFoOverFlow, and an exponent expNoOverFlow when there is no overflow. It is further configured to: if the overflow information indicates overflow, determine the preset target exponent as the target exponent of the multiplication operation result; if the overflow information indicates no overflow and the second judgment result indicates that the exponent meets the first preset carry condition, determine the carry result of the exponent as the target exponent of the multiplication operation result; and if the overflow information indicates no overflow and the second judgment result indicates that the exponent does not meet the first preset carry condition, determine the exponent of the shifted result as the target exponent of the multiplication operation result.

[0380] That is, the fifth multiplexer obtains the target exponent expNormal according to the following processing logic:

[0381]

[0382] For example, the circuit also includes a preset target index acquisition module connected to the fifth multiplexer, which is used to acquire the preset target index according to the following method:

[0383]

[0384]

[0385] That is, the preset target exponent acquisition unit is used to determine the preset target exponent as an exponent with a total number of bits equal to the preset floating-point exponent width and all bits equal to 1 if the preset rounding mode is a rounding mode other than rounding to zero, rounding down for positive numbers, or rounding up for negative numbers. The preset target exponent acquisition unit is also used to determine the preset target exponent as an exponent with a total number of bits equal to the preset floating-point exponent width, the least significant bit being 0, and all other bits being 1 if the preset rounding mode is a rounding mode, rounding down for positive numbers, or rounding up for negative numbers.

[0386] Among them, reference Figure 10 The fifth multiplexer is connected to the sixth multiplexer. The sixth multiplexer is used to obtain the second judgment result expIsRoundup of whether the exponent meets the first preset carry condition, the exponent expForRound of the shift result, and the exponent carry result expinitup. Based on these data, the exponent expNoOverFlow is obtained when the exponent does not overflow.

[0387] The circuit further includes: an overflow information obtaining unit, configured to obtain overflow information of the exponent of the shift result; a first flag bit obtaining unit, configured to determine that the flag bit of the multiplication result is overflow if the overflow information of the exponent is overflow; a second flag bit obtaining unit, configured to determine that the flag bit of the multiplication result is inexact if the shift result satisfies any one of the second conditions; the second conditions include: the overflow information is overflow, the value of the first round bit of the shift result is 1, and the value of the first sticky bit of the shift result is 1; and a third flag bit obtaining unit, configured to determine that the flag bit of the multiplication result is underflow if the target exponent of the multiplication result is equal to 0, the exponent of the shift result does not satisfy a preset second carry condition, and the shift result satisfies any one of the third conditions.

[0388] With reference to Figure 11 , the second flag bit obtaining unit includes a first OR operation unit, and a second OR operation unit connected to the first OR operation unit.

[0389] The first OR operation unit is configured to perform OR operation on the values of the first round bit and the first sticky bit of the shift result to obtain a first OR operation result, and the second OR operation unit is configured to perform AND operation on the first OR operation result and the overflow information of the exponent to obtain the value of the flag bit of the shift result whether the shift result is inexact, i.e.:

[0390]

[0391] With reference to Figure 11 , the third flag bit obtaining unit includes a first AND operation unit, and a second AND operation unit connected to the first AND operation unit, configured to perform AND operation on the result whether the exponent is equal to 0 and the result whether the exponent does not satisfy the second carry condition (!expRoundUpuf) to obtain an AND operation result, and the second AND operation unit is configured to perform AND operation on the AND operation result and the value of the flag bit of the shift result whether the shift result is inexact (flagNx) to obtain the value of the flag bit of the shift result whether the shift result is underflow (flagsNF).

[0392] The third flag bit obtaining unit further includes a third judgment result obtaining subunit, with reference to Figure 12 , the third judgment result obtaining subunit is configured to perform AND reduction operation on data of the preset most significant bit to the fifth bit of the mantissa ( ), and then perform AND operation on the AND reduction operation result, the value of the second guard bit guarduf, and the judgment result whether the mantissa satisfies the second rounding condition ( ) to obtain the third judgment result whether the exponent satisfies the second carry condition (expRoundUpuf). That is:

[0393]

[0394] In an example, referring to Figure 13 , the circuit further comprises a second parameter obtaining subunit, and a third judging result obtaining subunit connected with the second parameter obtaining subunit.

[0395] The second parameter obtaining subunit obtains the value of the second reserved bit of the shift result , the value of the second rounding bit , and the value of the second sticky bit The third judging result obtaining subunit is used for obtaining the judging result of whether the mantissa satisfies the second rounding condition according to the value of the second reserved bit , the value of the second rounding bit , and the value of the second sticky bit . .

[0396] Further, referring to Figure 13 , the values of the second reserved bit , the second rounding bit , and the second sticky bit are respectively:

[0397]

[0398]

[0399]

[0400] Further, referring to Figure 13 , the third judging result obtaining subunit is used for obtaining the fifth operation result according to the preset shift rounding mode, guard and sticky: .

[0401] The sixth operation result is obtained according to the preset shift rounding mode, round and sticky: .

[0402] The seventh operation result is obtained according to the preset shift rounding mode, round and sticky .

[0403] The eighth operation result is obtained according to the preset shift rounding mode and round .

[0404] Then, the operation results are subjected to or reduction operation, and the judging result of whether the mantissa satisfies the second rounding condition is obtained :

[0405]

[0406] ​​

[0407]

[0408]

[0409] For example, referring to Figure 14 , the circuit further comprises a third OR operation unit, a third AND operation unit, a fourth AND operation unit, a fourth OR operation unit connected to the third AND operation unit and the fourth AND operation unit, and a fifth OR operation unit connected to the third OR operation unit and the fourth OR operation unit.

[0410] The third OR operation unit is configured to perform an OR operation on a result of whether the first floating-point number is snan (fp_a_is_snan) and whether the second floating-point number is snan (fp_b_is_snan) to obtain a first OR operation result; the third AND operation unit is configured to perform an AND operation on a result of whether the first floating-point number is zero (fp_a_is_zero) and whether the first floating-point number is infinite (fp_a_is_inf) to obtain a first AND operation result; and the fourth AND operation unit is configured to perform an AND operation on a result of whether the second floating-point number is zero (fp_b_is_zero) and whether the second floating-point number is infinite (fp_b_is_inf) to obtain a second AND operation result.

[0411] The fourth OR operation unit is configured to perform an OR operation on the first AND operation result and the second AND operation result to obtain a second OR operation result, and the fifth OR operation unit is configured to perform an OR operation on the first OR operation result and the second AND operation result to obtain a value of an invalid flag. .

[0412]

[0413]

[0414] In addition, the circuit further comprises a fifth flag acquisition unit configured to obtain a value of a divide-by-zero flag, and the circuit is configured to perform the following operations:

[0415]

[0416] For example, referring to Figure 15 , the circuit further comprises a seventh multiplexer configured to obtain a result IsConst of determining whether the floating-point number is a special number, a value of a preset flag, , and values of five flags of 0, divide-by-zero, invalid operation, overflow, inaccuracy, and underflow, based on which a final output flag flags is obtained.

[0417]

[0418]

[0419] wherein, , and represent non-numeric, zero and infinity respectively.

[0420] With reference to Figure 16 , it shows a floating point multiplication device provided by an embodiment of the present application, the device comprising: a first obtaining module 401 configured to obtain a shift result of a product of a first floating point number and a second floating point number; the shift result is a result of a shift operation on a decimal part of the product; a second obtaining module 402 configured to perform a mantissa rounding operation on the shift result to obtain a mantissa rounding result of the shift result; a third obtaining module 403 configured to obtain a first judgment result of whether a mantissa satisfies a first preset rounding condition in the process of performing the mantissa rounding operation; and a fourth obtaining module 404 configured to, if the first judgment result is that the mantissa satisfies the first preset rounding condition, obtain a target mantissa of a multiplication result of the first floating point number and the second floating point number according to the mantissa rounding result.

[0421] Optionally, the third obtaining module 403 is further configured to: obtain a first parameter of the shift result; the first parameter comprises at least one of a value of a first reserved bit of the shift result, a value of a first rounding bit and a value of a first stick bit; and obtain the first judgment result of whether the mantissa satisfies the first preset rounding condition according to the first parameter.

[0422] Optionally, in the case where the shift operation comprises a right shift operation, the third obtaining module 403 is further configured to: obtain a shift mask; data of a first position of the shift mask to a lowest bit of the shift mask is 1, and data of other bits of the shift mask is 0; a total number of bits from the first position to the lowest bit of the shift mask is equal to a right shift number of the right shift operation on the decimal part of the product; obtain first data from a second position of the decimal part of the product to the lowest bit of the product; a total number of bits from the second position to the lowest bit of the product is equal to a difference between a total width corresponding to a preset floating point type and 1; perform an AND operation on the shift mask and the first data to obtain an AND operation result; and perform an OR reduction operation on the AND operation result to obtain the value of the first stick bit corresponding to the right shift operation.

[0423] Optionally, the second obtaining module 402 is further configured to perform a tail rounding operation on a preset tail of the shift result to obtain a tail rounding result of the shift result, wherein if the shift result satisfies a first condition, the preset tail comprises data from a third position to a lowest bit of the shift result, a total number of bits from the third position to the lowest bit of the shift result is equal to a sum of a tail bit width corresponding to a preset floating-point number type and 1, and the first condition comprises that the shift operation is a left shift operation, the decimal overflow of the product occurs, and the exponent of the product is not equal to 0; if the shift result does not satisfy the first condition, the preset tail comprises a zero padding result of performing a low-bit zero padding operation on data from a fourth position to the lowest bit of the shift result, and a total number of bits from the fourth position to the lowest bit of the shift result is equal to the tail bit width corresponding to the preset floating-point number type.

[0424] Optionally, the second obtaining module 402 is further configured to perform a plus 1 operation on data from a highest bit to a fifth position of the preset tail to obtain the tail rounding result of the shift result, wherein a total number of bits from the highest bit to the fifth position of the preset tail is equal to a tail width of the preset floating-point number type.

[0425] Optionally, the second obtaining module 402 is further configured to, if the first judgment result is that the tail does not satisfy the first preset rounding condition, obtain a target tail of the multiplication result of the first floating-point number and the second floating-point number according to the preset tail.

[0426] Optionally, the second obtaining module 402 is further configured to obtain overflow information of an exponent of the shift result, and if the overflow information is no overflow and the first judgment result is that the tail does not satisfy the first preset rounding condition, the method further comprises: determining data from a highest bit to a fifth position of the preset tail as the target tail of the multiplication result, and a total number of bits from the highest bit to the fifth position of the preset tail is equal to a tail width of a preset floating-point number type.

[0427] Optionally, the second obtaining module 402 is further configured to obtain overflow information of an exponent of the shift result, and if the overflow information is no overflow and the first judgment result is that the tail satisfies the first preset rounding condition, the obtaining, according to the tail rounding result, of the target tail of the multiplication result of the first floating-point number and the second floating-point number comprises: determining the tail rounding result as the target tail of the multiplication result.

[0428] Optionally, the second obtaining module 402 is further configured to: obtain overflow information of an exponent of the shift result; and determine a preset target mantissa as a target mantissa of the multiplication result if the overflow information is an overflow; wherein if the preset rounding mode is a rounding mode other than a rounding mode to zero, rounding down for positive numbers and rounding up for negative numbers, a total bit number of the preset target mantissa is equal to a mantissa bit width corresponding to a preset floating-point number type, and each bit value is 0; and if the preset rounding mode is the rounding mode to zero, the rounding down for positive numbers or the rounding up for negative numbers, the total bit number of the preset target mantissa is equal to the mantissa bit width corresponding to the preset floating-point number type, and each bit value is 1.

[0429] Optionally, the apparatus 40 further includes: a fifth obtaining module configured to obtain an exponent of the shift result and perform an exponent carry operation on the exponent of the shift result to obtain an exponent carry result; a sixth obtaining module configured to obtain a second determination result of whether the exponent of the shift result satisfies a first preset carry condition in the process of performing the exponent carry operation; and a seventh obtaining module configured to obtain a target exponent of a multiplication result of the first floating-point number and the second floating-point number according to the exponent carry result if the second determination result is that the exponent satisfies the first preset carry condition; and an eighth obtaining module configured to obtain the target exponent of the multiplication result of the first floating-point number and the second floating-point number according to the exponent if the second determination result is that the exponent does not satisfy the first preset carry condition.

[0430] Optionally, the sixth obtaining module is further configured to: determine that the second determination result is that the exponent of the shift result satisfies the first preset carry condition if the mantissa of the shift result satisfies the first preset rounding condition and each bit value of a preset mantissa of the shift result from a highest bit to a fifth bit position is 1; and determine that the second determination result is that the exponent of the shift result does not satisfy the first preset carry condition if the mantissa of the shift result does not satisfy the first preset rounding condition or any bit value of the preset mantissa of the shift result from the highest bit to the fifth bit position is 0.

[0431] Optionally, the apparatus 40 further comprises a ninth obtaining module configured to obtain overflow information of an exponent of the shift result; a first determining module configured to determine a preset target exponent as a target exponent of the multiplication result if the overflow information is an overflow; wherein, if the preset rounding mode is a rounding mode other than a rounding mode of rounding to zero, rounding down for positive numbers and rounding up for negative numbers, the preset target exponent is an exponent with a total bit number equal to an exponent bit width of the preset floating point number and each bit value being equal to 1; if the preset rounding mode is the rounding mode of rounding to zero, the rounding down for positive numbers or the rounding up for negative numbers, the preset target exponent is an exponent with a total bit number equal to the exponent bit width of the preset floating point number and a value of a lowest bit being 0 and values of other bits being 1.

[0432] Optionally, the apparatus 40 further comprises a tenth obtaining module configured to obtain overflow information of an exponent of the shift result; a fourth obtaining module configured to determine the exponent carry result as a target exponent of the multiplication result if the overflow information is not an overflow; and determine the exponent of the shift result as the target exponent of the multiplication result if the overflow information is not an overflow.

[0433] Optionally, the apparatus 40 further comprises an eleventh obtaining module configured to obtain overflow information of an exponent of the shift result; a second determining module configured to determine a sign bit of the multiplication result as an overflow if the overflow information of the exponent is an overflow; a third determining module configured to determine the sign bit of the multiplication result as an inaccuracy if the shift result satisfies any one of second conditions; the second conditions comprising: the overflow information is an overflow, the shift result first rounding bit and a value of the first stick bit are 1; a fourth determining module configured to determine the sign bit of the multiplication result as an underflow if the exponent of the product is equal to 0, the exponent of the shift result does not satisfy a preset second carry condition, and the shift result satisfies any one of the second conditions.

[0434] Optionally, the apparatus 40 further comprises a fifth determining module configured to determine the overflow information as an overflow if the exponent from a highest bit to a first bit is all 1 and the exponent satisfies a third condition; the third condition comprising: a value of a lowest bit of the exponent is 1 or the exponent satisfies the first preset carry condition; and a sixth determining module configured to determine that the exponent of the shift result does not satisfy a preset second carry condition if the shift result does not satisfy the third condition; the third condition comprising: data from a highest bit to a fifth bit of a preset mantissa of the shift result are all 1, a value of a second reserved bit of the shift result is 1, and the mantissa of the shift result satisfies a second preset rounding condition.

[0435] Optionally, the apparatus 40 further comprises a twelfth obtaining module configured to obtain a second parameter of the shift result; the second parameter comprises at least one of a value of a second reserved bit of the shift result, a value of a second rounding bit, and a value of a second sticky bit; and a thirteenth obtaining module configured to obtain a third determination result of whether the mantissa satisfies a second preset rounding condition according to the second parameter; wherein the value of the second reserved bit is a value of a sixth bit of the preset mantissa; a position interval between the sixth bit and a lowest bit of the preset mantissa is equal to a sum of a mantissa bit width of a preset floating-point number type and 1; the value of the second rounding bit is a value of a seventh bit of the preset mantissa; a total bit number from the seventh bit to the lowest bit of the preset mantissa is equal to the mantissa bit width of the preset floating-point number type; in a case where the shift operation is left shift, the value of the second sticky bit is an or reduction operation result of data from an eighth bit to the lowest bit of the preset mantissa; a total bit number from the eighth bit to the lowest bit of the preset mantissa is equal to a difference between the mantissa bit width of the preset floating-point number type and 1; and in a case where the shift operation is right shift, the value of the second sticky bit is equal to the value of the first sticky bit corresponding to the right shift operation.

[0436] In this embodiment, according to the first determination result and the parallel obtained mantissa rounding result, the target mantissa of the multiplication result can be directly obtained according to the calculated mantissa rounding result in a case where it is determined that the mantissa satisfies the first preset rounding condition. Compared with the method in the related art that first analyzes whether the mantissa needs to be rounded, and then calculates the mantissa rounding result in a case where it is determined that the mantissa needs to be rounded, this embodiment shortens the time for obtaining the target mantissa of the multiplication result, and shortens the multiplication operation period.

[0437] Figure 17 is a block diagram of an electronic device 500 according to an example embodiment. Referring to Figure 17 , the electronic device 500 can include one or more of the following components: a processing component 502, a memory 504, a power supply component 506, a multimedia component 508, an audio component 510, an input / output (I / O) interface 512, a sensor component 514, and a communication component 516.

[0438] The processing component 502 generally controls the overall operations of the electronic device 500. The processing component 502 can include one or more processors 520 to execute instructions. In addition, the processing component 502 can include one or more modules to facilitate the interaction between the processing component 502 and other components. The memory 504 is used to store data used by the electronic device 500. The memory 504 can be implemented using any type of volatile or non-volatile storage devices or a combination thereof, and the power component 506 provides power to the various components of the electronic device 500. The power component 506 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 500. The multimedia component 508 includes a screen to provide an output interface between the electronic device 500 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). In some embodiments, the multimedia component 508 includes a front camera and / or a rear camera.

[0439] The audio component 510 is configured to output and / or input audio signals. The received audio signals can be further stored in the memory 504 or transmitted via the communication component 516. In some embodiments, the audio component 510 further includes a speaker for outputting audio signals. The I / O interface 512 provides an interface between the processing component 502 and peripheral interface module. The sensor component 514 includes one or more sensors for providing status assessments of various aspects of the electronic device 500. For example, the sensor component 514 can detect an open / closed state of the electronic device 500, relative positioning of components, such as a display and a keypad of the electronic device 500, a change in position of the electronic device 500 or a component of the electronic device 500, the presence or absence of user contact with the electronic device 500, the orientation or acceleration / deceleration of the electronic device 500, and a temperature change of the electronic device 500. The sensor component 514 can include a proximity sensor configured to detect the presence of a nearby object without any physical touch. The sensor component 514 can also include a light sensor.

[0440] The communication component 516 is configured to facilitate wired or wireless communication between the electronic device 500 and other devices. The electronic device 500 can access a wireless network based on a communication standard. In an exemplary embodiment, the electronic device 500 can be implemented with one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic elements to implement a floating-point multiplication method provided by the embodiments.

[0441] In an example embodiment, a non-transitory computer readable storage medium including instructions, such as the memory 504 including instructions, is also provided, which can be executed by the processor 520 of the electronic device 500 to complete the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disc, and an optical data storage device, etc.

[0442] Figure 18 is a block diagram of an electronic device 600 according to an example embodiment. For example, the electronic device 600 can be provided as a server. Referring to Figure 18 , the electronic device 600 includes a processing component 622, which further includes one or more processors, and a memory resource represented by a memory 632, for storing instructions, such as an application program, executable by the processing component 622. The application program stored in the memory 632 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 622 is configured to execute the instructions to perform a floating point multiplication method provided by the embodiments of the present application.

[0443] The electronic device 600 can further include a power supply component 626 configured to perform power management of the electronic device 600, a wired or wireless network interface 650 configured to connect the electronic device 600 to a network, and an input / output (I / O) interface 658.

[0444] The embodiments of the present application also provide a computer program product including a computer program, which, when executed by a processor, implements a floating point multiplication method.

[0445] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. The specification and examples given are exemplary only. It is intended to include all such variations and modifications within the scope of the present application. The application disclosed herein is to be considered merely as illustrative and not restrictive of the inventive process.

[0446] It should be understood that the application is not limited to the precise structures as has been described and illustrated above, and that various modifications and changes can be made without departing from the scope thereof.

[0447] The above merely preferred embodiments of the present application, and not to limit the present application, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application, should be included in the protection scope of the present application. The above provides a floating point multiplication method, device, electronic equipment and computer readable storage medium, and the principle and implementation of the present application are described in this paper. The above embodiment is only used to help understand the method and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation and application range will be changed; in conclusion, the content of the specification should not be understood as the limitation of the present application.

Claims

1. A floating-point multiplication circuit, characterized in that, The circuit comprises a shift result acquisition unit, a mantissa rounding operation unit connected to the shift result acquisition unit, a rounding condition judging unit connected to the shift result acquisition unit, and a first multiplexer connected to the mantissa rounding operation unit and the rounding condition judging unit. The shift result acquisition unit is configured to acquire a shift result of a product of the first floating-point number and the second floating-point number; the shift result is a result of a shift operation on a decimal part of the product. The mantissa rounding operation unit is configured to perform a mantissa rounding operation on the shift result to obtain a mantissa rounding result of the shift result. The first judging result acquisition unit is configured to acquire a first judging result of whether the mantissa of the shift result satisfies a first preset rounding condition during the mantissa rounding operation. The first multiplexer is configured to acquire a target mantissa of a multiplication result of the first floating-point number and the second floating-point number according to the mantissa rounding result if the first judging result indicates that the mantissa satisfies the first preset rounding condition. The first judging result acquisition unit comprises a first parameter acquisition subunit and a first judging result acquisition subunit connected to the first parameter acquisition subunit; the first parameter acquisition subunit is configured to acquire a first parameter of the shift result; the first parameter comprises at least one of a value of a first reserved bit of the shift result, a value of a first rounding bit, and a value of a first stick bit; and the first judging result acquisition subunit is configured to acquire the first judging result of whether the mantissa satisfies the first preset rounding condition according to the first parameter.

2. The circuit of claim 1, wherein, The circuit further comprises an exponent carry unit, a target exponent acquisition unit connected to the exponent carry unit, and a second judging result acquisition unit connected to the target exponent acquisition unit. The exponent carry unit is configured to acquire an exponent of the shift result and perform an exponent carry operation on the exponent of the shift result to obtain an exponent carry result. The second judging result acquisition unit is configured to acquire a second judging result of whether the exponent of the shift result satisfies a first preset carry condition during the exponent carry operation. The target exponent acquisition unit is configured to acquire a target exponent of the multiplication result of the first floating-point number and the second floating-point number according to the exponent carry result if the second judging result indicates that the exponent satisfies the first preset carry condition. The target exponent acquisition unit is further configured to acquire the target exponent of the multiplication result of the first floating-point number and the second floating-point number according to the exponent if the second judging result indicates that the exponent does not satisfy the first preset carry condition.

3. The circuit of claim 1, wherein, The circuit further comprises: An overflow information acquisition unit configured to acquire overflow information of the exponent of the shift result. A first flag bit acquisition unit configured to determine that a flag bit of the multiplication result is overflow if the overflow information of the exponent is overflow. A second flag bit acquisition unit configured to determine that the flag bit of the multiplication result is inaccurate if the shift result satisfies any one of second conditions; the second conditions comprise that the overflow information is overflow and values of a first rounding bit and a first stick bit of the shift result are 1. The third flag acquisition unit is configured to determine the flag of the multiplication operation result as underflow if the exponent of the product is equal to 0, the exponent of the shift result does not satisfy a preset second carry condition, and the shift result satisfies any one of the second conditions.

4. The circuit of claim 1, wherein, The first parameter acquisition subunit is further configured to: acquire a shift mask, wherein data of a first position of the shift mask to a lowest bit of the shift mask is 1, data of other bits of the shift mask is 0, and a total number of bits from the first position to the lowest bit of the shift mask is equal to a right shift number of a decimal part of the product; acquire first data from a second position of the decimal part of the product to a lowest bit of the product; a total number of bits from the second position to the lowest bit of the product is equal to a difference between a total width corresponding to a preset floating-point number type and 1; perform an AND operation on the shift mask and the first data to obtain an AND operation result; perform an OR reduction operation on the AND operation result to obtain a value of the first sticky bit corresponding to the right shift operation.

5. The circuit of claim 1, wherein, The exponent rounding operation unit comprises an adder. The adder is configured to perform an exponent rounding operation on a preset exponent of the shift result to obtain an exponent rounding result of the shift result. If the shift result satisfies a first condition, the preset exponent comprises data of a third position to a lowest bit of the shift result, and a total number of bits from the third position to the lowest bit of the shift result is equal to a sum of an exponent bit width corresponding to a preset floating-point number type and 1. The first condition comprises that the shift operation is a left shift operation, the decimal part of the product overflows, and the exponent of the product is not equal to 0. If the shift result does not satisfy the first condition, the preset exponent comprises a zero padding result of performing a low bit zero padding operation on data of a fourth position to the lowest bit of the shift result, and a total number of bits from the fourth position to the lowest bit of the shift result is equal to the exponent bit width corresponding to the preset floating-point number type.

6. The circuit of claim 5, wherein, The exponent rounding operation unit is further configured to: perform a plus 1 operation on data of a highest bit to a fifth position of the preset exponent to obtain the exponent rounding result of the shift result. A total number of bits from the highest bit of the preset exponent to the fifth position is equal to an exponent width of the preset floating-point number type.

7. The circuit of claim 5, wherein, The circuit further comprises: an overflow information acquisition unit configured to acquire overflow information of the exponent of the shift result; If the overflow information is no overflow, and the first judgment result is that the exponent does not satisfy a first preset rounding condition, the first multiplexer is further configured to: determine data of a highest bit to a fifth position of the preset exponent as a target exponent of the multiplication operation result, and a total number of bits from the highest bit of the preset exponent to the fifth position is equal to the exponent width of the preset floating-point number type.

8. The circuit of claim 5, wherein, The circuit further comprises: an overflow information acquisition unit configured to acquire overflow information of the exponent of the shift result; If the overflow information is no overflow, and the first judgment result is that the exponent satisfies a first preset rounding condition, the first multiplexer is further configured to: determine data of a highest bit to a fifth position of the preset exponent as a target exponent of the multiplication operation result, and a total number of bits from the highest bit of the preset exponent to the fifth position is equal to the exponent width of the preset floating-point number type. The mantissa rounding result is determined as a target mantissa of the multiplication operation result.

9. The circuit of claim 5, wherein, The circuit further comprises: an overflow information obtaining unit configured to obtain overflow information of an exponent of the shift result; The first multiplexer is further configured to determine a preset target mantissa as the target mantissa of the multiplication operation result if the overflow information is an overflow; If the preset rounding mode is a rounding mode other than the rounding to zero mode, rounding down for positive numbers and rounding up for negative numbers, the total bit number of the preset target mantissa is equal to a mantissa bit width corresponding to the preset floating-point number type, and each bit value is 0. If the preset rounding mode is the rounding to zero mode, rounding down for positive numbers or rounding up for negative numbers, the total bit number of the preset target mantissa is equal to the mantissa bit width corresponding to the preset floating-point number type, and each bit value is 1.

10. The circuit of claim 2, wherein, The second judgment result obtaining unit is further configured to: If the mantissa of the shift result satisfies the first preset rounding condition, and each bit value of the preset mantissa of the shift result from the highest bit to the fifth bit is 1, it is determined that the second judgment result is that the exponent of the shift result satisfies a first preset carry condition. The total bit number from the highest bit of the preset mantissa to the fifth bit is equal to a mantissa width of the preset floating-point number type. If the mantissa of the shift result does not satisfy the first preset rounding condition, or the value of any bit of the preset mantissa of the shift result from the highest bit to the fifth bit is 0, it is determined that the second judgment result is that the exponent of the shift result does not satisfy the first preset carry condition.

11. The circuit of claim 2, wherein, The circuit further comprises: an overflow information obtaining unit configured to obtain overflow information of an exponent of the shift result; The target exponent obtaining unit is further configured to: If the overflow information is an overflow, a preset target exponent is determined as a target exponent of the multiplication operation result. If the preset rounding mode is a rounding mode other than the rounding to zero mode, rounding down for positive numbers and rounding up for negative numbers, the preset target exponent is an exponent with a total bit number equal to an exponent bit width of the preset floating-point number and each bit value equal to 1. If the preset rounding mode is the rounding to zero mode, rounding down for positive numbers or rounding up for negative numbers, the preset target exponent is an exponent with a total bit number equal to the exponent bit width of the preset floating-point number, a value of a lowest bit being 0 and values of other bits being 1.

12. The circuit of claim 2, wherein, The circuit further comprises: an overflow information obtaining unit configured to obtain overflow information of an exponent of the shift result; If the overflow information is not an overflow, and the second judgment result is that the exponent satisfies the first preset carry condition, the target exponent obtaining unit is further configured to: determine the exponent carry result as the target exponent of the multiplication operation result. If the overflow information is not an overflow, and the second judgment result is that the exponent does not satisfy the first preset carry condition, the target exponent obtaining unit is further configured to: determine the exponent of the shift result as the target exponent of the multiplication operation result.

13. The circuit of any one of claims 3, 7, 8, 9, 11 and 12, characterized by The overflow information obtaining unit is further configured to: If the exponent has a value of 1 from the highest bit to the first bit, and the exponent satisfies a third condition, the overflow information is determined to be an overflow; the third condition includes that the value of the lowest bit of the exponent is 1, or the exponent satisfies the first preset carry condition; If the shift result does not satisfy the third condition, it is determined that the exponent of the shift result does not satisfy a preset second carry condition, and the third condition includes that the data from the highest bit to the fifth bit of the preset mantissa of the shift result are all 1, the value of the second reserved bit of the shift result is 1, and the mantissa of the shift result satisfies a second preset rounding condition.

14. The circuit of any one of claims 3, 7, 8, 9, 11 and 12, characterized by The overflow information acquisition unit is further configured to: acquire a second parameter of the shift result; the second parameter includes at least one of the following: the value of the second reserved bit of the shift result, the value of the second rounding bit, and the value of the second stick bit; acquire a third determination result of whether the mantissa satisfies a second preset rounding condition according to the second parameter; the value of the second reserved bit is the value of the sixth bit of the preset mantissa; the interval between the sixth bit and the lowest bit of the mantissa is equal to the sum of the mantissa bit width of the preset floating-point number type and 1; the value of the second rounding bit is the value of the seventh bit of the preset mantissa; the total number of bits from the seventh bit to the lowest bit of the preset mantissa is equal to the mantissa bit width of the preset floating-point number type; in the case of left shift operation, the value of the second stick bit is the result of the or reduction operation of the data from the eighth bit to the lowest bit of the preset mantissa; the total number of bits from the eighth bit to the lowest bit of the preset mantissa is equal to the difference between the mantissa bit width of the preset floating-point number type and 1; in the case of right shift operation, the value of the second stick bit is equal to the value of the first stick bit corresponding to the right shift operation.

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