Optimization method of FPGA carry chain unit

Abstract

The invention discloses an optimization method of an FPGA carry chain unit. The optimization method comprises the steps that each calculation unit is traversed from the head and / or the tail of a carry chain to be optimized; whether elements meeting preset conditions exist in each calculation unit or not is determined, to-be-optimized elements are obtained, and the preset conditions comprise at least one of the following conditions: the input is a constant, the output is a constant, and the inputs are the same; and deleting the to-be-optimized element from the to-be-optimized carry chain, and reconstructing the connection topology of the to-be-optimized carry chain to obtain an optimized carry chain. By deleting and reconstructing the connection topology of the carry chain to be optimized, the part which can be reused or can be omitted in a logic calculation process is simplified, so that the number of resources, occupied by the carry chain, of an FPGA chip is reduced; according to the method, a lookup table is not used for optimizing the carry chain, so that the delay caused by the method can be avoided, and the computing efficiency is ensured while the resource occupation condition is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to an optimization method of a carry chain unit of an FPGA. BACKGROUND

[0002] As a core device of reconfigurable computing, the internal configurable logic block (CLB) of a field programmable gate array (FPGA) realizes flexible configuration through a programmable interconnection network and can realize different functions. The CLB contains different hardware resources, generally including a lookup table (LUT), a multiplexer (MUX), a carry chain, and a flip-flop (FF). The carry chain is a hardware structure in the FPGA that is specially used to accelerate arithmetic operations. In arithmetic operations (such as addition and subtraction), the carry signal needs to be transmitted from the lowest bit to the highest bit level by level. The traditional method uses general logic units (such as LUTs) to realize carry logic, but there is a delay of waiting level by level. The carry chain directly transmits the carry signal through a special hardware path, which can avoid this delay and is a key resource of high-speed adders, counters, and other arithmetic modules.

[0003] With the expansion of FPGA application scenarios to high-performance computing (such as AI inference and 5G baseband), the complexity of arithmetic logic increases exponentially, the number of required operations increases sharply, and the required carry chain resources also increase sharply.

[0004] Since there is an upper limit to the number of FPGA resources, some methods use lookup tables to realize the corresponding logic of the carry chain when the number of carry chain resources in the FPGA design reaches the upper limit, thereby reducing the use of carry chains and breaking through the resource bottleneck of the carry chain. However, the carry delay of the lookup table implementation is much higher than that of the carry chain, which will bring higher latency and cause the clock frequency to drop. In terms of function, the operation speed is slower, the time for completing a computing task is increased, and effective computing results cannot be obtained within a limited running time.

[0005] Another method is to directly select an FPGA chip with a higher number of resources, but the number of resources on the FPGA chip is strongly positively correlated with the price. When the required carry chain resources exceed the upper limit, more resources are needed to realize the expected function of the FPGA chip, and a higher-end and more expensive FPGA chip needs to be used.

[0006] Therefore, the current carry chain unit optimization method has the problems of high cost and poor computing efficiency of the optimized carry chain.

[0007] In view of the above problems, an optimization method of an FPGA carry chain unit is needed to realize high-performance arithmetic operation support under the constraint of limited FPGA chip resources by reducing the use of carry chain resources. SUMMARY

[0008] The embodiment of the present application provides an optimization method of an FPGA carry chain unit, which can solve the above technical problems.

[0009] The embodiment of the present application provides an optimization method of an FPGA carry chain unit, which is used on an FPGA chip, the FPGA chip comprises at least one to-be-optimized carry chain, the to-be-optimized carry chain is composed of a plurality of cascaded calculation units, and the method comprises the following steps of: traversing each calculation unit from the head and / or tail of the to-be-optimized carry chain; determining whether there is an element meeting a preset condition in each calculation unit to obtain a to-be-optimized element, wherein the preset condition comprises at least one of the following: input is a constant, output is a constant, or input is the same; deleting the to-be-optimized element from the to-be-optimized carry chain and reconstructing the connection topology of the to-be-optimized carry chain to obtain an optimized carry chain.

[0010] Compared with the prior art, the embodiment of the present application has the beneficial effects that: by deleting and reconstructing the connection topology of the to-be-optimized carry chain, the present application simplifies the part that can be reused or the logical calculation process that can be omitted, thereby reducing the number of resources of the FPGA chip occupied by the carry chain; since the present application does not use LUT to optimize the carry chain, the delay caused by this method can be avoided, and the calculation efficiency is ensured while the resource occupation is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 A structure diagram of a to-be-optimized carry chain is provided for the embodiment of the present application; Figure 2 An implementation flowchart of the optimization method of the FPGA carry chain unit is provided for the embodiment of the present application; Figure 3a A structure diagram of a carry chain after deleting an i-th level data selector is provided for the embodiment of the present application; Figure 3b A structure diagram of a carry chain after deleting an i-th level exclusive-OR gate is provided for the embodiment of the present application; Figure 3c A structure diagram of a carry chain after deleting an i-th level data selector and an i-th level exclusive-OR gate is provided for the embodiment of the present application; Figure 4A structure schematic diagram of a carry chain provided by an embodiment of the present application; Figure 5a A structure schematic diagram of a carry chain to be optimized after deleting a data selector and reconstructing a topology connection when an output is a constant provided by an embodiment of the present application; Figure 5b A structure schematic diagram of a carry chain to be optimized after deleting a data selector and reconstructing a topology connection when Si is a constant 1 or input is equal provided by an embodiment of the present application; Figure 5c A structure schematic diagram of a carry chain to be optimized after deleting a data selector and reconstructing a topology connection when Si is a constant 0 or input is equal provided by an embodiment of the present application; Figure 6a A structure schematic diagram of a carry chain to be optimized after deleting an XOR gate and reconstructing a topology connection when COi-1 is a constant 0 provided by an embodiment of the present application; Figure 6b A structure schematic diagram of a carry chain to be optimized after deleting an XOR gate and reconstructing a topology connection when COi-1 is a constant 1 provided by an embodiment of the present application; Figure 7a A structure schematic diagram of a carry chain to be optimized after deleting an XOR gate, a data selector and reconstructing a topology connection when Si, I1i, COi-1 are constants provided by an embodiment of the present application; Figure 7b A structure schematic diagram of a carry chain to be optimized after deleting an XOR gate, a data selector and reconstructing a topology connection when I1i, COi-1 are constants 1 provided by an embodiment of the present application; Figure 7c A structure schematic diagram of a carry chain to be optimized after deleting an XOR gate, a data selector and reconstructing a topology connection when I1i, COi-1 are constants 1 provided by another embodiment of the present application; Figure 8 A scenario schematic diagram of optimization of a carry chain provided by an embodiment of the present application.

[0012] Reference signs: XOR(i): the i-th XOR gate; MUX(i): the i-th data selector; COi: the i-th carry data; Si: the i-th signal data; Oi: the i-th calculation result; I1i: the i-th data to be calculated; SO: signal data output end; DO: sum input end; IO: data to be calculated output end.

[0013] Reference signs: XOR(i): the i-th XOR gate; MUX(i): the i-th data selector; COi: the i-th carry data; Si: the i-th signal data; Oi: the i-th calculation result; Ili: the i-th data to be calculated; SO: signal data output terminal; DO: sum input terminal; IO: data to be calculated output terminal. DETAILED DESCRIPTION

[0014] In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, circuits, and

[0015] It will be understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0016] It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0017] As used in the description of the application and the appended claims, the term "if' can be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted to mean "upon determining" or "in response to determining" or "upon [the described condition or event] being detected" or "in response to [the described condition or event] being detected," depending on the context.

[0018] In addition, the terms "first," "second," "third," etc. are used herein only to describe different aspects of the application and are not intended to denote relative importance of the different aspects.

[0019] Reference within the specification of this document to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in some embodiments" in various places within specified

[0020] The application will be further described in detail with reference to specific embodiments, but the embodiments of the application are not limited thereto.

[0021] Embodiment 1 Figure 1 An example of a structure of a carry chain to be optimized is shown. By way of example and not limitation, see Figure 1 A carry chain to be optimized can be composed of Imax cascaded calculation units.

[0022] In a possible implementation, see Figure 1 Each calculation unit can include a data selector and an XOR gate.

[0023] Specifically, when i is greater than 0, the I0 input end of the i-th XOR gate XOR(i) in the (i+1)-th calculation unit can be connected to the output end of the (i-1)-th data selector MUX(i-1) in the i-th calculation unit, the I0 input end inputs the (i-1)-th carry data COi-1 to the XOR gate XOR(i); the I1 input end is connected to the signal data output end SO, inputs the i-th signal data Si; and the output end is connected to the sum input end DO, outputs the i-th calculation result Oi to the sum input end DO.

[0024] Specifically, when i is greater than 0, the I0 input end of the i-th data selector MUX(i) can also be connected to the output end of the (i-1)-th data selector MUX(i-1), the I0 input end inputs the (i-1)-th carry data COi-1 to the i-th data selector MUX(i); the I1 input end is connected to the to-be-calculated data output end IO, inputs the i-th to-be-calculated data I1i; the signal input end is connected to the signal data output end SO, inputs the i-th signal data Si; and the output end is connected to the I0 input end of the (i+1)-th data selector MUX(i+1) and the (i+1)-th XOR gate XOR(i+1), outputs the i-th carry data COi to them.

[0025] Here, i can be a non-negative integer less than or equal to Imax-1, when i = 0, the signal inputted into the 0th level XOR gate XOR(0) and the I0 input end of the 0th level data selector MUX(0) in the 1st calculation unit can be the initial carry signal Cin set.

[0026] In one example, the combinational logic expression of the ith level data selector MUX(i) can be expressed as: (1.1), Wherein, represents negation.

[0027] In one example, the combinational logic expression of the ith level XOR gate XOR(i) can be expressed as: (1.2).

[0028] Embodiment 2 Figure 2 An implementation flowchart of the optimization method of the FPGA carry chain unit is shown. As an example but not limitation, the method can include steps S201-S205, which are described below.

[0029] S201, starting from the head and / or tail of the carry chain to be optimized, each calculation unit is traversed.

[0030] In one example, the data selector and XOR gate in each calculation unit can be traversed and checked from the head or tail of the carry chain to be optimized to determine whether it meets the preset condition.

[0031] In another example, the data selector / XOR gate in each calculation unit can also be traversed and checked from the head of the carry chain to be optimized, and the XOR gate / data selector in each calculation unit can be traversed and checked from the tail.

[0032] Starting from the head and / or tail to check the carry chain, and preferentially deleting the elements at both ends, can ensure that the carry chain to be optimized will not be split into two, and ensure the integrity of the carry chain.

[0033] S202, determine whether there is an element in each calculation unit that meets the preset condition, and obtain the element to be optimized.

[0034] In some embodiments, the element to be optimized can include a data selector and / or an XOR gate.

[0035] For example, the user can select the type of the element to be optimized according to the resource occupation in the FPGA chip. For example, the number of data selectors / XOR gates in the FPGA chip is limited, and the resources of other elements are sufficient, and the data selector / XOR gate needs to be released in priority, at this time, the user can screen the data selector / XOR gate meeting the preset condition from the calculation unit. Or when the resources of the data selector and the XOR gate in the FPGA chip are both relatively tight, the data selector and the XOR gate meeting the preset condition can be screened at the same time.

[0036] It should be understood that when the element to be optimized herein includes the data selector and the XOR gate, the optimized data selector and the XOR gate can belong to the same calculation unit or belong to different calculation units.

[0037] In a possible implementation, the preset condition can include at least one of the following: the input is a constant, the output is a constant, or the input is the same.

[0038] For example, the output is a constant, that is, each input is a constant, and when the preset condition includes the output being a constant, the implicit condition is that the input is a constant.

[0039] In an example, if the element to be optimized includes the data selector, the preset condition includes the first type of preset condition, which can specifically include: the i-th level carry data COi is a constant (the output is a constant), the i-th level signal data Si is a constant (the input is a constant), or the i-th level to-be-calculated data I1i is equal to the i-1-th level carry data COi-1 (the input is equal).

[0040] In another example, if the element to be optimized includes the XOR gate, the preset condition includes the second type of preset condition, which can specifically include: the i-th level calculation result Oi is a constant (the output is a constant) or the i-1-th level carry data COi-1 is a constant (the input is a constant).

[0041] S203, deleting the element to be optimized from the carry chain to be optimized, and reconstructing the connection topology of the carry chain to be optimized to obtain an optimized carry chain.

[0042] In a possible implementation, the element to be optimized can be deleted from the carry chain by disconnecting the connection relationship between the element to be optimized and other elements in the carry chain.

[0043] In an example, referring to Figure 3aIf the element to be optimized comprises the i-th data selector MUX(i), the connection between the I0 input of the i-th data selector MUX(i) and the output of the (i-1)-th data selector MUX(i-1), the connection between the I1 input of the i-th data selector MUX(i) and the data output to be calculated IO, the connection between the signal input of the i-th data selector MUX(i) and the signal data output SO, and the connection between the output of the i-th data selector MUX(i) and the I0 input of the (i+1)-th data selector MUX(i+1) and the I0 input of the (i+1)-th XOR gate XOR(i+1) can be disconnected, so as to delete the i-th data selector MUX(i) in the carry chain to be optimized.

[0044] In another example, referring to Figure 3b If the element to be optimized comprises the i-th XOR gate XOR(i), the connection between the I0 input of the i-th XOR gate XOR(i) and the output of the (i-1)-th data selector MUX(i-1), the connection between the I1 input of the i-th XOR gate XOR(i) and the signal data output SO, and the connection between the output of the i-th XOR gate XOR(i) and the sum input DO can be disconnected, so as to delete the i-th XOR gate XOR(i) in the carry chain to be optimized.

[0045] In yet another example, referring to Figure 3c If the element to be optimized comprises the i-th data selector MUX(i) and the i-th XOR gate XOR(i), the two elements can be disconnected from the remaining elements and ports in the carry chain by referring to the method described above Figure 3a , Figure 3b , and deleted from the carry chain to be optimized.

[0046] In a possible implementation, after deleting the element, the connection topology of the carry chain to be optimized can be reconstructed based on the preset condition met by the element to be optimized, so as to obtain the optimized carry chain.

[0047] Optionally, the optimization method can further comprise steps S204-S205.

[0048] S204, determining whether there is a carry chain with the same logic in the FPGA chip.

[0049] For example, the same logic means that the input and output are the same. Referring to the complete carry chain structure shown in Figure 4 , the same input and output means that the initial carry signal Cin, the i-th signal data Si, and the i-th data to be calculated I1i are the same. Since the data of the I0 input of the MUX(i) and XOR(i) is COi-1, the two data are necessarily the same when the aforementioned data are the same, and thus comparison is not needed here.

[0050] S205, selecting one optimized carry chain from the carry chains with the same logic, keeping the selected carry chain, deleting the rest of the optimized carry chains, and reconstructing the output relationship of the kept carry chain to obtain the optimized FPGA chip.

[0051] For example, the output of the kept carry chain can be connected to the sum input DO of the other deleted carry chain to obtain the optimized FPGA chip.

[0052] For example, referring to the two netlists shown in Table 1 below, where xor_i represents the i-th XOR gate XOR(i), I0(·), I1(·), and O(·) after xor_i represent the data COi-1 / Cin input to the I0 input, the data Si input to the I1 input, and the data Oi output by the i-th XOR gate XOR(i); mux_i represents the i-th data selector MUX(i), and I0(·), I1(·), S(·), and O(·) after mux_i represent the data COi-1 / Cin input to the I0 input, the data I1i input to the I1 input, the data Si input to the signal input, and the data COi output by the i-th data selector MUX(i). As can be seen from Table 1, the inputs and outputs of the first and second calculation units in the carry chain aft_opt and the carry chain bef_opt are the same, so the carry chain bef_opt can be kept, the first and second calculation units in the carry chain bef_opt can be deleted, and then the 0-th and 1-st level outputs COi and Oi of the carry chain bef_opt can be connected to the 0-th and 1-st level output ports of the carry chain aft_opt.

[0053] Table 1

[0054] The method provided by the application optimizes the carry chain, simplifies the part that can be reused or the part whose logic calculation process can be omitted by deleting and reconstructing the connection topology of the carry chain to be optimized, thereby reducing the number of resources occupied by the carry chain in the FPGA chip; since the application does not use LUT, the calculation efficiency can be ensured while reducing the resource occupation.

[0055] By deleting and optimizing the carry chains with the same logic, the resources occupied by the carry chain in the FPGA chip can be further reduced.

[0056] Embodiment 3 Figure 5a - Figure 5c The structure of the carry chain to be optimized after the data selector is deleted and the topology connection is reconstructed is shown.

[0057] Here, the case that the elements to be optimized in the same calculation unit only includes the data selector is discussed.

[0058] As an example, referring to Figure 5a , if the i-th level signal data Si, the i-th level data to be calculated I1i, and the i-1-th level carry data COi-1 are all constants, the output of the i-th level data selector, i.e. the i-th level carry data COi, is also a constant; at this time, after deleting the i-th level data selector MUX(i), the pre-calculated i-th level carry data COi can be directly output to the i+1-th level data selector MUX(i+1) and the i+1-th level XOR gate XOR(i+1).

[0059] Alternatively, if the value of COi is the same as one of Si, I1i, and COi-1, for example, Si, the signal data output terminal SO can be connected to the I0 input terminal of the i+1-th level data selector MUX(i+1) and the i+1-th level XOR gate XOR(i+1), and Si can be output as COi.

[0060] As another example, if the i-th level carry data Si is a constant, according to the above formula (1.1), it can be seen that when Si=1, the COi output by the i-th level signal data selector is I1i; when Si=0, the COi output by the i-th level signal data selector is COi-1. Therefore, referring to Figure 5b , when Si is a constant 1, after deleting the i-th level data selector MUX(i), the data to be calculated output terminal IO can be connected to the I0 input terminal of the i+1-th level data selector MUX(i+1) and the i+1-th level XOR gate XOR(i+1), and I1i can be output as COi. Referring to Figure 5c , when Si is a constant 0, after deleting the i-th level data selector MUX(i), the output terminal of the i-1-th level data selector MUX(i-1) can be connected to the I0 input terminal of the i+1-th level data selector MUX(i+1) and the i+1-th level XOR gate XOR(i+1), and COi-1 can be output as COi.

[0061] As yet another example, if the i-th level data to be calculated I1i is equal to the i-1-th level carry data COi-1, according to the above formula (1.1), COi=COi-1=I1i; therefore, referring to Figure 5b , the data to be calculated output terminal IO can be connected to the I0 input terminal of the i+1-th level data selector MUX(i+1) and the i+1-th level XOR gate XOR(i+1), and I1i can be output as COi; referring to Figure 5c, you can also connect the output end of the i-1th level data selector MUX(i-1) and the i+1th level data selector MUX(i+1) and the I0 input end of the i+1th level exclusive OR gate XOR(i+1), and output COi-1 as COi.

[0062] Example 4 Figure 6a - Figure 6b The figure shows a schematic structural diagram of a carry chain to be optimized after deleting XOR gates and reconstructing topological connections, provided by an embodiment of the present invention.

[0063] Here, the case where the elements to be optimized in the same computing unit only include XOR gates is discussed.

[0064] As an example, if the i-th level signal data Si and the i-1-th level carry data COi-1 are both constants, then the i-th level calculation result Oi is also a constant. Therefore, after deleting the i-th level exclusive OR gate XOR(i), the pre-calculated i-th level calculation result Oi can be directly output to the AND input terminal.

[0065] Similarly, if the value of Oi is the same as one of Si and COi-1, for example COi-1, the output terminal of the i-1th stage data selector MUX(i-1) can be connected to the input terminal DO, and COi-1 can be output as Oi.

[0066] As another example, see Figure 6a , if only COi-1 is a constant between COi-1 and Si, and COi-1=0, according to the above formula (1.2), it can be seen that Oi= Si; therefore, after deleting the i-th level exclusive OR gate XOR(i), the signal data output terminal SO and the input terminal DO can be connected, and the i-th level signal data Si can be output as the i-th level calculation result Oi.

[0067] As yet another example, see Figure 6b , if COi-1 is the only constant between COi-1 and Si, and COi-1=1, according to the above formula (1.2), it can be seen that Therefore, after deleting the i-th level exclusive OR gate XOR(i), the signal data output terminal SO and the input terminal DO can be connected, and the i-th level signal data Si can be inverted and output as the i-th level calculation result Oi.

[0068] Optionally, an inverter may be added between the signal data output terminal SO and the sum input terminal DO to perform an inversion operation and output the inverted value of Si to the sum input terminal.

[0069] Example 5 Figure 7a - Figure 7c The figure shows a schematic structural diagram of a carry chain to be optimized after deleting an XOR gate and a data selector and reconstructing the topological connection, provided by an embodiment of the present invention.

[0070] Here, the case where the elements to be optimized in the same calculation unit include both the XOR gate and the data selector is discussed.

[0071] Referring to Table 2 below, it can be seen that the case where the elements to be optimized include both the XOR gate and the data selector of the same calculation unit can occur under the following three conditions: (1) Si, I1i, COi-1 are constants, (2) I1i= COi-1 is a constant 1, (3) I1i= COi-1 is a constant 0.

[0072] As an example, referring to Figure 7a , if the i-th calculation unit satisfies the above condition (1), after deleting the i-th data selector MUX(i) and the i-th XOR gate XOR(i), the pre-calculated i-th carry-in data COi can be directly output to the i+1-th data selector MUX(i+1) and the i+1-th XOR gate XOR(i+1), and the pre-calculated i-th calculation result Oi can be output to the sum input DO.

[0073] As another example, referring to Figure 7b , if the i-th calculation unit satisfies the above condition (2), after deleting the i-th data selector MUX(i) and the i-th XOR gate XOR(i), the output of the i-1-th data selector MUX(i-1) can be connected to the I0 input of the i+1-th data selector MUX(i+1) and the I0 input of the i+1-th XOR gate XOR(i+1), the signal data output SO can be connected to the sum input DO with an inverter added thereto, the i-1-th carry-in data COi-1 can be input as the i-th carry-in data COi to the I0 inputs of the i+1-th data selector and the i+1-th XOR gate, and the i-th signal data Si can be output as the i-th calculation result Oi after being inverted.

[0074] Alternatively, referring to Figure 7c , if the i-th calculation unit satisfies the above condition (2), after deleting the i-th data selector MUX(i) and the i-th XOR gate XOR(i), the data to be calculated input IO can be connected to the I0 input of the i+1-th data selector MUX(i+1) and the I0 input of the i+1-th XOR gate XOR(i+1), the signal data output SO can be connected to the sum input DO with an inverter added thereto, the i-th data to be calculated I1i can be input as the i-th carry-in data COi to the I0 inputs of the i+1-th data selector MUX(i+1) and the i+1-th XOR gate XOR(i+1), and the i-th signal data Si can be output as the i-th calculation result Oi after being inverted.

[0075] As another example, if the i-th stage computing unit satisfies the above condition (3), the carry chain to be optimized can be restructured in the above manner Figure 7b , and the restructuring manner of each port is the same as Figure 7b , except that the i-th stage signal data Si is directly outputted as the i-th stage computing result Oi without adding an inverter.

[0076] Alternatively, if the i-th stage computing unit satisfies the above condition (3), the carry chain to be optimized can be restructured in the above manner Figure 7c , and the restructuring manner of each port is the same as Figure 7c , except that the i-th stage signal data Si is directly outputted as the i-th stage computing result Oi without adding an inverter.

[0077] Table 2: the element to be optimized includes a data selector and an XOR gate in the same computing unit

[0078] Embodiment 6 Figure 8 A scene schematic diagram of optimizing a carry chain provided by an embodiment of the application is shown.

[0079] For example, referring to the netlist of the carry chain before and after optimization shown in the following Table 3, it can be seen that the carry chain includes 4 stages of computing units, and similarly, xor_i represents the i-th stage XOR gate XOR(i), and I0(·), I1(·) and O(·) after xor_i represent the data COi-1 / Cin inputted by the I0 input end of the i-th stage XOR gate XOR(i), the data Si inputted by the I1 input end, and the data Oi outputted by the output end; mux_i represents the i-th stage data selector MUX(i), and I0(·), I1(·), S(·) and O(·) after mux_i represent the data COi-1 / Cin inputted by the I0 input end of the i-th stage data selector MUX(i), the data I1i inputted by the I1 input end, the data Si inputted by the signal input end, and the data COi outputted by the output end.

[0080] Table 3

[0081] Specifically, referring to Figure 8and the above table 3, mux_0 can be processed from the beginning, it can be seen that the inputs of mux_0 are all constants, according to the logic expression (1.1), the output is constant 0, this MUX can be optimized to be deleted, and the MUX is transmitted by the GND signal, and is directly connected to I0 of xor_1 and I0 of mux_1. The inputs of xor_0 are all constants, according to the logic expression (1.2), the output is constant 1, this XOR can be optimized to be deleted, and is directly connected to the and input port DO as O0 output by VCC. After mux_0 and xor_0 are processed, mux_1 is processed, I0 of mux_1 is reconnected to GND, and I1 is connected to GND, the two input signals are consistent, this MUX can be optimized to be deleted, and the MUX is transmitted by the GND signal, and is directly connected to I0 of xor_2 and I0 of mux_2. I0 of xor_1 is reconnected to GND, according to the logic expression, the output is the input signal a, this XOR can be optimized to be deleted, and a is directly connected to the and input port DO as O1 output. It can be seen that the inputs of mux_2 are not all constants, the input signal of the signal input end is variable a, and I0 of mux_2 is reconnected to GND, and I1 is connected to the input signal b, the two input signals are inconsistent, and cannot be deleted. I0 of xor_2 is reconnected to GND, according to the logic expression, the output is a, this XOR can be optimized to be deleted, and a is directly connected to the and input port DO as O2 output. At the same time, mux_3 is processed from the tail, the inputs of mux_3 are not all constants, the input signal of the signal input end is constant VCC, this MUX can be optimized to be deleted, and the signal of the input end I1 is transmitted by the MUX, and a is directly connected to the I0 input end of and_0 Figure 8 The topmost and gate in the above table 3.

[0082] Through the above processing process, the carry chain to be optimized in the above table 3 can be simplified to the carry chain optimized in the above table 4. Figure 8 Through the above processing process, the carry chain to be optimized in the above table 3 can be simplified to the carry chain optimized in the above table 4. Figure 8 Through the optimization process of the present application, nearly 3 / 4 of the data selectors and XOR gates can be reduced, and the resources in the FPGA chip are greatly released.

[0083] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

Claims

1. A method for optimizing an FPGA carry chain unit, characterized in that: The method is used on an FPGA chip, wherein the FPGA chip includes at least one carry chain to be optimized, and the carry chain to be optimized is composed of multiple cascaded computing units. The method includes: Traversing each computing unit starting from the head and / or tail of the carry chain to be optimized; Determining whether there is an element in each of the computing units that meets a preset condition, and obtaining an element to be optimized, wherein the preset condition includes at least one of the following: the input is constant, the output is constant, or the input is the same; The elements to be optimized are deleted from the carry chain to be optimized, and the connection topology of the carry chain to be optimized is reconstructed to obtain an optimized carry chain.

2. The method according to claim 1, characterized in that The computing unit includes a data selector and an XOR gate, and the element to be optimized includes a data selector and / or an XOR gate; The I0 input terminal of the i-th level XOR gate is connected to the output terminal of the i-1-th level data selector to input the i-1-th level carry data COi-1, the I1 input terminal is connected to the signal data output terminal to input the i-th level signal data Si, the output terminal is connected to the and input terminal to output the i-th level calculation result Oi, i is a non-negative integer less than or equal to Imax-1, and Imax is the total number of calculation units in the carry chain to be optimized; The I0 input terminal of the i-th level data selector is also connected to the output terminal of the i-1-th level data selector to input the i-1-th level carry data COi-1, the I1 input terminal is connected to the output terminal of the data to be calculated to input the i-th level data to be calculated I1i, the signal input terminal is connected to the signal data output terminal to input the i-th level signal data Si, and the output terminal is connected to the I0 input terminal of the i+1-th level data selector and the i+1-th level exclusive OR gate to output the i-th level carry data COi.

3. The method according to claim 2, characterized in that If the i-th stage data selector is the element to be optimized, the preset conditions specifically include: the i-th stage carry data COi is a constant, the i-th stage signal data Si is a constant, or the i-th stage to-be-calculated data I1i is equal to the i-1-th stage carry data COi-1; If the i-th level XOR gate is the element to be optimized, the preset conditions specifically include: the i-th level calculation result Oi is a constant or the i-1-th level carry data COi-1 is a constant.

4. The method according to claim 3, characterized in that The i-th stage data selector is the element to be optimized, and the i-th stage carry data COi is a constant; Reconstructing the connection topology of the carry chain to be optimized includes: The pre-calculated i-th stage carry data COi is directly input to the i+1-th stage data selector and the I0 input terminal of the i+1-th stage XOR gate.

5. The method according to claim 3, characterized in that The i-th stage data selector is the element to be optimized, and the i-th stage signal data Si is a constant; If the i-th level signal data Si is a constant 1, then reconstructing the connection topology of the carry chain to be optimized includes: Connecting the output terminal of the data to be calculated to the I0 input terminal of the (i+1)-th stage data selector and the (i+1)-th stage exclusive OR gate, and inputting the i-th stage data to be calculated I1i as the i-th stage carry data COi to the (i+1)-th stage data selector and the (i+1)-th stage exclusive OR gate; If the i-th level signal data Si is a constant 0, then reconstructing the connection topology of the carry chain to be optimized includes: Connect the output end of the i-1th level data selector to the i+1th level data selector and the I0 input end of the i+1th level exclusive OR gate, and input the i-1th level carry data COi-1 as the i-th level carry data COi to the i+1th level data selector and the I0 input end of the i+1th level exclusive OR gate.

6. The method according to claim 3, characterized in that The i-th stage data selector is the element to be optimized, and the i-th stage to-be-calculated data I1i is equal to the i-1-th stage carry data COi-1; Reconstructing the connection topology of the carry chain to be optimized includes: Connecting the output terminal of the data to be calculated to the I0 input terminal of the (i+1)-th stage data selector and the (i+1)-th stage exclusive OR gate, and inputting the i-th stage data to be calculated I1i as the i-th stage carry data COi to the (i+1)-th stage data selector and the (i+1)-th stage exclusive OR gate; Alternatively, the output end of the i-1th level data selector is connected to the i+1th level data selector and the I0 input end of the i+1th level exclusive OR gate, and the i-1th level carry data COi-1 is input as the i-level carry data COi to the i+1th level data selector and the I0 input end of the i+1th level exclusive OR gate.

7. The method according to claim 3, characterized in that The i-th level XOR gate is the element to be optimized, and the i-th level calculation result Oi is a constant; Reconstructing the connection topology of the carry chain to be optimized includes: The pre-calculated i-th level calculation result Oi is directly output to the sum input terminal.

8. The method according to claim 3, characterized in that The i-th level XOR gate is the element to be optimized, and the i-1-th level carry data COi-1 is a constant 0; Reconstructing the connection topology of the carry chain to be optimized includes: The signal data output terminal is connected to the sum input terminal, and the i-th level signal data Si is output as the i-th level calculation result Oi.

9. The method according to claim 3, characterized in that The i-th level XOR gate is the element to be optimized, and the i-1-th level carry data COi-1 is a constant 1; Reconstructing the connection topology of the carry chain to be optimized includes: The signal data output terminal is connected to the sum input terminal, and the i-th level signal data Si is inverted and output as the i-th level calculation result Oi.

10. The method according to claim 1, characterized in that The method further comprises: Determine whether there are logically identical carry chains in the FPGA chip, wherein the logically identical carry chains include at least two optimized carry chains having identical inputs and outputs; An optimized carry chain is selected from the carry chains with the same logic and retained, the remaining optimized carry chains are deleted, and the output relationship of the retained carry chains is reconstructed to obtain an optimized FPGA chip.

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