An input protection circuit of a vehicle-mounted USB charger

Abstract

The application discloses an input protection circuit of a vehicle-mounted USB charger, which comprises several operational amplifiers, several triodes, several resistors and field effect tubes. The inverting terminal of an operational amplifier U1 in the several operational amplifiers is connected with one end of a resistor R4 and one end of a resistor R6, and the output terminal is connected with the non-inverting terminal of an operational amplifier U3 and the other end of the resistor R6. The inverting terminal of the operational amplifier U2 is connected with one end of a resistor R2 and one end of a resistor R3, and the output terminal is connected with the other end of the resistor R2 and the other end of the resistor R4. The inverting terminal of the operational amplifier U3 is connected with one end of a resistor R14 and a 1_1 node, and the output terminal is connected with the base of a triode Q1. The emitter of the triode Q1 is connected with one end of a resistor R5, and the collector is connected with the base of a triode Q2. The collector of the triode Q2 is connected with the gate of a field effect tube Q3 and one end of a resistor R1, and the emitter is connected with the source of the field effect tube Q3, the other end of the resistor R3 and a VIN node. The drain of the field effect tube Q3 is connected with an Out node. The non-inverting terminal of the operational amplifier U1, the non-inverting terminal of the operational amplifier U2, the other end of the resistor R1, the other end of the resistor R5 and the other end of the resistor R14 are grounded.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, and in particular to an input protection circuit for a vehicle-mounted USB charger. Background Technology

[0002] Existing onboard charger overvoltage protection circuits generally use transient voltage suppressor diodes (TVS) as the core protection component. This design can respond quickly to voltage fluctuations and clamp the output voltage within a safe range, thus effectively protecting the equipment. However, its inherent response speed and clamping voltage characteristics limit its applicability in higher power scenarios. With the rapid development of fast charging technology, charging power and voltage requirements have increased significantly. TVS, due to its limitations in voltage withstand and energy absorption capabilities, can no longer meet the high requirements of fast charging power supply. Furthermore, in addition to public fast charging protocols, some manufacturers develop proprietary protocols as exclusive technologies to improve charging efficiency and user stickiness. This results in multiple voltage level requirements. To be compatible with output voltages under different protocols (from 5V to 20V or even higher), traditional single-stage TVS protection circuits must be expanded into multi-stage structures to cover a wider voltage range. However, this not only increases circuit complexity but also leads to limited PCB layout space. Summary of the Invention

[0003] To address the aforementioned technical problems, the purpose of this invention is to provide an input protection circuit for a car USB charger, comprising several operational amplifiers, several transistors, several resistors, and a field-effect transistor. Operational amplifier U1 has its inverting input connected to one end of resistor R4 and one end of resistor R6, and its output terminal connected to the non-inverting input of operational amplifier U3 and the other end of resistor R6. Operational amplifier U2 has its inverting input connected to one end of resistor R2 and one end of resistor R3, and its output terminal connected to the other end of resistor R2 and the other end of resistor R4. Operational amplifier U3 has its inverting input connected to a resistor... One end of R14, node 1_1, and the output terminal are connected to the base of transistor Q1; the emitter of transistor Q1 is connected to one end of resistor R5, and the collector is connected to the base of transistor Q2; the collector of transistor Q2 is connected to the gate of MOSFET Q3, one end of resistor R1, the emitter is connected to the source of MOSFET Q3, the other end of resistor R3, and node VIN; the drain of MOSFET Q3 is connected to node Out; the non-inverting inputs of operational amplifier U1 and U2, the other end of resistor R1, the other end of resistor R5, and the other end of resistor R14 are grounded.

[0004] Furthermore, it also includes several operational amplifiers, several diodes, several resistors, and a digital potentiometer. Among the several operational amplifiers, operational amplifier U4's non-inverting input is connected to one end of resistor R18 and the D+ node, its inverting input is connected to the non-inverting inputs of operational amplifiers U8 and U9, and its output terminal is connected to the anode of diode D2; operational amplifier U5's inverting input is connected to one end of resistor R16 and one end of resistor R17, and its output terminal is connected to one end of resistor R15 and the other end of resistor R17; operational amplifier U6's non-inverting input is connected to the other end of resistor R15 and the other end of resistor R18, its inverting input is connected to one end of resistor R9 and one end of resistor R10, and its output terminal is connected to the non-inverting input of operational amplifier U7 and the other end of resistor R9; operational amplifier U7's output... The output terminal is connected to the anode of diode D3; the inverting terminal of operational amplifier U8 is connected to the cathode of diode D2 and one end of resistor R13, and the output terminal is connected to pin 1A of decoder U10; the inverting terminal of operational amplifier U9 is connected to the cathode of diode D3 and one end of resistor R19, and the output terminal is connected to pin 1B of decoder U10; the 1Y0, 1Y1, 1Y2, and 1Y3 pins of decoder U10, corresponding to nodes 1_5, 1_4, 1_3, and 1_2, are connected to the processor or switching unit; the other end of diode D16 is connected to the D- node; the inverting pin 1G of decoder U10, the other end of resistor R10, and the other end of resistor R19 are grounded.

[0005] Furthermore, the switching unit also includes a relay, a diode, a transistor, and several resistors. The relay is a relay K1, one end of which is connected to one end of resistor R21 and one end of resistor R22, and the other end is connected to node 1-1. One end of the coil is connected to the emitter of transistor Q4, and the other end of the coil, the cathode of diode D4, and the other end of resistor R22 are connected to the power supply. The base of transistor Q4 is connected to one end of resistor R20 and node 1-2, and the collector is connected to one end of resistor R23. The other ends of resistor R20, resistor R21, and resistor R23 are grounded.

[0006] Furthermore, it also includes several resistors, one end of which, resistor R12, is connected to the power supply, and the other end is connected to the inverting input of operational amplifier U7 and one end of resistor R11; the other end of resistor R11 is grounded.

[0007] Furthermore, it also includes several resistors, one end of which, resistor R8, is connected to the power supply, and the other end is connected to the inverting input of operational amplifier U4 and one end of resistor R7; the other end of resistor R7 is grounded.

[0008] Furthermore, the resistor R3 is an adjustable resistor.

[0009] Furthermore, the processor is used to feed back the 1_1 reference voltage corresponding to the handshake protocol power supply voltage when it receives a low-level signal from any of nodes 1_2, 1_3, 1_4, or 1_5.

[0010] The advantages of this invention compared to existing technologies are: the power supply protection can cover a wider voltage selection range and does not require multi-level expansion. Furthermore, it can automatically control the power supply protection according to the charging protocol. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the overall circuit structure provided by the present invention.

[0013] Figure 2 A schematic diagram of the switching unit circuit structure provided by the present invention. Detailed Implementation

[0014] To make the objectives and advantages of the present invention clearer, the present invention will be specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or more specific embodiments of the present invention and does not strictly limit the scope of protection specifically claimed by the present invention.

[0015] This invention discloses an input protection circuit for a car USB charger, comprising several operational amplifiers, several transistors, several resistors, and a field-effect transistor. Operational amplifier U1 has its inverting input connected to one end of resistor R4 and one end of resistor R6, and its output terminal connected to the non-inverting input of operational amplifier U3 and the other end of resistor R6. Operational amplifier U2 has its inverting input connected to one end of resistor R2 and one end of resistor R3, and its output terminal connected to the other end of resistor R2 and the other end of resistor R4. Operational amplifier U3 has its inverting input connected to one end of resistor R14. At node 1_1, the output terminal is connected to the base of transistor Q1; the emitter of transistor Q1 is connected to one end of resistor R5, and the collector is connected to the base of transistor Q2; the collector of transistor Q2 is connected to the gate of MOSFET Q3 and one end of resistor R1, and the emitter is connected to the source of MOSFET Q3, the other end of resistor R3, and node VIN; the drain of MOSFET Q3 is connected to node Out; the non-inverting input of operational amplifier U1, the non-inverting input of operational amplifier U2, the other end of resistor R1, the other end of resistor R5, and the other end of resistor R14 are grounded.

[0016] Specifically, it also includes several operational amplifiers, several diodes, several resistors, and a digital potentiometer. Among the operational amplifiers, operational amplifier U4's non-inverting input is connected to one end of resistor R18 and the D+ node, its inverting input is connected to the non-inverting inputs of operational amplifiers U8 and U9, and its output is connected to the anode of diode D2; operational amplifier U5's inverting input is connected to one end of resistor R16 and one end of resistor R17, and its output is connected to one end of resistor R15 and the other end of resistor R17; operational amplifier U6's non-inverting input is connected to the other end of resistor R15 and the other end of resistor R18, its inverting input is connected to one end of resistor R9 and one end of resistor R10, and its output is connected to the non-inverting input of operational amplifier U7 and the other end of resistor R9; operational amplifier U7 outputs... The inverting input of operational amplifier U8 is connected to the anode of diode D3; the inverting input of operational amplifier U8 is connected to the cathode of diode D2 and one end of resistor R13, and the output is connected to pin 1A of decoder U10; the inverting input of operational amplifier U9 is connected to the cathode of diode D3 and one end of resistor R19, and the output is connected to pin 1B of decoder U10; the 1Y0, 1Y1, 1Y2, and 1Y3 pins of decoder U10, corresponding to nodes 1_5, 1_4, 1_3, and 1_2, are connected to the processor or switching unit; the other end of diode D16 is connected to node D-; the inverting input of decoder U10, the other end of resistor R10, and the other end of resistor R19 are grounded.

[0017] Specifically, the switching unit includes a relay, a diode, a transistor, and several resistors. The relay is relay K1, one end of which is connected to one end of resistor R21 and one end of resistor R22, and the other end is connected to node 1-1. One end of the coil is connected to the emitter of transistor Q4, and the other end of the coil, the cathode of diode D4, and the other end of resistor R22 are connected to the power supply. The base of transistor Q4 is connected to one end of resistor R20 and node 1-2, and the collector is connected to one end of resistor R23. The other ends of resistor R20, resistor R21, and resistor R23 are grounded.

[0018] Specifically, it also includes several resistors, one end of which is connected to the power supply and the other end is connected to the inverting input of the operational amplifier U7 and one end of the resistor R11; the other end of the resistor R11 is grounded.

[0019] Specifically, it also includes several resistors, one end of which is connected to the power supply and the other end is connected to the inverting input of the operational amplifier U4 and one end of the resistor R7; the other end of the resistor R7 is grounded.

[0020] Specifically, the resistor R3 is an adjustable resistor.

[0021] Specifically, the processor is used to feed back the 1_1 reference voltage corresponding to the handshake protocol power supply voltage when it receives a low-level signal from any of nodes 1_2, 1_3, 1_4, or 1_5.

[0022] In one embodiment, the goal is to provide corresponding overvoltage protection for different power supply voltage levels. Compared to existing transient voltage suppression diodes, this can cover a wider voltage range and does not require multi-stage expansion. In the circuit, the VIN node is the power supply input, and the Out node is the power supply output. 1_1 is used to input the corresponding power supply voltage reference signal. Initially, the VIN input voltage is fed back to the Out node via the field-effect transistor Q3 for power supply. At the same time, the VIN input is also fed back to the inverting input of op-amp U2 via resistor R3. Subsequently, one output of op-amp U2 is fed back to the inverting input of op-amp U2 via resistor R2, and the other is fed back to the inverting input of op-amp U1 via resistor R4. After negative feedback via resistor R6, the output of op-amp U1 inverts the output of op-amp U2 and inputs it to the non-inverting input of op-amp U3. 1_1 sets the reference voltage of the required power supply, and the voltage ratio is controlled by resistor R3. Assuming the required power supply input is 20V, resistor R3 is 10K. When the reference voltage for 1_1 is 2V, resistor R3 can also be set as an adjustable resistor. The detection range of the reference voltage corresponding to different required power supply voltages can be increased according to the power supply of the circuit to avoid interference. When the reference voltage for 1_1 is exceeded, the op-amp U3 outputs a signal to the base of transistor Q1, transistor Q1 turns on. The VIN voltage passes through the emitter, base, collector, emitter, resistor R5, and ground circuit of transistor Q2, transistor Q2 turns on. VIN then passes through the emitter, collector, resistor R1, and ground circuit of transistor Q2 and is fed back to the gate of MOSFET Q3, MOSFET Q3 turns off, and the power supply to MOSFET Q3 is stopped. After the circuit is packaged independently, different resistors with different R3 coefficients can be connected to the 1_1 node according to different voltage levels, or the reference voltage of 1_1 corresponding to the resistor R3 ratio can be input through the processor according to the required power supply voltage.

[0023] In one embodiment, based on the above scheme, a solution is provided that can automatically control power supply protection according to the charging protocol. Taking the common QC2.0 fast charging protocol as an example, this protocol corresponds to 3.3V and 0.6V logic voltages, and the power supply range is 5V, 9V, 12V, and 20V. The corresponding D+ and D- signals are 0.6V, 0V / 3.3V, 0.6V / 0.6V, 0.6V / 3.3V, and 3.3V, respectively. During the handshake, the corresponding D+ and D- signals are connected to the D+ and D- nodes in the circuit. The D+ input signal is fed back to the non-inverting input of operational amplifier U4, and the D- signal is input to the inverting input of operational amplifier U5 through resistor R16. The inverting input of operational amplifier U4... A reference signal is set. In the example specification, the reference signal range is 0.7-3.2V. When D+ is input, op-amp U4 compares and outputs the corresponding result level signal to the inverting input of op-amp U8. Op-amp U8 is used to isolate the output when op-amp U4 receives a negative input signal, obtains the first bit processing condition of the corresponding D+ detection, and feeds it back to decoder U10. Resistor R13 is used as a pull-down circuit when op-amp U4 outputs a negative output signal. The D+ signal is also output to op-amp U6 via resistor R18. When D- is output, op-amp U5 follows the output and obtains a proportionally inverted output through the resistor R17 circuit. The output signal is fed back to op-amp U6 via resistor R15. Op-amp U6 performs differential processing on the D+ and D- voltages and outputs the signal. After the grounding loop of resistors R9 and R10, the feedback is returned to the inverting input of op-amp U6 in a closed loop. Op-amp U7 then samples the output voltage of op-amp U6 and outputs it to the inverting input of op-amp U9 via diode D3. The power supply at the resistor R12 terminal is fed back to the inverting input of op-amp U7 after passing through the grounding loop of resistor R11. The voltage divider parameters of resistors R12 and R11 correspond to an output voltage of 0.1-0.5V. When the differential voltage of op-amp U6 is greater than the reference voltage of op-amp U7, op-amp U7 outputs a high-potential positive voltage signal, which is fed back to the inverting input of op-amp U9 via diode D3. Conversely, it outputs a low level. When the voltage is low, diode D3 prevents reverse polarity. The inverting input of op-amp U9 passes through the resistor R19 loop, and op-amp U9 outputs a signal at the output of op-amp U4. When a negative pressure signal is input, the isolated output acquires the corresponding D-detection second bit processing condition and feeds it back to the decoder U10. The decoder U10 generates corresponding four true values ​​1_2, 1_3, 1_4, and 1_5 node signals based on the two-bit processing signal input and sends them to the processor. The processor inputs the corresponding 1_1 reference voltage according to the received node signal or inputs different 1_1 node voltages through the switching unit. Among them, the 1G inverted pin of the U10 decoder is the enable pin, which is activated when low level. The 1A and 1B pins are the selection pins, and the 1Y0 to 1Y3 pins are the output pins. The decoder U10 outputs any low level signal from 1Y0 to 1Y3 according to the 1A and 1B states input by the circuit.

[0024] In one embodiment, a switching unit is used instead of the upper-level output. The choice of this scheme depends on the number of processor ports. Each node 1_2, 1_3, 1_4, and 1_5 is connected to a corresponding switching unit. The attached figure only shows one switching unit. The input terminal of each switching unit is set with a reference voltage 1_1 that corresponds to the required power supply voltage. After the switching unit is turned on, the corresponding 1_1 is fed back to the operational amplifier U3. The reference voltages at the inverting terminals of operational amplifiers U4 and U7 can be set by voltage division or by the power supply. In each switching unit, the voltages at nodes R22 and R21 correspond to the required power supply voltage. When 1_2 is at a low level output, the power supply at one end of the relay K1 coil is routed through the coil, the emitter and base of transistor Q4, resistor R20, and the ground terminal. After transistor Q4 is turned on, the current of relay K1 is amplified, relay K1 is energized, and the normally open contact of relay K1 turns to normally closed. The voltages at nodes R22 and R21 are fed back to 1_1. Resistor R23 is used for current limiting.

[0025] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No markings in the claims should be construed as limiting the scope of the claims.

Claims

1. An input protection circuit for a car USB charger, characterized in that, The system includes several operational amplifiers (op-amps), several transistors, several resistors, several diodes, field-effect transistors (FETs), and a digital potentiometer. Among the op-amps, op-amp U1's inverting input is connected to one end of resistor R4 and one end of resistor R6, and its output is connected to the non-inverting input of op-amp U3 and the other end of resistor R6. Op-amp U2's inverting input is connected to one end of resistor R2 and one end of resistor R3, and its output is connected to the other end of resistor R2 and the other end of resistor R4. Op-amp U3's inverting input is connected to one end of resistor R14 and node 1-1, and its output is connected to the base of transistor Q1. The emitter of transistor Q1 is connected to one end of resistor R5, and its collector is connected to the base of transistor Q2. The collector of transistor Q2 is connected to the gate of FET Q3 and one end of resistor R1, and its emitter is connected to the source of FET Q3 and resistor R3. The other end is connected to the VIN node; the drain of the field-effect transistor Q3 is connected to the Out node; the non-inverting input of op-amp U1, the non-inverting input of op-amp U2, the other end of resistor R1, the other end of resistor R5, and the other end of resistor R14 are grounded; the non-inverting input of op-amp U4 is connected to one end of resistor R18 and the D+ node; the inverting input is connected to the non-inverting input of op-amp U8 and the non-inverting input of op-amp U9; the output is connected to the anode of diode D2; the inverting input of op-amp U5 is connected to one end of resistor R16 and one end of resistor R17; the output is connected to one end of resistor R15 and the other end of resistor R17; the non-inverting input of op-amp U6 is connected to the other end of resistor R15 and the other end of resistor R18; the inverting input is connected to one end of resistor R9 and one end of resistor R10; the output is connected to the non-inverting input of op-amp U7 and the other end of resistor R9. The output of operational amplifier U7 is connected to the anode of diode D3; the inverting input of operational amplifier U8 is connected to the cathode of diode D2 and one end of resistor R13, and its output is connected to pin 1A of decoder U10; the inverting input of operational amplifier U9 is connected to the cathode of diode D3 and one end of resistor R19, and its output is connected to pin 1B of decoder U10; the 1Y0, 1Y1, 1Y2, and 1Y3 pins of decoder U10, corresponding to nodes 1_5, 1_4, 1_3, and 1_2, are connected to the processor or switching unit; the other end of diode D16 is connected to node D-; the inverting pin 1G of decoder U10, the other end of resistor R10, and the other end of resistor R19 are grounded.

2. The input protection circuit of the vehicle-mounted USB charger according to claim 1, characterized in that, The switching unit includes a relay, a diode, a transistor, and several resistors. The relay is relay K1, one end of which is connected to one end of resistor R21 and one end of resistor R22, and the other end is connected to node 1-1. One end of the coil is connected to the emitter of transistor Q4, and the other end of the coil, the cathode of diode D4, and the other end of resistor R22 are connected to the power supply. The base of transistor Q4 is connected to one end of resistor R20 and node 1-2, and the collector is connected to one end of resistor R23. The other ends of resistor R20, resistor R21, and resistor R23 are grounded.

3. The input protection circuit of the vehicle-mounted USB charger according to claim 1, characterized in that, It also includes several resistors, one end of which is connected to the power supply and the other end is connected to the inverting input of the operational amplifier U7 and one end of the resistor R11; the other end of the resistor R11 is grounded.

4. The input protection circuit of the vehicle-mounted USB charger according to claim 1, characterized in that, It also includes several resistors, one end of which is connected to the power supply and the other end is connected to the inverting input of the operational amplifier U4 and one end of the resistor R7; the other end of the resistor R7 is grounded.

5. The input protection circuit of the vehicle-mounted USB charger according to claim 1, characterized in that, The resistor R3 is an adjustable resistor.

6. The input protection circuit of the vehicle-mounted USB charger according to claim 1, characterized in that, The processor is used to feed back the 1_1 reference voltage corresponding to the handshake protocol power supply voltage when it receives a low-level signal from any of nodes 1_2, 1_3, 1_4, or 1_5.

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